Digital display control buffer circuit and digital display control buffer device

Abstract

The application provides a digital display control buffer circuit and a digital display control buffer device. The digital display control buffer circuit comprises at least a deburring circuit, a first comparison unit, a second comparison unit and a first switching device. A first end of the first switching device and a first input end of the second comparison unit are used for inputting an upstream signal of the digital display control buffer circuit. A first input end of the first comparison unit is used for inputting a downstream signal of the digital display control buffer circuit. The deburring circuit is used for outputting a control signal to a control end of the first switching device to make the first switching device off in the case that a first signal output at an output end of the second comparison unit is a falling edge. The circuit solves the problem of long delay of the switching device on the upstream in the process of transmitting the signal from the upstream to the downstream of the digital display control buffer and the generation of glitches.

Description

Technical Field

[0001] This application relates to the field of communications, and more specifically, to a digital display control buffer circuit and a digital display control buffer device. Background Technology

[0002] A digital display control buffer (DDC buffer) is a buffer used in repeater circuits supporting wired multimedia communication protocols to connect upstream and downstream circuits. The DDC buffer monitors upstream and downstream signals and sends the monitored signals back to the upstream and downstream circuits respectively, enabling communication between them. Furthermore, the DDC buffer isolates the load capacitance of the upstream and downstream circuits. The DDC buffer uses an open-drain N-type field-effect transistor and a resistor in series to achieve pull-up and pull-down functions for the output signal level; this design effectively achieves 5V voltage withstand capability.

[0003] However, in the working mode of the DDC buffer monitoring the upstream signal and sending the signal downstream, the monitored upstream signal will generate a large glitch on the rising edge. This glitch will not only affect the duty cycle of the upstream signal, but also increase the risk of incorrect conversion of the upstream signal to the digital signal.

[0004] Therefore, there is an urgent need for a de-glitch circuit that can remove the glitches generated during the process of sending signals from upstream to downstream in the digital display control buffer. Summary of the Invention

[0005] The main objective of this application is to provide a digital display control buffer circuit and a digital display control buffer device, so as to at least solve the problem of long delay in turning off the upstream switching device and generating glitches in the process of sending signals from upstream to downstream in the prior art digital display control buffer.

[0006] According to one aspect of this application, a digital display control buffer circuit is provided. The digital display control buffer circuit includes at least a de-glitch circuit, a first comparison unit, a second comparison unit, and a first switching device. A first terminal of the first switching device and a first input terminal of the second comparison unit are used to input an upstream signal of the digital display control buffer circuit. A first input terminal of the first comparison unit is used to input a downstream signal of the digital display control buffer circuit. A first input terminal of the de-glitch circuit is electrically connected to the output terminal of the first comparison unit. A second input terminal of the de-glitch circuit is electrically connected to the output terminal of the second comparison unit. The output terminal of the de-glitch circuit is electrically connected to the control terminal of the first switching device. The de-glitch circuit is used to output a control signal to the control terminal of the first switching device when the first signal output by the output terminal of the second comparison unit is a falling edge, so as to turn off the first switching device.

[0007] Optionally, the de-glitch circuit includes: a trigger unit, wherein a first input terminal of the trigger unit is a first input terminal of the de-glitch circuit, a second input terminal of the trigger unit is a second input terminal of the de-glitch circuit, and an output terminal of the trigger unit is connected to a third input terminal of the trigger unit; the trigger unit is used to trigger and output a trigger signal when the first signal is a falling edge; and a filtering unit, wherein a first input terminal of the filtering unit is electrically connected to the first input terminal of the trigger unit, a second input terminal of the filtering unit is connected to the output terminal of the trigger unit, and the output terminal of the filtering unit is the output terminal of the de-glitch circuit; the filtering unit is used to output the control signal when the edges of the second signal output by the first comparison unit and the trigger signal are opposite.

[0008] Optionally, the triggering unit includes a first D flip-flop, the first D flip-flop being triggered on a falling edge, the reset pin of the first D flip-flop being the first input terminal of the triggering unit, the CLK pin of the first D flip-flop being the second input terminal of the triggering unit, the D pin of the first D flip-flop being the third input terminal of the triggering unit, and the Q pin of the first D flip-flop being the output terminal of the triggering unit.

[0009] Optionally, the triggering unit includes an inverter and a second D flip-flop, the second D flip-flop being rising-edge triggered, the input terminal of the inverter being the second input terminal of the triggering unit, the output terminal of the inverter being electrically connected to the CLK pin of the second D flip-flop, the reset pin of the second D flip-flop being the first input terminal of the triggering unit, the D pin of the second D flip-flop being the third input terminal of the triggering unit, and the Q pin of the second D flip-flop being the output terminal of the triggering unit.

[0010] Optionally, the digital display control buffer circuit further includes an operational amplifier, the first comparison unit is a first comparator, the second comparison unit is a second comparator, the first switching device is a first NMOS transistor, the inverting input terminal of the first comparator is the first input terminal of the first comparison unit, the non-inverting input terminal of the first comparator is the second input terminal of the first comparison unit and is used to input a first reference signal, the output terminal of the first comparator is the output terminal of the first comparison unit, the inverting input terminal of the second comparator is the first input terminal of the second comparison unit, the non-inverting input terminal of the second comparator is the second input terminal of the second comparison unit and is used to input a second reference signal, the output terminal of the second comparator is the output terminal of the second comparison unit, the gate of the first NMOS transistor is the control terminal of the first switching device, the drain of the first NMOS transistor is the first terminal of the first switching device, the inverting input terminal of the operational amplifier is electrically connected to the output terminal of the operational amplifier and the source of the first NMOS transistor, the source of the first NMOS transistor is the second terminal of the first switching device, and the non-inverting input terminal of the operational amplifier is used to input a third reference signal.

[0011] Optionally, the digital display control buffer circuit further includes: a second switching device, wherein the control terminal of the second switching device is electrically connected to the output terminal of the second comparison unit, the first terminal of the second switching device is electrically connected to the first terminal of the first comparison unit, and the second terminal of the second switching device is grounded.

[0012] Optionally, the second switching device is a second NMOS transistor, the gate of the second NMOS transistor is the control terminal of the second switching device, the drain of the second NMOS transistor is the first terminal of the second switching device, and the source of the second NMOS transistor is the second terminal of the second switching device.

[0013] Optionally, the digital display control buffer circuit further includes: a third comparator, wherein the inverting input terminal of the third comparator is used to input a fourth reference signal, the non-inverting input terminal of the third comparator is used to input an upstream signal of the digital display control buffer circuit, and the output terminal of the third comparator is used to output a digital signal corresponding to the upstream signal.

[0014] According to another aspect of this application, a digital display control buffer device is provided, comprising: any of the digital display control buffer circuits described above.

[0015] Furthermore, the digital display control buffer device further includes: an upstream pull-down circuit, which includes a first impedance, a second impedance, and a third switching device. One end of the first impedance is used to connect to an upstream power supply terminal, and the other end of the first impedance is electrically connected to the first end of the third switching device and the first end of the second impedance, respectively. The other end of the first impedance is used to input an upstream signal to the digital display control buffer circuit, and the other end of the second impedance and the second end of the third switching device are used to ground; and a downstream pull-down circuit, which includes a third impedance, a fourth impedance, and a fourth switching device. One end of the third impedance is used to connect to a downstream power supply terminal, and the other end of the third impedance is electrically connected to the first end of the fourth switching device and the first end of the fourth impedance, respectively. The other end of the third impedance is used to input a downstream signal to the digital display control buffer circuit, and the other end of the fourth impedance and the second end of the fourth switching device are used to ground.

[0016] The present application provides a digital display control buffer circuit, which includes at least a de-glitch circuit, a first comparison unit, a second comparison unit, and a first switching device. The first terminal of the first switching device and the first input terminal of the second comparison unit are used to input upstream signals of the digital display control buffer circuit. The first input terminal of the first comparison unit is used to input downstream signals of the digital display control buffer circuit. The first input terminal of the de-glitch circuit is electrically connected to the output terminal of the first comparison unit, the second input terminal of the de-glitch circuit is electrically connected to the output terminal of the second comparison unit, and the output terminal of the de-glitch circuit is electrically connected to the control terminal of the first switching device. When the first signal output by the output terminal of the second comparison unit is low, the de-glitch circuit outputs a control signal to the control terminal of the first switching device to turn off the first switching device. By introducing a de-glitch circuit into the aforementioned digital display control buffer circuit, when a high-level signal is sent upstream of the digital display control buffer, a low-level output signal from the downstream second comparison unit is received, and a control signal is output to the control terminal of the first switching device to turn off the first switching device. This shortens the delay in turning off the first switching device, thereby avoiding interruption of the upstream voltage rise process. This achieves the effect of removing circuit glitches and solves the problem of long delay in turning off the upstream switching device and generating glitches during the process of the digital display control buffer sending signals from upstream to downstream. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1A structural block diagram of a digital display control buffer circuit provided in an embodiment of this application is shown;

[0019] Figure 2 A structural block diagram of a deburring circuit according to an embodiment of this application is shown;

[0020] Figure 3 A structural block diagram of a trigger unit provided according to an embodiment of this application is shown;

[0021] Figure 4 A structural block diagram of another triggering unit provided according to an embodiment of this application is shown;

[0022] Figure 5 A structural block diagram of another digital display control buffer circuit provided according to an embodiment of this application is shown;

[0023] Figure 6 A schematic diagram of an upstream signal voltage change is shown;

[0024] Figure 7 A schematic diagram showing the voltage changes of the output signal of the second comparison unit, the output signal of the trigger unit, the output signal of the first comparison unit, and the control signal output by the filtering unit provided in an embodiment of this application is shown.

[0025] Figure 8 A schematic diagram of signal voltage variation provided according to an embodiment of this application is shown;

[0026] Figure 9 A structural block diagram of a digital display control buffer device provided according to an embodiment of this application is shown.

[0027] The above figures include the following reference numerals:

[0028] 100. Digital display control buffer circuit; 101. De-glitch circuit; 102. First comparison unit; 103. Second comparison unit; 104. First switching device; 105. Trigger unit; 106. Filtering unit; 107. First D flip-flop; 108. AND gate; 109. Second D flip-flop; 110. Inverter; 111. Operational amplifier; 112. Upstream pull-down circuit; 113. Downstream pull-down circuit. Detailed Implementation

[0029] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0030] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] As described in the background section, in the prior art, during the process of sending signals from upstream to downstream, the delay in shutting down the upstream switching device in the digital display control buffer is relatively long, which will produce glitches. In order to solve the above problems, the embodiments of this application provide a digital display control buffer circuit and a digital display control buffer device.

[0033] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0034] Figure 1 This is a structural block diagram of a digital display control buffer circuit according to an embodiment of this application. Figure 1As shown, the digital display control buffer circuit 100 includes at least a de-glitch circuit 101, a first comparison unit 102, a second comparison unit 103, and a first switching device 104. The first terminal of the first switching device 104 and the first input terminal of the second comparison unit 103 are used to input upstream signals of the digital display control buffer circuit 100. The first input terminal of the first comparison unit 102 is used to input downstream signals of the digital display control buffer circuit 100. The first input terminal of the de-glitch circuit 101 is electrically connected to the output terminal of the first comparison unit 102. The second input terminal of the de-glitch circuit 101 is electrically connected to the output terminal of the second comparison unit 103. The output terminal of the de-glitch circuit 101 is electrically connected to the control terminal of the first switching device 104. When the first signal output from the output terminal of the second comparison unit 103 is a falling edge, the de-glitch circuit 101 outputs a control signal to the control terminal of the first switching device 104 to turn off the first switching device 104.

[0035] Specifically, the Digital Display Control (DDC) buffer circuit is a buffer circuit used in repeater circuits supporting wired multimedia communication protocols to connect upstream and downstream circuits. The DDC buffer can monitor signals from both the upstream and downstream circuits and send the monitored signals to each, thus enabling communication between them. In practical applications, when the DDC buffer monitors the upstream circuit sending signals to the downstream circuit, a transient overvoltage, or glitch, can occur on the rising edge of the monitored upstream signal. Although this glitch does not affect the DDC buffer's ability to send signals downstream, it does affect the duty cycle of the upstream signal and increases the risk of incorrect conversion between the upstream electrical signal and the digital signal. In practice, this glitch-reducing circuit directly acquires the low-level control signal output from the second comparison unit, triggers it, and outputs a control signal to directly control the first switching device, significantly reducing the delay in turning off the first switching device and further eliminating the aforementioned glitch.

[0036] This embodiment provides a digital display control buffer circuit, which includes at least a de-glitch circuit, a first comparison unit, a second comparison unit, and a first switching device. The first terminal of the first switching device and the first input terminal of the second comparison unit are used to input upstream signals of the digital display control buffer circuit. The first input terminal of the first comparison unit is used to input downstream signals of the digital display control buffer circuit. The first input terminal of the de-glitch circuit is electrically connected to the output terminal of the first comparison unit, the second input terminal of the de-glitch circuit is electrically connected to the output terminal of the second comparison unit, and the output terminal of the de-glitch circuit is electrically connected to the control terminal of the first switching device. When the first signal output by the output terminal of the second comparison unit is low, the de-glitch circuit outputs a control signal to the control terminal of the first switching device to turn off the first switching device. By introducing a de-glitch circuit into the aforementioned digital display control buffer circuit, when a high-level signal is sent upstream of the digital display control buffer, a low-level output signal from the downstream second comparison unit is received, and a control signal is output to the control terminal of the first switching device to turn off the first switching device. This shortens the delay in turning off the first switching device, thereby avoiding interruption of the upstream voltage rise process. This achieves the effect of removing circuit glitches and solves the problem of long delay in turning off the upstream switching device and generating glitches during the process of the digital display control buffer sending signals from upstream to downstream.

[0037] In the specific implementation process, such as Figure 2 As shown, the deburring circuit 101 includes: a trigger unit 105, wherein the first input terminal of the trigger unit 105 is the first input terminal of the deburring circuit 101, the second input terminal of the trigger unit 105 is the second input terminal of the deburring circuit 101, and the output terminal and the third input terminal of the trigger unit 105 are connected. The trigger unit 105 is used to trigger and output a trigger signal when the first signal is a falling edge; and a filter unit 106, wherein the first input terminal of the filter unit 106 is electrically connected to the first input terminal of the trigger unit 105, the second input terminal of the filter unit 106 is connected to the output terminal of the trigger unit 105, and the output terminal of the filter unit 106 is the output terminal of the deburring circuit 101. The filter unit 106 is used to output the control signal when the level of the second signal output by the first comparison unit 102 is opposite to that of the trigger signal. The combination of the trigger unit and the filter unit to implement the deburring circuit further simplifies the deburring circuit.

[0038] Specifically, a flip-flop is an electronic component used to store and stabilize signals, and it can change its output state under specific input conditions. Flip-flops are commonly used in digital circuits to store and process binary data. Various flip-flops have different input and output characteristics and can be used to implement various logic functions and timing controls. Those skilled in the art can select the appropriate flip-flop based on actual functional requirements.

[0039] To further simplify the above triggering unit, such as Figure 3 As shown, the trigger unit 105 of this application includes a first D flip-flop 107, which is triggered on a falling edge. The reset pin of the first D flip-flop 107 is the first input terminal of the trigger unit 105, the CLK pin of the first D flip-flop 107 is the second input terminal of the trigger unit 105, the D pin of the first D flip-flop 107 is the third input terminal of the trigger unit 105, and the Q pin of the first D flip-flop 107 is the output terminal of the trigger unit 105. Since D flip-flops have the characteristics of high stability, high reliability, simple operation, wide applicability, strong programmability, and high-speed performance, setting the trigger unit as a D flip-flop in this circuit can further improve the effect of the de-glitch circuit in removing circuit glitches.

[0040] Specifically, a D flip-flop is a basic digital logic circuit element used to store and transmit single bits of information. It has two input pins and two output pins: the D input pin, the clock input pin, the Q output pin, and the Q' output pin. The D input pin is used to input the data to be stored. When the clock signal arrives, the D flip-flop stores the value on the D input pin in its internal memory cell. The clock input pin is used to control the operation of the memory cell. When the edge of the clock signal arrives, the D flip-flop updates the state of the memory cell according to the value on the D input pin. The Q output pin is used to output the value stored in the memory cell. When the edge of the clock signal arrives, the value on the Q output pin is updated to the value in the memory cell. The Q' output pin is the complement of the Q output pin, i.e., the inverse value of the Q output pin. When the edge of the clock signal arrives, the value on the Q' output pin is updated to the inverse value of the Q output pin. By controlling the values ​​on the D input pins and the edges of the clock signal, different functions of the D flip-flop can be achieved, such as storage, transmission, and timing control. The D flip-flop has high stability during operation, resisting the effects of noise and interference, ensuring stable data transmission and storage. Due to the storage characteristics of D flip-flops, data can be reliably transmitted and stored under the action of clock signals, effectively avoiding data loss and errors. Furthermore, D flip-flops have a fast response speed and transmission rate, meeting the requirements of high-speed sequential circuits and making them suitable for high-speed data transmission and processing scenarios.

[0041] likeFigure 4 As shown, the trigger unit 105 includes an inverter 110 and a second D flip-flop 109. The second D flip-flop 109 is triggered on the rising edge. The input terminal of the inverter 110 is the second input terminal of the trigger unit 105. The output terminal of the inverter 110 is electrically connected to the CLK pin of the second D flip-flop 109. The reset pin of the second D flip-flop 109 is the first input terminal of the trigger unit 105. The D pin of the second D flip-flop 109 is the third input terminal of the trigger unit 105. The Q pin of the second D flip-flop 109 is the output terminal of the trigger unit 105. Because D flip-flops have the characteristics of high stability, high reliability, simple operation, wide applicability, strong programmability, and high-speed performance, setting the trigger unit as a D flip-flop in this circuit can further improve the effect of the de-glitch circuit in removing circuit glitches.

[0042] Specifically, high-level triggering means that when the clock signal of the D flip-flop is high, changes in the data input level can be read by the flip-flop; low-level triggering means that when the clock signal of the D flip-flop is low, changes in the data input level can be read by the flip-flop. In high-level triggering mode, changes in the data input are only read by the flip-flop on the rising edge of the clock signal, therefore, output changes only occur on the rising edge of the clock signal. In low-level triggering mode, changes in the data input are only read by the flip-flop on the falling edge of the clock signal.

[0043] In some embodiments, such as Figure 5As shown, the digital display control buffer circuit further includes an operational amplifier 111. The first comparison unit is a first comparator, the second comparison unit is a second comparator, the first switching device is a first NMOS transistor, the inverting input terminal of the first comparator is the first input terminal of the first comparison unit, the non-inverting input terminal of the first comparator is the second input terminal of the first comparison unit and is used to input a first reference signal, the output terminal of the first comparator is the output terminal of the first comparison unit, the inverting input terminal of the second comparator is the first input terminal of the second comparison unit, and the non-inverting input terminal of the second comparator is the output terminal of the second comparison unit. The input terminal is the second input terminal of the second comparator unit and is used to input the second reference signal. The output terminal of the second comparator is the output terminal of the second comparator unit. The gate of the first NMOS transistor is the control terminal of the first switching device. The drain of the first NMOS transistor is the first terminal of the first switching device. The inverting input terminal of the operational amplifier 111 is electrically connected to the output terminal of the operational amplifier 111 and the source of the first NMOS transistor. The source of the first NMOS transistor is the second terminal of the first switching device. The non-inverting input terminal of the operational amplifier 111 is used to input the third reference signal. The configuration of the operational amplifier 111 further ensures that the DDC buffer sends a low-voltage level signal upstream.

[0044] Specifically, the aforementioned operational amplifier is used during the process of the upstream circuit sending a high-level signal. At this time, the DDC buffer monitors the upstream data and transmits the data to the downstream. Since both the first and second switching devices are turned on during the process of the upstream sending a low-level signal, the operational amplifier first converts V through a unity-gain buffer. SRC From V SS Pull to V SRC_OL .like Figure 5 As shown, the deburring circuit 101 consists of an AND gate 108, a second D flip-flop 109, and an inverter 110.

[0045] The digital display control buffer circuit of this application further includes: a second switching device, wherein the control terminal of the second switching device is electrically connected to the output terminal of the second comparison unit, the first terminal of the second switching device is electrically connected to the first terminal of the first comparison unit, and the second terminal of the second switching device is grounded. The second switching device is used to further control the downstream circuit.

[0046] Specifically, due to the third reference signal V OL_REF Compared to the second reference signal V SNK_REFAt this point, the negative input voltage of the second comparator is higher than the positive input voltage, thus turning off the second switching device. Downstream, there is no drive from the second switching device, so the negative input voltage of the first comparator is also higher than the positive input voltage, causing the first switching device to turn off. V SRC With V SRC_OL The pathway is broken. That is to say, as... Figure 6 As shown, when the DDC buffer monitors the high-level signal sent from the upstream end, V SRC Rise to V DD_SRC The process is divided into three stages: first from V SS Rise to V SRC_OL Subsequently at level V SRC_OL It lasted for a period of time, eventually rising to V. DD_SRC , where V OS It represents V SRC Pulled to V by operational amplifier SRC_OL Overshoot voltage during the process. V SRC In V SRC_OL The duration depends on the duration after the second switching device is turned off, and because the downstream load capacitance is large, the duration is longer, and the spike is also due to the overshoot voltage V. OS The existence and V SCR At level V SRC_OL This occurs due to the excessively long duration. In fact, the purpose of the aforementioned deburring circuit is to shorten the duration of the second stage.

[0047] In some embodiments, the second switching device is a second NMOS transistor, with the gate of the second NMOS transistor serving as the control terminal, the drain of the second NMOS transistor being the first terminal, and the source of the second NMOS transistor being the second terminal. By using a second NMOS transistor as the second switching device, the circuit can further simplify the second switching device and enable it to control downstream signals.

[0048] Specifically, when the upstream sends a high-level signal, the voltage changes as follows: Figure 7 As shown, in V SRC From V SS Pulled to V SRC_OL During the process, V SRC The level is first higher than that of the second reference signal V. SNK_REF And make the output signal V of the second comparator SNK_COMP A falling edge is generated at this time, at which point the output signal V of the first comparator... SRC_COMP Still high, falling edge triggers the register, after a delay t from the trigger unit. CK-Q Make the output signal V of the trigger unit DThe output is low, and then it passes through the filter unit for a delay t. AND_DLY Pull the gate of the first switching device low to disconnect V. SCR With V SRC_OL The path. Because the gate of the second switching device is controlled by the output signal V of the second comparator. SNK_COMP After being pulled down, the downstream signal V SNK The level is slowly rising, when V SNK Higher than the first reference signal V SRC_REF At that time, the output signal V of the first comparator SRC_COMP The change from high to low resets the flip-flop in the trigger unit, V D The reset signal is high, but the output signal V of the filter unit is low. DG The value remains low, and the upstream signal V has not been interrupted. SRC The pull-up process completes the aforementioned burr removal process. It is important to note that the output signal V of the second comparator... SNK_COMP A falling edge is generated to the output signal V of the first comparator. SRC_COMP The time t for the jump from high to low II That is, corresponding to the above Figure 6 The duration of the second phase is determined by the output signal V of the second signal comparator. SNK_COMP The trigger in the trigger unit is activated to turn off the first switching device, by V SRC Rise to V SNK_REF The time required from triggering the trigger to turning off the first switching device is only the delay of the trigger unit and the filter unit (t) CK-Q +t AND_DLY The duration of ) is much shorter than Figure 6 The second stage duration t II After the burrs are removed, V SRC Rising waveform as Figure 8 As shown.

[0049] The digital display control buffer circuit of this application further includes: a third comparator, wherein the inverting input terminal of the third comparator is used to input a fourth reference signal, the non-inverting input terminal of the third comparator is used to input an upstream signal of the digital display control buffer circuit, and the output terminal of the third comparator is used to output a digital signal corresponding to the upstream signal. This circuit can thus generate a digital signal of the upstream signal.

[0050] Specifically, the process of generating the aforementioned digital signal using a comparator is as follows: Determine the input and output level ranges of the comparator. A comparator typically has one or more input terminals and one output terminal. The input terminal receives analog signals, and the output terminal outputs digital signals. Determine the input and output level ranges according to the application requirements. A resistor divider network or other circuits can be used to generate a reference level. Connect the analog signal that needs to be converted into a digital signal to the input terminal of the comparator, and connect the output terminal of the comparator to the circuit that needs to receive the digital signal. Depending on the actual needs, it may be necessary to adjust the threshold of the comparator so that it outputs a high or low level when the input signal exceeds or falls below a certain level. After connecting the circuit, test and verify the comparator to ensure that it can correctly convert analog signals into digital signals.

[0051] This application also provides a digital display control buffer device, which will be described below.

[0052] The device includes any one of the aforementioned digital display control buffer circuits. The aforementioned digital display control buffer circuit includes at least a de-glitch circuit, a first comparison unit, a second comparison unit, and a first switching device. The first terminal of the first switching device and the first input terminal of the second comparison unit are used to input an upstream signal to the digital display control buffer circuit. The first input terminal of the first comparison unit is used to input a downstream signal to the digital display control buffer circuit. The first input terminal of the de-glitch circuit is electrically connected to the output terminal of the first comparison unit. The second input terminal of the de-glitch circuit is electrically connected to the output terminal of the second comparison unit. The output terminal of the de-glitch circuit is electrically connected to the control terminal of the first switching device. When the first signal output from the output terminal of the second comparison unit is low, the de-glitch circuit outputs a control signal to the control terminal of the first switching device to turn off the first switching device. The digital display control buffer circuit is a buffer circuit used in repeater circuits supporting wired multimedia communication protocols to connect upstream and downstream circuits.

[0053] Specifically, the DDC buffer can monitor upstream and downstream circuit signals and send the monitored signals to the upstream and downstream circuits respectively, thereby enabling communication between them. In practical applications, in the operating mode where the DDC buffer monitors the upstream circuit sending signals to the downstream circuit, the monitored upstream signal will generate transient overvoltages, i.e., glitches, on the rising edge. Although these glitches do not affect the function of the DDC buffer sending signals downstream, they will affect the duty cycle of the upstream signal and increase the risk of incorrect conversion of the upstream electrical signal to a digital signal. In fact, this glitch removal circuit is triggered by directly acquiring the low-level control signal output from the second comparison unit and outputting a control signal to directly control the first switching device, greatly reducing the delay in turning off the first switching device and further eliminating the aforementioned glitches.

[0054] In this embodiment, a digital display control buffer device is provided. The digital display control buffer device includes a digital display control buffer circuit, which includes at least a de-glitch circuit, a first comparison unit, a second comparison unit, and a first switching device. The first terminal of the first switching device and the first input terminal of the second comparison unit are used to input upstream signals of the digital display control buffer circuit. The first input terminal of the first comparison unit is used to input downstream signals of the digital display control buffer circuit. The first input terminal of the de-glitch circuit is electrically connected to the output terminal of the first comparison unit, and the second input terminal of the de-glitch circuit is electrically connected to the output terminal of the second comparison unit. The output terminal of the de-glitch circuit is electrically connected to the control terminal of the first switching device. When the first signal output by the output terminal of the second comparison unit is low, the de-glitch circuit outputs a control signal to the control terminal of the first switching device to turn off the first switching device. By introducing a de-glitch circuit into the aforementioned digital display control buffer circuit, when a high-level signal is sent upstream of the digital display control buffer, a low-level output signal from the downstream second comparison unit is received, and a control signal is output to the control terminal of the first switching device to turn off the first switching device. This shortens the delay in turning off the first switching device, thereby avoiding interruption of the upstream voltage rise process. This achieves the effect of removing circuit glitches and solves the problem of long delay in turning off the upstream switching device and generating glitches during the process of the digital display control buffer sending signals from upstream to downstream.

[0055] As an alternative solution, such as Figure 9As shown, the aforementioned digital display control buffer device further includes: an upstream pull-down circuit 112, comprising a first impedance, a second impedance, and a third switching device. One end of the first impedance is connected to an upstream power supply terminal, and the other end of the first impedance is electrically connected to the first terminal of the third switching device and the first terminal of the second impedance, respectively. The other end of the first impedance is used to input an upstream signal to the digital display control buffer circuit 100, and the other end of the second impedance and the second terminal of the third switching device are grounded. A downstream pull-down circuit 113 includes a third impedance, a fourth impedance, and a fourth switching device. One end of the third impedance is connected to a downstream power supply terminal, and the other end of the third impedance is electrically connected to the first terminal of the fourth switching device and the first terminal of the fourth impedance, respectively. The other end of the third impedance is used to input a downstream signal to the digital display control buffer circuit 100, and the other end of the fourth impedance and the second terminal of the fourth switching device are grounded. The upstream pull-down circuit 112 can further adjust the upstream signal, and the downstream pull-down circuit 113 can further adjust the downstream signal.

[0056] Specifically, in addition to the aforementioned digital display control buffer circuit, an upstream pull-down circuit and a downstream pull-down circuit are also included. The first and third impedances can be pull-up resistors, the second and fourth impedances can be load capacitors, and the third and fourth switching devices can be NMOS transistors, which are used to send data to the upstream and downstream circuits respectively.

[0057] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0058] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0059] 1) The digital display control buffer circuit of this application includes at least a de-glitch circuit, a first comparison unit, a second comparison unit, and a first switching device. The first terminal of the first switching device and the first input terminal of the second comparison unit are used to input the upstream signal of the digital display control buffer circuit. The first input terminal of the first comparison unit is used to input the downstream signal of the digital display control buffer circuit. The first input terminal of the de-glitch circuit is electrically connected to the output terminal of the first comparison unit. The second input terminal of the de-glitch circuit is electrically connected to the output terminal of the second comparison unit. The output terminal of the de-glitch circuit is electrically connected to the control terminal of the first switching device. When the first signal output by the output terminal of the second comparison unit is a falling edge, the de-glitch circuit outputs a control signal to the control terminal of the first switching device to turn off the first switching device. By introducing a de-glitch circuit into the aforementioned digital display control buffer circuit, when a high-level signal is sent upstream of the digital display control buffer, a low-level output signal from the downstream second comparison unit is received, and a control signal is output to the control terminal of the first switching device to turn off the first switching device. This shortens the delay in turning off the first switching device, thereby avoiding interruption of the upstream voltage rise process. This achieves the effect of removing circuit glitches and solves the problem of long delay in turning off the upstream switching device and generating glitches during the process of the digital display control buffer sending signals from upstream to downstream.

[0060] 2) The digital display control buffer device of this application includes a digital display control buffer circuit. The digital display control buffer circuit includes at least a de-glitch circuit, a first comparison unit, a second comparison unit, and a first switching device. The first terminal of the first switching device and the first input terminal of the second comparison unit are used to input upstream signals of the digital display control buffer circuit. The first input terminal of the first comparison unit is used to input downstream signals of the digital display control buffer circuit. The first input terminal of the de-glitch circuit is electrically connected to the output terminal of the first comparison unit. The second input terminal of the de-glitch circuit is electrically connected to the output terminal of the second comparison unit. The output terminal of the de-glitch circuit is electrically connected to the control terminal of the first switching device. When the first signal output by the output terminal of the second comparison unit is a falling edge, the de-glitch circuit outputs a control signal to the control terminal of the first switching device to turn off the first switching device. By introducing a de-glitch circuit into the aforementioned digital display control buffer circuit, when a high-level signal is sent upstream of the digital display control buffer, a low-level output signal from the downstream second comparison unit is received, and a control signal is output to the control terminal of the first switching device to turn off the first switching device. This shortens the delay in turning off the first switching device, thereby avoiding interruption of the upstream voltage rise process. This achieves the effect of removing circuit glitches and solves the problem of long delay in turning off the upstream switching device and generating glitches during the process of the digital display control buffer sending signals from upstream to downstream.

[0061] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A digital display control buffer circuit, characterized in that, The digital display control buffer circuit includes at least a de-glitch circuit, a first comparison unit, a second comparison unit, and a first switching device. The first terminal of the first switching device and the first input terminal of the second comparison unit are used to input upstream signals of the digital display control buffer circuit. The first input terminal of the first comparison unit is used to input downstream signals of the digital display control buffer circuit. The first input terminal of the de-glitch circuit is electrically connected to the output terminal of the first comparison unit. The second input terminal of the de-glitch circuit is electrically connected to the output terminal of the second comparison unit. The output terminal of the de-glitch circuit is electrically connected to the control terminal of the first switching device. The de-glitch circuit is used to output a control signal to the control terminal of the first switching device when the first signal output by the output terminal of the second comparison unit is a falling edge, so as to turn off the first switching device. The deburring circuit includes: a trigger unit, wherein the first input terminal of the trigger unit is the first input terminal of the deburring circuit, the second input terminal of the trigger unit is the second input terminal of the deburring circuit, the output terminal of the trigger unit is connected to the third input terminal of the trigger unit, and the trigger unit is used to trigger when the first signal is a falling edge and output a trigger signal; The filtering unit has a first input terminal electrically connected to the first input terminal of the trigger unit, a second input terminal connected to the output terminal of the trigger unit, and the output terminal of the filtering unit is the output terminal of the deburring circuit. The filtering unit is used to output the control signal when the edges of the second signal output by the first comparison unit and the trigger signal are opposite.

2. The digital display control buffer circuit according to claim 1, characterized in that, The triggering unit includes a first D flip-flop, which is triggered on a falling edge. The reset pin of the first D flip-flop is the first input terminal of the triggering unit, the CLK pin of the first D flip-flop is the second input terminal of the triggering unit, the D pin of the first D flip-flop is the third input terminal of the triggering unit, and the Q pin of the first D flip-flop is the output terminal of the triggering unit.

3. The digital display control buffer circuit according to claim 1, characterized in that, The triggering unit includes an inverter and a second D flip-flop. The second D flip-flop is triggered on the rising edge. The input terminal of the inverter is the second input terminal of the triggering unit. The output terminal of the inverter is electrically connected to the CLK pin of the second D flip-flop. The reset pin of the second D flip-flop is the first input terminal of the triggering unit. The D pin of the second D flip-flop is the third input terminal of the triggering unit. The Q pin of the second D flip-flop is the output terminal of the triggering unit.

4. The digital display control buffer circuit according to claim 1, characterized in that, The digital display control buffer circuit further includes an operational amplifier. The first comparison unit is a first comparator, the second comparison unit is a second comparator, the first switching device is a first NMOS transistor, the inverting input terminal of the first comparator is the first input terminal of the first comparison unit, the non-inverting input terminal of the first comparator is the second input terminal of the first comparison unit and is used to input a first reference signal, the output terminal of the first comparator is the output terminal of the first comparison unit, the inverting input terminal of the second comparator is the first input terminal of the second comparison unit, the non-inverting input terminal of the second comparator is the second input terminal of the second comparison unit and is used to input a second reference signal, the output terminal of the second comparator is the output terminal of the second comparison unit, the gate of the first NMOS transistor is the control terminal of the first switching device, the drain of the first NMOS transistor is the first terminal of the first switching device, the inverting input terminal of the operational amplifier is electrically connected to the output terminal of the operational amplifier and the source of the first NMOS transistor, the source of the first NMOS transistor is the second terminal of the first switching device, and the non-inverting input terminal of the operational amplifier is used to input a third reference signal.

5. The digital display control buffer circuit according to claim 1, characterized in that, The digital display control buffer circuit also includes: The second switching device has its control terminal electrically connected to the output terminal of the second comparison unit, its first terminal electrically connected to the first terminal of the first comparison unit, and its second terminal grounded.

6. The digital display control buffer circuit according to claim 5, characterized in that, The second switching device is a second NMOS transistor, the gate of the second NMOS transistor is the control terminal of the second switching device, the drain of the second NMOS transistor is the first terminal of the second switching device, and the source of the second NMOS transistor is the second terminal of the second switching device.

7. The digital display control buffer circuit according to claim 1, characterized in that, The digital display control buffer circuit also includes: The third comparator has an inverting input terminal for inputting a fourth reference signal, a non-inverting input terminal for inputting an upstream signal of the digital display control buffer circuit, and an output terminal for outputting a digital signal corresponding to the upstream signal.

8. A digital display control buffer device, characterized in that, include: The digital display control buffer circuit according to any one of claims 1 to 7.

9. The digital display control buffer device according to claim 8, characterized in that, The digital display control buffer device further includes: An upstream pull-down circuit includes a first impedance, a second impedance, and a third switching device. One end of the first impedance is used to connect to the upstream power supply. The other end of the first impedance is electrically connected to the first end of the third switching device and the first end of the second impedance. The other end of the first impedance is used to input an upstream signal to the digital display control buffer circuit. The other end of the second impedance and the second end of the third switching device are used to ground. The downstream pull-down circuit includes a third impedance, a fourth impedance, and a fourth switching device. One end of the third impedance is used to connect to the downstream power supply. The other end of the third impedance is electrically connected to the first end of the fourth switching device and the first end of the fourth impedance, respectively. The other end of the third impedance is used to input a downstream signal to the digital display control buffer circuit. The other end of the fourth impedance and the second end of the fourth switching device are used to ground.

Images