Voltage regulator device, corresponding method and data storage system

Abstract

This application relates to voltage regulator devices, corresponding methods, and data storage systems. In one embodiment, a device includes: a power node configured to receive a power supply voltage; an output node configured to provide an output voltage; a plurality of switching stages coupled to the power node and coupled to the output node; a sensing circuit coupled to the power node and configured to provide at least one sensing signal based on the power supply voltage; and a drive circuit coupled to the sensing circuit and the plurality of switching stages, wherein the drive circuit is configured to provide a drive signal based on the at least one sensing signal exceeding or not exceeding at least one reference voltage level and to selectively bypass a selected number of switching stages among the plurality of switching stages based on the drive signal, thereby changing the output voltage level at the output node.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Italian application No. 102022000006488, filed on 1 April 2022, which is incorporated herein by reference. Technical Field

[0003] This specification relates to voltage regulator devices. For example, one or more embodiments can be applied to charge pump devices. One or more embodiments can be applied to data storage systems, such as to generate a high operating voltage to program flash memory cells configured to store data. Background Technology

[0004] A charge pump circuit is a voltage regulator (or DC-DC converter) configured to receive a DC power supply voltage and includes a capacitor as an energy storage element to provide an output DC voltage that is higher or lower than the input DC power supply voltage.

[0005] Charge pump circuits are known, for example, from U.S. Patent No. 10038372.

[0006] In some cases, the power supply voltage can vary between low (e.g., about 1.55V) and high (e.g., about 3.6V).

[0007] A voltage regulator can be coupled to a varying load to provide an output DC voltage, allowing the intensity of the current flowing through the load to also vary. Depending on the type of load, the ripple of the output DC voltage may have a limited acceptable range.

[0008] A closed-loop control system can be coupled to a charge pump to regulate the output voltage provided therefrom.

[0009] Charge pump circuit design can involve worst-case scenarios, sizing the number of capacitors, their capacitance, and clock frequency, for example:

[0010] The input power supply voltage is at its minimum value.

[0011] The current in the load is expected to be at its maximum intensity.

[0012] The output voltage ripple has reached the maximum tolerance.

[0013] The temperature value is at the corner level of the worst-case scenario.

[0014] To match performance under these worst-case conditions (e.g., at low supply voltages), the charge pump circuit parameters may be too large.

[0015] As a result, the charge pump device may have an excessively large footprint, leading to excessive power consumption in operating scenarios that differ from the worst-case scenario.

[0016] In addition, existing solutions have one or more of the following drawbacks:

[0017] When operating in low-power mode, the non-negligible current consumption involved in the control of the current consumed by the pump is significant.

[0018] It is difficult to provide a system that can respond quickly to demands for high drive capability levels.

[0019] It is difficult to provide compatibility between the ramp / rate of change of the power supply voltage and the continuity of closed-loop control. Summary of the Invention

[0020] The embodiment provides reduced power consumption under the operating conditions of the charge pump circuit.

[0021] The embodiments may relate to flash memory systems and related methods.

[0022] One or more embodiments provide a way to adapt the parameters of a charge pump to operating conditions (e.g., power supply level, requested current, ripple).

[0023] For example, the solutions illustrated in this paper help reduce power consumption in voltage regulators such as charge pumps.

[0024] One or more embodiments help to align the power consumption in a regulator (or converter) device with the performance requirements of its specific application.

[0025] For example, one or more embodiments can help adapt converter performance to power supply voltage levels by changing several (e.g., charge pump) stages based on whether the sensed signal sensed at the charge pump stage exceeds or does not exceed a user-selectable threshold level.

[0026] One or more embodiments advantageously utilize a hysteresis comparator to filter noise on the power supply voltage.

[0027] For example, when the supply voltage has approximately the same characteristics as the comparator threshold, using a hysteresis comparator can promote energy saving by also offsetting the risk of continuous switching. Attached Figure Description

[0028] One or more embodiments will now be described by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0029] Figures 1-2 This is an example diagram of a charge pump circuit based on this disclosure;

[0030] Figure 3This is an example diagram of a clock generator in a charge pump circuit;

[0031] Figure 4 This is an example diagram of the control circuit according to this disclosure;

[0032] Figure 5 This is a diagram of a comparator circuit based on this disclosure;

[0033] Figure 6 It is a timing diagram of signals that can be used in one or more embodiments; and

[0034] Figures 7-12 These are example diagrams based on the principles of one or more alternative embodiments of this disclosure.

[0035] Unless otherwise stated, the corresponding numbers and symbols in different figures usually refer to the corresponding parts.

[0036] The accompanying drawings are provided to clearly illustrate relevant aspects of the embodiments, and the drawings are not necessarily drawn to scale.

[0037] The edges of features drawn in the attached figures do not necessarily indicate the end of the feature range. Detailed Implementation

[0038] In the following description, one or more specific details are shown to provide a thorough understanding of examples of embodiments described herein. Embodiments may be obtained without one or more specific details or by other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been detailed or described in order not to obscure certain aspects of the embodiments.

[0039] References to “embodiment” or “an embodiment” within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as “in an embodiment” or “in one embodiment” that may appear at one or more points in this specification do not necessarily refer to one and the same embodiment.

[0040] Furthermore, in one or more embodiments, a particular construction, structure, or feature may be combined in any suitable manner.

[0041] The accompanying diagram is a simplified version and is not drawn to scale.

[0042] Throughout the accompanying figures, similar parts or elements are indicated by similar reference numerals / numbers unless the context otherwise requires, and for the sake of brevity, the corresponding descriptions for each figure will not be repeated.

[0043] The reference numerals used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of embodiments.

[0044] For simplicity, the same reference symbols will be used in the following detailed description to indicate nodes / lines in the circuit and signals that may appear at those nodes or lines.

[0045] Voltage regulators or DC-DC converter devices (such as charge pumps) can have various circuit arrangements or topologies.

[0046] like Figure 1 As illustrated, the flash memory system FL includes a device 10, which includes a (e.g., Dickson type) charge pump circuit coupled to a corresponding pump regulator (or voltage regulator) 30.

[0047] As illustrated herein, a data storage system FL includes:

[0048] The power supply voltage source VDD is configured to provide the power supply voltage level VDD for reference ground GND.

[0049] like Figure 1 and Figure 2 The illustrated set of devices 10, 20 is configured to operate at a set of output nodes V based on the power supply voltage level VDD. OUT The corresponding set of output voltages V is provided at the location. OUT ,

[0050] A set of data storage units C L Z L It is coupled to the group of devices to receive a set of output voltages provided at the respective set of output nodes.

[0051] For example, one of the data storage units in the set of data storage units is configured to be programmed to store data via a set of received output voltages.

[0052] like Figure 1 As illustrated in , the device 10 includes:

[0053] The power node VDD is configured to be coupled to the power supply to receive the power supply voltage VDD.

[0054] Multiple charge pump stages 101, 10J, 10N, including, for example, cascaded charge pump stages coupled between them, are coupled to a power node VDD to receive a power supply voltage VDD therefrom, and based on the power supply voltage VDD, are coupled to the corresponding output node VDD. OUT The output voltage V is provided at the location. OUT ,

[0055] Load impedance C L Z L (Such as cells in flash memory FL), coupled to output node V OUT To receive the output voltage V from it OUT Load impedance C L Z L Including reactive components (e.g., capacitors) C L and load resistance Z L The load current I L Because the output voltage V OUT Applied to the load impedance C L Z L And flows into the load resistor Z L middle.

[0056] like Figure 1 As illustrated, the charge pump stages in the multiple charge pump stages 101, 10J, 10N include capacitor branches C1, C2, C3, C4, C5, C6, C7, C8, C9 ... j C N and switching transistors M1, M j M N The j-th switching transistor (e.g., M) in the j-th charge pump stage (e.g., 10J) j ) has been configured (e.g., via the j-th capacitor branch C) j The control node that receives the (digital or binary) clock signal CK, and the j-th switching transistor (e.g., M). j ) in the j-th charge pump stage (e.g., 10 J) and the j-th capacitor branch (e.g., C j ) and the (j+1)th charge pump stage (e.g., 10N) and the (j+1)th capacitor branch (e.g., C N There is a current path through which the two are configured to turn on or off in response to a clock signal CK received at their control node having a first (e.g., "1" or "high") or a second (e.g., "0" or "low") logic value.

[0057] For example, multiple switching transistors M1, M2, M3 in multiple charge pump stages 101, 10J, 10N j M N It can follow an "interleaved" pattern (which is known in itself), where the j-th switching transistor (e.g., M) j The control signal CK is received, and the adjacent switching transistors with indices (i-1) and (i+1) (e.g., M1 and M2) are connected. N ) Receive control signal CK inverted or out-of-phase version (For example, generated via inverter 12, such as...) Figure 1 exemplified in ).

[0058] like Figure 1 As illustrated, the multiple switching stages 101, 10J, 10N include: a first subset of the switching stages 101, 10N, including corresponding switching transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M1 ... N Switching transistors M1 and M N The first subset of the switching stage has a corresponding control node coupled to a first clock node CK to receive a first clock signal CK from it. The corresponding switching transistors in the first subset of the switching stage are configured to turn on and off their respective current paths based on the first clock signal CK received at the corresponding control node having a first or second logic value. The second subset 10J of the switching stage includes corresponding switching transistors M. j Switching transistor M j It has a coupling to the second clock node 12 to receive the second clock signal therefrom. The corresponding control node, the corresponding switching transistor in the second subset of the switching stage is configured based on the second clock signal received at the corresponding control node. It has a first or second logic value that turns the corresponding current path through it on or off. For example, the second clock signal is the inverse of the first clock signal.

[0059] In the exemplary scenario, the maximum output voltage level that the charge pump circuit can provide can be expressed as:

[0060]

[0061] Where VDD is the power supply voltage level, and N is the number of charge pump stages 101, 10J, and 10N.

[0062] Still within the exemplary scenario under consideration, with load resistance Z L The output current I flowing in L The intensity can be expressed as:

[0063]

[0064] Where fc is the frequency of the clock signal CK.

[0065] Still in the exemplary scenario under consideration, the current IDD dissipated in the power supply VDD is equal to the current supplied to the load Z. L Output current I L The relationship between them can be expressed as:

[0066] IDD=ηI L

[0067] Where η is the inefficiency factor and is proportional to the number N of charge pump stages 101, 10J, and 10N.

[0068] In various exemplary scenarios, the received power supply voltage level VDD can vary over a wide range of values. For example, regarding the regulated output voltage level VDD... OUT The setpoint value may be affected by significant variations in the power supply voltage level VDD, which may be lower than and / or higher than the output voltage level V. OUT The situation regarding the setpoint value.

[0069] One or more embodiments provide a method for adjusting the number N of stages / modules 101, 10J, 10N used in device 10 based on the input power supply voltage level VDD.

[0070] For example, in one application scenario, the number N of charge pump stages 101, 10J, 10N is selected in order to reduce (e.g., minimize) the current IDD dissipated in the power generator VDD.

[0071] like Figure 1 As illustrated, the charge pump circuit preferably includes a plurality of switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S1, S1, S1, S2, S3, S4 ...5, S6, S7, S8, S9, S1, S1, S1, S2, S3, S8, S9, S1, S1, S1, S2, S1, S1, S2, j S N (For example, the quantity is equal to the number N of levels 101, 10J, and 10N), multiple switches S1, S... j S N Coupled to multiple charge pump circuit stages (or modules) 101, 10J, 10N.

[0072] For example, the j-th switch (e.g., S) j ) is interposed between adjacent stages (e.g., 101, 10N) at indices (j-1) and (j+1), and with the corresponding j-th switching transistor (e.g., M). j ) in parallel, the j-th switch (e.g., S) j The control signal CTRL is configured to close or conduct in a first (e.g., "on") state and open or de-conduct in a second (e.g., "off") state in response to at least one control signal CTRL having a first or second value.

[0073] In one or more embodiments, the control signal CTRL can be a 1-bit or multi-bit digital signal.

[0074] For simplicity, the basic principles of the embodiments will be discussed below with reference to the 1-bit control signal CTRL; otherwise, it should be understood that such a number of bits is merely exemplary and by no means limiting.

[0075] For example:

[0076] When the control signal CTRL is asserted to have a first (e.g., "1" or "high") value, the j-th switch (e.g., S)j The circuit is closed to short-circuit the j-th charge pump stage (e.g., 10J), thereby disabling stage 10J and changing (e.g., from N to N-1) the number of effective charge pump stages 101, 10N in the charge pump circuit 10.

[0077] When the control signal CTRL is activated to have a second (e.g., "0" or "low") value, the j-th switch (e.g., S) j The charge pump circuit stage j is turned off in order to reactivate the j-th charge pump circuit stage (e.g., 10J), thereby increasing (e.g., from N-1 to N) and restoring the number of effective charge pump stages 101, 10J, 10N in the charge pump circuit 10.

[0078] As illustrated herein, at least one bit of the control signal CTRL can be activated to have a first (e.g., "1" or "high") or a second (e.g., "0" or "low") logic value based on whether the power supply voltage level VDD exceeds or does not exceed a certain threshold, as discussed below.

[0079] like Figure 1 As illustrated, the switching stages in the plurality of switching stages 101, 10J, 10N are arranged to have current paths passing through them, which are cascaded at the output node V of the device 10. OUT In the current line between the power node VDD and the power supply node.

[0080] The following mainly concerns what is used to selectively bypass the charge pump stage / module. Figure 1 or Figure 2 The switches S1 and S2 shown in the example j S N or S 1j S jN The arrangements are discussed to illustrate one or more embodiments. It should be noted that these arrangements are purely exemplary and not restrictive.

[0081] One or more embodiments can eliminate this switching arrangement. For example, in an alternative scenario, the drive signal CTRL can be provided directly to the charge pump stages 101, 10J, 10N to selectively bypass the corresponding charge pump modules among the multiple charge pump modules 101, 10J, 10N (e.g., using the control signal CTRL as an enable signal to turn the switchable charge pump stages or modules 101, 10J, 10N on / off).

[0082] like Figure 2 As illustrated, multiple charge pump stages (or modules) 101, 10i, 10N can be arranged to form an alternative charge pump circuit topology 20, wherein multiple charge pump modules 101, 10i, 10N are coupled between them, for example, stacked in parallel at the power node VDD and the output node V.OUT Between, thus at the power node VDD and the output node V OUT A current path is provided between them.

[0083] like Figure 1 As illustrated, the switching stages in the plurality of switching stages 101, 10J, 10N are arranged to have current paths through them, thereby at the output node V of device 20 OUT A corresponding current path is provided between the power node VDD and the power supply node.

[0084] exist Figure 2 In the alternatives illustrated herein, device 20 preferably includes a plurality of switches S 1j S jN (For example, the quantity is reduced by one relative to the number N of levels 101, 10J, 10N) and is configured to receive at least one control signal CTRL and multiple switches S. 1j S jN Interleaved between multiple charge pump circuit modules 101, 10J, and 10N, wherein multiple switches S 1j The j-th switch in (e.g., S) 1j The control signal CTRL is configured to, in response to (e.g., 1 bit) a control signal having a first (e.g., "1" or "high") or a second (e.g., "0" or "low") logic value, alternately close or turn on when in the first (e.g., "on") state and turn off or not turn on when in the second (e.g., "off") state.

[0085] For example, Figure 2 The multiple charge pump circuit modules 101, 10J, and 10N of the charge pump circuit 20 illustrated herein are respectively connected via clock signals CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8, CK9, CK1 ... J CK N (e.g., having corresponding clock phases) operate and work in parallel to (each) provide the load current I. L The corresponding part.

[0086] Still in the example under consideration, configuration 20 reduces the output voltage V by changing the number of operating charge pump stages 101, 10J, 10N. OUT The ripple on the circuit is a function of the power supply level VDD, for example:

[0087] - Change (e.g., reduce) the number of coupling levels in response to an increase in VDD, and / or

[0088] - Change (e.g., decrease) the clock signals CK1 and CK2. J CK N The clock frequency (or increasing the clock cycle), as mainly discussed below. Figures 7 to 12 The subject of discussion.

[0089] As illustrated in this document, at least one bit of the control signal CTRL can be activated to have a first or second logic value based on the power supply voltage level VDD being higher or lower than a certain threshold, as discussed below.

[0090] like Figure 1 and Figure 2 As illustrated, for a flash memory system FL, reducing power dissipation may be advantageous, wherein voltage regulator 10 can be used to regulate the load data units C of the memory system FL. L To do programming.

[0091] For simplicity, the principles of the solution illustrated herein are discussed primarily with reference to devices 10 and 20 comprising three levels 101, 10J, and 10N; otherwise, it should be understood that such a number of levels / modules 101, 10J, ... Figure 10 N is merely exemplary and by no means limiting, as theoretically any number greater than two charge pump stages / modules 101, 10J, 10N can be used. Figure 1 and Figure 3 As illustrated, the clock signal CK of devices 10 and 20 is generated via clock generator (or pump regulator) circuit block 30.

[0092] In one or more embodiments, the circuitry discussed in document US10038372B2 may be suitable as a clock generator circuit block 30 to generate a clock signal CK for charge pump circuits 10, 20.

[0093] like Figure 3 As illustrated, clock generator circuit block 30 includes:

[0094] Voltage divider 31 (e.g., including cascaded transistors Q0, Q1, Q2) j Q M ), coupled to the output node V of charge pumps 10 and 20 OUT To receive the output voltage V from it OUT And provide with output voltage V OUT Proportional feedback voltage V FB ,as well as

[0095] Dynamic comparator 32 (known in itself) includes a first input node V coupled to voltage divider 31. FB For example, coupled to its last Mth switching transistor Q M And is configured to receive the output voltage V of the charge pump circuit 10. OUT Proportional feedback signal V FB ,

[0096] Second input node V REFIt is configured to receive reference signal V REF For example, a reference voltage level V provided by the user or in a manner known to the user itself. REF ,

[0097] Synchronization Node S H It is configured to receive synchronization signal S H Comparator 32 is a dynamic comparator, which is configured to respond to the synchronization signal S. L The comparison result is output at the edge (e.g., rising edge or falling edge).

[0098] like Figure 3 As illustrated, comparator 32 is configured to perform on the sensed signal V FB and reference signal V REF The comparison between the two signals generates a clock signal CK as the result of the comparison, thereby providing a (e.g., Boolean) digital output whose logic value is based on the signal V input to comparator 32. FB V REF Is the difference between them positive or negative?

[0099] For example, the clock signal CK responds to the feedback signal V FB Exceeding the reference signal V REF And has a first (binary) value (e.g., "1"), and responds to the feedback signal V FB Not exceeding the reference signal V REF And has a second (binary) value (e.g., "0").

[0100] like Figure 3 As illustrated, comparator 32 only operates on the synchronization signal S. H The comparison is performed during the time interval when it is enabled to have a first logic value (e.g., "high"), so that the current consumption of comparator 32 is reduced relative to a comparator that operates in a continuous manner.

[0101] like Figure 4 As illustrated, control circuit 40 is configured to provide control signal CTRL (e.g., drive switches S1, S2). j S N S 1j S jN Or directly supplied to charge pump stages 101, 10J, 10N, so that their effective quantities can be adjusted sequentially) including:

[0102] Sensing circuit device 41 (e.g., including diode transistors D0, D1, D2 cascaded with a reference ground) j D MThe voltage divider 41) is coupled to the power node VDD of the charge pumps 10 and 20 to receive the power supply voltage VDD from it and to provide a set of sensing signals V based on the power supply voltage VDD. FB (For example, providing at least one sensing signal V) FB As at least a part of the power supply voltage VDD,

[0103] At least one comparator 50 includes a first input node V coupled to a voltage divider 41. 01 For example, the first diode D1 or the last diode D in the diode branch is coupled to the diode branch. N And is configured to receive the sensing signal V sensed at the node of voltage divider 41. 01 V jN For example, the first voltage level V at the diode node of the first diode D1 reference ground GND. 01 Or the Mth diode D N The second voltage level V at the diode node jM The hysteresis comparator 50 is configured to receive a reference voltage level (e.g., a first reference voltage level VT). 01 Or the second reference voltage level VT 02 The second input node VT 01 VT jN Comparator 50 is configured to perform sensing of signal V 01 V jN With reference voltage level VT 01 VT jN The comparison and the bit of the control signal CTRL are made. <0> CTRL <1> The numeric logical value takes effect (e.g., the first CTRL key). <1> Or the second CTRL <0> The value determines the charge pump stage or module 101, 10J, 10N (coupled to switches S1, S). N or S 1j S jN The on / off status of )

[0104] like Figure 4 As illustrated, the optional RC network circuits R and C are preferably inserted between the input power supply VDD and the voltage divider 41. The RC network R and C are configured to filter out any ripple that may exist on the power supply voltage VDD output by the power generator VDD (e.g., with the synchronization signal S). L The frequency of the voltage divider 41 is such that the filtered power supply voltage level VDDf is provided to the voltage divider 41; for example, the voltage drop across the resistor R of the RC network is very low because the current flowing in the (sufficiently sized) diode channel is very small.

[0105] like Figure 4As illustrated, comparator 50 also includes a synchronization signal S configured to receive the synchronization signal S. L Synchronization node S L The hysteresis comparator 50 is configured to perform on the sensed signal V 01 V jN With reference voltage level VT 01 VT jN The comparison between them is configured to be used with the synchronization signal S. L The edge (e.g., rising or falling edge) is in time with the output of the result, as discussed below.

[0106] By comparison Figure 3 and Figure 4 The synchronization signal S shown in the figure H S L As can be seen from the exemplary timing diagram, the synchronization signal S used to delay the hysteresis comparator 50 L The synchronization signal S of comparator 32 in clock generator circuit block 30 is used to delay the clock generator circuit block 30. H It has a lower frequency.

[0107] For example, synchronization signal S L The frequency is adapted to the specifications of the ramp change of the power supply voltage VDD (e.g., a low frequency of about 1-2 MHz filters noise and reduces power consumption to achieve a slower ramp change of the power supply voltage VDD over time, and a higher frequency is used to achieve a faster ramp change of the power supply voltage VDD over time), and is used to delay the synchronization signal S of comparator 32 in clock generator circuit block 30. H With a relatively higher frequency F H (For example, approximately 128MHz).

[0108] like Figure 4 As illustrated, the control circuit 40 includes multiple comparators 50, 501, such as:

[0109] The first (e.g., hysteretic) comparator 50 includes an Nth diode transistor D coupled to the voltage divider 41. N The first input node V jN To receive the first sensing signal V from it jN The first hysteresis comparator 50 has a configuration to receive a first reference voltage level VT jN The second input node VT jN The first hysteresis comparator 50 is configured to execute the first sensing signal V jN and the first reference voltage level VT jNThe comparison, and the first bit of the control signal CTRL is set to CTRL. <1> Effective, its value determines the charge pump circuit stages 101, 10J, 10N (coupled to switches S1, S...) j S N or S ij S jN The on / off status of ) and

[0110] The second (e.g., hysteresis) comparator 501 includes a first diode transistor D1 coupled thereto to receive a second sensing signal V. 01 The first input node V 01 The second hysteresis comparator 501 is configured to receive a second reference voltage level VT. 01 The second input node VT 01 The second hysteresis comparator 501 is configured to execute the second sensing signal V 01 Second reference voltage level VT 01 The comparison is performed, and the second bit of the control signal CTRL is set to CTRL. <0> Effective, its values ​​determine charge pump stages 101, 10J, 10N (coupled to second switches S1, S). j S N or S ij S jN The on / off status of )

[0111] In one or more exemplary cases, the number of comparators 50, 501 used in the control circuit 40 is determined independently of the number of charge pump stages 101, 10J, 10N in devices 10, 20.

[0112] For example, more than one module 101, 10J, 10N can be selectively bypassed via the same control signal CTRL (e.g., more than one switch S1, S2, S3, S4, S5, S6, S7, S8, S9, S1, S1, S1, S9, S1, S1, S1, S2 ...2, S1, S2, S2, S1, S2, S2, S2, S3, S1, S2, S2, S3, S2, S2, S3, j S N S 1j S 1N ).

[0113] For example, based on the threshold VT to be detected 01 VT jN The number of comparators 50 and 501 is selected based on the number of comparators.

[0114] In an exemplary case, for example, the number N of diodes in the voltage divider of the sensing circuit 41 is equal to the number of diodes in the voltage divider 31 in the clock generation circuit block 30.

[0115] Matching the number of diodes in sensing circuit 41 with the number of diodes in voltage divider 31 of pump regulator 30 helps to set the reference threshold VT. 01 VTjN One of them is the regulated output voltage V OUT Matching.

[0116] like Figures 1 to 4 As illustrated in , the devices 10, 20 include:

[0117] The power node VDD is configured to be coupled to a power supply voltage source to receive the power supply voltage VDD from it.

[0118] Output node V OUT It is configured to supply power to the load circuit C based on the power supply voltage. L Z L Provide output voltage V OUT ;

[0119] Multiple switching stages 101, 10J, and 10N are coupled to a power node to receive a power supply voltage from it and are coupled to an output node to provide an output voltage to it.

[0120] Sensing circuit 41 is coupled to power node VDD to sense at least one sensing signal V based on power supply voltage VDD. 01 V jN ,as well as

[0121] The drive circuits 40 and 100 are coupled to the sensing circuit to receive at least one sensing signal and are coupled to multiple switching stages to provide the drive signal CTRL. For example, the drive circuits are configured as follows:

[0122] Based on at least one sensing signal V 01 V jN Exceeding or not exceeding at least one reference voltage level VT 01 VT jN This generates drive signals 50 and 501, and

[0123] By selectively bypassing a selected number of switching stages from multiple switching stages based on the drive signal CTRL, the output voltage level V supplied to the output node is changed. OUT .

[0124] like Figure 1 or Figure 2 As illustrated, the device also includes multiple bypass switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S1, S1, S2, S1, S2, S3, S4 ...1, S2, S3, j S N S 1j S jN .For example:

[0125] The bypass switches in a plurality of bypass switches include a corresponding control node configured to receive a drive signal, and a corresponding current path through which the bypass switches are configured to be turned on or off based on the drive signal.

[0126] Based on the drive signal, the current path of the bypass switch among the plurality of bypass switches is turned on to selectively bypass the selected number of switch stages among the plurality of switch stages, and

[0127] The output voltage level supplied to the output node varies depending on the selected number of switch stages among the multiple switch stages that are bypassed.

[0128] In one or more exemplary cases, the comparators 50, 501 in the drive circuit 40 include a dynamic comparator 32, as described above (see main reference). Figure 3 As discussed in the article.

[0129] In an alternative exemplary embodiment, comparators 50, 501 in control circuit 40 include hysteresis comparators, as follows (see main reference). Figure 5 As discussed above. For example, when the supply voltage VDD has a voltage level close to (one or more) threshold voltage levels VT. 01 VT jN When the voltage level is VDD, this helps to reduce or avoid continuous switching of the charge pump circuit 10.

[0130] like Figure 5 As illustrated, the hysteresis comparator 50 includes:

[0131] The first transistor pair (e.g., matched) T1, T2 includes transistors configured to receive (e.g., a first V) jN The first transistor T1 of the control node for sensing signals and having a transistor configured to receive (e.g., the first VT) jN The second transistor T2 is a control node with a reference voltage level. The first transistor T1 and the second transistor T2 have a common (e.g., source) node therebetween, which is coupled to a synchronization signal S. L Controlled switch bias current generator T0,

[0132] The second transistor pair T3, T4 includes a third transistor T3 and a fourth transistor T4. The third transistor T3 has a corresponding control node coupled to the control node of the first transistor T1, and the fourth transistor T4 has a corresponding control node coupled to the control node of the second transistor T2. The third transistor T3 and the fourth transistor T4 have a common (e.g., source) node therebetween, and this common node is coupled to the common node of the first transistor T1 and the second transistor T2 in the first transistor pair T1, T2.

[0133] A first balancing switch T5 is coupled to a first transistor T1 and a third transistor T3, and is configured to selectively couple between corresponding transistor nodes based on a control signal Q received at the corresponding control node of the first switch T5.

[0134] The second balancing switch T6 is coupled to the second transistor T2 and the fourth transistor T4, and is configured to operate based on the bias signal V received at the corresponding control node of the second switch T6. BIAS To couple the corresponding transistor nodes between them.

[0135] The third switch T56 is coupled to the first switch T5 and the second switch T6, and is configured to work with the synchronization signal S. L The signal edges selectively connect to the corresponding current paths passing through them in sync.

[0136] A set of inverter circuits 501, 502, and 503 are coupled to a pair of first and second transistors T1 and T2, and are configured to provide an input signal V. jN VT jN Comparison results between (e.g., CTRL) <1> The first inverter pair 501 and 502 are opposite each other and configured to provide a latch comparator, and the third inverter 503 is configured to correct the comparison signal CTRL. <1> Signal polarity,

[0137] A pair of coupling switches T7 and T8 are coupled to the power node VDD. This bias switch pair includes a first coupling transistor T7 coupled to a first transistor T1 and a second coupling transistor T8 coupled to a second transistor T2, wherein the first coupling transistor T7 and the second coupling transistor T8 are configured to... L When a second logic value is present (e.g., "0" or ground), it is switched on to preset both sides of the comparison signal output to VDD, and when the synchronization signal S... L When a first logic value (e.g., "1" or VDD) is present, it is switched off and comparator 50 is turned on.

[0138] Sequential logic circuit 504, coupled to inverter groups 501, 502, and 503 and to a first switch T5, is configured to receive a compare signal (e.g., CTRL). <1> And via synchronization signal S L The timing is used to output the drive signal Q for the first switch T5 of comparator 50.

[0139] like Figure 5As illustrated, transistors T3 and T4 in the second transistor pair T3, T4 can be scaled replicas of the corresponding transistors in the first matched transistor pair T1, T2. For example, T3 and T4 can have twice the size of the first transistor T1, which is equal to the size of the second transistor T2.

[0140] like Figure 5 and Figure 6 As illustrated, the hysteresis behavior of the hysteresis comparator 50 is related to the synchronization signal S. L The result of dynamically changing the state of the input stage of comparator 50 in sync with the synchronization signal S L The period determines the duration of each state or phase.

[0141] like Figure 6 As illustrated in the example, the driving signal Q has an output signal CTRL in the phase preceding the phase under consideration. <1> The value of .

[0142] like Figure 6 For example, as shown in the examples:

[0143] At the first moment K0, the synchronization signal S is... L The first (e.g., rising) edge, the first sensing signal V jN The rising voltage exceeds the second reference voltage level VT jN As a result, comparator 50 outputs a comparison result CTRL with a first (e.g., "1" or "high") logic value. <1> Meanwhile, the drive signal Q, having retained the memory of the comparison result, has a second (e.g., "0" or "low") logic value, causing the first balance switch T5 to turn off (that is, to be disconnected and not conducting).

[0144] The synchronization signal S following the first time K0 at the second time K1. L During the period, compare the signal CTRL <1> The signal is reset, and its logic value is "stored" in Q, which is then updated and becomes equal to the first (e.g., "1" or "high") logic value. The updated value of the drive signal Q turns on the first switch, causing the first transistor pair T1, T2 and the second transistor pair T3, T4 to form a balanced differential amplifier that operates as a balanced comparator. Its threshold value is equal to the reference value (e.g., the first reference value VT) input at the control node of the second transistor T2. jN ).

[0145] like Figure 6 As illustrated, this process does not work perfectly symmetrically when the input signal is decreasing. For example:

[0146] At the third moment K2, corresponding to the synchronization signal S L The first (e.g., rising) edge, the first sensing signal VjN The voltage drop is equal to (i.e., does not exceed) the second reference voltage level VT. jN As a result, comparator 50 outputs a comparison result CTRL with a second (e.g., "0" or "low") logic value. <1> Meanwhile, the drive signal Q maintains a first logic value (such as "1" or "high"), so that the first balance switch T5 remains on (i.e. closed and conducting).

[0147] At time 4, K3, the synchronization signal S follows time 3, K2. L During the period, compare the signal CTRL <1> The value is reset, and its logic value is "stored" in Q, which is updated and thus becomes equal to the second (e.g., "0" or "low") logic value; the updated value of the drive signal Q turns off the first switch T5, causing the first transistor pair T1, T2 and the second transistor pair T3, T4 to form an unbalanced comparator circuit, the threshold for which it operates is equal to the reference value plus the input stage (e.g., VT). jN The offset Δ caused by the imbalance.

[0148] like Figure 5 and Figure 6 As illustrated, comparator 50 is hysteretic because the output comparator signal CTRL... <1> Not only considering the input sensing signal V jN Does it exceed or not exceed the reference voltage VT? jN Furthermore, it also considers whether it has undergone an evolution that increases or decreases over time.

[0149] As illustrated in this article, at least one sensing signal V 01 V jN It has a time-varying ramp; the drive circuit is configured to detect at least one sensing signal V from 504. 01 V jN Whether the time-varying ramp rises or falls over time, and generate 50, 501 drive signals CTRL based on whether at least one sensing signal exceeds or does not exceed at least one reference voltage level and based on the detected rise or fall of the time-varying ramp over time based on at least one sensing signal.

[0150] like Figure 4 As illustrated, the sensing circuit 41 includes an integer number N of sensing circuit stages D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D1 ... j D N They are cascaded in the current path between the power node VDD and ground GND. For example, the sensing circuit 41 is configured as follows:

[0151] The first sensing signal V is sensed at node D0 of the first sensing circuit stage in the sensing circuit stage. jN As the first part of the power supply voltage VDD, and

[0152] The Nth sensing circuit level D in the sensing circuit level N The second sensing signal V is sensed at the node. jN As the second part of the power supply voltage.

[0153] like Figure 4 As illustrated, the drive circuit includes:

[0154] The first comparator 50 is configured to: respond to a first sensing signal exceeding a first reference threshold VT jN And generate a first comparison signal CTRL with a first logic value. <0> And in response to the first sensing signal not exceeding the first reference threshold, a first comparison signal CTRL with a second logic value is generated. <0> ;

[0155] The second comparator 501 is configured to respond to the second sensing signal V 01 Exceeding the second reference threshold VT 01 This generates a second comparison signal CTRL with a first logic value. <1> And in response to the second sensing signal not exceeding the second reference threshold, a second comparison signal CTRL with a second logic value is generated. <1> ,as well as

[0156] Combinational logic 42 is configured as the first comparison signal CTRL in a logical combination. <0> Second comparison signal CTRL <1> This provides the drive signal CTRL as the result of logic combination 42.

[0157] like Figures 4 to 6 As illustrated, the driving circuit includes: a first comparator 50 configured to detect a first time-varying ramp of a first sensing signal, and configured to respond to the first sensing signal exceeding a first reference threshold VT. jN Furthermore, the detected first time-varying ramp increases over time, generating a first comparison signal CTRL with a first logic value. <0> In response to the first sensing signal V jN The first reference threshold VT was not exceeded. jN And the first comparison signal CTRL with a second logic value is generated by the detected first time-varying ramp decreasing over time. <0> The second comparator 501 is configured to detect a second time-varying ramp of the second sensing signal and is configured to respond to the second sensing signal exceeding a first reference threshold VT. 01 And the detected second time-varying ramp generates a second comparison signal CTRL with a first logic value as it rises over time. <1> In response to the second sensing signal V jNThe second comparison signal CTRL, which has a second logic value, is generated as the detected second time-varying ramp decreases over time and does not exceed the first reference threshold. <1> ; and combinational logic 42, configured to logically combine a first comparison signal and a second comparison signal, thereby providing a drive signal CTRL as the result of its logical combination.

[0158] For example, the drive signal CTRL is a multi-bit digital signal that includes the least significant bit equal to the second comparison signal and the most significant bit equal to the first comparison signal.

[0159] As illustrated herein, the device includes an RC network R, C located between the power node VDD and the sensing circuit 41. The RC network is configured to receive the power supply voltage level VDD from the power node, apply filtering to it, and then provide the filtered power supply voltage level VDDf to the sensing circuit 41.

[0160] like Figure 4 As illustrated, the control signal CTRL is achieved by combining (e.g., in combinational circuit block 42) a 1-bit signal CTRL. <0> CTRL <1> The resulting digital signal, 1-bit signal CTRL <0> CTRL <1> The output of the hysteresis comparator 50 is used (e.g., by driving switches S1 and S2) N or S ij S jN Selectively bypass the charge pump stages 101, 10J, and 10N of devices 10 and 20.

[0161] For example, at the first reference voltage level VT jN Greater than the second reference voltage level VT 01 In an exemplary scenario, combinational logic 42 can combine control signal bits CTRL. <0> CTRL <1> , so that:

[0162] When the (filtered) power supply voltage levels VDD and VDDf are lower than the second reference voltage level VT 01 (e.g., VDD) <VT 01 When ), the control signal CTRL = CTRL<1:0> = 00.

[0163] When the (filtered) power supply voltage levels VDD and VDDf are lower than the first reference voltage level VT jN And higher than the second reference voltage level VT 01 (For example, VT) 01 <VDD<VT jN When ), the control signal CTRL = CTRL<1:0> = 01.

[0164] When the (filtered) power supply voltage levels VDD and VDDf are higher than the first reference voltage level VTjN (For example, VDD>VT) jN When ), the control signal CTRL = CTRL<1:0> = 11.

[0165] like Figure 1 , Figure 2 and Figure 4 As illustrated in the example, based on the use of Figure 4 The control circuits 40 and 42 illustrated herein are obtained and implemented to Figure 1 The control signal CTRL in the control circuit 100 illustrated herein can be selectively activated / deactivated. Figure 1 The charge pump circuit 10 (or) illustrated in the figure Figure 2 The charge pump circuit 20 illustrated herein has one or more stages 101, 10J, 10N (e.g., for charging switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S1, S1, S9, S1, S1, S9, S1, S1, S1, S2 ... j S N S 1j S jN Provide the drive signal CTRL or directly provide the drive signal CTRL to stages 101, 10J, and 10N of devices 10 and 20.

[0166] Note that more than two comparators 50 can be used and more than two reference voltage levels VT can be selected. 01 VT jN Various finer or coarser methods are used to implement the adjustment of the number of N stages / modules 101, 10J, 10N of the charge pump circuits 10, 20.

[0167] For example, the third comparator can be the diodes D0, D1, and D2 in the voltage divider 41 of the control circuit 40. j D N Another sensing signal is sensed at any point between them.

[0168] like Figures 7 to 12 As illustrated, when the charge pump includes a "bundle" arrangement 20, the control circuit 100 can also be configured to drive clock signals CK1 and CK2. J CK N The clock cycle varies in response to changes in the input voltage VDD.

[0169] like Figure 7 As illustrated, in the exemplary case of a charge pump 20 comprising three charge pump stages 101, 10J, and 10N, in the "worst-case" scenario where VDD is at its minimum, the control circuit 100 drives the switch S. 1j S jN All charge pump stages 101, 10J, and 10N are coupled in parallel at the input node VDD and the output node V. OUTBetween. For example, in such an exemplary scenario, at load Z L The load current I flowing in L It is the sum of the currents I1, I2, and I3 supplied by each charge pump stage 101, 10J, and 10N. For example, the current supplied by each charge pump stage is a small fraction of the output current, such as I1 = I2 = I3 = I L / N

[0170] like Figure 8 As illustrated, in such a configuration, control circuit 100 drives (e.g., simultaneously) switch S 1j S jN The states of clock signals CK1, CK2, and CK3 have the same period T (e.g., provided by the master clock embedded in the control circuit 100).

[0171] like Figure 8 As illustrated in the example, the output voltage may experience ripple V. R .

[0172] like Figure 9 and Figure 10 As illustrated, in response to at least one sensing signal V 01 V jN Exceeding or not exceeding at least one reference voltage level VT 01 VT jN (For example, because the input signal changes from a minimum value to a maximum value, as in the "optimal" scenario), the control circuit 100 selectively bypasses a selected number of charge pump stages (e.g., two stages 10J and 10N in the considered example) based on the drive signal CTRL, thereby changing the supply to the output node V. OUT Output voltage level V OUT .

[0173] like Figure 10 As illustrated, decoupling the charge pump stages 10J and 10N results in a voltage ripple V on the output voltage VOUT. R The decrease of ', for example, relative to the amplitude V R For example, the decoupling stages 10J and 10N do not contribute to the output current, and therefore they are not powered by any clock, while the output current I... L It is entirely supplied by the current provided by the first stage I1.

[0174] like Figure 11 As illustrated in the example, as Figure 9 An alternative to the exemplary case is, in response to at least one sensing signal V 01 V jN Exceeding or not exceeding at least one reference voltage level VT 01 VT jN(For example, because the input signal changes from a minimum to a maximum value, as in the "optimal" scenario), the control circuit 100 selectively bypasses a selected number of charge pump stages (e.g., the last stage 10N in the considered example) and reduces the clock signals CK1, CK2 of the stages 101, 10J that maintain coupling, based on the drive signal CTRL. J The period of V is thus changed, thereby altering the supply provided to the output node V. OUT Output voltage level V OUT .

[0175] like Figure 12 As illustrated, the charge pump stage 10N is decoupled and the clock signals CK1 and CK2 are changed. J The period T (e.g., obtaining a larger period T', T' being, for example, twice the initial period T) leads to the same Figure 11 The reduction shown is equivalent to the reduction in output voltage V. OUT Voltage ripple V R The decrease of '.

[0176] like Figure 11 As illustrated in the example, regarding Figure 10 The solution, with more stages connected to the output node, allows the current supplied by each stage (101, 10J) to have a lower intensity, for example, I1 = I j =I L / 2 L .

[0177] As illustrated in this document, the switching stages in the multiple switching stages 101, 10J, 10N are configured to respond to corresponding clock signals CK1, CK2, CK3 with corresponding clock periods. J CK N The system switches to the first state at the first edge of the clock signal and responds to the corresponding clock signals CK1 and CK2 with the corresponding clock cycle. J CK N The second edge switches to the second state, wherein the drive circuits 40 and 100 are configured to, based on the drive signal CTRL:

[0178] Based on the selected number of switch stages, the period of the corresponding clock signal of the switch stage among the plurality of switch stages is changed and a phase shift is applied to it.

[0179] As a result, the output voltage level V supplied to the output node of the device was changed. OUT (Specifically, voltage ripple V) R ).

[0180] As illustrated herein, the operating device 20 includes:

[0181] ​At least one sensing signal V is sensed based on the power supply voltage VDD. 01 V jN ;

[0182] Based on the at least one sensing signal V 01 V jN Exceeding or not exceeding at least one reference voltage level VT 01 VT jN To generate the drive signal CTRL described in 50;

[0183] Based on the drive signal CTRL:

[0184] Selectively bypassing 40, 100 in the selected number of switch stages 101, 10J, 10N; and

[0185] The period of the clock signal supplied to one of the plurality of switch stages 101, 10J, 10N is varied according to the selected number of switch stages (e.g., by multiplying the period by the number of remaining stages that are not selectively bypassed).

[0186] The clock signals supplied to the multiple switch stages 101, 10J, and 10N are phase-shifted so that they are out of phase (or quadrature) among them.

[0187] As a result, the output voltage level V supplied to the output node of the device was changed. OUT (Specifically, voltage ripple V) R ).

[0188] For simplicity, the preceding discussion has focused primarily on the use of capacitors C1 and C2. j C N Devices 10 and 20 serve as energy storage elements (i.e., charge pumps) in corresponding levels 101, 10J, and 10N. This type of energy storage element is merely exemplary and not limiting. One or more embodiments may also be applied to devices using other reactive elements as energy storage elements, such as inductors or combinations of inductors and capacitors.

[0189] It will also be understood that the various individual implementation options illustrated in the accompanying drawings are not necessarily intended to be employed in the same combinations illustrated in the drawings. Therefore, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations relative to the combinations illustrated in the drawings.

[0190] Without prejudice to the fundamental principles, details and embodiments may vary, even significantly, relative to what has been described by way of example only, without departing from the scope of protection. The scope of protection is defined by the appended claims.

Claims

1. An apparatus comprising: The power node is configured to receive the power supply voltage. An output node is configured to provide an output voltage to a load circuit, the output voltage being based on the power supply voltage; Multiple switching stages are coupled to the power node and the output node; A sensing circuit is coupled to the power node and configured to provide at least one sensing signal based on the power supply voltage; as well as The driver circuit is coupled to the sensing circuit and the plurality of switching stages. The driving circuit is configured to receive the at least one sensing signal and to provide driving signals to the plurality of switching stages. The driving circuit is further configured to: The drive signal is provided based on whether the at least one sensing signal exceeds or does not exceed at least one reference voltage level, and The output voltage level at the output node is changed by selectively bypassing a selected number of switching stages from the plurality of switching stages based on the drive signal.

2. The apparatus of claim 1, wherein the plurality of switching stages includes a current path cascaded in the current line between the power supply node and the output node.

3. The apparatus of claim 1, wherein the plurality of switching stages include current paths to provide a current line between the power supply node and the output node.

4. The apparatus according to claim 1, further comprising: Multiple bypass switches are coupled to the multiple switch stages and to the drive circuit. The plurality of bypass switches include: a corresponding control node configured to receive the drive signal, and a corresponding current path through which it is configured to be turned on or off based on the drive signal. The current paths of the plurality of bypass switches are turned on based on the drive signal to selectively bypass the selected number of switch stages among the plurality of switch stages, and The output voltage level provided to the output node varies according to the selected number of switch stages among the plurality of bypassed switch stages.

5. The apparatus of claim 1, further comprising a plurality of bypass switches coupled to the plurality of switch stages and coupled to the driver circuit.

6. The apparatus of claim 5, wherein the bypass switch includes a control node configured to receive the drive signal and the current path, and wherein the bypass switch is configured to turn the current path on or off based on the drive signal.

7. The apparatus of claim 6, wherein the output voltage level varies according to the selected number of switching stages among the plurality of switching stages.

8. The apparatus according to claim 1, The at least one sensing signal has a time-varying ramp, and The driving circuit is configured as follows: Detecting whether the time-varying slope of the at least one sensing signal rises or falls over time, and The drive signal is provided based on whether the at least one sensing signal exceeds or does not exceed the at least one reference voltage level, and based on the detected rise or fall of the time-varying ramp over time of the at least one sensing signal.

9. The apparatus according to claim 1, The sensing circuit includes an integer number N sensing circuit stages cascaded in the current line between the power node and ground, and The sensing circuit is configured as follows: A first sensing signal is sensed at a node of the first sensing circuit stage in the sensing circuit stage as a first part of the power supply voltage, and A second sensing signal is sensed at a node of the Nth sensing circuit stage in the sensing circuit stage as a second part of the power supply voltage.

10. The apparatus of claim 9, wherein the driving circuit comprises: A first comparator is configured to: provide a first comparison signal having a first logic value in response to the first sensing signal exceeding a first reference threshold, and provide a first comparison signal having a second logic value in response to the first sensing signal not exceeding the first reference threshold. The second comparator is configured to: provide a second comparison signal having a first logic value in response to the second sensing signal exceeding a second reference threshold, and provide the second comparison signal having a second logic value in response to the second sensing signal not exceeding the second reference threshold. Combinational logic is configured to logically combine the first comparison signal and the second comparison signal to provide the drive signal.

11. The apparatus of claim 9, wherein the driving circuit comprises: The first comparator is configured as follows: The first time-varying slope for detecting the first sensing signal, and In response to the first sensing signal exceeding a first reference threshold and the detected first time-varying ramp increasing over time, a first comparison signal with a first logic value is provided; in response to the first sensing signal not exceeding the first reference threshold and the detected first time-varying ramp decreasing over time, a first comparison signal with a second logic value is provided. The second comparator is configured as follows: The second time-varying ramp that detects the second sensing signal, and In response to the second sensing signal exceeding the first reference threshold and the detected second time-varying ramp rising over time, a second comparison signal with a first logic value is provided; in response to the second sensing signal not exceeding the first reference threshold and the detected second time-varying ramp falling over time, a second comparison signal with a second logic value is provided. as well as Combinational logic is configured to logically combine the first comparison signal and the second comparison signal to provide the drive signal.

12. The apparatus of claim 11, wherein the drive signal is a multi-bit digital signal, the multi-bit digital signal comprising the least significant bit equal to the second comparison signal and the most significant bit equal to the first comparison signal.

13. The apparatus of claim 1, wherein the plurality of switching stages include respective switching transistors coupled to respective energy storage elements, and wherein the energy storage element includes a capacitor having respective capacitances having the same capacitance value.

14. The apparatus of claim 1, wherein the plurality of switching stages comprises: A first subset of the switching stage includes a switching transistor having a control node coupled to a first clock node to receive a first clock signal, wherein the switching transistor in the first subset of the switching stage is configured to turn on and off the current path through the switching transistor in the first subset of the switching stage based on the first clock signal received at the control node having a first logic value or a second logic value. as well as A second subset of the switching stage includes switching transistors having control nodes coupled to a second clock node to receive a second clock signal. The switching transistors in this second subset are configured to turn on and off the current path through the switching transistors based on whether the second clock signal received at the corresponding control node has a first or a second logic value. The second clock signal is the inverse of the first clock signal.

15. The apparatus of claim 1, wherein the plurality of switching stages are configured to switch to a first state in response to a first edge of a corresponding clock signal having a corresponding clock period, and to switch to a second state in response to a second edge of a corresponding clock signal having a corresponding clock period.

16. The apparatus of claim 15, wherein the driving circuit is further configured to: change the period of the corresponding clock signals of the plurality of switching stages and apply a phase shift to the corresponding clock signals of the plurality of switching stages based on the driving signal and according to the selected number of switching stages, thereby changing the output voltage level at the output node.

17. A method for operating the apparatus according to claim 1, the method comprising: The at least one sensing signal is sensed based on the power supply voltage; The drive signal is provided based on whether the at least one sensing signal exceeds or does not exceed the at least one reference voltage level; as well as The output voltage level at the output node is changed by selectively bypassing a selected number of switching stages from the plurality of switching stages based on the drive signal.

18. The method according to claim 17, The at least one sensing signal has a time-varying slope, and The method further includes: Detecting whether the time-varying slope of the at least one sensing signal rises or falls over time, and The drive signal is provided based on whether the at least one sensing signal exceeds or does not exceed the at least one reference voltage level, and based on the detected rise or fall of the time-varying ramp over time of the at least one sensing signal.

19. A data storage system, comprising: A power supply voltage source is configured to provide a power supply voltage level; A set of devices, each device being the device according to claim 1, The set of devices is configured to provide a set of output voltages at a set of output nodes based on the power supply voltage level; as well as A set of data storage units is coupled to the set of devices and configured to receive the set of output voltages, and The data storage unit in the set of data storage units is configured to be programmed to store data via the received set of output voltages.

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