Pixel readout circuit and imaging system

Abstract

The present disclosure relates to re-stabilization timing for low power pixel readout. A pixel readout circuit includes an analog-to-digital converter coupled to a bit line output of the pixel circuit. A switch is coupled between the bit line output of the pixel circuit and a reference voltage. The switch is pulsed on and off a first time to stabilize the bit line to the reference voltage prior to an auto-zero operation of the analog-to-digital converter. The switch is pulsed on and off a second time to stabilize the bit line to the reference voltage after the auto-zero operation and prior to a first analog-to-digital conversion. The switch is configured to be pulsed on and off a third time to stabilize the bit line to the reference voltage after the first analog-to-digital conversion operation and prior to a second analog-to-digital conversion operation.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to image sensors, and in particular, but not exclusively, to reading out image sensors through column bit lines. BACKGROUND

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, surveillance cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, etc. in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design as well as image acquisition processing. The technology for manufacturing image sensors continues to evolve at a rapid pace. For example, the demand for higher resolution and lower power consumption has encouraged further miniaturization and integration of these devices.

[0003] A typical complementary metal-oxide-semiconductor (CMOS) image sensor operates in response to image light from an external scene being incident on the image sensor. The image sensor includes an array of pixels having a photosensitive element (e.g., a photodiode) that absorbs incident image light and generates image charge after absorbing the image light. The image charge generated by the pixel can be measured as an analog output image signal on a column bit line that varies in accordance with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out from the column bit line as an analog signal and converted to a digital value to produce a digital image (i.e., image data) representative of the external scene. SUMMARY

[0004] One aspect of the present disclosure relates to a pixel readout circuit comprising: an analog-to-digital converter coupled to a bit line output of the pixel circuit; and a switch coupled between the bit line output of the pixel circuit and a reference voltage, wherein the switch is configured to be pulsed on and off a first time to stabilize a bit line to the reference voltage before an auto-zero operation of each readout of the pixel circuit by the analog-to-digital converter, wherein the switch is configured to be pulsed on and off a second time to stabilize the bit line to the reference voltage after the auto-zero operation and before a first analog-to-digital conversion operation of each readout of the pixel circuit by the analog-to-digital converter, wherein the switch is configured to be pulsed on and off a third time to stabilize the bit line to the reference voltage after the first analog-to-digital conversion operation and before a second analog-to-digital conversion operation of each readout of the pixel circuit by the analog-to-digital converter.

[0005] Another aspect of the disclosure relates to an imaging system, comprising: a pixel array including a plurality of pixel circuits; a readout circuit coupled to the pixel array by a plurality of bit lines, wherein the readout circuit includes a plurality of pixel readout circuits coupled to the plurality of bit lines, wherein each of the plurality of pixel readout circuits comprises: an analog-to-digital converter coupled to one of the plurality of bit lines to read out image data from a pixel circuit output of the one of the plurality of pixel circuits coupled to the one of the plurality of bit lines; and a switch coupled to the one of the plurality of bit lines between the pixel circuit output and a reference voltage, wherein the switch is configured to be pulsed on and off a first time to stabilize the one of the plurality of bit lines to the reference voltage before an auto-zero operation of each readout of one of the plurality of pixel circuits by the analog-to-digital converter, wherein the switch is configured to be pulsed on and off a second time to stabilize the one of the plurality of bit lines to the reference voltage after the auto-zero operation and before a first analog-to-digital conversion operation of each readout of the one of the plurality of pixel circuits by the analog-to-digital converter, wherein the switch is configured to be pulsed on and off a third time to stabilize the one of the plurality of bit lines to the reference voltage after the first analog-to-digital conversion operation and before a second analog-to-digital conversion operation of each readout of the one of the plurality of pixel circuits by the analog-to-digital converter. BRIEF DESCRIPTION OF DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0007] Figure 1 One example of an imaging system including a pixel array coupled to a readout circuit by bit lines in accordance with the teachings of this disclosure is described.

[0008] Figure 2 One example of a pixel circuit included in a pixel array coupled to an example readout circuit by bit lines in accordance with the teachings of this disclosure is described.

[0009] Figure 3 One example of a timing diagram for an example readout circuit configured to read out a pixel circuit by bit lines in accordance with the teachings of this disclosure is described.

[0010] Corresponding reference numerals indicate corresponding components throughout the several figures of the drawings. It will be understood that the elements of the figures are illustrated for simplicity and clarity and that typically, numerous other elements are commonly present in commercial and industrial settings. However, because these elements are well known in the art, they are not depicted in the figures to avoid obscuring the inventive aspects as described herein. Further, numerous methodologies are contemplated for implementing the inventive concepts described herein. DETAILED DESCRIPTION

[0011] Described herein relate to imaging systems that include a pixel array of pixel circuits coupled to readout circuitry by bit lines. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the technology described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of certain aspects.

[0012] Reference throughout this specification to "one example" or "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, appearances of the phrases "in one example" or "in one embodiment" or "in at least one example" or "in at least one embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more examples.

[0013] For ease of description, spatial terms, such as "below", "under", "above", "over", "on", "top", "bottom", "left", "right", "centre", "intermediate", and the like, can be used herein to describe a relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device is turned over or rotated by ninety degrees, a downward dependency described as "below" or "under" another element or feature would then be oriented upwards or over the other element or feature. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 180 degrees, or rotated in other orientations) and the spatially relative descriptors used herein interpreted accordingly. Furthermore, it will be understood that when an element is referred to as being "between" two other elements, it can be the only element between the two other elements or one or more other elements can also be present between the two other elements.

[0014] Throughout this specification, several terms of art in the imaging field are used. These terms are intended to have their ordinary meaning to one skilled in the art from which the term is from, unless otherwise expressly defined herein or the context of their use clearly dictates otherwise. It is noted that element names and symbols can be used interchangeably throughout this document (e.g., Si for silicon); however, both have the same meaning.

[0015] As will be discussed, an imaging system is described that includes a pixel array of pixel circuits coupled to a readout circuit through bit lines. In various examples, the readout circuit includes a plurality of pixel readout circuits coupled to pixel circuits in the pixel array through bit lines. In various examples, a pixel readout circuit includes an analog-to-digital converter coupled to a bit line output of a pixel circuit through a bit line. A bias current source is coupled between the bit line output of the pixel circuit and ground. A switch is coupled between the bit line output of the pixel circuit and a reference voltage. In operation, the switch is configured to be pulsed on and off a first time to stabilize the bit line to the reference voltage before an auto-zero operation by the analog-to-digital converter for each readout of the pixel circuit. The switch is configured to be pulsed on and off a second time to stabilize the bit line to the reference voltage after the auto-zero operation and before a first analog-to-digital conversion operation by the analog-to-digital converter for each readout of the pixel circuit. The switch is configured to be pulsed on and off a third time to stabilize the bit line to the reference voltage after the first analog-to-digital conversion operation and before a second analog-to-digital conversion operation by the analog-to-digital converter for each readout of the pixel circuit.

[0016] It is appreciated that example readout circuits according to the teachings of this disclosure reduce DC bias current during readout and, when generating pixel circuit readouts, correlated double sampling can be used to eliminate fixed pattern noise and / or vertical smear issues.

[0017] To illustrate, Figure 1 An example of an imaging system 100 including an imaging device having an array of pixel circuits according to the teachings of this disclosure is described. In particular, the imaging system 100 includes a pixel array 102, a control circuit 110, a readout circuit 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array of pixel circuits 104 (e.g., PI, P2,..., Pn). As illustrated in the depicted example, the pixel circuits 104 are arranged in rows (e.g., Rl to Ry) and columns (e.g., CI to Cx) to acquire image data of a person, location, object, etc. that can then be used to acquire and render a 2D image of the person, location, object, etc.

[0018] In one example, one or more photodiodes in each pixel circuit 104 in the pixel array 102 are configured to photo generate image charge in response to incident light. Image charge generated in each photodiode in the pixel circuit 104 is transferred to a floating diffusion in each pixel circuit 104, which is converted to an image signal and then read out from each pixel circuit 104 by a pixel readout circuit included in the readout circuit 106 over a respective bit line 112. In various examples, the signals read out from the pixel array 102 can be amplified, digitized, and then transferred to the functional logic 108. In various examples, the readout circuit 106 includes amplification circuitry, an analog-to-digital converter (ADC), or other. In one example, the readout circuit 106 can read out one row of data at a time along the column bit lines 112 as described in Figure 1

[0019] Figure 2 One example of a pixel circuit 204 included in a pixel array 202 coupled to an example pixel readout circuit 238 included in a readout circuit 206 by a bit line 212 in accordance with the teachings of this disclosure is illustrated. It should be appreciated that Figure 2 The pixel array 202, pixel circuit 204, bit line 212, and readout circuit 206 can be examples of the pixel array 102, pixel circuit 104, bit line 112, and readout circuit 106 described above, and similarly named and numbered elements described above are similarly coupled and function below. Figure 1

[0020] In the example depicted in Figure 2 The pixel circuit 204 includes a photodiode 214 coupled to a transfer transistor 216, which is coupled to a floating diffusion 220. In operation, the transfer transistor 216 is coupled to be controlled in response to a transfer control signal TX. As such, charge photo generated in the photodiode 214 in response to incident light is transferred to the floating diffusion 220 in response to the transfer control signal TX.

[0021] Continuing with the example depicted in Figure 2 The reset transistor 218 is coupled between a voltage source (e.g., VDD) and the floating diffusion 220. In operation, the reset transistor 218 is configured to reset the pixel circuit 204 including charge in the floating diffusion 220 in response to a reset control signal RST.

[0022] ​​As shown in the illustrated example, the gate of the source follower transistor 222 is coupled to the floating diffuser 220. In this example, the drain of the source follower transistor 222 is coupled to a voltage source (e.g., VDD), and the source of the source follower transistor 222 is coupled to the column bit line 212 via the row select transistor 223. Therefore, in other words, the source follower transistor 222 and the row select transistor 224 are coupled between the voltage source (e.g., VDD) and the column bit line 212. In operation, the row select transistor 224 is configured to output an analog signal (e.g., PIXOUT 226) representing the charge in the floating diffuser 220 from the source follower transistor 222 of the pixel circuit 204 to the column bit line 212 in response to the row select signal SEL. Therefore, it should be understood that the output terminal of the row select transistor 224 coupled to the bit line 212 is the bit line output of the pixel circuit 204.

[0023] Figure 2 The example depicted shows that the readout circuit 206 includes a pixel readout circuit 238 coupled to bit line 212. In various examples, according to the teachings of the invention, the readout circuit 206 may include a plurality of pixel readout circuits 238, each of which may be coupled to a corresponding bit line 212. As shown in the depicted example, an analog-to-digital converter (ADC) 234 is coupled to the column bit line 212 to perform ADC conversion of the analog signal PIXOUT 226 received from the pixel circuit 204 via the column bit line 212. In the depicted example, an auto-zero operation of the ADC 234 may be performed in response to an auto-zero signal 236. The digital output of the ADC 234 is shown as a digital output signal DOUT 240. In one example, the pixel readout circuit 238 may also include a bias current source 228 coupled between the bit line output of the pixel circuit 204 and ground to the bit line 212. In one example, the bias current source 228 is configured to draw a small bias current I. B .

[0024] In various examples, each readout of the pixel circuit 204 by the pixel readout circuit 238 includes an auto-zero operation, a first analog-to-digital conversion operation, and then a second analog-to-digital conversion operation. In an example, a correlated double sampling output of the pixel circuit 204 is configured to be generated in response to a difference between the first and second analog-to-digital conversion operations of the analog-to-digital converter 234. For example, the first analog-to-digital conversion operation of the analog-to-digital converter 234 is configured to convert a reset value of the PIXOUT 226 from the pixel circuit 204 through the bit line 212 and the second analog-to-digital conversion operation of the analog-to-digital converter 234 is configured to convert a signal value of the PIXOUT 226 from the pixel circuit 204 through the bit line 212. It should be appreciated that by finding a difference between the signal value of the PIXOUT 226 from the pixel circuit through the bit line 212 and the reset value of the PIXOUT 226, fixed pattern noise and vertical smear issues can be eliminated in accordance with the teachings of this disclosure.

[0025] As shown in the depicted example, the pixel readout circuit 238 also includes a switch 230 coupled to the bit line 212 between the bit line output of the pixel circuit 204 and the reference voltage 232. In operation, the switch 230 is configured to be pulsed on and off a first time in response to a control signal PDN to stabilize the bit line 212 to the reference voltage 232 before the auto-zero operation of each readout of the pixel circuit 204 by the analog-to-digital converter 234 in response to the auto-zero signal 236. The switch 230 is configured to be pulsed on and off a second time in response to the control signal PDN to stabilize the bit line 212 to the reference voltage 232 after the auto-zero operation of the analog-to-digital converter 234 and before the first analog-to-digital conversion operation of each readout of the pixel circuit 204 by the analog-to-digital converter 234. The switch 230 is then configured to be pulsed on and off a third time in response to the control signal PDN to stabilize the bit line 212 to the reference voltage 232 after the first analog-to-digital conversion operation of the analog-to-digital converter 234 and before the second analog-to-digital conversion operation of each readout of the pixel circuit 204 by the analog-to-digital converter 234.

[0026] In various examples, the reference voltage 232 can equal the first reference voltage VCOM1 or the second reference voltage VCOM2. For example, in one example, the reference voltage 232 is configured to equal the first reference voltage VCOM1 when the switch 230 is configured to be pulsed on and off a first time to stabilize the bit line 212 prior to an auto-zero operation in the analog-to-digital converter 234. In examples, the reference voltage 232 is configured to equal the second reference voltage VCOM2 when the switch 230 is configured to be pulsed on and off a second and third time to stabilize the bit line 212 prior to first and second analog-to-digital conversion operations by the analog-to-digital converter 234. In various examples, the first reference voltage VCOM1 is greater than the second reference voltage VCOM2. For example, in one example, the first reference voltage VCOM1 is about 1.0 volts and the second reference voltage VCOM2 is about 0.0 volts. It should be appreciated that with the bit line 212 stabilized to the same second reference voltage VCOM2 during the second and third time the switch 230 is pulsed on and off, the load on the bit line 212 in response to the switch 230 being pulsed on and off a second time prior to a first analog-to-digital conversion operation by the analog-to-digital converter 234 is substantially equal to the load on the bit line 212 in response to the switch 230 being pulsed on and off a third time prior to a second analog-to-digital conversion operation by the analog-to-digital converter 234.

[0027] Figure 3 One example of a timing diagram of signals in an example pixel readout circuit configured to read out a pixel circuit through a bit line in accordance with the teachings of this disclosure is illustrated. It should be appreciated that, Figure 3 The example pixel readout circuit read out in the depicted example can be Figure 2 the pixel readout circuit 238 of FIG. 1, and similarly named and numbered elements described above are similarly coupled and function below.

[0028] As shown in the depicted example, the PDN signal 330 is pulsed on and off a first time between time TO and time Tl prior to performing an auto-zero operation in the analog-to-digital converter in response to being turned on and then off between time T2 and time T3 of the auto-zero signal 336. As such, the PIXOUT signal 326 is pulled down to a reference voltage between time TO and time Tl, which in the depicted example equals the first reference voltage VCOM1 332A between time TO and time Tl. In the depicted example, the first reference voltage VCOM1 332A equals about 1.0 volts. It should be appreciated that, as a result, the bit line 212 discharges to the first reference voltage VCOM1 332A between time TO and time Tl. In various examples, the source follower transistor 222 pulls up the bit line 212 as governed by the voltage at the floating diffusion 220 without any DC bias current, or in one example, with a very small bias current I BL .

[0029] Continuing with the depicted example, after the bit line 212 is stabilized to the reset level as determined by the reference voltage VCOM13332A between time TO and time Tl, and after the auto-zero operation of the operation of the analog-to-digital converter 234 is performed between time T2 and time T3, the PDN signal 330 is then pulsed on and off between time T4 and time T5. As such, the PIXOUT signal 326 is pulled down to a reference voltage between time T4 and time T5, which in the depicted example is equal to the second reference voltage VCOM23332B between time T4 and time T5. In the depicted example, the second reference voltage VCOM23332B is equal to approximately 0.0 volts. It will be appreciated that, as such, the bit line 212 discharges to the second reference voltage VCOM23332B between time T4 and time T5.

[0030] After the bit line 212 is re-stabilized to the reset level as determined by the reference voltage VCOM23332B between time T4 and time T5, a first analog-to-digital conversion is performed between time T6 and time T7, as indicated using the ADC signal 334. As such, in the example, the first analog-to-digital conversion performed between time T6 and time T7 has the reset level value of the PIXOUT signal 326.

[0031] Continuing with the depicted example, after the first analog-to-digital conversion is performed between time T6 and time T7, the PDN signal 330 is then pulsed on and off a third time between time T8 and time T9. As such, the PIXOUT signal 326 is again pulled down to a reference voltage between time T8 and time T9, which in the depicted example is again equal to the second reference voltage VCOM23332B between time T8 and time T9. In the depicted example, the second reference voltage VCOM23332B is equal to approximately 0.0 volts. It will be appreciated that, as such, the bit line 212 discharges to the second reference voltage VCOM23332B between time T8 and time T9.

[0032] In various examples, it will be appreciated that, with the bit line 212 stabilized to the same second reference voltage VCOM23332B between time T4 and T5 and between time T8 and T9 during the second and third time the switch 230 is pulsed on and off, the load on the bit line 212 between time T4 and T5 is substantially equal to the load on the bit line 212 between time T8 and T9. As such, the state of the bit line 212 between time T4 and T5 is substantially equal to the state of the bit line 212 between time T8 and T9 and, therefore, the state of the bit line 212 after time T5 (e.g., between time T5 and T6) and after time T9 (e.g., between time T9 and TlO) will also be the same.

[0033] After the bit line 212 is re-stabilized to the reset level as determined by the reference voltage VCOM2332B between time T8 and time T9, a second analog-to-digital conversion is performed between time T10 and time T11 as indicated using the ADC signal 334. In one example, the second analog-to-digital conversion performed between time T10 and time T11 is performed on the signal level of the PIXOUT signal 326.

[0034] In the depicted example, the next readout of the pixel circuit can begin at time T12, with the readout process repeating as described above between time TO and time T11. Thus, the first pulse enable and disable of the PDN signal 330 again begins at time T12 before another auto-zero operation is performed on the next readout of the pixel circuit in the analog-to-digital converter.

[0035] In various examples, it should be appreciated that a correlated double sampling value of the PIXOUT signal 326 can be generated in response to a difference between the second and first analog-to-digital conversions of the PIXOUT signal 326. It should be further appreciated that, since the stable loading of the bit line 212 after time T5 (e.g., between time T5 and T6) is substantially equal to the stable loading of the bit line 212 after time T9 (e.g., between time T9 and T10), the fixed pattern noise and vertical smear problems are eliminated by correlated double sampling without involving auto-zeroing.

[0036] It should also be appreciated that, in examples in which the first stabilization of the bit line 212 between time TO and time Tl is to a higher voltage VCOM1332A (as compared to the lower voltage VCOM2332B) of 1.0 volts, the voltage swing of the PIXOUT signal 326 on the bit line 212 can also begin from the higher voltage set by VCOM1332A to reduce the bit line voltage swing by about 1.0 volts at the expense of larger auto-zeroing errors. However, according to the teachings of the present disclosure, these larger auto-zeroing errors can be eliminated by correlated double sampling.

[0037] The foregoing description of the illustrated examples of the present disclosure (including what is described in the Abstract) is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. While specific examples of this disclosure are described herein for illustrative purposes, various modifications are possible within the scope of this disclosure as those skilled in the relevant art will recognize.

[0038] These modifications can be made in light of the above detailed description of the application. The terms used in the following claims should not be construed to limit the present disclosure to the specific examples disclosed in the specification and drawings. Rather, the scope of the present disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

1. A pixel readout circuit, comprising: an analog-to-digital converter coupled to a bit line output of a pixel circuit; and a switch coupled between the bit line output of the pixel circuit and a reference voltage, wherein the switch is configured to be pulsed on and off a first time to stabilize a bit line to a first reference voltage before an auto-zero operation by the analog-to-digital converter for each readout of the pixel circuit, wherein the switch is configured to be pulsed on and off a second time to stabilize the bit line to a second reference voltage after the auto-zero operation and before a first analog-to-digital conversion operation by the analog-to-digital converter for each readout of the pixel circuit, wherein the switch is configured to be pulsed on and off a third time to stabilize the bit line to the second reference voltage after the first analog-to-digital conversion operation and before a second analog-to-digital conversion operation by the analog-to-digital converter for each readout of the pixel circuit.

2. The pixel readout circuit of claim 1, further comprising a bias current source coupled between the bit line output of the pixel circuit and ground.

3. The pixel readout circuit of claim 1, wherein each readout of the pixel circuit includes the auto-zero operation, the first analog-to-digital conversion operation, and the second analog-to-digital conversion operation in sequence.

4. The pixel readout circuit of claim 3, wherein a correlated double sampling output of the pixel circuit is configured to be generated in response to a difference between the first and second analog-to-digital conversion operations.

5. The pixel readout circuit of claim 4, wherein the first analog-to-digital conversion operation is configured to convert a reset value from the pixel circuit through the bit line, wherein the second analog-to-digital conversion operation is configured to convert a signal value from the pixel circuit through the bit line.

6. The pixel readout circuit of claim 1, wherein the first reference voltage is greater than the second reference voltage.

7. The pixel readout circuit of claim 6, wherein the first reference voltage is 1 volt and the second reference voltage is 0 volts.

8. The pixel readout circuit of claim 1, wherein a first load of the bit line in response to the switch being pulsed on and off a second time is equal to a second load of the bit line in response to the switch being pulsed on and off a third time.

9. An imaging system, comprising: a pixel array including a plurality of pixel circuits; a readout circuit coupled to the pixel array by a plurality of bit lines, wherein the readout circuit includes a plurality of pixel readout circuits coupled to the plurality of bit lines, wherein each of the plurality of pixel readout circuits comprises: an analog-to-digital converter coupled to one of the plurality of bit lines to read out image data from a pixel circuit output of the plurality of pixel circuits coupled to the one of the plurality of bit lines; and a switch coupled to the one of the plurality of bit lines between the pixel circuit output and a reference voltage, wherein the switch is configured to be pulsed on and off a first time to stabilize the one of the plurality of bit lines to a first reference voltage before the auto-zero operation for each readout of the one of the plurality of pixel circuits by the analog-to-digital converter, wherein the switch is configured to be pulsed on and off a second time to stabilize the one of the plurality of bit lines to a second reference voltage after the auto-zero operation and before a first analog-to-digital conversion operation for each readout of the one of the plurality of pixel circuits by the analog-to-digital converter, wherein the switch is configured to be pulsed on and off a third time to stabilize the one of the plurality of bit lines to the second reference voltage after the first analog-to-digital conversion operation and before a second analog-to-digital conversion operation for each readout of the one of the plurality of pixel circuits by the analog-to-digital converter.

10. The imaging system of claim 9, wherein each of the plurality of pixel readout circuits further comprises a bias current source coupled between a bit line output of the pixel circuit and ground.

11. The imaging system of claim 9, wherein each readout of the one of the plurality of pixel circuits includes the auto-zero operation, the first analog-to-digital conversion operation, and the second analog-to-digital conversion operation following.

12. The imaging system of claim 11, wherein a correlated double sampling output of the one of the plurality of pixel circuits is configured to be generated in response to a difference between the first and second analog-to-digital conversion operations.

13. The imaging system of claim 12, wherein the first analog-to-digital conversion operation is configured to convert a reset value from the one of the plurality of pixel circuits through the one of the plurality of bit lines, wherein the second analog-to-digital conversion operation is configured to convert a signal value from the one of the plurality of pixel circuits through the one of the plurality of bit lines.

14. The imaging system of claim 9, wherein the first reference voltage is greater than the second reference voltage.

15. The imaging system of claim 14, wherein the first reference voltage is 1 volt and the second reference voltage is 0 volts.

16. The imaging system of claim 9, wherein a first load of the one of the plurality of bit lines in response to the switch being pulsed on and off a second time is equal to a second load of the one of the plurality of bit lines in response to the switch being pulsed on and off a third time.

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