A method of implementing a generic fault detection module

Abstract

The application provides an implementation method of a general fault detection module for an airborne embedded system, which comprises a fault detection signal acquisition module, a system on chip (SOC), a power line carrier communication interface, auxiliary tool software and a data loading and unloading tool.The fault detection signal acquisition module is the physical entity of the general fault detection module, uses the power supply of a resident system, sets the interface resources of the general fault detection module according to the signal types and the number of signals required by the resident system, loads the corresponding working configuration and acquires node information.The SOC provides storage space for configuration files and fault logs, runs state acquisition software, judges the signal check state and records fault logs.The power line carrier communication interface completes the data exchange between the fault detection signal acquisition modules through the power supply line.The auxiliary tool software is resident in an upper computer, completes the parameter setting of the general fault detection module and generates node configuration files.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of airborne embedded system testing, and more particularly, to a method for implementing a general-purpose fault detection module. BACKGROUND

[0002] Generally, the testability design of an embedded system mainly relies on the inherent hardware resources of the product, supplemented by software to complete the detection and isolation of product faults. Due to the existence of auxiliary BIT test software, the architecture of the product will be affected to some extent. At the same time, due to the influence of the inherent hardware resources of the product, the coverage and isolation rate of the product fault mode are usually low. If the hardware resources are increased in order to pursue higher fault detection rate, the hardware architecture of the product will change greatly, and the inherent reliability of the product will be negatively affected.

[0003] The traditional way of testability design of embedded system first relies on the inherent resources and data transmission path of embedded system to preset initial BIT test items, and then carries out product FMEA (Failure Mode and Effects Analysis) analysis according to the hardware architecture and software function of the product. Then, according to the analysis results of FMEA, find the fault modes in the embedded product that cannot be detected by the existing BIT, and carry out further BIT design improvement accordingly. But due to the limitation of product hardware architecture and resources, there are usually some important fault modes that cannot be detected by the existing resources, and even some fault modes will cause the existing BIT design to fail completely (such as processor failure, external communication interface failure). This kind of fault will bring great difficulty to the subsequent fault troubleshooting of the product, and often needs to develop special detection tools to assist professional technicians to troubleshoot the faulty product. Severely affect the maintainability and maintenance cost of the product. SUMMARY

[0004] The application is a kind of general fault detection module implementation method, including fault detection signal acquisition module, system on chip (SOC), power line carrier communication interface, auxiliary tool software, data loading and unloading tool, the fault detection signal acquisition module is the physical entity of the general fault detection module, using the power supply of the resident system, setting the interface resources of the general fault detection module according to the signal type and quantity required by the resident system, obtaining the node information of the installation position, loading the corresponding working configuration according to the node information; the system on chip (SOC) provides storage space for configuration file and fault log, and the system on chip (SOC) also runs the state acquisition software, judges the signal verification state and records the fault log; the power line carrier communication interface couples the serial communication signal into the power supply line by signal modulation, and completes the data exchange between each fault detection signal acquisition module through the power supply line; the auxiliary tool software resides in the host computer, completes the parameter setting of the general fault detection module, and generates the node configuration file; the data loading and unloading tool completes the uploading and downloading of each node fault log and configuration file through the power supply interface of the fault detection signal acquisition module resident system and using the data transmission link of the module.

[0005] Preferably, the general fault detection module parameter setting includes node setting, communication address setting, data query period setting, mapping relationship setting of acquisition signal and physical port, acquisition signal filtering equation and sampling rate setting, associated signal verification logic setting, and fault data reporting threshold setting.

[0006] Preferably, the state acquisition software of the system on chip (SOC) loads the corresponding configuration file to complete parameter setting according to the obtained node configuration file, the nodes are divided into master node, backup master node and slave node, for the master node, the state acquisition software queries and stores the fault log of the backup master node and slave node of the system according to the configuration period; for the backup master node, if the state acquisition software does not receive the query message of the master node within the configuration period, the backup master node will set itself as the master node to replace the work of the master node; for the slave node, the state acquisition software periodically sends the fault log of the node according to the message request of the master node.

[0007] Preferably, when the fault log capacity of each node reaches the upper limit of storage, the earliest fault information is automatically overwritten.

[0008] Preferably, the fault detection signal acquisition module collects data including I2C interface, discrete quantity, analog quantity, LED indicator, temperature acquisition and fan state.

[0009] Preferably, all the data collected by the fault detection signal acquisition module is attached with a time tag, which is accurate to milliseconds, and the timing reference comes from the initial setting of the master node of the fault detection signal acquisition module.

[0010] Preferably, the fault detection signal acquisition module is also designed with three LED indicators, the first LED indicator is used to indicate the power supply state of the fault detection signal acquisition module, the second LED indicator is used to indicate the working state of the module, and the third LED indicator is used to over-temperature alarm.

[0011] Preferably, the communication signal coupling transmission mode adopts one of AC power line carrier communication or DC secondary power carrier communication.

[0012] Preferably, the auxiliary tool software judges the fault occurrence point according to the two-dimensional relationship matrix of test items and fault modes generated by the resident system FMEA.

[0013] The beneficial effects of the present application are:

[0014] The universal fault detection module provided by the present application can significantly reduce the influence of the testability design of the embedded system on the original function architecture of the product, and can improve the fault detection and isolation rate of the embedded product in a universal and low-cost manner, significantly reduce the development schedule and development cost of the embedded product, and greatly improve the fault detection efficiency of the product.

[0015] In addition, the detection and monitoring points that can cover the faults that cannot be detected in the early stage are selected based on the FMEA results of the embedded product to supplement the blind area of the initial testability design of the product. Since the universal fault detection module does not intervene in the data processing process of the original system, but can form a mutual monitoring structure with the control unit in the original system, the risk of increasing the number of product fault modes and reducing the fault detection rate due to the increase of hardware resources is avoided. The auxiliary tool software of the universal fault detection module can quickly locate one or more faults in the embedded system by combining the unloaded fault detection records and the two-dimensional matrix of the relationship between test items and fault modes generated by the system FMEA. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 It is a universal fault detection module system composition schematic diagram of the present application.

[0017] Figure 2 It is a universal fault detection module embodiment data acquisition unit architecture schematic diagram of the present application. DETAILED DESCRIPTION

[0018] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application based on the airborne data acquisition unit are described in detail below with reference to the drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application. Any device system and implementation method in the industry and field similar to the embodiments of the present application belong to the scope of protection of the present patent.

[0019] As shown in Figure 1 , the present application collects the key states in the running process of the embedded system by implanting the general fault detection module in each physical component unit of the embedded system to assist in completing the state monitoring and fault detection of the system. The airborne data acquisition unit is a data acquisition and control information transmission device in the avionics system, responsible for the data interaction between various sensors and actuators on the aircraft and the task data processing computer. Specifically, the sensor data collected through discrete, analog, 422 and 429 interfaces are transmitted to the task data processing computer through the CAN bus, and then the calculation results of the task data processing computer are transmitted back to the actuator through the airborne data acquisition unit. The airborne data acquisition unit undertakes the transmission of important application data and needs to have high reliability and fault detection rate. The use of the general fault detection module of the present application in the system can improve the fault detection rate and isolation rate of the system without changing the original system architecture, which helps the system maintenance personnel to quickly isolate faults and maintain equipment. The logical architecture of the data acquisition unit is shown in Figure 2 .

[0020] In specific implementation, as shown in Figure 2 , the present application sets different signal acquisition resources and fault data interaction channel quantities according to the resident system of the fault detection module, so that the general fault detection module can meet the signal acquisition requirements of different component units of the resident system to support the test design improvement and fault diagnosis of the entire product.

[0021] In the system, the general fault detection module communication signal coupling adopts two modes, one of which uses the dual-redundancy 28V DC power between products as the transmission link carrier, and the other uses the DC secondary power inside the data acquisition unit as the transmission link carrier, so the general fault detection module of the system selects to use two different types of power line carrier communication interfaces. In other airborne systems, the carrier mode of alternating power lines can also be used. According to the FMEA analysis results of the resident system, according to the target level of system fault diagnosis isolation, the fault detection blind area of the inherent BIT design is sorted out, the fault detection signal type and quantity are sorted out in units of modules, and the least common multiple of the required fault detection signal type and quantity of each module is used as the design requirement of the signal acquisition interface resource of the general fault detection module. In view of the fact that the NVRAM storage system BIT diagnosis result of each module in the data acquisition unit is provided with an IIC interface, the general fault detection module reserves an IIC interface, which is connected with the IIC bus in the original system. Under the normal working state of the data acquisition unit equipment, the general fault detection module does not operate the IIC bus, and only when the data acquisition unit fails, the general fault detection module reads the fault log data saved by each module in the system through the IIC interface, so as to assist the tool software to perform fault analysis and diagnosis.

[0022] Subsequently, the fault detection module function circuit is combined with each functional module of the original system after selecting the signal acquisition point according to the fault reason of the related fault mode in FMEA, the auxiliary tool software configures the mapping relationship of the acquisition signal and the physical port of each fault detection module, node setting, data communication address setting, data query period, acquisition signal filtering equation, sampling rate setting, associated signal verification logic setting, fault data reporting threshold setting, and generates a loadable configuration file of each fault detection module according to the monitoring signal points of each fault detection module.

[0023] After the fault detection module is powered on with the resident system, the auxiliary tool software loads the configuration file of each fault detection module through the power supply of the system with the assistance of the data loading and unloading tool. After the system is powered on again, each fault detection module in the system will monitor the state of each signal acquisition point preset in the resident system according to the parameter setting of the configuration file. When the state acquisition software of the general fault detection module detects the number of states inconsistent with the signal verification logic reaching the preset threshold number of times, a log file of the fault is formed and stored in the non-volatile memory, and then the related fault data is transmitted to the master node according to the setting of the configuration file. The master node transmits the fault information to the functional unit responsible for health management of the system in real time through the IIC interface, and the system maintenance personnel can also download and analyze it afterwards.

[0024] After obtaining the fault record data of all fault detection modules in the system, the auxiliary tool software generates a complete test result vector S fault = (T1, T2, T3, T4, …Tn) according to the fault record data, where Tn is the test result of each test item. When the test result of the Nth test item is fault, Tn = 1; when the test result of the Nth test item is no fault, Tn = 0.

[0025] After the auxiliary tool software obtains the test vector S fault of the system fault state, it matches S fault with the test vector of each fault mode in the test item fault mode relationship matrix generated by the system FMEA (see Table 1 for an example of the test item fault mode relationship matrix). The fault mode represented by the matching consistent vector is the fault occurrence point. When there are multiple fault vectors that match, it means that the system fault detection point is not set reasonably and cannot isolate each fault.

[0026] Table 1 Test item and fault mode relationship matrix example

[0027]

Claims

1. A method for implementing a general fault detection module, characterized in that, The system includes a fault detection signal acquisition module, a system-on-a-chip (SOC), a power line carrier communication interface, auxiliary software tools, and a data loading / unloading tool. The fault detection signal acquisition module is the physical entity of the general fault detection module. It operates using the power supply of the resident system, sets the interface resources of the general fault detection module according to the type and quantity of signals to be acquired by the resident system, obtains node information of its installation location, and loads the corresponding working configuration based on the node information. The SOC provides storage space for configuration files and fault logs. The SOC also runs status acquisition software to determine signal verification status and record fault logs. The power line carrier communication interface couples serial communication signals to the power supply line through signal modulation, enabling data exchange between the fault detection signal acquisition modules. The auxiliary software resides on the host computer, completes the parameter settings of the general fault detection module, and generates node configuration files. The data loading / unloading tool, through the power supply interface of the fault detection signal acquisition module residing in the resident system, uses the data transmission link of this module to upload and download fault logs and configuration files for each node.

2. The implementation method of a general fault detection module according to claim 1, characterized in that, The parameter settings for the general fault detection module include node settings, communication address settings, data query cycle settings, mapping relationship settings between acquired signals and physical ports, acquisition signal filtering equation and sampling rate settings, associated signal verification logic settings, and fault data reporting threshold settings.

3. The implementation method of a general fault detection module according to claim 1, characterized in that, The status acquisition software of the System-on-a-Chip (SoC) loads the corresponding configuration files based on the acquired node configuration files to complete parameter settings. Nodes are divided into master nodes, backup master nodes, and slave nodes. For master nodes, the status acquisition software queries and stores the fault logs of the backup master nodes and slave nodes according to the configuration period. For backup master nodes, the status acquisition software sets a timer internally. If no query message is received from the master node within the configuration period, the backup master node sets itself as the master node and takes over the work of the master node. For slave nodes, the status acquisition software periodically sends the fault logs of the node according to the message requests of the master node.

4. The implementation method of a general fault detection module according to claim 1, characterized in that, Once the storage capacity of the fault logs stored on each node reaches its storage limit, the oldest fault information will be automatically overwritten.

5. The implementation method of a general fault detection module according to claim 1, characterized in that, The fault detection signal acquisition module collects data including: I2C interface, discrete quantities, analog quantities, LED indicator lights, temperature acquisition, and fan status.

6. The implementation method of a general fault detection module according to claim 1, characterized in that, All data collected by the fault detection signal acquisition module is accompanied by a time stamp, which is accurate to milliseconds. The timing reference comes from the initial settings of the fault detection signal acquisition module master node.

7. The implementation method of a general fault detection module according to claim 1, characterized in that, The fault detection signal acquisition module is also designed with three LED indicators. The first LED indicator is used to indicate the power supply status of the fault detection signal acquisition module, the second LED indicator is used to indicate the working status of the module, and the third LED indicator is used for over-temperature alarm.

8. The implementation method of a general fault detection module according to claim 1, characterized in that, The communication signal coupling transmission method adopts either AC power line carrier communication or DC secondary power supply carrier communication.

9. The implementation method of a general fault detection module according to claim 1, characterized in that, The auxiliary software tool determines the fault location based on a two-dimensional relationship matrix of test items and fault modes generated by the FMEA of the resident system.

Images