Semiconductor structure and method of forming the same
By forming a first trench with a large lateral dimension and a grinding stop layer in the semiconductor structure, the problem of inconsistent gate structure height of the device is solved, and the performance of the semiconductor structure is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT TIANJIN
- Filing Date
- 2022-04-08
- Publication Date
- 2026-07-24
AI Technical Summary
In semiconductor structures, existing technologies for planarizing device gate structures result in insufficient lateral contact area of the sidewalls, leading to inconsistent gate structure heights and affecting semiconductor structure performance.
A trench structure consisting of a second trench and a first trench connected thereto is formed in a semiconductor structure. The lateral dimension of the first trench is larger than that of the second trench. A polishing stop layer is formed at the bottom and sidewalls of the first trench, and an isolation structure is formed in the remaining space of the trench. The height of the device gate structure is controlled by utilizing the larger polishing stop layer and the contact area with the planarization equipment.
By increasing the lateral contact area of the grinding stop layer, the probability of inconsistent gate structure height in the device is reduced, thereby improving the performance of the semiconductor structure.
Smart Images
Figure CN116936619B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity.
[0003] In the development of integrated circuits, the functional density (i.e. the number of interconnects in each chip) usually increases gradually while the geometric size (i.e. the smallest component size that can be produced by process steps) gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.
[0004] Currently, with technology nodes constantly shrinking, improving the performance of semiconductor structures has become a challenge. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improve the performance of the semiconductor structure.
[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a device gate structure located on the substrate; an interlayer dielectric layer located on the top of the substrate where the device gate structure is exposed, and covering the sidewalls of the device gate structure; a trench located between adjacent device gate structures and penetrating the interlayer dielectric layer, the trench including a second trench and a first trench located on and connected to the second trench, wherein the lateral direction is perpendicular to the extension direction of the device gate structure and parallel to the surface of the substrate, and the lateral dimension of the first trench is larger than the lateral dimension of the second trench; a polishing stop layer located at the bottom and sidewalls of the second trench and in the first trench; and an isolation structure located in the remaining space of the trench.
[0007] Accordingly, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a gate structure is formed on the substrate, an interlayer dielectric layer is formed on the top of the exposed portion of the gate structure, and the interlayer dielectric layer covers the top of the gate structure; removing a portion of the gate structure to form a trench surrounded by the remaining gate structure and the interlayer dielectric layer, the trench including a second trench and a first trench located on and connected to the second trench, wherein the lateral direction is perpendicular to the extension direction of the gate structure and parallel to the surface of the substrate, and the lateral dimension of the first trench is larger than the lateral dimension of the second trench; forming a polishing stop layer at the bottom and sidewalls of the second trench, at the bottom of the first trench, and forming an isolation structure in the remaining space of the trench; after forming the polishing stop layer and the isolation structure, removing the remaining gate structure to form a gate opening in the interlayer dielectric layer; forming a device gate structure in the gate opening; and planarizing the device gate structure above the top of the polishing stop layer, using the top of the polishing stop layer in the first trench as a stop position.
[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0009] This invention provides a method for forming a semiconductor structure. A portion of the gate structure is removed to form a trench surrounded by the remaining gate structure and an interlayer dielectric layer. The trench includes a second trench and a first trench located on and connected to the second trench. The lateral direction is perpendicular to the extension direction of the gate structure and parallel to the substrate surface. The lateral dimension of the first trench is larger than that of the second trench. A polishing stop layer is formed at the bottom and sidewalls of the second trench and at the bottom of the first trench. Compared to existing methods that use the top of the sidewall of the device gate structure as the polishing stop layer, the lateral dimension of the polishing stop layer formed at the bottom of the first trench in this invention is larger than that of the sidewall. Consequently, during the planarization process of the device gate structure above the top of the polishing stop layer, the polishing stop layer has a larger contact area with the planarization equipment, enabling the polishing stop layer to stop the polishing process. This ensures that the height of the device gate structure meets the target height required by the process, reducing the probability of inconsistent height of the device gate structure and thus improving the performance of the semiconductor structure. Attached Figure Description
[0010] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0011] Figures 7 to 8 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;
[0012] Figures 9 to 19 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0013] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.
[0014] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0015] refer to Figure 1 A substrate 10 is provided, on which a gate structure 13 is formed, a sidewall 20 is formed on the sidewall of the gate structure 13, and an interlayer dielectric layer 12 is formed on the top of the exposed portion of the substrate 10 of the gate structure 13, the interlayer dielectric layer 12 covering the top of the gate structure 13 and the sidewall 20.
[0016] refer to Figure 2 A portion of the gate structure 13 is removed to form a trench 15 surrounded by the interlayer dielectric layer 12.
[0017] refer to Figure 3 An isolation material layer 16 is formed in the trench 15 and on top of the interlayer medium layer 12.
[0018] refer to Figure 4 With the top of the gate structure 13 as the stop position, the interlayer dielectric layer 12 and the isolation material layer 16 above the gate structure 13 are planarized.
[0019] refer to Figure 5 Remove the gate structure 13, form a gate opening (not shown) in the interlayer dielectric layer 12, and then form a device gate structure 17 in the gate opening.
[0020] refer to Figure 6 The device gate structure 17 is planarized with the top of the sidewall 20 as the stop position.
[0021] The device gate structure 17 is a metal gate structure.
[0022] It should be noted that, taking the direction perpendicular to the extension direction of the gate structure 17 and parallel to the surface of the substrate 10 as the lateral direction, during the planarization process of the device gate structure 17, since the device gate structure 17 is a metal gate structure, the process difficulty of planarizing the device gate structure 17 is increased. At the same time, the lateral contact area between the equipment used for planarization and the sidewall 20 is too small, so the sidewall 20 cannot play the role of stopping the grinding, which increases the probability of inconsistent height of the device gate structure 17, thereby affecting the performance of the semiconductor structure.
[0023] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, on which a gate structure is formed, and an interlayer dielectric layer is formed on the exposed top of the gate structure, the interlayer dielectric layer covering the top of the gate structure; removing a portion of the gate structure to form a trench surrounded by the remaining gate structure and the interlayer dielectric layer, the trench including a second trench and a first trench located on and connected to the second trench, the trench having a lateral direction perpendicular to the extension direction of the gate structure and parallel to the surface of the substrate, the lateral dimension of the first trench being larger than the lateral dimension of the second trench; forming a polishing stop layer at the bottom and sidewalls of the second trench, at the bottom of the first trench, and forming an isolation structure in the remaining space of the trench; after forming the polishing stop layer and the isolation structure, removing the remaining gate structure to form a gate opening in the interlayer dielectric layer; forming a device gate structure in the gate opening; and planarizing the device gate structure above the top of the polishing stop layer, using the top of the polishing stop layer in the first trench as a stop position.
[0024] This invention provides a semiconductor structure forming a trench surrounded by a residual gate structure and an interlayer dielectric layer. The trench includes a second trench and a first trench located on and connected to the second trench. The lateral direction is perpendicular to the extension direction of the gate structure and parallel to the substrate surface. The lateral dimension of the first trench is larger than that of the second trench. A polishing stop layer is formed at the bottom and sidewalls of the second trench and at the bottom of the first trench. Compared with the existing scheme that uses the top of the sidewall of the device gate structure as the polishing stop layer, the lateral dimension of the polishing stop layer formed at the bottom of the first trench in this invention is larger than that of the sidewall. Correspondingly, during the planarization process of the device gate structure above the top of the polishing stop layer, the polishing stop layer has a larger contact area with the planarization equipment, enabling the polishing stop layer to play a polishing stop role. This allows the height of the device gate structure to reach the target height required by the process, reduces the probability of height inconsistency of the device gate structure, and thus improves the performance of the semiconductor structure.
[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0026] Figures 7 to 8 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention, wherein... Figure 7 It is a top view. Figure 8 yes Figure 7 A sectional view along the AB direction.
[0027] The semiconductor structure includes: a substrate (not shown); a device gate structure 219 located on the substrate; an interlayer dielectric layer 202 located on the top of the substrate where the device gate structure 219 is exposed, and covering the sidewalls of the device gate structure 219; a trench (not shown) located between adjacent device gate structures 219 and penetrating the interlayer dielectric layer 202, the trench including a second trench (not shown) and a first trench (not shown) located on and connected to the second trench, with the lateral direction being perpendicular to the extension direction of the device gate structure and parallel to the surface of the substrate, the lateral dimension of the first trench being larger than the lateral dimension of the second trench; a polishing stop layer 213 located at the bottom and sidewalls of the first trench and in the second trench; and an isolation structure 212 located in the remaining space of the trench.
[0028] The substrate is used to provide a process platform for the manufacturing process.
[0029] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 200 and fins 201 protruding from the substrate 200. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is correspondingly a planar substrate.
[0030] In this embodiment, the material of the fin 201 is the same as that of the substrate 200, which is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium ionide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
[0031] In this embodiment, the semiconductor structure further includes an isolation layer (not shown) located on the substrate 200 exposed by the fin 201, the isolation layer covering part of the sidewall of the fin 201.
[0032] The isolation layer is used to isolate adjacent devices.
[0033] The material of the isolation layer can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer is silicon oxide.
[0034] In this embodiment, the semiconductor structure further includes a source / drain doped layer (not shown) located in the fins 201 on both sides of the device gate structure 219.
[0035] The source and drain doped layers are used as the source and drain regions of the transistor.
[0036] When the semiconductor structure is an NMOS transistor, the source / drain doped layer includes a stress layer doped with N-type ions. The stress layer is made of Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P-ions, As-ions, or Sb-ions. When the semiconductor structure is a PMOS transistor, the source / drain doped layer includes a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The P-type ions are B-ions, Ga-ions, or In-ions.
[0037] The interlayer dielectric layer 202 is used to isolate the gate structure 219 of adjacent devices.
[0038] The interlayer dielectric layer 202 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the interlayer dielectric layer 202 is made of silicon oxide.
[0039] The sidewall 206 is used to protect the sidewall of the device gate structure 219. The sidewall 206 can be a single-layer structure or a multilayer structure, and the material of the sidewall 206 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 206 is a single-layer structure, and the material of the sidewall 206 is silicon oxide.
[0040] The grooves provide space for the grinding stop layer 213 and the isolation structure 212.
[0041] In this embodiment, since the lateral dimension of the first trench is larger than that of the second trench, during the planarization process of the device gate structure 219 formed above the top of the grinding stop layer 213, the grinding stop layer 213 formed at the bottom of the first trench has a larger contact area with the equipment used for planarization, so that the grinding stop layer 213 can play the role of stopping grinding, thereby enabling the height of the device gate structure 219 to reach the target height required by the process, reducing the probability of height inconsistency of the device gate structure 219, and thus improving the performance of the semiconductor structure.
[0042] In this embodiment, along the extending direction of the device gate structure 219, the trench is located in the device gate structure 219, and the sidewall of the first trench is flush with the sidewall of the second trench.
[0043] Specifically, along the extension direction of the device gate structure 219, the sidewalls of the first trench and the second trench are flush, so that the interlayer dielectric layer 202 can completely cover the remaining sidewalls of the device gate structure 219, reducing the probability of contact between the device gate structures 219, thereby improving the performance of the semiconductor structure.
[0044] During the planarization process of the device gate structure 219 formed above the top of the grinding stop layer 213, the grinding stop layer 213 located at the bottom of the first trench plays the role of stopping the grinding, so that the height of the device gate structure 219 can reach the target height, and the probability of the device gate structure 219 having a consistent height is increased.
[0045] In this embodiment, the material of the grinding stop layer 213 includes one or both of a-Si and SiOC.
[0046] Specifically, during the planarization process of the device gate structure 219 above the top of the grinding stop layer 213, the material used for the device gate structure 219 has a higher grinding selectivity than a-Si and SiOC. This allows the grinding stop layer 213 to be retained while removing part of the device gate structure 219, meaning that the top of the grinding stop layer 213 can be used as the stop position for the planarization process, thereby increasing the probability of the device gate structure 219 having a high degree of uniformity.
[0047] It should be noted that the lateral dimension of the polishing stop layer 213 located at the bottom of the first trench should not be too large or too small. If the lateral dimension of the polishing stop layer 213 is too large, it will easily occupy too much space of the isolation structure 212, making the process dimensions of the isolation structure 212 unable to meet the process requirements. Consequently, the electrical isolation effect of the isolation structure 212 on the gate structure 219 of adjacent devices will be reduced, increasing the probability of contact between the gate structures 219 of adjacent devices, thereby affecting the performance of the semiconductor structure. If the lateral dimension of the polishing stop layer 213 is too small, during the planarization process of the gate structure 219 of the device above the top of the polishing stop layer 213, the contact area between the polishing stop layer 213 and the planarization equipment will be small, making the polishing stop effect of the polishing stop layer 213 weak. As a result, the height of the gate structure 219 of the device cannot reach the target height required by the process, increasing the probability of inconsistent height of the gate structure 219 of the device, and thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the lateral dimension of the polishing stop layer 213 located at the bottom of the first trench is 6 nanometers to 20 nanometers. As an example, the lateral dimension of the polishing stop layer 213 located at the bottom of the first trench is 10 nanometers or 15 nanometers.
[0048] It should also be noted that the thickness of the polishing stop layer 213 should not be too large or too small. If the thickness of the polishing stop layer 213 is too large, it will easily lead to a smaller remaining space in the second trench. During the formation of the isolation structure, the increased aspect ratio of the remaining space in the second trench will increase the difficulty of forming the isolation structure. Furthermore, during the planarization process of the device gate structure 219 above the top of the polishing stop layer 213, some of the polishing stop layer 213 will also be consumed. If the thickness of the polishing stop layer 213 is too small, the risk of the polishing stop layer 213 being completely consumed increases, rendering it unable to stop the polishing process and increasing the probability of inconsistent heights of the device gate structure 219, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the polishing stop layer 213 is 3 nanometers to 8 nanometers.
[0049] In this embodiment, the top of the grinding stop layer 213 is flush with the top of the interlayer medium layer 202, which improves the flatness of the top surface of the grinding stop layer 213 and the interlayer medium layer 202.
[0050] The isolation structure 212 provides electrical isolation for the gate structures 219 of adjacent devices, reducing the risk of contact between the gate structures 219 of adjacent devices.
[0051] In this embodiment, the material of the isolation structure 212 includes one or more of SiN, SiO2, Al2O3 and AlN.
[0052] It should be noted that SiN, SiO2, Al2O3, and AlN are all dielectric materials with good insulating properties, which can provide electrical isolation for the gate structures 219 of adjacent devices. As an example, the material of the isolation structure 212 is SiN.
[0053] In this embodiment, the top of the isolation structure 212 is flush with the top of the grinding stop layer 213. Since the top of the grinding stop layer 213 is flush with the top of the interlayer dielectric layer 202, the tops of the isolation structure 212, the grinding stop layer 213, and the interlayer dielectric layer 202 are flush, which improves the flatness of the top surfaces of the isolation structure 212, the grinding stop layer 213, and the interlayer dielectric layer 202.
[0054] When the device is in operation, the device gate structure 219 is used to control the opening or closing of the conductive channel.
[0055] In this embodiment, the device gate structure 219 is a metal gate structure.
[0056] The device gate structure 219 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) covering the gate dielectric layer.
[0057] The gate dielectric layer is used to isolate the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.
[0058] The gate electrode layer is used for subsequent electrical connection with external interconnect structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.
[0059] As an example, the gate electrode layer may include a work function layer and an electrode layer located on the work function layer, wherein the work function layer is used to regulate the threshold voltage of the transistor. In other embodiments, the gate electrode layer may also consist only of a work function layer.
[0060] Figures 9 to 19 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0061] refer to Figure 9A substrate (not shown) is provided, on which a gate structure 103 is formed, and an interlayer dielectric layer 102 is formed on the top of the exposed portion of the substrate of the gate structure 103, the interlayer dielectric layer 102 covering the top of the gate structure 103.
[0062] The substrate is used to provide a process platform for subsequent process manufacturing.
[0063] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 100 and fins 101 protruding from the substrate 100. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is correspondingly a planar substrate.
[0064] In this embodiment, the material of the fin 101 is the same as the material of the substrate 100, which is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium ionide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
[0065] In this embodiment, the method for forming the semiconductor structure further includes: after forming the fin 101, forming an isolation layer (not shown) on the substrate 100 exposed by the fin 101, the isolation layer covering part of the sidewall of the fin 101.
[0066] The isolation layer is used to isolate adjacent devices. The material of the isolation layer can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer is silicon oxide.
[0067] The gate structure 103 is a pseudo-gate structure, used to occupy space for the subsequent formation of the device gate structure.
[0068] In this embodiment, the gate structure 103 is a polysilicon gate structure, that is, the gate structure 103 includes a pseudo gate layer, and the material of the pseudo gate layer is polysilicon.
[0069] In other embodiments, the material of the dummy gate layer may also be other materials such as amorphous carbon, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon carbonitride.
[0070] As an example, the gate structure 103 is a single-layer structure, and the gate structure 103 is a pseudo-gate layer.
[0071] In other embodiments, the gate structure may also be a stacked structure, which includes a dummy gate oxide layer and a dummy gate layer located on the dummy gate oxide layer.
[0072] In this embodiment, during the step of forming the gate structure 103, a gate cap layer 105 is also formed on the top of the gate structure 103.
[0073] The gate cap layer 105 is used as an etching mask for forming the gate structure 103.
[0074] The gate cap layer 105 is made of one or more of silicon oxide, silicon nitride, titanium nitride, and aluminum oxide. As an example, the gate cap layer 105 is made of silicon nitride.
[0075] In this embodiment, during the step of providing the substrate, an active drain doped layer (not shown) is formed in the fins 101 on both sides of the gate structure 103.
[0076] The source and drain doped layers are used as the source and drain regions of the transistor.
[0077] In this embodiment, after the gate structure 103 is formed, the source and drain doped layers are formed in the fins 101 on both sides of the gate structure 103 by an epitaxial process.
[0078] When forming an NMOS transistor, the source / drain doped layer includes a stress layer doped with N-type ions. The stress layer is made of Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P-ions, As-ions, or Sb-ions. When forming a PMOS transistor, the source / drain doped layer includes a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The P-type ions are B-ions, Ga-ions, or In-ions.
[0079] The interlayer dielectric layer 102 serves to isolate adjacent devices and also provides a process basis for the subsequent formation of grooves.
[0080] The interlayer dielectric layer 102 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the interlayer dielectric layer 102 is made of silicon oxide.
[0081] The sidewall 106 is used to protect the sidewalls of the gate structure 103. The sidewall 106 can be a single-layer structure or a multilayer structure, and the material of the sidewall 106 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 106 is a single-layer structure, and the material of the sidewall 106 is silicon oxide.
[0082] refer to Figures 10 to 11A portion of the gate structure 103 is removed to form a trench 109 surrounded by the remaining gate structure 103 and the interlayer dielectric layer 102. The trench 109 includes a first trench 108 and a second trench 107 located on and connected to the first trench 108. The lateral direction is perpendicular to the extension direction of the gate structure 103 and parallel to the substrate surface. The lateral dimension of the first trench 107 is larger than the lateral dimension of the second trench 108.
[0083] The groove 109 provides space for the subsequent formation of the grinding stop layer and isolation structure.
[0084] In this embodiment, since the lateral dimension of the first trench 107 is larger than that of the second trench 108, the lateral dimension of the grinding stop layer subsequently formed at the bottom of the first trench 107 meets the process requirements. Correspondingly, during the subsequent planarization process of the device gate structure formed above the top of the grinding stop layer, the grinding stop layer has a large contact area with the equipment used for planarization, enabling the grinding stop layer to play the role of grinding stop. This allows the height of the device gate structure to reach the target height required by the process, reducing the probability of height inconsistency of the device gate structure and thus improving the performance of the semiconductor structure.
[0085] In this embodiment, along the extending direction of the gate structure 103, the trench 109 is located in the gate structure 103, and the sidewall of the first trench 107 is flush with the sidewall of the second trench 108.
[0086] Specifically, along the extension direction of the gate structure 103, the sidewall of the first trench 107 is flush with the sidewall of the second trench 108, so that the interlayer dielectric layer 102 can completely cover the remaining sidewall of the gate structure 103, reducing the probability of contact between the gate structures of the device formed subsequently, thereby improving the performance of the semiconductor structure.
[0087] In this embodiment, the step of forming the trench 109 includes: as follows Figure 10 As shown, a portion of the thickness of the gate structure 103 and the adjacent portion of the interlayer dielectric layer 102 are removed, and a first trench 107 is formed in the interlayer dielectric layer 102; as Figure 11 As shown, along the first trench 107, the remaining gate structure 103 is removed, and a second trench 108 is formed in the interlayer dielectric layer 102. The second trench 108 and the first trench 107 located on the second trench 108 and connected to the second trench 108 constitute the trench 109.
[0088] In this embodiment, the process for forming the trench 109 includes a dry etching process. In other embodiments, the process for forming the trench 109 may also be a wet etching process.
[0089] In other embodiments, the step of forming the trench may further include: removing a portion of the gate structure to form an opening in the interlayer dielectric layer; forming a filling layer in the opening, wherein the filling layer exposes a portion of the sidewall of the opening (i.e., exposes a portion of the sidewall of the interlayer dielectric layer); etching the portion of the sidewall of the interlayer dielectric layer exposed by the filling layer; and after etching the portion of the sidewall of the interlayer dielectric layer exposed by the filling layer, removing the filling layer to form a trench surrounded by the remaining gate structure and the interlayer dielectric layer.
[0090] It should be noted that, in the step of forming the trench 109, the gate cap layer 105 and the sidewall 106 located in the trench 109 are also removed.
[0091] refer to Figures 12 to 14 A grinding stop layer 113 is formed at the bottom and sidewall of the second trench 108 and at the bottom of the first trench 107, and an isolation structure 112 is formed in the remaining space of the second trench 108 and at the bottom of the first trench 107.
[0092] Specifically, during the subsequent planarization process of the device gate structure formed above the top of the grinding stop layer 113, the grinding stop layer 113 located at the bottom of the first trench 107 plays a role in stopping the grinding, so that the height of the device gate structure can reach the target height, thereby increasing the probability of the device gate structure having a consistent height.
[0093] The isolation structure 112 provides electrical isolation for the gate structures of adjacent devices that are subsequently formed, reducing the risk of contact between the gate structures of adjacent devices.
[0094] Reference Figures 12 to 14 The steps for forming the grinding stop layer 113 and the isolation structure 112 are described in detail.
[0095] refer to Figure 12 A grinding stop material layer 110 is formed on the sidewalls and bottom of the first trench 107, the sidewalls and bottom of the second trench 108, and the top of the interlayer medium layer 102.
[0096] The grinding stop material layer 110 provides the process basis for forming the grinding stop layer 113.
[0097] In this embodiment, the process for forming the grinding stop material layer 110 includes atomic layer deposition.
[0098] Specifically, the atomic layer deposition process includes multiple atomic layer deposition cycles, which helps to improve the thickness uniformity of the grinding stop layer 113. Furthermore, the atomic layer deposition process has good step coverage performance, resulting in a high degree of adhesion between the grinding stop material layer 110 and the interlayer dielectric layer 102.
[0099] refer to Figure 13 After the grinding stop material layer 110 is formed, the remaining space in the groove 109 is filled with an isolation material layer 111.
[0100] The insulating material layer 111 provides the technological basis for forming the insulating structure 112.
[0101] In this embodiment, the process for forming the isolation material layer 111 includes chemical vapor deposition. In other embodiments, the process for forming the isolation material layer may also be atomic layer deposition.
[0102] It should be noted that, in the step of forming the isolation material layer 111, the isolation material layer 111 also covers the top of the interlayer dielectric layer 102.
[0103] refer to Figure 14 The grinding stop material layer 110 on the top of the interlayer medium layer 102 and the sidewall of the first trench 107, as well as the isolation material layer 111 on the top of the interlayer medium layer 102 and the first trench 107, are removed. The remaining grinding stop material layer 110 located at the bottom and sidewall of the second trench 108 and the bottom of the first trench 107 serves as the grinding stop layer 113, and the isolation material layer 111 located in the second trench 108 and the bottom of the first trench 107 serves as the isolation structure 112.
[0104] It should be noted that in this embodiment, the grinding stop material layer 110 on the top of the interlayer dielectric layer 102 and the sidewall of the first trench 107, as well as the isolation material layer in the top of the interlayer dielectric layer 102 and the first trench 107, are removed in the same etching step, reducing the number of process steps and lowering the process cost. In other embodiments, the isolation material layer in the top of the interlayer dielectric layer 102 and the first trench 107 may be removed first, and then the grinding stop material layer 110 in the top of the interlayer dielectric layer 102 and the sidewall of the first trench 107 may be removed.
[0105] In this embodiment, the process of removing the grinding stop material layer 110 on the top of the interlayer dielectric layer 102 and the sidewall of the first trench 107, as well as the isolation material layer 111 in the top of the interlayer dielectric layer 102 and the first trench 107, includes a dry etching process.
[0106] Since the polishing stop material layer 110 and the isolation material layer 111 have a high etching selectivity with the interlayer dielectric layer 102, the dry etching process has anisotropic dry etching characteristics. In the process of removing the polishing stop material layer 110 from the top of the interlayer dielectric layer 102 and the sidewall of the first trench 107, as well as the isolation material layer 111 from the top of the interlayer dielectric layer 102 and the first trench 107, the use of the dry etching process can reduce damage to other films in the semiconductor structure.
[0107] Moreover, the dry etching process has the characteristics of anisotropic etching, which can achieve vertical etching. This reduces the thickness of the polishing stop material layer 110 and the isolation material layer 111, while improving the flatness and thickness uniformity of the top surface of the polishing stop layer 113 and the isolation structure 112, thereby increasing the probability of high consistency of the gate structure of the device formed subsequently.
[0108] It should be noted that the lateral dimension of the polishing stop layer 113 located at the bottom of the first trench 107 should not be too large or too small. If the lateral dimension of the polishing stop layer 113 is too large, it will easily occupy too much space in the formation of the isolation structure 112, making the process dimensions of the isolation structure 112 unable to meet the process requirements. Consequently, the electrical isolation effect of the isolation structure 112 on the gate structures of adjacent devices is reduced, increasing the probability of contact between the gate structures of adjacent devices, thereby affecting the performance of the semiconductor structure. If the lateral dimension of the polishing stop layer 113 is too small, during the subsequent planarization process of the device gate structure above the top of the polishing stop layer 113, the contact area between the polishing stop layer 113 and the planarization equipment is small, making the polishing stop layer 113 unable to play its role in stopping the polishing. As a result, the height of the device gate structure cannot reach the target height required by the process, increasing the probability of inconsistent device gate structure heights, and thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the lateral dimension of the polishing stop layer 113 located at the bottom of the first trench 107 is 6 nanometers to 20 nanometers. As an example, the lateral dimension of the grinding stop layer 113 located at the bottom of the first trench 107 is 10 nanometers or 15 nanometers.
[0109] It should also be noted that the thickness of the polishing stop layer 113 should not be too large or too small. If the thickness of the polishing stop layer 113 is too large, it will easily lead to a smaller remaining space in the second trench 108. During the subsequent formation of the isolation structure, the increased aspect ratio of the remaining space in the second trench 108 will increase the difficulty of forming the isolation structure. Furthermore, during the planarization process of the device gate structure above the top of the polishing stop layer 113, some of the polishing stop layer 113 will be consumed. If the thickness of the polishing stop layer 113 is too small, the risk of the polishing stop layer 113 being completely consumed increases, rendering it unable to stop the polishing process and increasing the probability of inconsistent device gate structure height, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the polishing stop layer 113 is 3 nanometers to 8 nanometers.
[0110] In this embodiment, the material of the grinding stop layer 113 includes one or more of a-Si and SiOC.
[0111] Specifically, during the subsequent planarization process of the device gate structure above the top of the grinding stop layer 113, the material used for the device gate structure has a higher grinding selectivity than a-Si and SiOC. This allows the grinding stop layer 113 to be retained during the removal of part of the device gate structure, meaning that the top of the grinding stop layer 113 can be used as the stop position for the planarization process, thereby increasing the probability of the device gate structure being highly consistent.
[0112] In this embodiment, the material of the isolation structure 112 includes one or more of SiN, SiO2, Al2O3 and AlN.
[0113] It should be noted that SiN, SiO2, Al2O3, and AlN are all dielectric materials with good insulating properties, which can provide electrical isolation for the gate structures of adjacent devices. As an example, the material of the isolation structure 112 is SiN.
[0114] refer to Figures 15 to 16 A protective layer 116 is formed in the first trench 107, and the top of the protective layer 116 is flush with the top of the gate structure 103.
[0115] During the subsequent formation of the gate opening in the interlayer dielectric layer 102, the protective layer 116 protects the polishing stop layer 113 and the isolation structure 112, reducing the risk of damage to the polishing stop layer 113 and the isolation structure 112 caused by the relevant etching process, thereby improving the performance of the semiconductor structure.
[0116] In this embodiment, the step of forming the protective layer 116 includes: as follows Figure 15 As shown, a protective material layer 161 is formed in the first groove 107 and on top of the interlayer dielectric layer 102; as Figure 16 As shown, with the top of the gate cap layer 105 as the grinding stop position, the interlayer dielectric layer 102 and the protective layer material layer 161 above the gate cap layer 105 are planarized, and the remaining protective material layer 161 in the first trench 107 serves as the protective layer 116.
[0117] In this embodiment, the process of forming a protective material layer 161 in the first groove 107 and on top of the interlayer dielectric layer 102 includes a chemical vapor deposition process. In other embodiments, the process of forming the protective material layer can also be a spin coating process.
[0118] The protective layer 116 is made of one or both of SiO2 and SiN. As an example, the protective layer 116 is made of SiO2. Since the protective layer 116 and the interlayer dielectric layer 102 are made of the same material, during the planarization process of the interlayer dielectric layer 102 and the protective layer material layer 161 above the gate cap layer 105, the grinding selectivity between the interlayer dielectric layer 102 and the protective layer material layer 161 and the gate cap layer 105 can be utilized to planarize the interlayer dielectric layer 102 and the protective layer material layer 161 above the gate cap layer 105 in the same step.
[0119] In this embodiment, the process of planarizing the interlayer dielectric layer 102 and the protective layer material layer 161 above the gate cap layer 105 includes a chemical mechanical polishing process.
[0120] refer to Figure 17 After forming the polishing stop layer 113 and the isolation structure 112, the remaining gate structure 103 is removed, and a gate opening 117 is formed in the interlayer dielectric layer 102.
[0121] Specifically, the gate opening 117 provides space for the subsequent formation of the device gate structure.
[0122] In this embodiment, the step of forming a gate opening 117 in the interlayer dielectric layer 102 includes: forming a mask layer 118 on top of the protective layer 116 and the interlayer dielectric layer 102, the mask layer 118 exposing the top of the gate structure 103; patterning the gate structure 103 using the mask layer 118 as a mask, and forming a gate opening 117 in the interlayer dielectric layer 102.
[0123] In this embodiment, the mask layer 118 includes an organic material layer, an anti-reflective coating on the organic material layer, and a photoresist layer on the anti-reflective coating.
[0124] The organic material layer is made of organic materials. In this embodiment, the organic material layer is spin-on carbon (SOC). In other embodiments, the organic material layer may also be made of other organic materials, such as one or more of the following: ODL (organic dielectric layer), DUO (Deep UV Light Absorbing Oxide), and APF (Advanced Patterning Film).
[0125] The materials used in anti-reflective coatings include BARC (bottom anti-reflective coating) materials. As an example, the BARC material is Si-ARC (silicon-containing anti-reflective coating) material.
[0126] Specifically, during the formation of the mask layer 118, the photoresist layer is used as a mask to sequentially etch the anti-reflective coating and the organic material layer, thereby forming the mask layer 118 on top of the protective layer 116 and the interlayer dielectric layer 102, and exposing the gate structure 103.
[0127] It should be noted that during the formation of the mask layer 118, the anti-reflective coating and the organic material layer are etched sequentially using the photoresist layer as a mask.
[0128] It should also be noted that in other embodiments, the mask layer may also be made of a dielectric material. For example, the dielectric material may include one or both of silicon oxide and silicon nitride.
[0129] In this embodiment, the process of patterning the gate structure 103 includes a dry etching process.
[0130] refer to Figure 18 A device gate structure 119 is formed in the gate opening 117.
[0131] When the device is in operation, the device gate structure 119 is used to control the opening or closing of the conductive channel.
[0132] In this embodiment, the device gate structure 119 is a metal gate structure.
[0133] The device gate structure 119 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) covering the gate dielectric layer.
[0134] The gate dielectric layer is used to isolate the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.
[0135] The gate electrode layer is used for subsequent electrical connection with external interconnect structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.
[0136] As an example, the gate electrode layer may include a work function layer and an electrode layer located on the work function layer, wherein the work function layer is used to regulate the threshold voltage of the transistor. In other embodiments, the gate electrode layer may also consist only of a work function layer.
[0137] refer to Figure 19 Using the top of the polishing stop layer 113 in the first trench 107 as the stop position, the device gate structure 119 above the top of the polishing stop layer 113 is planarized.
[0138] Specifically, the device gate structure 119 above the top of the grinding stop layer 113 is planarized so that the height of the device gate structure 119 reaches the target height and meets the process requirements.
[0139] In this embodiment, the process for planarizing the device gate structure 119 above the top of the polishing stop layer 113 includes a chemical mechanical polishing process.
[0140] In this embodiment, during the planarization process of the device gate structure 119 above the top of the polishing stop layer 113, the removal rate of the polishing stop layer 113 is less than the removal rate of the device gate structure 119. Accordingly, while removing a portion of the thickness of the device gate structure 119, the polishing stop layer 113 can be retained, so that the top of the polishing stop layer 113 can play the role of stopping the polishing.
[0141] It should be noted that the polishing selectivity ratio between the device gate structure 119 and the polishing stop layer 113 should not be too small or too large. If the polishing selectivity ratio between the device gate structure 119 and the polishing stop layer 113 is too small, it means that the removal rate of the device gate structure 119 is similar to that of the polishing stop layer 113. During the planarization process of the device gate structure 119 above the top of the polishing stop layer 113, the probability of the polishing stop layer 113 being removed increases, thereby greatly increasing the probability of inconsistent height of the device gate structure 119. If the polishing selectivity ratio between the device gate structure 119 and the polishing stop layer 113 is too large, the device gate structure 119 is easily damaged during the planarization process of the device gate structure 119 above the top of the polishing stop layer 113. Therefore, in this embodiment, in the step of planarizing the device gate structure above the top of the polishing stop layer, the polishing selectivity ratio between the device gate structure and the polishing stop layer is between 10:1 and 20:1.
[0142] In this embodiment, the process of planarizing the device gate structure 119 above the top of the grinding stop layer 113 also includes removing the protective layer 116.
[0143] Specifically, removing the protective layer 116 results in a high degree of flatness on the top of the polishing stop layer 113, the isolation structure 112, the interlayer dielectric layer 102, and the device gate structure 119, providing a process foundation for subsequent process fabrication, which will not be elaborated further here.
[0144] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a gate structure is formed, sidewalls are formed on the sidewalls of the gate structure, and an interlayer dielectric layer is formed on the top of the exposed portion of the substrate of the gate structure, the interlayer dielectric layer covering the top of the gate structure; A portion of the gate structure is removed to form a trench surrounded by the remaining gate structure and the interlayer dielectric layer. The trench includes a second trench and a first trench located on and connected to the second trench. The trench is lateral in a direction perpendicular to the extension direction of the gate structure and parallel to the substrate surface. The lateral dimension of the first trench is larger than that of the second trench. A grinding stop layer is formed at the bottom and sidewall of the second trench, at the bottom of the first trench, and an isolation structure is formed in the remaining space of the trench, wherein the lateral dimension of the grinding stop layer at the bottom of the first trench is larger than the lateral dimension of the sidewall. After forming the grinding stop layer and isolation structure, the remaining gate structure is removed, and a gate opening is formed in the interlayer dielectric layer; A device gate structure is formed in the gate opening; Using the top of the grinding stop layer in the first trench as the stop position, the device gate structure above the top of the grinding stop layer is planarized.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, Along the extending direction of the gate structure, the trench is located in the gate structure, and the sidewall of the first trench is flush with the sidewall of the second trench.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps of forming the grinding stop layer and the isolation structure include: forming a grinding stop material layer on the sidewall and bottom of the first trench, the sidewall and bottom of the second trench, and the top of the interlayer dielectric layer; after forming the grinding stop material layer, filling the remaining space of the trench with an isolation material layer; removing the grinding stop material layer on the top of the interlayer dielectric layer and the sidewall of the first trench, as well as the isolation material layer on the top of the interlayer dielectric layer and in the first trench, with the remaining grinding stop material layer located at the bottom and sidewall of the second trench and the bottom of the first trench serving as the grinding stop layer, and the isolation material layer located in the second trench and the bottom of the first trench serving as the isolation structure.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the trench includes: removing a portion of the thickness of the gate structure and a portion of the interlayer dielectric layer adjacent to the gate structure, forming a first trench in the interlayer dielectric layer; removing the remaining gate structure along the first trench, forming a second trench in the interlayer dielectric layer, wherein the second trench and the first trench located at the top of the second trench and connected to the second trench constitute the trench.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the polishing stop layer and the isolation structure, and before removing the remaining gate structure, the method further includes: forming a protective layer in the first trench, the top of the protective layer being flush with the top of the gate structure; The step of forming a gate opening in the interlayer dielectric layer includes: forming a mask layer on top of the protective layer and the interlayer dielectric layer, the mask layer exposing the top of the gate structure; patterning the gate structure using the mask layer as a mask to form a gate opening in the interlayer dielectric layer; The process of planarizing the device gate structure above the top of the grinding stop layer also includes removing the protective layer.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The lateral dimensions of the grinding stop layer located at the bottom of the first trench are 6 nanometers to 20 nanometers.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the grinding stop layer is 3 nanometers to 8 nanometers.
8. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of planarizing the device gate structure above the top of the polishing stop layer, the removal rate of the polishing stop layer is less than the removal rate of the device gate structure.
9. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of planarizing the device gate structure above the top of the polishing stop layer, the polishing selectivity ratio of the device gate structure to the polishing stop layer is between 10:1 and 20:
1.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the grinding stop layer includes one or both of a-Si and SiOC.
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The gate structure of the device is a metal gate structure.
12. A semiconductor structure formed using the formation method according to any one of claims 1 to 11, characterized in that, include: Base; The device gate structure is located on the substrate; Sidewall, located on the sidewall of the gate structure of the device; An interlayer dielectric layer is located on top of the substrate exposed by the device gate structure and covers the sidewalls of the device gate structure; A trench is located between adjacent device gate structures and penetrates the interlayer dielectric layer. The trench includes a second trench and a first trench located on and connected to the second trench. The trench is lateral in a direction that is perpendicular to the extension direction of the device gate structure and parallel to the substrate surface. The lateral dimension of the first trench is larger than that of the second trench. A grinding stop layer is located at the bottom and sidewall of the second trench, as well as in the first trench, and the lateral dimension of the grinding stop layer is greater than the lateral dimension of the sidewall; An isolation structure is located in the remaining space of the trench.
13. The semiconductor structure as described in claim 12, characterized in that, Along the extension direction of the device gate structure, the trench is located in the device gate structure, and the sidewall of the first trench is flush with the sidewall of the second trench.
14. The semiconductor structure as claimed in claim 12, characterized in that, The lateral dimensions of the grinding stop layer located in the first trench are 6 nanometers to 20 nanometers.
15. The semiconductor structure as described in claim 12, characterized in that, The material of the grinding stop layer includes one or both of a-Si and SiOC.
16. The semiconductor structure as claimed in claim 12, characterized in that, The material of the isolation structure includes one or more of SiN, SiO2, Al2O3 and AlN.
17. The semiconductor structure as claimed in claim 12, characterized in that, The gate structure of the device is a metal gate structure.
18. The semiconductor structure as claimed in claim 12, characterized in that, The device gate structure includes a gate dielectric layer and a gate electrode layer covering the gate dielectric layer; The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.