IGBT device and method of manufacturing the same

Abstract

An IGBT device includes an n-type semiconductor layer, a p-type collector region formed within the n-type semiconductor layer, an n-type field stop region located above the p-type collector region, an n-type drift region located above the n-type field stop region, a plurality of trenches extending into the n-type drift region, the trenches including first trenches in an upper portion and second trenches in a lower portion, the first trenches having a width greater than the second trenches, p-type pillars located within the second trenches, an insulating dielectric layer located within the first trenches and above the p-type pillars, a gate oxide and a gate located within the first trenches and proximate to a sidewall of the first trenches, p-type body regions located between adjacent first trenches, n-type emitter regions located within the p-type body regions, and n-type charge storage regions located below the p-type body regions and between adjacent trenches.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of IGBT devices, and particularly relates to an IGBT device and a manufacturing method thereof. BACKGROUND

[0002] An insulated gate bipolar transistor (IGBT) device is a device combined by a MOS transistor and a bipolar transistor, the input terminal of which is a MOS transistor and the output terminal of which is a PNP transistor. The IGBT device combines the advantages of the two devices, has the advantages of small driving power and fast switching speed of the MOS transistor, and has the advantages of low saturation voltage drop and large capacity of the bipolar transistor. The IGBT device has been widely used in modern power electronics technology, especially occupies a dominant position in high-frequency large and medium power tube applications. The field stop IGBT (FS-IGBT) device in the prior art uses a single deep trench MOS structure as the main structure of the active region, and reduces the saturation voltage drop and the turn-off loss of the device by increasing the doping concentration of the n-type charge storage region. However, in the reverse bias state, the higher the doping concentration at the n-type charge storage region is, the smaller the breakdown voltage of the device is. The influence of the doping concentration of the n-type charge storage region on the breakdown voltage limits the optimization of the saturation voltage drop and the turn-off loss of the FS-IGBT device by adjusting the doping concentration of the n-type charge storage region. SUMMARY

[0003] Therefore, the purpose of the present application is to provide an IGBT device and a manufacturing method thereof, so as to optimize the saturation voltage drop and the turn-off loss of the IGBT device.

[0004] An IGBT device provided by an embodiment of the present application comprises an n-type semiconductor layer, and a p-type collector region, an n-type field stop region, an n-type drift region, a plurality of trenches, a p-type column, an insulating dielectric layer and a gate electrode are formed in the n-type semiconductor layer.

[0005] The p-type collector region is located on the bottom of the n-type semiconductor layer.

[0006] The n-type field stop region is located on the p-type collector region.

[0007] The n-type drift region is located on the n-type field stop region.

[0008] The plurality of trenches extend into the n-type drift region, and the plurality of trenches comprise a first trench at an upper portion and a second trench at a lower portion.

[0009] The p-type column is located in the second trench.

[0010] The insulating dielectric layer is located in the first trench and above the p-type column.

[0011] a gate oxide layer and a gate electrode located in the first trench and at a position close to a side wall of the first trench;

[0012] a p-type body region located between adjacent first trenches, and an n-type emitter region located in the p-type body region;

[0013] an n-type charge storage region located below the p-type body region and between adjacent trenches.

[0014] Optionally, the p-type pillar extends upward from the second trench into the first trench.

[0015] Optionally, the gate electrode surrounds the insulating medium layer in the first trench.

[0016] A manufacturing method of an IGBT device according to an embodiment of the present application, comprising:

[0017] forming a hard mask layer on the provided n-type semiconductor layer, defining a position of a trench through a photoetch process, and etching the hard mask layer to expose the n-type semiconductor layer;

[0018] using the hard mask layer as a mask, performing anisotropic etching and isotropic etching on the n-type semiconductor layer to form a first trench in the n-type semiconductor layer;

[0019] using the hard mask layer as a mask, performing n-type ion implantation on the n-type semiconductor layer through the first trench and annealing to form an n-type charge storage region at the bottom of the first trench in the n-type semiconductor layer;

[0020] forming a gate oxide layer on the surface of the first trench;

[0021] forming a gate polysilicon layer and performing back-etching on the gate polysilicon layer using the hard mask layer as a mask to form a gate electrode at a position of a side wall of the first trench;

[0022] forming a protective oxide layer on the surface of the gate electrode;

[0023] etching away the gate oxide layer at the bottom of the first trench using the hard mask layer as a mask, and continuing to etch the n-type semiconductor layer to form a second trench below the first trench;

[0024] performing p-type polysilicon epitaxial growth and performing back-etching on the p-type polysilicon using the hard mask layer as a mask to form a p-type pillar in the second trench;

[0025] depositing an insulating layer and performing back-etching on the insulating layer using the hard mask layer as a mask to form an insulating medium layer above the p-type pillar in the first trench;

[0026] Etching away the hard mask layer, forming a p-type body region in the n-type semiconductor layer, and forming an n-type emitter region in the p-type body region.

[0027] Optionally, further comprising: forming an interlayer insulating layer on the surface of the n-type semiconductor layer, and a source metal and a gate metal.

[0028] Optionally, further comprising: forming an n-type field stop region and a p-type collector region at the bottom of the n-type semiconductor layer.

[0029] Optionally, further comprising: forming a collector metal on the bottom surface of the n-type semiconductor layer.

[0030] The present application sets a p-type column in the second trench, forms a super junction structure between the p-type column and the n-type drift region, can enhance the conductivity modulation effect of the drift region, improve the withstand voltage of the IGBT device, and thus can realize the optimization of the saturation voltage drop and the turn-off loss of the IGBT device by improving the doping concentration of the n-type charge storage region. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the example embodiments of the present application, the drawings needed in the description of the embodiments will be briefly introduced as follows.

[0032] Figure 1 is a cross-sectional structure schematic diagram of an embodiment of the IGBT device of the present application;

[0033] Figures 2 to 9 is a cross-sectional structure schematic diagram of the main process nodes of an embodiment of the manufacturing method of the IGBT device of the present application. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the present application more clear, the technical solutions of the present application will be described in detail below by combining the drawings in the embodiments of the present application, through specific ways.

[0035] Figure 1 is a cross-sectional structure schematic diagram of an embodiment of the IGBT device provided by the present application, as Figure 1 shown, the IGBT device of the present application comprises an n-type semiconductor layer 20, and the n-type semiconductor layer 20 is formed with: a p-type collector region 41, an n-type field stop region 42 located above the p-type collector region 41, and an n-type drift region 43 located above the n-type field stop region 42.

[0036] A plurality of trenches extending into the n-type drift region 43, for the convenience of display, only two trench structures are exemplarily shown in the embodiment of the present application. The trenches include a first upper trench and a second lower trench, and the width of the first trench is greater than the width of the second trench. The p-type pillars 25 are located in the second trench, and the p-type pillars 25 can be located only in the second trench (as shown), or the p-type pillars 25 can extend upward from the second trench into the first trench (not shown in the figure). The insulating medium layer 26 is located in the first trench and above the p-type pillars 25, and the gate oxide layer 22 and the gate 23 are located in the first trench and close to the side wall position of the first trench. Figure 1 In the cross-sectional structure shown, the gate 23 is located on both sides of the insulating medium layer 26, and optionally, the gate 26 can surround the insulating medium layer 26 in the first trench. It should be noted that the IGBT device provided by the embodiment of the present application can also include a protective oxide layer (not shown in the figure) between the gate 23 and the insulating medium layer 26, which is used to protect the gate 23 during etching of the gate oxide layer 22. Alternatively, it can also be understood that the insulating medium layer 26 includes insulating layers of multiple different materials, and the insulating medium layer close to the gate 23 side can be used as a protective oxide layer to protect the gate 23 during etching of the gate oxide layer 22. Figure 2

[0037] The p-type body region 27 is located between adjacent first trenches, the n-type emitter region 28 is located in the p-type body region 27, and the n-type charge storage region 21 is located below the p-type body region 27 and between adjacent trenches.

[0038] The IGBT device of the present application sets the p-type pillars in the second trench, and forms a super-junction structure between the p-type pillars and the n-type drift region, which can enhance the conductivity modulation effect of the drift region and improve the withstand voltage of the IGBT device, so that the optimization of the saturation voltage drop and the off-state loss of the IGBT device can be realized by increasing the doping concentration of the n-type charge storage region.

[0039] Figures 2 to 9 is a cross-sectional structure schematic diagram of the main process nodes of an embodiment of the manufacturing method of the IGBT device of the present application. As shown in Figures 2 to 9 The manufacturing method of an IGBT device of the present application includes:

[0040] First, as shown in Figure 2 A hard mask layer 30 is formed on the provided n-type semiconductor layer 20, and the position of the trench is defined by a photolithography process. The specific process includes: forming a layer of photoresist on the hard mask layer 30, then exposing and developing to form a pattern, then etching the hard mask layer 30 to expose the n-type semiconductor layer 20, and then removing the photoresist.

[0041] Next, as shown in Figure 3 ​As shown, the n-type semiconductor layer 20 is anisotropically etched and isotropically etched with the hard mask layer 30 as a mask, the anisotropic etching is used to etch the n-type semiconductor layer 20 downward, and the isotropic etching is used to etch the n-type semiconductor layer 20 in all directions, so as to form a first groove 31 in the n-type semiconductor layer 20, and the width of the first groove 31 can be larger than the opening width in the hard mask layer 30 through the isotropic etching.

[0042] Next, as shown in FIG. 3, a gate oxide layer 22 is formed on the surface of the first groove, and then a gate polysilicon layer is formed and etched back with the hard mask layer 30 as a mask to form a gate 23 at the sidewall position of the first groove 31. Figure 4 As shown, n-type ion implantation is performed on the n-type semiconductor layer 20 through the first groove 31 with the hard mask layer 30 as a mask, and annealing is performed, so as to form an n-type charge storage region 21 at the bottom of the first groove 31 in the n-type semiconductor layer 20, and the n-type ion can diffuse to a preset position through control of the annealing temperature and time, i.e., the forming region of the n-type charge storage region 21 is controlled.

[0043] Next, as shown in FIG. 4, a protective oxide layer 24 is formed on the surface of the gate 23, the protective oxide layer 24 is used to protect the gate 23 from etching in the process of etching the gate oxide layer 22, and then the gate oxide layer 22 at the bottom of the first groove is etched away with the hard mask layer 30 as a mask, and etching is continuously performed on the n-type semiconductor layer 20 to form a second groove 32 below the first groove. Figure 5 Next, as shown in FIG. 5, p-type polysilicon epitaxial growth is performed, and the formed p-type polysilicon is etched back with the hard mask layer 30 as a mask to form a p-type pillar 25 in the second groove. Through control of the etching process, the p-type pillar 25 can be located only in the second groove, or the p-type pillar 25 can be located in the second groove and extend upward into the first groove.

[0044] Figure 6 Next, as shown in FIG. 6, an insulating layer is deposited and etched back with the hard mask layer as a mask to form an insulating medium layer 26 above the p-type pillar 25 in the first groove, and then the hard mask layer is etched away. Since the gate 23 and the insulating medium layer 26 are both formed through a self-alignment process, the gate 23 surrounds the insulating medium layer 26 in the first groove at this time.

[0045] Next, as shown in FIG. 7, a protective oxide layer 24 is formed on the surface of the gate 23, the protective oxide layer 24 is used to protect the gate 23 from etching in the process of etching the gate oxide layer 22, and then the gate oxide layer 22 at the bottom of the first groove is etched away with the hard mask layer 30 as a mask, and etching is continuously performed on the n-type semiconductor layer 20 to form a second groove 32 below the first groove. Figure 7 Next, as shown in FIG. 8, p-type polysilicon epitaxial growth is performed, and the formed p-type polysilicon is etched back with the hard mask layer 30 as a mask to form a p-type pillar 25 in the second groove. Through control of the etching process, the p-type pillar 25 can be located only in the second groove, or the p-type pillar 25 can be located in the second groove and extend upward into the first groove.

[0046] Figure 8 Next, as shown in FIG. 9, an insulating layer is deposited and etched back with the hard mask layer as a mask to form an insulating medium layer 26 above the p-type pillar 25 in the first groove, and then the hard mask layer is etched away. Since the gate 23 and the insulating medium layer 26 are both formed through a self-alignment process, the gate 23 surrounds the insulating medium layer 26 in the first groove at this time.

[0047] Next, as shown in FIG. 10, a protective oxide layer 24 is formed on the surface of the gate 23, the protective oxide layer 24 is used to protect the gate 23 from etching in the process of etching the gate oxide layer 22, and then the gate oxide layer 22 at the bottom of the first groove is etched away with the hard mask layer 30 as a mask, and etching is continuously performed on the n-type semiconductor layer 20 to form a second groove 32 below the first groove. Figure 9 ​​As shown, the p-type body region 27 is formed in the n-type semiconductor layer 20, and the n-type emitter region 28 is formed in the p-type body region 27. It should be noted that when the p-type body region 27 and the n-type emitter region 28 are formed, an annealing process is needed, at this time, the n-type ions in the n-type charge storage region 21 will further diffuse, so that the n-type charge storage region 22 between the two adjacent p-type pillars 25 can be connected into a whole after diffusion (as shown in Figure 9 Alternatively, the n-type charge storage region 22 can not be connected after diffusion (this structure is not shown in the embodiments of the present application).

[0048] Finally, the manufacturing method of the IGBT device of the embodiments of the present application further comprises: forming an interlayer insulating layer on the surface of the n-type semiconductor layer, and forming a source metal and a gate metal; forming an n-type field stop region and a p-type collector region at the bottom of the n-type semiconductor layer; forming a collector metal on the bottom surface of the n-type semiconductor layer, and the above processes are all conventional processes in the industry, and will not be specifically shown and described in the embodiments of the present application.

[0049] Although the embodiments of the present application have been disclosed as above, it is not limited to the application listed in the specification and the embodiments, and can be fully applied to various fields suitable for the present application, and other modifications can be easily realized by those skilled in the art, therefore, the present application is not limited to specific details and the figures shown and described herein, without departing from the general concept defined by the claims and the equivalent scope.

Claims

1. A method of manufacturing an IGBT device, characterized by, The application relates to a method for manufacturing a vertical double diffused MOS transistor (VDMOS) and a vertical double diffused MOS transistor (VDMOS) manufactured by the method. The method comprises the following steps: forming a hard mask layer on a provided n-type semiconductor layer, defining the position of a groove through a photoetching process, and exposing the n-type semiconductor layer by etching the hard mask layer; Taking the hard mask layer as a mask, the n-type semiconductor layer is subjected to anisotropic etching and isotropic etching, and a first groove is formed in the n-type semiconductor layer; Taking the hard mask layer as a mask, the n-type semiconductor layer is subjected to n-type ion implantation through the first groove and annealing, and an n-type charge storage region is formed at the bottom of the first groove in the n-type semiconductor layer; A gate oxide layer is formed on the surface of the first groove; A gate polysilicon layer is formed, and the gate polysilicon layer is subjected to back etching taking the hard mask layer as a mask, and a gate is formed at the position of the sidewall of the first groove; A protective oxide layer is formed on the surface of the gate; The gate oxide layer at the bottom of the first groove is etched away taking the hard mask layer as a mask, and the n-type semiconductor layer is continuously etched, and a second groove is formed below the first groove; P-type polysilicon epitaxial growth is performed, and the p-type polysilicon is subjected to back etching taking the hard mask layer as a mask, and a p-type column is formed in the second groove; An insulating layer is deposited, and the insulating layer is subjected to back etching taking the hard mask layer as a mask, and an insulating medium layer is formed above the p-type column in the first groove; The hard mask layer is etched away, and a p-type body region is formed in the n-type semiconductor layer, and an n-type emitter region is formed in the p-type body region.

2. The method of manufacturing an IGBT device according to claim 1, wherein The application further comprises the following steps: An interlayer insulating layer, a source metal and a gate metal are formed on the surface of the n-type semiconductor layer.

3. The method of manufacturing an IGBT device according to claim 2, wherein The application further comprises the following steps: An n-type field stop region and a p-type collector region are formed at the bottom of the n-type semiconductor layer.

4. The method of manufacturing an IGBT device according to claim 3, wherein The application further comprises the following steps: A collector metal is formed on the bottom surface of the n-type semiconductor layer.

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