Trench gate super junction MOSFET and manufacturing method thereof

Abstract

The application provides a trench gate super junction MOSFET and a manufacturing method thereof. The trench gate super junction MOSFET comprises a substrate, a buffer zone, a first conductive type column, a second conductive type column, a body region, a source region, a body contact region, a trench gate structure, a gate structure, a source and a drain. The buffer zone is stacked above the substrate. The first conductive type column and the second conductive type column are juxtaposed and adjacent to the upper surface of the buffer zone. The body region is stacked on the second conductive type column. The source region and the body contact region are adjacent and both located on the upper surface layer of the body region. The trench gate structure penetrates the body region and the body contact region and extends into the second conductive type column. The gate structure is located on the upper surface of the first conductive type column. The source covers the upper surface of the device, and the drain covers the bottom surface of the substrate. The application sets the trench gate structure in the body contact region of the super junction MOSFET, so that the breakdown point of the device is located below the trench gate structure, the opening of the parasitic triode is inhibited, and the avalanche resistance of the device is increased.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a trench gate superjunction MOSFET and its fabrication method. Background Technology

[0002] The doping concentration of the N-type first pillar region in a superjunction power MOSFET can be much higher than that of a conventional power MOSFET, thus achieving a lower on-resistance at the same breakdown voltage. This is because the N-type and P-type first pillar regions are alternately arranged in the body region, compensating for each other at the breakdown voltage. Therefore, to achieve the same on-resistance, superjunction power MOSFETs have a smaller chip area, lower parasitic capacitance, and higher cost-effectiveness, and can be widely used in higher power and higher frequency applications. However, due to the mutual depletion of the N-type and P-type first pillar regions, the output capacitance of a superjunction power MOSFET exhibits abrupt changes, and when both the N-type and P-type first pillar regions are completely depleted, the output capacitance drops abruptly by several orders of magnitude. This results in extremely large dI / dt and dV / dt during the switching process of the superjunction MOSFET, leading to strong RLC oscillations and extremely high electromagnetic interference (EMI).

[0003] Currently, external circuit optimization and internal device optimization are commonly used to reduce excessive dI / dt and dV / dt during the switching process of superjunction power MOSFETs. External circuit optimization can be achieved by using a larger drive resistor or an RC snubber. Internal device optimization involves integrating a gate resistor and a larger Miller capacitor. However, using a larger drive resistor reduces switching speed, thereby increasing switching power consumption. Using an RC snubber increases system cost and reduces switching speed. Integrating a gate resistor may cause avalanche arcing within the device, leading to reliability issues. Integrating a larger Miller capacitor requires sacrificing part of the electron channel, thereby increasing the device's on-resistance and reducing switching speed, thus increasing switching losses.

[0004] Therefore, there is an urgent need for a superjunction MOSFET that can optimize the output capacitance without increasing the on-resistance and switching losses of the device. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a trench gate superjunction MOSFET and its fabrication method, which solves the problem of increased on-resistance and switching losses caused by optimizing the output capacitance of the superjunction MOSFET in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a trench gate superjunction MOSFET, comprising:

[0007] First conductivity type substrate;

[0008] A first conductivity type buffer is stacked on top of the substrate;

[0009] Multiple first conductive type pillars are disposed on the upper surface of the buffer and extend in a direction away from the substrate, and the first conductive type pillars include a first pillar region and a second pillar region stacked on the first pillar region;

[0010] Multiple second conductive type pillars are disposed on the upper surface of the buffer zone and located on both sides of the first pillar area. The sidewalls of the second conductive type pillars are adjacent to the sidewalls of the first pillar area, and the upper surface of the second conductive type pillars is flush with the upper surface of the first pillar area.

[0011] The second type of conductive body region is stacked on the second type of conductive pillar, and the upper surface of the body region is flush with the upper surface of the second pillar region, and the sidewall of the body region is adjacent to the sidewall of the second pillar region.

[0012] The adjacent first conductivity type source region and second conductivity type body contact region are located on the upper surface of the body region, and the source region and the body contact region are spaced at a predetermined distance from the first conductivity type pillar;

[0013] At least one trench gate structure extends through the body region and the body contact region, with the bottom of the trench gate structure extending downward into a second conductivity type pillar. The trench gate structure includes an isolation dielectric layer and a first gate, wherein the isolation dielectric layer at least covers the sidewalls and bottom surface of the first gate.

[0014] A gate structure is located on the upper surface of the second pillar region, and both ends of the gate structure extend above the source region. The gate structure includes a gate dielectric layer and a second gate, and the gate dielectric layer encloses the second gate.

[0015] The source and drain are provided, wherein the source covers the exposed surfaces of the gate structure, the trench gate structure, the body region, the source region and the body contact region, and the drain covers the bottom surface of the substrate.

[0016] Optionally, the first gate is electrically connected to at least one of the source and the second gate.

[0017] Optionally, the breakdown point of the trench gate superjunction MOSFET is located below the trench gate structure.

[0018] Optionally, the superjunction MOSFET further includes at least one second conductivity type conductive layer located in the second conductivity type pillar, and the doping concentration of the conductive layer is different from the doping concentration of the second conductivity type pillar.

[0019] Optionally, the trench gate structure extends into the conductive layer.

[0020] Optionally, the thickness of the conductive layer is less than the thickness of the second conductive type post, and the upper surface of the conductive layer is flush with the upper surface of the second conductive type post.

[0021] Optionally, when the first gate is electrically connected to the second gate and the conductive layer cannot form a fully depleted layer, the first gate, the isolation dielectric layer, and the conductive layer act as an input capacitance.

[0022] Optionally, when the first gate is electrically connected to the second gate and the conductive layer forms a fully depleted layer, the first gate, the isolation dielectric layer, and the conductive layer act as an output capacitance.

[0023] Optionally, at least one of the thickness and doping concentration of the conductive layer in the plurality of sequentially arranged second conductive type pillars is different, and at least one of the thickness and doping concentration of the plurality of conductive layers decreases or increases sequentially along the arrangement direction.

[0024] This invention also provides a method for fabricating a trench gate superjunction MOSFET, comprising the following steps:

[0025] A substrate of a first conductivity type is provided, and a buffer zone of the first conductivity type is formed on the upper surface of the substrate;

[0026] A plurality of first conductive type first pillar areas and second conductive type pillars located on both sides of the first pillar areas are formed on the upper surface of the buffer zone, and the sidewalls of the second conductive type pillars are adjacent to the sidewalls of the first pillar areas, and the upper surface of the first pillar areas is flush with the upper surface of the second conductive type pillars.

[0027] A first conductive type second column region is formed on the upper surface of the first column region to form a first conductive type column, and a second conductive type body region is formed on both sides of the second column region, located on the upper surface of the second conductive type column and adjacent to the side wall of the second column region, wherein the upper surface of the body region is flush with the upper surface of the second column region;

[0028] A first conductive type source region and a second conductive type body contact region are formed adjacent to each other in the upper surface layer of the body region, and the source region and the body contact region are spaced apart from the first conductive type pillar by a predetermined distance;

[0029] A trench is formed in at least one of the body contact areas, opening upwards, penetrating the body contact area and the body area and extending into the second conductivity type pillar, and an isolation dielectric layer and a first gate are formed in the trench to cover the inner wall of the trench to form a trench gate structure, and the isolation dielectric layer at least covers the sidewall and bottom surface of the first gate.

[0030] A gate structure is formed on the upper surface of the second pillar region, and both ends of the gate structure extend above the source region. The gate structure includes a gate dielectric layer and a second gate, and the gate dielectric layer encapsulates the second gate.

[0031] An exposed surface covering the gate structure and the trench gate structure, as well as a source electrode covering the upper surface of the source region and the body contact region, are formed on the upper surface of the gate structure, and a drain electrode is formed on the bottom surface of the substrate.

[0032] As described above, the trench-gate superjunction MOSFET and its fabrication method of the present invention redesign the structure of the superjunction MOSFET by setting a trench gate structure in the body contact region that penetrates the body contact region and the body region and extends downward to the second conductivity type pillar. This makes the breakdown point of the trench-gate superjunction MOSFET located at the bottom of the trench, suppressing the turn-on of parasitic transistors and increasing the avalanche tolerance of the device. By electrically connecting the first gate and the second gate or the source in the trench gate structure, and controlling the voltage between the source and the drain to completely deplete the conductive layer, the output capacitance of the device is increased, while the on-resistance and switching losses of the device are not increased. Furthermore, by adjusting the thickness and doping concentration of the conductive layer in the multiple sequentially arranged second conductivity type pillars, a gradual change in output capacitance is achieved. In addition, the fabrication process of the trench-gate superjunction MOSFET is not increased, making it highly valuable for industrial applications. Attached Figure Description

[0033] Figure 1 The diagram shown is a cross-sectional view of the trench gate superjunction MOSFET of the present invention.

[0034] Figure 2 The diagram shows a cross-sectional view of the trench gate superjunction MOSFET of the present invention with the first gate and source electrically connected.

[0035] Figure 3 The diagram shown is a cross-sectional view of a structure in which a conductive layer is provided in the second conductivity type pillar of the trench gate superjunction MOSFET of the present invention.

[0036] Figure 4 The diagram shows a cross-sectional view of another structure of the trench gate superjunction MOSFET of the present invention, in which a conductive layer is provided in the pillar of the second conductivity type.

[0037] Figure 5 The diagram shows a cross-sectional view of a third structure of a second conductivity type pillar of the trench gate superjunction MOSFET of the present invention, in which a conductive layer is provided.

[0038] Figure 6 The diagram shows a cross-sectional structure of the trench gate superjunction MOSFET of the present invention, in which a conductive layer is provided in the second conductivity type pillar and the first gate is electrically connected to the source.

[0039] Figure 7 Displayed as Figure 1 The Miller capacitance variation curves of the trench gate superjunction MOSFET and another superjunction MOSFET are shown.

[0040] Figure 8 The diagram shows a process flow chart of the fabrication method of the trench gate superjunction MOSFET of the present invention.

[0041] Component designation explanation

[0042] 1 Substrate

[0043] 2. Buffer

[0044] 3 First type of conductive column

[0045] 31 First column area

[0046] 32 Second column area

[0047] 4. Second type of conductive column

[0048] 5 body areas

[0049] 6 source regions

[0050] 7. Body contact area

[0051] 8. Groove grid structure

[0052] 81 Isolation Medium Layer

[0053] 82 First gate

[0054] 9 gate structure

[0055] 91 Gate dielectric layer

[0056] 92 Second gate

[0057] 10 Source Pole

[0058] 11 Drain

[0059] A. Miller capacitance variation curve of a superjunction MOSFET

[0060] B. Miller capacitance variation curve of trench gate superjunction MOSFET Detailed Implementation

[0061] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0062] Please see Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0063] Example 1

[0064] This embodiment provides a trench gate superjunction MOSFET structure, such as Figure 1The diagram shown is a cross-sectional view of the trench gate superjunction MOSFET, including a first conductivity type substrate 1, a first conductivity type buffer zone 2, multiple first conductivity type pillars 3, multiple second conductivity type pillars 4, a second conductivity type body region 5, a first conductivity type source region 6, a second conductivity type body contact region 7, a trench gate structure 8, a gate structure 9, a source 10, and a drain 11. The buffer zone 2 is stacked above the substrate 1. The first conductivity type pillars 3 are disposed on the upper surface of the buffer zone 2 and extend away from the substrate 1, and each first conductivity type pillar 3 includes a first pillar region 31 and a second pillar region 32 stacked on the first pillar region 31. The second conductivity type pillars 4 are located on both sides of the first pillar region 31, and the sidewalls of the second conductivity type pillars 4 are adjacent to the sidewalls of the first pillar region 31. The upper surface of the second conductivity type pillars 4 is flush with the upper surface of the first pillar region 31. The body region 5 is stacked on the second conductivity type pillars 4, and the upper surface of the body region 5 is flush with the upper surface of the second pillar region 32. The wall is adjacent to the sidewall of the second pillar region 32; the source region 6 is adjacent to the body contact region 7, the source region 6 and the body contact region 7 are located on the upper surface of the body region 5, and the source region 6 and the body contact region 7 are spaced apart from the first conductive type pillar 3 by a predetermined distance; at least one trench gate structure 8 is provided, the trench gate structure 8 penetrates the body region 5 and the body contact region 7 and the bottom of the trench gate structure 8 extends downward into the second conductive type pillar 4, the trench gate structure 8 includes an isolation dielectric layer 81 and a first gate 82. The isolation dielectric layer 81 at least covers the sidewalls and bottom surface of the first gate 82; the gate structure 9 is located on the upper surface of the second pillar region 32, and both ends of the gate structure 9 extend above the source region 6. The gate structure 9 includes a gate dielectric layer 91 and a second gate 92, and the gate dielectric layer 91 covers the second gate 92; the source 10 covers the exposed surfaces of the gate structure 9 and the trench gate structure 8, as well as the upper surfaces of the source region 6 and the body contact region 7; and the drain 11 covers the bottom surface of the substrate 1.

[0065] Specifically, the first conductivity type includes either N-type or P-type, the second conductivity type includes either N-type or P-type, and the conductivity type of the first conductivity type is opposite to that of the second conductivity type.

[0066] Specifically, the substrate 1 is made of silicon or other suitable semiconductor materials.

[0067] Specifically, the conductivity type of the substrate 1 includes either N-type or P-type. In this embodiment, the conductivity type of the substrate 1 is N-type.

[0068] Specifically, the doping concentration of the substrate 1 is higher than that of the buffer 2, and the doping concentration of the first conductivity type pillar 3 is higher than that of the buffer 2.

[0069] Specifically, the thickness of the substrate 1 can be set according to the actual situation, and is not limited here; the thickness of the buffer zone 2 can be set according to the actual situation, and is not limited here; the height of the first conductive type pillar 3 can be set according to the actual situation, and is not limited here.

[0070] Specifically, the first column region 31 and the second column region 32 have the same doping concentration.

[0071] Specifically, the doping concentration of the second conductivity type column 4 can be set according to the actual situation, and is not limited here.

[0072] Specifically, the doping concentration of the body region 5 is lower than the doping concentration of the second conductivity type pillar 4.

[0073] Specifically, the thickness of the body region 5 can be set according to the actual situation, and is not limited here.

[0074] Specifically, the doping concentration of the body contact region 7 is higher than that of the body region 5, and the doping concentration of the source region 6 is higher than that of the first conductivity type pillar 3.

[0075] Specifically, the material of the isolation dielectric layer 81 includes silicon oxide or other suitable high dielectric constant materials.

[0076] Specifically, the first gate 82 is made of polycrystalline silicon or other suitable conductive materials.

[0077] Specifically, the gate dielectric layer 91 is made of silicon oxide or other suitable high dielectric constant materials.

[0078] Specifically, the material of the second gate 92 includes polysilicon or other suitable conductive materials.

[0079] Specifically, the two ends of the second gate 92 extend above the source region 6.

[0080] Specifically, the second gate 92 controls the conduction of the conductive channel in the body region 5 between the source region 6 and the second pillar region 32 in the control device, thereby controlling the conduction of the control device.

[0081] Specifically, the source electrode 10 is made of one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or other suitable conductive materials.

[0082] Specifically, the material of the drain electrode 11 includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or other suitable conductive materials.

[0083] As an example, the first gate 82 is electrically connected to at least one of the source 10 and the second gate 92. That is, the first gate 82 may be electrically connected to the second gate 92, or to the source 10, or a portion of it may be electrically connected to the second gate 92 and the remainder to the source 10.

[0084] As an example, the breakdown point of the trench gate superjunction MOSFET is located below the trench gate structure 8.

[0085] Specifically, such as Figure 2 The diagram shows a cross-sectional view of the first gate 82 when it is electrically connected to the source 10. When the first gate 82 is electrically connected to the source 10, the isolation dielectric layer 81 that encloses the first gate 82 may not cover the upper surface of the first gate 82.

[0086] Specifically, when the first gate 82 is electrically connected to the source 10 and the reverse bias voltage between the source 10 and the drain 11 exceeds the withstand voltage of the trench gate superjunction MOSFET, the breakdown point of the trench gate superjunction MOSFET is located below the trench gate structure 8 because the electric field strength between the bottom of the trench gate structure 8 and the drain 11 is large and the bottom of the trench gate structure 8 is close to the drain 11.

[0087] Specifically, when the first gate 82 is electrically connected to the second gate 92, the surface of the isolation dielectric layer 81 at the bottom of the trench gate structure 8, which is in contact with the second conductivity type pillar 4, is induced to generate charge accumulation. As a result, when the reverse bias voltage between the source 10 and the drain 11 exceeds the withstand voltage of the trench gate superjunction MOSFET, the breakdown point of the trench gate superjunction MOSFET is located below the trench gate structure 8.

[0088] Specifically, when the device is reverse biased, the breakdown point of the trench gate superjunction MOSFET is located below the trench gate structure 8, which can effectively suppress the conduction of the parasitic transistor formed by the buffer 2, the source region 6, the second conductivity type pillar, and the body region, thereby increasing the avalanche tolerance of the device.

[0089] Specifically, the depth to which the trench grid structure 8 extends into the second conductive type post 4 can be set according to the actual situation, and is not limited here.

[0090] Specifically, the thickness of the isolation medium layer 81 can be set according to the actual situation, and is not limited here.

[0091] Specifically, the distance between the source region 6 and the second pillar region 32 in the trench gate superjunction MOSFET is not changed, that is, the conductive channel is not sacrificed, and the thickness and doping concentration of the first conductive type pillar 3 are not changed, so the on-resistance of the device is not increased.

[0092] As an example, such as Figure 3 , Figure 4 and Figure 5 The figures shown are cross-sectional schematic diagrams of one structure of the trench gate superjunction MOSFET, another structure of the trench gate superjunction MOSFET, and a third structure of the trench gate superjunction MOSFET having a second conductivity type conductive layer 41. The superjunction MOSFET also includes at least one second conductivity type conductive layer 41 located in the second conductivity type pillar 4, and the doping concentration of the conductive layer 41 is different from the doping concentration of the second conductivity type pillar 4.

[0093] Specifically, the doping concentration of the conductive layer 41 ranges from 10. 15 cm -3 ~10 17 cm -3 .

[0094] As an example, the thickness of the conductive layer 41 is less than the thickness of the second conductive type pillar 4, and the upper surface of the conductive layer 41 is flush with the upper surface of the second conductive type pillar 4.

[0095] Specifically, the thickness of the conductive layer 41 can be set according to the actual situation, and is not limited here.

[0096] As an example, the trench gate structure 8 extends into the conductive layer 41 to control the depletion state of the conductive layer 41.

[0097] Specifically, such as Figure 6 The diagram shows a cross-sectional view of the trench gate superjunction MOSFET when the first gate 82 is electrically connected to the source 10. When the first gate 82 is electrically connected to the source 10, the potentials of the first gate 82 and the source 10 are the same, and there is a voltage difference between the drain 11 and the first gate 82. The depletion state of the conductive layer 41 can be controlled by adjusting the voltage between the source 10 and the drain 11.

[0098] Specifically, when the first gate 82 is electrically connected to the source 10, the isolation dielectric layer 81 that encapsulates the first gate 82 may not cover the upper surface of the first gate 82.

[0099] Specifically, when the first gate 82 is electrically connected to the second gate 92, the first gate 82 and the second gate 92 have the same potential, and there is a voltage difference between the second gate 92 and the drain 11. The depletion state of the conductive layer 41 can be controlled by adjusting the voltage between the second gate 92 and the drain 11.

[0100] As an example, when the first gate 82 is electrically connected to the second gate 92 and the conductive layer 41 cannot form a fully depleted layer, the first gate 82, the isolation dielectric layer 81, and the conductive layer 41 act as an input capacitance.

[0101] Specifically, the first gate 82 is electrically connected to the second gate 92. When the carriers in the conductive layer 41 are not depleted, that is, when the voltage between the source 10 and the drain 11 is low, the built-in electric field formed in the conductive layer 41 is narrow. Since the carriers in the conductive layer 41 are not depleted, the source 10 is directly electrically connected to the conductive layer 41 and the second conductive type pillar 4. The first gate 82, the isolation dielectric layer 81, and the conductive layer 41 act as the capacitance between the source 10 and the second gate 92, that is, as the input capacitance. This is equivalent to increasing the capacitance between the gate and the source, that is, increasing the input capacitance.

[0102] As an example, when the first gate 82 is electrically connected to the second gate 92 and the conductive layer 41 forms a fully depleted layer, the first gate 82, the isolation dielectric layer 81, and the conductive layer 41 act as an output capacitance.

[0103] Specifically, the first gate 82 is electrically connected to the second gate 92. When the carriers in the conductive layer 41 are depleted, that is, when the voltage between the source 10 and the drain 11 causes the carriers in the conductive layer 41 to be depleted, a depletion layer is formed. The first gate 82, the isolation dielectric layer 81, and the conductive layer 41 are represented by the capacitance between the drain 11 and the first gate 82 (the capacitance between the drain and the gate), which is the output capacitance.

[0104] Specifically, when the device is turned on, only the output capacitance of the device when the voltage between the source 10 and the drain 11 is high is increased, while the output capacitance of the device when the voltage between the source 10 and the drain 11 is low is not increased, and consequently the switching loss of the device is not increased.

[0105] As an example, at least one of the thickness and doping concentration of the conductive layer 41 in the plurality of sequentially arranged second conductive type pillars 4 is different, and at least one of the thickness and doping concentration of the plurality of conductive layers 41 decreases or increases sequentially along the arrangement direction of the second conductive type pillars 4, so that the output capacitance changes gradually.

[0106] Specifically, in one example, along the arrangement direction of the plurality of second conductivity type pillars 4, the doping concentration of the conductive layer 41 in the previous second conductivity type pillar 4 is less than the doping concentration of the conductive layer 41 in the subsequent second conductivity type pillar 4.

[0107] Specifically, in the second example, along the arrangement direction of the plurality of second conductivity type pillars 4, the doping concentration of the conductive layer 41 in the previous second conductivity type pillar 4 is greater than the doping concentration of the conductive layer 41 in the subsequent second conductivity type pillar 4.

[0108] Specifically, in the third example, along the arrangement direction of the plurality of second conductive type pillars 4, the thickness of the conductive layer 41 in the previous second conductive type pillar 4 is less than the thickness of the conductive layer 41 in the subsequent second conductive type pillar 4.

[0109] Specifically, in the fourth example, along the arrangement direction of the plurality of second conductive type pillars 4, the thickness of the conductive layer 41 in the previous second conductive type pillar 4 is greater than the thickness of the conductive layer 41 in the subsequent second conductive type pillar 4.

[0110] Specifically, in the fifth example, along the arrangement direction of the plurality of second conductivity type pillars 4, the thickness and doping concentration of the conductive layer 41 in the previous second conductivity type pillar 4 are both less than the thickness and doping concentration of the conductive layer 41 in the subsequent second conductivity type pillar 4.

[0111] Specifically, in the sixth example, along the arrangement direction of the plurality of second conductivity type pillars 4, the thickness and doping concentration of the conductive layer 41 in the previous second conductivity type pillar 4 are both greater than the thickness and doping concentration of the conductive layer 41 in the subsequent second conductivity type pillar 4.

[0112] Specifically, the thickness and doping concentration of the conductive layer 41 are adjusted to control the thickness of the depletion layer between the trench gate structure 8 and the drain 11, thereby controlling the output capacitance.

[0113] Specifically, when the doping concentration of the conductive layer 41 is the same but the thickness is different, the thickness of the depletion layer formed when the conductive layer 41 is completely depleted is also different, and the narrower the thickness, the smaller the output capacitance is.

[0114] Specifically, when the conductive layers 41 have the same thickness but different doping concentrations, the thickness of the depletion layer formed when the conductive layers 41 are completely depleted will also be different, resulting in different output capacitances. In this embodiment, the thickness of the multiple conductive layers 41 along the arrangement direction of the second conductivity type pillars 4 is the same, and the doping concentration increases sequentially to make the output capacitance decrease slowly.

[0115] Specifically, when the device is forward-biased, the body region 5 between the source region 6 and the second pillar region 32 forms a conductive channel under the control of the second gate 92, so that the source 10 is connected to the drain 11 through the source region 6, the conductive channel, the second pillar region 32, the first pillar region 31, the buffer zone 2 and the substrate 1, and the on-resistance of the device does not change.

[0116] Specifically, such as Figure 7 As shown, Figure 1 The diagram shows the Miller capacitance variation of a trench-gate superjunction MOSFET and another superjunction MOSFET. The structure of the superjunction MOSFET is as follows: Figure 1 The trench gate superjunction MOSFET structure shown is the structure excluding the trench gate structure, wherein the doping concentration of the substrate 1 in the trench gate superjunction MOSFET is 5 × 10⁻⁶. 19 cm -3 The thickness is 2 μm, and the doping concentration of buffer 2 is 1.5 × 10⁻⁶. 15 cm -3 The thickness is 8 μm, and the doping concentration of the second conductivity type pillar 4 is 6 × 10⁻⁶. 15 cm -3 The width is 4μm and the thickness is 40μm. The doping concentration of the first conductivity type pillar 3 is 6×10⁻⁶. 15 cm -3 The width is 4μm and the thickness is 40μm. The doping concentration of the body region 5 is 1×10⁻⁶. 17 cm -3 The thickness is 2 μm, and the doping concentration of both the bulk contact region 7 and the source region 6 is 5 × 10⁻⁶. 19 cm -3 The thickness of each layer is 0.4 μm. The thickness of the isolation dielectric layer 81 and the gate dielectric layer 91 is 100 nm. The width of the first gate 82 is 1 μm and the thickness is 2.9 μm. The first gate 82 and the second gate 92 are electrically connected. The parameters of each part of the superjunction MOSFET are... Figure 1The parameters of each part of the trench gate superjunction MOSFET shown are the same. When the voltage between the drain 11 and the source 10 is low, the Miller capacitance of the superjunction MOSFET is almost the same as that of the trench gate superjunction MOSFET. When the voltage between the drain 11 and the source 10 is high, the second conductivity type pillar 4 located near the trench gate structure 8 is gradually depleted, and the overlapping area of ​​the trench gate structure 8 and the second conductivity type pillar 4 gradually becomes the Miller capacitance (the capacitance between the gate and the drain).

[0117] This embodiment of the trench gate superjunction MOSFET redesigns the structure of the trench gate superjunction MOSFET by providing a structure that penetrates the body contact region 7, the body region 5, and extends into the second conductivity type pillar 4. This electrically connects the first gate 82 in the trench gate structure 8 to the source 10 or the second gate 92, placing the breakdown point of the device below the trench gate structure 8. This suppresses the turn-on of parasitic transistors in the device and increases the avalanche withstand capability. When the first gate 82 is electrically connected to the second gate 92 and the voltage between the source 10 and the drain 11 causes incomplete charge carrier activity in the conductive layer 41... When fully depleted, the source 10 is electrically connected to the conductive layer 41, and the first gate 82, the isolation dielectric layer 81, and the conductive layer 41 act as an input capacitor. When the first gate 82 is electrically connected to the second gate 92 and the voltage between the source 10 and the drain 11 causes the carriers in the conductive layer 41 to be completely depleted, the first gate 82, the isolation dielectric layer 81, and the conductive layer 41 act as an output capacitor. By adjusting the thickness and doping concentration of the conductive layer 41, the output capacitor can be gradually changed, and while optimizing the output capacitor, the on-resistance and switching loss of the device are not increased.

[0118] Example 2

[0119] This embodiment provides a method for fabricating a trench gate superjunction MOSFET, such as... Figure 8 The diagram shown is a process flow chart of the fabrication method of the trench gate superjunction MOSFET, including the following steps:

[0120] S1: Provide a substrate of a first conductivity type, and form a buffer zone of the first conductivity type on the upper surface of the substrate;

[0121] S2: A plurality of first conductive type first pillar areas and second conductive type pillars located on both sides of the first pillar areas are formed on the upper surface of the buffer zone, and the sidewalls of the second conductive type pillars are adjacent to the sidewalls of the first pillar areas, and the upper surface of the first pillar areas is flush with the upper surface of the second conductive type pillars.

[0122] S3: A first conductive type second pillar region is formed on the upper surface of the first pillar region to form a first conductive type pillar, and a second conductive type body region is formed on both sides of the second pillar region, located on the upper surface of the second conductive type pillar and adjacent to the side wall of the second pillar region, wherein the upper surface of the body region is flush with the upper surface of the second pillar region;

[0123] S4: A first conductive type source region and a second conductive type body contact region are formed adjacent to each other in the upper surface layer of the body region, and the source region and the body contact region are spaced apart from the first conductive type pillar by a predetermined distance;

[0124] S5: A trench is formed in at least one of the body contact areas, opening upwards, penetrating the body contact area and the body area and extending into the second conductive type pillar, and an isolation dielectric layer and a first gate are formed in the trench to cover the inner wall of the trench to form a trench gate structure, and the isolation dielectric layer at least covers the sidewall and bottom surface of the first gate.

[0125] S6: A gate structure is formed on the upper surface of the second pillar region, the two ends of the gate structure extend to the top of the source region, the gate structure includes a gate dielectric layer and a second gate, and the gate dielectric layer encloses the second gate;

[0126] S7: A source electrode is formed on the upper surface of the gate structure, covering the exposed surface of the gate structure and the trench gate structure, and the upper surface of the source region and the body contact region, and a drain electrode is formed on the bottom surface of the substrate.

[0127] Perform step S1: Provide a substrate of a first conductivity type and form a buffer zone of a first conductivity type on the upper surface of the substrate.

[0128] Specifically, the method for forming the buffer zone includes chemical vapor deposition or other suitable methods.

[0129] Perform steps S2 and S3: Form a plurality of first conductive type first pillar areas and second conductive type pillars located on both sides of the first pillar areas on the upper surface of the buffer, wherein the second conductive type pillars are adjacent to the sidewalls of the first pillar areas, and the upper surface of the first pillar areas is flush with the upper surface of the second conductive type pillars; form a first conductive type second pillar area on the upper surface of the first pillar areas to form first conductive type pillars, and form second conductive type body areas on both sides of the second pillar areas located on the upper surface of the second conductive type pillars and adjacent to the sidewalls of the second pillar areas, wherein the upper surface of the body areas is flush with the upper surface of the second pillar areas.

[0130] Specifically, the method for forming the first conductive type pillar and the first pillar region includes forming multiple pillar region semiconductor layers stacked upwards on the upper surface of the buffer, and forming the first pillar region and the second conductive type pillar in a designated area of ​​the semiconductor layer after each pillar region semiconductor layer is formed, until the thickness of the first pillar region and the second conductive type pillar reaches a preset thickness.

[0131] Specifically, the method for forming the semiconductor layer in the pillar region includes chemical vapor deposition or other suitable methods.

[0132] Specifically, the methods for forming the second type of conductive column include ion implantation or other suitable methods.

[0133] Specifically, after forming the first pillar region and the second conductivity type pillar, a first semiconductor layer is formed on the upper surface of the pillar region semiconductor layer, and the second pillar region is formed in the first semiconductor layer above the first pillar region to obtain the first conductivity type pillar, and the body region is formed in the first semiconductor layer above the second conductivity type pillar.

[0134] Specifically, the methods for forming the second column region include ion implantation or other suitable methods.

[0135] Specifically, the methods for forming the body region include ion implantation or other suitable methods.

[0136] Specifically, the method for forming the first semiconductor layer includes chemical vapor deposition or other suitable methods.

[0137] Specifically, when a second conductivity type conductive layer is formed in the second conductivity type pillar, a predetermined concentration of impurity particles is doped at a designated location of the semiconductor layer in the pillar region to make the doping concentration of the conductive layer reach a predetermined value.

[0138] Perform steps S4 and S5: Form an adjacent first conductivity type source region and a second conductivity type body contact region in the upper surface layer of the body region, and the source region and the body contact region are spaced apart from the first conductivity type pillar by a predetermined distance; form an upward-opening trench in at least one of the body contact regions, penetrating the body contact region and the body region and extending into the second conductivity type pillar, and form an isolation dielectric layer and a first gate in the trench covering the inner wall of the trench to form a trench gate structure, and the isolation dielectric layer at least covers the sidewall and bottom surface of the first gate.

[0139] Specifically, the method for forming the source region in the body region includes ion implantation or other suitable methods.

[0140] Specifically, the method for forming the body contact region in the body region includes ion implantation or other suitable methods.

[0141] Specifically, after the body contact area is formed, the body contact area is etched at a designated location to form a trench that opens upward, penetrates the body contact area and the body area, and extends into the second conductive type pillar.

[0142] Specifically, the method for forming the trench includes either dry etching or wet etching, or other suitable methods.

[0143] Specifically, after the trench is formed, an isolation dielectric layer covering the inner wall of the trench is formed on the inner wall of the trench, and after the isolation dielectric layer is formed, a first gate is formed in the trench, filling the trench and including the sidewalls and bottom of the isolation dielectric layer.

[0144] Specifically, when the first gate is electrically connected to the second gate, after the first gate is formed, an isolation dielectric layer covering the first gate needs to be formed on the exposed surface of the first gate to isolate the first gate from the source.

[0145] Specifically, the method for forming the first gate includes chemical vapor deposition or other suitable methods.

[0146] Specifically, the methods for forming the isolation medium layer include thermal oxidation, chemical vapor deposition, or other suitable methods.

[0147] Perform steps S6 and S7: form a gate structure on the upper surface of the second pillar region, with both ends of the gate structure extending above the source region, the gate structure including a gate dielectric layer and a second gate, the gate dielectric layer enclosing the second gate; form an exposed surface covering the gate structure and the trench gate structure and a source electrode on the upper surface of the source region and the upper surface of the body contact region on the upper surface of the gate structure, and form a drain electrode on the bottom surface of the substrate.

[0148] Specifically, the methods for forming the gate dielectric layer include thermal oxidation, chemical vapor deposition, or other suitable methods.

[0149] Specifically, the method for forming the second gate includes chemical vapor deposition or other suitable methods.

[0150] Specifically, the methods for forming the source electrode include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0151] Specifically, the methods for forming the drain include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0152] The trench gate superjunction MOSFET fabrication method of this embodiment ensures the stability of the doping concentration of the first pillar region and the second conductivity type pillar by forming the pillar region semiconductor layer multiple times and performing ion implantation multiple times to form the first pillar region and the second conductivity type pillar, without increasing the difficulty of the process.

[0153] In summary, the trench-gate superjunction MOSFET and its fabrication method of the present invention improve the structure of the trench-gate superjunction MOSFET by providing an upward-opening trench gate structure in the body contact region, penetrating the body contact region and the body region, and extending to the bottom of the second conductivity type pillar. The first gate in the trench gate structure is electrically connected to the source or the second gate. The breakdown point of the device is located below the trench gate structure, suppressing the turn-on of parasitic transistors in the device and increasing the avalanche withstand capability. At least one conductive layer is formed in the second conductivity type pillar, and the conductive layer is electrically connected to the second gate. When the source and... When the voltage between the drain and the source is low, the carriers in the conductive layer are not completely depleted. The first gate, the isolation dielectric layer, and the conductive layer act as the input capacitance, electrically connecting the conductive layer to the source. When the voltage between the source and the drain is high, the carriers in the conductive layer are depleted, and the first gate, the isolation dielectric layer, and the conductive layer act as the output capacitance, increasing the output capacitance. Adjusting the thickness and doping concentration of the conductive layer allows for a gradual change in the device's output capacitance without increasing the Miller capacitance. This optimizes the output capacitance without increasing the on-resistance or switching losses. Furthermore, the fabrication process for the trench-gate superjunction MOSFET is not complicated. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0154] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A trench-gate superjunction MOSFET, characterized in that, include: First conductivity type substrate; A first conductivity type buffer is stacked on top of the substrate; Multiple first conductive type pillars are disposed on the upper surface of the buffer and extend in a direction away from the substrate, and the first conductive type pillars include a first pillar region and a second pillar region stacked on the first pillar region; Multiple second conductive type pillars are disposed on the upper surface of the buffer zone and located on both sides of the first pillar area. The sidewalls of the second conductive type pillars are adjacent to the sidewalls of the first pillar area, and the upper surface of the second conductive type pillars is flush with the upper surface of the first pillar area. The second type of conductive body region is stacked on the second type of conductive pillar, and the upper surface of the body region is flush with the upper surface of the second pillar region, and the sidewall of the body region is adjacent to the sidewall of the second pillar region. The adjacent first conductivity type source region and second conductivity type body contact region are located on the upper surface of the body region, and the source region and the body contact region are spaced at a predetermined distance from the first conductivity type pillar; At least one trench gate structure extends through the body region and the body contact region, with the bottom of the trench gate structure extending downward into a second conductivity type pillar. The trench gate structure includes an isolation dielectric layer and a first gate, wherein the isolation dielectric layer at least covers the sidewalls and bottom surface of the first gate. A gate structure is located on the upper surface of the second pillar region, and both ends of the gate structure extend above the source region. The gate structure includes a gate dielectric layer and a second gate, and the gate dielectric layer encloses the second gate. The source and drain are provided, wherein the source covers the exposed surfaces of the gate structure, the trench gate structure, the body region, the source region and the body contact region, and the drain covers the bottom surface of the substrate.

2. The trench gate superjunction MOSFET according to claim 1, characterized in that: The first gate is electrically connected to at least one of the source and the second gate.

3. The trench gate superjunction MOSFET according to claim 1, characterized in that: The breakdown point of the trench gate superjunction MOSFET is located below the trench gate structure.

4. The trench gate superjunction MOSFET according to claim 1, characterized in that: The trench gate superjunction MOSFET further includes at least one second conductivity type conductive layer located in the second conductivity type pillar, and the doping concentration of the conductive layer is different from the doping concentration of the second conductivity type pillar.

5. The trench gate superjunction MOSFET according to claim 4, characterized in that: The trench gate structure extends into the conductive layer.

6. The trench gate superjunction MOSFET according to claim 5, characterized in that: The thickness of the conductive layer is less than the thickness of the second conductive type pillar, and the upper surface of the conductive layer is flush with the upper surface of the second conductive type pillar.

7. The trench gate superjunction MOSFET according to claim 5, characterized in that: When the first gate is electrically connected to the second gate and the conductive layer cannot form a fully depleted layer, the first gate, the isolation dielectric layer, and the conductive layer exhibit an input capacitance.

8. The trench gate superjunction MOSFET according to claim 5, characterized in that: When the first gate is electrically connected to the second gate and the conductive layer forms a fully depleted layer, the first gate, the isolation dielectric layer, and the conductive layer act as an output capacitance.

9. The trench gate superjunction MOSFET according to claim 5, characterized in that: At least one of the thickness and doping concentration of the conductive layer in the plurality of sequentially arranged second conductive type pillars is different, and at least one of the thickness and doping concentration of the plurality of conductive layers decreases or increases sequentially along the arrangement direction of the second conductive type pillars.

10. A method for fabricating a trench-gate superjunction MOSFET, characterized in that, Includes the following steps: A substrate of a first conductivity type is provided, and a buffer zone of the first conductivity type is formed on the upper surface of the substrate; A plurality of first conductive type first pillar areas and second conductive type pillars located on both sides of the first pillar areas are formed on the upper surface of the buffer zone, and the sidewalls of the second conductive type pillars are adjacent to the sidewalls of the first pillar areas, and the upper surface of the first pillar areas is flush with the upper surface of the second conductive type pillars. A first conductive type second column region is formed on the upper surface of the first column region to form a first conductive type column, and a second conductive type body region is formed on both sides of the second column region, located on the upper surface of the second conductive type column and adjacent to the side wall of the second column region, wherein the upper surface of the body region is flush with the upper surface of the second column region; A first conductive type source region and a second conductive type body contact region are formed adjacent to each other in the upper surface layer of the body region, and the source region and the body contact region are spaced apart from the first conductive type pillar by a predetermined distance; A trench is formed in at least one of the body contact areas, opening upwards, penetrating the body contact area and the body area and extending into the second conductivity type pillar, and an isolation dielectric layer and a first gate are formed in the trench to cover the inner wall of the trench to form a trench gate structure, and the isolation dielectric layer at least covers the sidewall and bottom surface of the first gate. A gate structure is formed on the upper surface of the second pillar region, and both ends of the gate structure extend above the source region. The gate structure includes a gate dielectric layer and a second gate, and the gate dielectric layer encapsulates the second gate. An exposed surface covering the gate structure and the trench gate structure, as well as a source electrode covering the upper surface of the source region and the body contact region, are formed on the upper surface of the gate structure, and a drain electrode is formed on the bottom surface of the substrate.

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