Deadlock avoidance method depending on multi-channel ring network

Abstract

This invention discloses a deadlock avoidance method relying on multi-channel ring networks. It includes setting up a CrossBridge between a multi-channel ring network and a single-channel ring network, interconnecting the two networks via the CrossBridge. Separate physical channels are allocated for various information types in the multi-channel ring network, including Request for Query (REQ), Listening for Subsequent Partitions (SNP), Acknowledgment (ACK), and Response for Subsequent Partitions (RSP). Each physical channel is assigned an independent data transmission queue by the CrossBridge to inject or offload data packets into or from the independent multi-channel and single-channel ring networks, ensuring that the various information types are independent of each other. This invention can avoid deadlock in on-chip interconnect networks, improving their efficiency and reliability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit chip design, and more specifically to a deadlock avoidance method applicable to on-chip interconnect networks that relies on multi-channel ring networks. Background Technology

[0002] With the continuous development of large-scale integrated circuit technology, the design of integrated circuit chips has become increasingly complex. The combined pressure from ever-increasing power consumption and the gradually decreasing performance returns of single-processor architectures has led to the emergence of multi-core chips, with processor chips integrating more and more cores, thus becoming many-core. Currently, almost all processor chips are multi-core or many-core. As semiconductor process dimensions continue to shrink, the challenges faced by integrated circuit manufacturing are increasing, leading to the emergence of Chiplet technology. Chiplet technology divides the SoC into smaller dies, interconnects these modular chips (dies), and uses new packaging technologies to package chips with different functions and manufactured using different processes together, forming a heterogeneous integrated chip. With the increase in the number of on-chip computing cores in multi-core or many-core chips and the development of Chiplet technology, the on-chip interconnect network used to connect them has become crucial. The processor on-chip interconnect network transmits various data packets, such as request (REQ), listen (SNP), acknowledge (ACK), and response (RSP). There are certain dependencies between various messages (REQ->SNP->ACK->RSP), which can easily lead to deadlock. To address performance and deadlock issues, a multi-channel ring network is typically formed by assigning a separate physical channel to each type of data packet, such as... Figure 1 As shown, deadlock can easily occur when data packets need to communicate between a multi-channel ring network and a single-channel ring network. How to solve the deadlock problem during communication between multi-channel and single-channel ring networks has become a critical technical issue that urgently needs to be addressed. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a deadlock avoidance method for multi-channel ring networks, which can avoid deadlock in on-chip interconnect networks and improve the efficiency and reliability of on-chip interconnect networks.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0005] A deadlock avoidance method relying on a multi-channel ring network includes setting up a CrossBridge between a multi-channel ring network and a single-channel ring network. The CrossBridge interconnects the multi-channel ring network and the single-channel ring network. Separate physical channels are set up for various information in the multi-channel ring network, such as request (REQ), listen (SNP), acknowledge (ACK), and response (RSP). The CrossBridge sets up an independent data transmission queue for each physical channel to inject or unload data packets into the independent multi-channel ring network and the single-channel ring network, so that the various information are independent of each other.

[0006] Optionally, each physical channel is provided with an independent data transmission queue, including each physical channel being provided with an independent pair of input queues or output queues. The input queue is used to inject data packets from the single-channel ring network into the multi-channel ring network, and the output queue is used to offload data packets from the multi-channel ring network into the single-channel ring network. Furthermore, each channel of the single-channel ring network and the multi-channel ring network has a data path between its input queue and its output queue.

[0007] Optionally, the CrossBridge further includes a first multi-channel selection switch and a multi-channel ring network output register arranged sequentially on the output side of the input queue facing the multi-channel ring network. The first multi-channel selection switch is used to select the data packets output by the multi-channel ring network output register or the output queue to be sent to the multi-channel ring network output register, and to send the input data packets to the corresponding physical channel in the multi-channel ring network through the multi-channel ring network output register. The CrossBridge further includes a second multi-channel selection switch and a multi-channel ring network input register arranged sequentially on the input side of the output queue facing the multi-channel ring network. The multi-channel ring network input register is used to register and output the data packets output by the physical channel corresponding to the multi-channel ring network. The second multi-channel selection switch is used to select the output data packets of the multi-channel ring network input register to be output to the output queue or the first multi-channel selection switch.

[0008] Optionally, the CrossBridge further includes a first single-channel selection switch, a single-channel ring network output register, a second single-channel selection switch, and a single-channel ring network input register. The first single-channel selection switch is used to select one data packet from the output queues of each physical channel and the output data packets of the second single-channel selection switch, and then send it to the single-channel ring network output register. After being stored in the single-channel ring network output register, it is output to the single-channel ring network. The single-channel ring network input register is used to store the data packets output from the single-channel ring network and output them to the second single-channel selection switch. After being sent to the first single-channel selection switch and one of the input queues and output queues of each physical channel, it is then sent to the second single-channel selection switch.

[0009] Optionally, sending data packets from a single-channel ring network to a multi-channel ring network includes:

[0010] S101, when a data packet on a single-channel ring network arrives at the single-channel ring network input register, it is stored in the single-channel ring network input register and then sent to the first single-channel selection switch. In the first single-channel selection switch, the data packet is unloaded into the input queue of the corresponding physical channel in the multi-channel ring network according to the type of the data packet.

[0011] S102, the input queue schedules the incoming data packets, sends them to the multi-channel ring network output register through the first multi-channel selection switch, and sends them to the corresponding physical channel in the multi-channel ring network after being registered in the multi-channel ring network output register.

[0012] Optionally, sending data packets from a multi-channel ring network to a single-channel ring network includes:

[0013] S201, when a data packet on the multi-channel ring network arrives at the multi-channel ring network input register, it is stored in the multi-channel ring network input register and then sent to the second multi-channel selection switch. In the second multi-channel selection switch, the data packet is unloaded into the output queue of the corresponding physical channel in the multi-channel ring network according to the type of the data packet.

[0014] S202, when there is an empty time slot in the single-channel ring network, the first single-channel selection switch selects one of the output queues of each physical channel in the multi-channel ring network based on a preset scheduling strategy and injects it into the single-channel ring network output register. After being registered in the single-channel ring network output register, it is sent to the single-channel ring network.

[0015] Optionally, the CrossBridge further includes detecting data packets on the single-channel ring network. When a data packet on the single-channel ring network is detected to be injected from the multi-channel ring network to the single-channel ring network, the data packet is unloaded from the single-channel ring network and then added to the output queue of the corresponding physical channel according to the data packet type, while releasing the time slot. The size of the output queue is L+N, where the constant L is twice the number of hops in the single-channel ring network, and N is the length of the output queue used to store the portion of the packet unloaded from the multi-channel ring network.

[0016] Optionally, in step S202, when the first single-channel selection switch selects one of the output queues of each physical channel in the multi-channel ring network and injects it into the single-channel ring network output register based on a preset scheduling strategy, it selects one of the output queues of each physical channel in the multi-channel ring network and injects it into the single-channel ring network output register according to the priority relationship of RSP>ACK>SNP>REQ, where RSP represents the physical channel for transmitting response RSP data packets, ACK represents the physical channel for transmitting acknowledgment ACK data packets, SNP represents the physical channel for transmitting listening SNP data packets, and REQ represents the physical channel for transmitting request REQ data packets.

[0017] Furthermore, the present invention also provides a microprocessor using the aforementioned deadlock avoidance method relying on multi-channel ring networks, comprising multiple processor cores, wherein a portion of the processor cores are connected via multi-channel ring networks and another portion of the processor cores are connected via single-channel ring networks, and adjacent multi-channel ring networks and single-channel ring networks are connected via crossBridges.

[0018] Optionally, the plurality of processor cores form two multi-channel ring networks and a single single-channel ring network, each of the single-channel ring networks being connected to the multi-channel ring network via a CrossBridge.

[0019] Compared with existing technologies, the present invention has the following main advantages: The present invention includes setting up a CrossBridge between a multi-channel ring network and a single-channel ring network, and interconnecting the multi-channel ring network and the single-channel ring network through the CrossBridge. Separate physical channels are set up for various information types of the multi-channel ring network, such as request (REQ), listen (SNP), acknowledge (ACK), and response (RSP). The CrossBridge sets up an independent data transmission queue for each physical channel to inject or unload data packets into the independent multi-channel ring network and the single-channel ring network, ensuring that the various information types are independent of each other. The present invention can achieve connectivity between multi-channel ring networks and single-channel ring networks through the CrossBridge, thereby achieving connectivity between multi-channel ring networks. Furthermore, it can support on-chip high-performance local and global network interconnection, as well as multi-chip interconnection, avoiding deadlock in on-chip interconnect networks and improving the efficiency and reliability of on-chip interconnect networks. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a multi-channel ring network in the existing technology.

[0021] Figure 2 This is a schematic diagram of the interconnection topology between a multi-channel ring network and a single-channel ring network in an embodiment of the present invention.

[0022] Figure 3This is a schematic diagram of the cross-linked bridge structure in an embodiment of the present invention. Detailed Implementation

[0023] This embodiment provides a deadlock avoidance method relying on multi-channel ring networks, including setting a crossbridge (such as...) between the multi-channel ring network and the single-channel ring network. Figure 2 As shown in CB0 / CB1, the multi-channel ring network and the single-channel ring network are interconnected through the CrossBridge. Separate physical channels are set up for various information such as request REQ, listen SNP, acknowledgment ACK, and response RSP in the multi-channel ring network. The CrossBridge sets up an independent data transmission queue for each physical channel to inject or unload data packets into the independent multi-channel ring network and the single-channel ring network, so that the various information are independent of each other.

[0024] like Figure 3 As shown, in this embodiment, each physical channel is configured with an independent data transmission queue, including a pair of independent input queues for each physical channel. Figure 3 (②, ③) or the output queue (e.g., Figure 3 In diagrams ⑥ and ⑦, the input queue is used to inject data packets from the single-channel ring network into the multi-channel ring network, and the output queue is used to offload data packets from the multi-channel ring network into the single-channel ring network. Each channel in both the single-channel and multi-channel ring networks has a data path between its input and output queues. It should be noted that, for simplicity, only two physical channels of the multi-channel ring network are shown in the diagram as an example.

[0025] like Figure 3 As shown, in this embodiment, the CrossBridge also includes a first multi-channel selection switch and a multi-channel ring network output register (e.g., arranged sequentially on the output side of the input queue toward the multi-channel ring network) Figure 3 (④ and ⑤ in the text) The first multi-channel selection switch is used to select whether the data packet output by the multi-channel ring network output register or the output queue is sent to the multi-channel ring network output register, and the input data packet is sent to the corresponding physical channel in the multi-channel ring network through the multi-channel ring network output register; the CrossBridge also includes a second multi-channel selection switch and a multi-channel ring network input register (e.g., ...) arranged sequentially on the input side of the output queue facing the multi-channel ring network. Figure 3 In section ⑧ and ⑨), the multi-channel ring network input register is used to store and output the data packets output by the physical channel corresponding to the multi-channel ring network, and the second multi-channel selection switch is used to select the output data packets of the multi-channel ring network input register to be output to the output queue or the first multi-channel selection switch.

[0026] like Figure 3 As shown, in this embodiment, the CrossBridge also includes a first single-channel selection switch and a single-channel ring network output register (such as...). Figure 3 (10) The second single-channel selection switch and the single-channel ring network input register (e.g.) Figure 3 In ①), the first single-channel selection switch is used to select one data packet from the output queues of each physical channel and the output data packets of the second single-channel selection switch, and then send it to the single-channel ring network output register. After being stored in the single-channel ring network output register, it is output to the single-channel ring network. The single-channel ring network input register is used to store the data packets output by the single-channel ring network and output them to the second single-channel selection switch. After being sent to the first single-channel selection switch and one of the input queues and output queues of each physical channel, it is then sent to the first single-channel selection switch and one of the input queues and output queues of each physical channel.

[0027] In this embodiment, the input queue and output queue control logic includes: a) When a data packet is injected from a single-channel ring network into a multi-channel ring network, it is injected into the input queue of the corresponding channel in the multi-channel ring network according to the data packet type; b) If a packet on the single-channel ring network is detected as having been injected by the sender, the packet is unloaded from the single-channel ring network and added to the corresponding output queue, while the time slot is released; c) Packets unloaded from the multi-channel ring network can only use a portion of the output queue depth (denoted as N), and the other portion is twice the hop count of the single-channel ring network (denoted as L). As long as N is not full, packets can be unloaded from the multi-channel ring network; d) Selecting packets from multiple output queues to inject into the single-channel ring network needs to be done according to the multi-channel dependency relationship, with a priority relationship such as RSP>ACK>SNP>REQ; e) The timing for injecting packets from the output queue into the single-channel ring network is when there is an empty time slot (IDLE SLOT) on the single-channel ring network. Specifically, in this embodiment, sending data packets from the single-channel ring network to the multi-channel ring network includes:

[0028] S101, when a data packet on a single-channel ring network arrives at the single-channel ring network input register, it is stored in the single-channel ring network input register and then sent to the first single-channel selection switch. In the first single-channel selection switch, the data packet is unloaded into the input queue of the corresponding physical channel in the multi-channel ring network according to the type of the data packet.

[0029] S102, the input queue schedules the incoming data packets, sends them to the multi-channel ring network output register through the first multi-channel selection switch, and sends them to the corresponding physical channel in the multi-channel ring network after being registered in the multi-channel ring network output register.

[0030] See Figure 3 When a data packet on a single-channel ring network arrives at the input register of the single-channel ring network ( Figure 3 ①), according to the data packet type, is offloaded to the input queue of the corresponding channel in the multi-channel ring network. Figure 3 In the diagram, ② and ③ (each corresponding to a channel in the multi-channel ring network) are injected into the multi-channel ring network output register. Figure 3 (④ and ⑤ in the text); When a packet on a single-channel ring network is detected to be injected from a multi-channel ring network into a single-channel ring network, the packet needs to be offloaded from the single-channel ring network and then added to the corresponding output queue. Figure 3 (⑥ and ⑦ in the original text) and release the time slot at the same time.

[0031] In this embodiment, sending data packets from a multi-channel ring network to a single-channel ring network includes:

[0032] S201, when a data packet on the multi-channel ring network arrives at the multi-channel ring network input register, it is stored in the multi-channel ring network input register and then sent to the second multi-channel selection switch. In the second multi-channel selection switch, the data packet is unloaded into the output queue of the corresponding physical channel in the multi-channel ring network according to the type of the data packet.

[0033] S202, when there is an empty time slot in the single-channel ring network, the first single-channel selection switch selects one of the output queues of each physical channel in the multi-channel ring network based on a preset scheduling strategy and injects it into the single-channel ring network output register. After being registered in the single-channel ring network output register, it is sent to the single-channel ring network.

[0034] See Figure 3 Messages sent from a multi-channel ring network to a single-channel ring network arrive at the multi-channel ring network input register. Figure 3 ⑧, ⑨), and then injected into the output queue respectively. Figure 3 Of the options ⑥ and ⑦, one is ultimately selected and injected into the single-channel ring network output register. Figure 3 ⑩).

[0035] In this embodiment, the CrossBridge further includes detecting data packets on the single-channel ring network. When a data packet on the single-channel ring network is detected as being injected from a multi-channel ring network to the single-channel ring network, the data packet is unloaded from the single-channel ring network and then added to the output queue of the corresponding physical channel according to the data packet type, while simultaneously releasing the time slot. The size of the output queue is L+N, where the constant L is twice the hop count of the single-channel ring network, and N is the length of the output queue used to store the portion of the packet unloaded from the multi-channel ring network. See also Figure 3 In this embodiment, packets offloaded from the multi-channel ring network can only use the output queue ( Figure 3 Part of the depth in ⑥ and ⑦ (denoted as N) is equal to twice the hop count of a single-channel ring network (denoted as L). As long as N is not full, messages can be offloaded from the multi-channel ring network.

[0036] In this embodiment, when the first single-channel selection switch in step S202 selects one of the output queues of each physical channel in the multi-channel ring network to inject into the single-channel ring network output register based on a preset scheduling strategy, it selects one of the output queues of each physical channel in the multi-channel ring network to inject into the single-channel ring network output register according to the priority relationship of RSP>ACK>SNP>REQ. Here, RSP represents the physical channel for transmitting response RSP data packets, ACK represents the physical channel for transmitting acknowledgment ACK data packets, SNP represents the physical channel for transmitting listening SNP data packets, and REQ represents the physical channel for transmitting request REQ data packets. The timing for injecting packets from the output queue into the single-channel ring network is when there is an empty time slot (IDLESLOT) on the single-channel ring network.

[0037] Furthermore, this embodiment also provides a microprocessor using the deadlock avoidance method relying on multi-channel ring networks described above, including multiple processor cores, wherein some processor cores are connected through a multi-channel ring network and other processor cores are connected through a single-channel ring network, and adjacent multi-channel ring networks and single-channel ring networks are connected by a CrossBridge. See also Figure 2 In this embodiment, multiple processor cores form two multi-channel ring networks and a single single-channel ring network. Each single-channel ring network is connected to the multi-channel ring network through a cross-bridge. See [link to documentation]. Figure 2 It can be seen that the single-channel ring network (middle section) is connected to the multi-channel ring network on the left through a crossBridge (CB0), and is also connected to the multi-channel ring network on the right through another crossBridge (CB1). The left and right sides are each independent 4-channel ring networks, which are connected to the single-channel ring network through crossBridge CB0-CB1.

[0038] In multi-core or many-core chips and chiplets using Chiplet technology, an on-chip interconnect network combining multi-channel and single-channel ring networks is required to interconnect computing cores or chiplets. This embodiment addresses this scenario with a deadlock avoidance method relying on multi-channel ring networks. By designing an interconnect structure (CrossBridge) combining multi-channel and single-channel ring networks, deadlock in the on-chip interconnect network can be avoided, while simultaneously improving the efficiency and reliability of the on-chip interconnect network in multi-core processors or Chiplet chips.

[0039] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0040] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A deadlock avoidance method relying on multi-channel ring networks, characterized in that, This includes setting up a CrossBridge between a multi-channel ring network and a single-channel ring network, connecting the two networks together. Separate physical channels are set up for various information types in the multi-channel ring network, such as REQ, SNP, ACK, and RSP. Each physical channel in the CrossBridge has an independent data transmission queue for injecting or unloading data packets into the independent multi-channel and single-channel ring networks, ensuring that the various information types are independent of each other. Each physical channel is provided with an independent data transmission queue, including an independent pair of input queues or output queues for each physical channel. The input queue is used to inject data packets from the single-channel ring network into the multi-channel ring network, and the output queue is used to offload data packets from the multi-channel ring network into the single-channel ring network. Each channel of the single-channel ring network and the multi-channel ring network has a data path between its input queue and its output queue. The CrossBridge further includes a first multi-channel selection switch and a multi-channel ring network output register arranged sequentially on the output side of the input queue facing the multi-channel ring network. The first multi-channel selection switch is used to select the data packets output by the multi-channel ring network output register or the output queue to be sent to the multi-channel ring network output register, and to send the input data packets to the corresponding physical channel in the multi-channel ring network through the multi-channel ring network output register. The CrossBridge further includes a second multi-channel selection switch and a multi-channel ring network input register arranged sequentially on the input side of the output queue facing the multi-channel ring network. The multi-channel ring network input register is used to register and output the data packets output by the physical channel corresponding to the multi-channel ring network. The second multi-channel selection switch is used to select the output data packets of the multi-channel ring network input register to be output to the output queue or the first multi-channel selection switch.

2. The deadlock avoidance method for multi-channel ring networks according to claim 1, characterized in that, The CrossBridge further includes a first single-channel selection switch, a single-channel ring network output register, a second single-channel selection switch, and a single-channel ring network input register. The first single-channel selection switch is used to select one data packet from the output queues of each physical channel and the output data packets of the second single-channel selection switch, and then send it to the single-channel ring network output register. After being stored in the single-channel ring network output register, it is output to the single-channel ring network. The single-channel ring network input register is used to store the data packets output from the single-channel ring network and output them to the second single-channel selection switch. After being sent to the first single-channel selection switch and one of the input queues and output queues of each physical channel, it is then sent to the second single-channel selection switch.

3. The deadlock avoidance method for multi-channel ring networks according to claim 2, characterized in that, Sending data packets from a single-channel ring network to a multi-channel ring network includes: S101, when a data packet on a single-channel ring network arrives at the single-channel ring network input register, it is stored in the single-channel ring network input register and then sent to the first single-channel selection switch. In the first single-channel selection switch, the data packet is unloaded into the input queue of the corresponding physical channel in the multi-channel ring network according to the type of the data packet. S102, the input queue schedules the incoming data packets, sends them to the multi-channel ring network output register through the first multi-channel selection switch, and sends them to the corresponding physical channel in the multi-channel ring network after being registered in the multi-channel ring network output register.

4. The deadlock avoidance method for multi-channel ring networks according to claim 3, characterized in that, Sending data packets from a multi-channel ring network to a single-channel ring network includes: S201, when a data packet on the multi-channel ring network arrives at the multi-channel ring network input register, it is stored in the multi-channel ring network input register and then sent to the second multi-channel selection switch. In the second multi-channel selection switch, the data packet is unloaded into the output queue of the corresponding physical channel in the multi-channel ring network according to the type of the data packet. S202, when there is an empty time slot in the single-channel ring network, the first single-channel selection switch selects one of the output queues of each physical channel in the multi-channel ring network based on a preset scheduling strategy and injects it into the single-channel ring network output register. After being registered in the single-channel ring network output register, it is sent to the single-channel ring network.

5. The deadlock avoidance method for multi-channel ring networks according to claim 4, characterized in that, The CrossBridge also includes the detection of data packets on the single-channel ring network. When a data packet on the single-channel ring network is detected to be injected from the multi-channel ring network to the single-channel ring network, the data packet is unloaded from the single-channel ring network and then added to the output queue of the corresponding physical channel according to the data packet type, while releasing the time slot. The size of the output queue is L+N, where the constant L is twice the number of hops in the single-channel ring network, and N is the length of the output queue used to store the portion of the packet unloaded from the multi-channel ring network.

6. The deadlock avoidance method for multi-channel ring networks according to claim 5, characterized in that, In step S202, when the first single-channel selection switch selects one of the output queues of each physical channel in the multi-channel ring network and injects it into the single-channel ring network output register based on a preset scheduling strategy, it selects one of the output queues of each physical channel in the multi-channel ring network and injects it into the single-channel ring network output register according to the priority relationship of RSP>ACK>SNP>REQ. Here, RSP represents the physical channel for transmitting response RSP data packets, ACK represents the physical channel for transmitting acknowledgment ACK data packets, SNP represents the physical channel for transmitting listening SNP data packets, and REQ represents the physical channel for transmitting request REQ data packets.

7. A microprocessor using the deadlock avoidance method for multi-channel ring networks according to any one of claims 1 to 6, comprising a plurality of processor cores, characterized in that, Furthermore, some processor cores are connected through a multi-channel ring network, while others are connected through a single-channel ring network, and adjacent multi-channel and single-channel ring networks are connected through a CrossBridge.

8. The microprocessor according to claim 7, characterized in that, The multiple processor cores form two multi-channel ring networks and a single single-channel ring network. Each single-channel ring network is connected to the multi-channel ring network through a cross-bridge.

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