Read / write operation execution methods and SoC chips

Abstract

This application discloses a read / write operation execution method and a SoC chip, used to ensure that the globally visible execution order of read / write operations performed by nodes conforming to RO constraints meets the requirements of nodes conforming to SO constraints. The read / write operation execution method includes: a first node receiving a first message and a second message from a second node; the first message is used to request read / write operations on a first address managed by a third node; the second message is used to request read / write operations on a second address managed by the third node; the execution order constraint of the read / write operations of the second node is stricter than that of the third node; the first node obtains operation permissions for the first address and the second address from the third node; the first node performs read / write operations on the first address and the second address.

Description

Technical Field

[0001] This application relates to the field of storage, and more particularly to a method for performing read and write operations and a system on chip (SoC). Background Technology

[0002] Multiple processes (software) can transfer data by accessing shared memory. Specifically, multiple processes send read and write commands to hardware (such as the central processing unit, CPU), which then performs read and write operations on the shared memory. The order in which the hardware performs read and write operations affects the final execution result seen by the software. Therefore, a memory consistency model can be used to impose different levels of requirements on the execution order of read and write operations to ensure that the execution result meets the software's expectations.

[0003] Different storage consistency models require different levels of strictness in the execution order. When a node in a storage consistency model that adheres to strict order (SO) constraints (referred to as a strong order model) requests read and write operations from a node in a storage consistency model that adheres to relaxed order (RO) constraints (referred to as a weak order model), the read and write operations must be executed in the weak order model according to the execution order of the strong order model to ensure that the order in which the execution results are globally observable (GO) meets the requirements of the strong order model. Summary of the Invention

[0004] This application provides a read / write operation execution method and a SoC chip to ensure that the global visibility of the execution results of read / write operations performed by nodes that comply with RO constraints meets the requirements of nodes that comply with SO constraints.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a method for executing read and write operations is provided, comprising: a first node receiving a first message and a second message from a second node; the first message being used to request read and write operations on a first address managed by a third node; the second message being used to request read and write operations on a second address managed by the third node; the execution order constraints of the read and write operations of the second node being stricter than those of the third node; the first node obtaining operation permissions for the first address and the second address from the third node; and the first node performing read and write operations on the first address and the second address.

[0007] The read / write operation execution method provided in this application embodiment involves a first node receiving a first message and a second message from a second node. The second node adheres to SO constraints. The first message requests read / write operations on a first address managed by a third node, and the second message requests read / write operations on a second address managed by the third node. The third node adheres to RO constraints. The first node then acquires operation permissions for both the first and second addresses from the third node, enabling it to participate in cache consistency management. Other nodes are unable to perform read / write operations requiring specific permissions on the first and second addresses. In other words, the execution order of read / write operations on the first and second addresses is controlled by the first node, and consequently, the order in which the execution results are globally visible is also controlled by the first node. This ensures that the globally visible order of read / write operation results performed by nodes adhering to RO constraints meets the requirements of nodes adhering to SO constraints.

[0008] In one possible implementation, the first node performs read and write operations on the first and second addresses, including: the first node performs read and write operations on the first and second addresses in parallel. This implementation can achieve parallel processing of read and write operation requests from nodes that comply with SO constraints, thereby improving the transmission bandwidth and interaction efficiency between the node that complies with SO constraints (the second node) and the node that complies with RO constraints (the third node).

[0009] In one possible implementation, the first node performs read and write operations on the first and second addresses in parallel, including: the first node performs read and write operations on the first and second addresses in parallel according to the order in which the first and second messages are received. This implementation can ensure that the globally visible order of execution results conforms to the requirements of a strong ordering model.

[0010] In one possible implementation, the second node adheres to a strict order (SO) constraint, while the third node adheres to a loose order (RO) constraint. This implementation explains why the execution order constraint for read and write operations on the second node is stricter than that on the third node.

[0011] In one possible implementation, the method further includes: after completing a read / write operation on a first address, the first node releases the access permission for that first address to the third node. This allows the third node or other nodes to continue reading / writing operations on the first address. Similarly, after completing a read / write operation on a second address, the first node releases the access permission for that second address to the third node. This allows the third node or other nodes to continue reading / writing operations on the second address.

[0012] In one possible implementation, the first node obtains operation permissions for a first address and a second address from the third node, including: the first node obtaining the E-state of the first address and the E-state of the second address from the third node. This implementation provides a specific form of operation permissions for the first and second addresses.

[0013] In one possible implementation, when a first node requests access to a first address but fails to obtain such access, and then receives a request from a third node for a read / write operation requiring access to the first address, or requests access to the first address itself, the first node indicates to the third node that it has not obtained access to the first address; thus enabling the third node or other nodes to perform read / write operations on the first address. Similarly, when a first node requests access to a second address but fails to obtain such access, and then receives a request from a third node for a read / write operation requiring access to the second address, or requests access to the second address itself, the first node indicates to the third node that it has not obtained access to the second address; thus enabling the third node or other nodes to perform read / write operations on the second address.

[0014] In one possible implementation, after the first node obtains operation permissions for the first address and the second address from the third node, the method further includes: when preset conditions are met, the first node releases the operation permissions for the first address and the second address to the third node. This allows the third node or other nodes to perform read and write operations on the first address and the second address.

[0015] In one possible implementation, the preset condition is that a third node requests access to both the first and second addresses. This allows the third node or other nodes to perform read and write operations on both addresses.

[0016] In one possible implementation, the preset conditions are that the time it takes for the first node to obtain operation permission for the first address from the third node is greater than or equal to a first preset time, and the time it takes for the first node to obtain operation permission for the second address from the third node is greater than or equal to a second preset time. After receiving a read / write request from the second node, the first node does not need to execute the process of obtaining operation permission for the first address again, and can quickly perform read / write operations on the first address. Similarly, after receiving a read / write request from the second node, the first node does not need to execute the process of obtaining operation permission for the second address again, and can quickly perform read / write operations on the second address.

[0017] In one possible implementation, the method further includes: after the first node acquires operation permissions for the first address and before it begins reading and writing operations on the first address, if the third node requests to perform read and write operations on the first address requiring operation permissions, or requests operation permissions for the first address, then the first node releases the operation permissions for the first address to the third node and reacquires them from the third node; once the first node reacquires operation permissions for the first address from the third node, it can continue reading and writing operations on the first address. Similarly, after the first node acquires operation permissions for the second address and before it begins reading and writing operations on the second address, if the third node requests to perform read and write operations on the second address requiring operation permissions, or requests operation permissions for the first address, then the first node releases the operation permissions for the second address to the third node and reacquires them from the third node. Once the first node reacquires operation permissions for the second address from the third node, it can continue reading and writing operations on the second address.

[0018] In one possible implementation, the method further includes: when the first node begins a write operation to the first address but has not yet obtained the corresponding cache address, the third node requests a read / write operation requiring access permissions to the first address, or requests access permissions to the first address. Then, after obtaining the corresponding cache address, the first node sends the data written to the cache address corresponding to the first address to the third node, or indicates that access permissions to the first address have been released; thus enabling the third node or other nodes to perform read / write operations on the first address. Similarly, when the first node begins a write operation to the second address but has not yet obtained the corresponding cache address, the third node requests a read / write operation requiring access permissions to the second address, or requests access permissions to the second address. Then, after obtaining the corresponding cache address, the first node sends the data written to the cache address corresponding to the second address to the third node, or indicates that access permissions to the second address have been released. This enables the third node or other nodes to perform read / write operations on the second address.

[0019] In one possible implementation, the second node is an input / output I / O device outside the System-on-a-Chip (SoC) chip, the first node is the memory management unit (MMU) within the SoC chip (which can be an SMMU), and the third node is the memory controller within the SoC chip or a local agent (HA) within the memory controller. This implementation provides a specific application scenario.

[0020] In one possible implementation, the second node is the processor in the SoC chip, the first node is the on-chip interconnect network (NOC) in the SoC chip or the interface module of the processor, and the third node is the memory controller in the SoC chip or the HA (High Availability) in the memory controller. This implementation provides another specific application scenario.

[0021] In a second aspect, a System-on-a-Chip (SoC) chip is provided, characterized in that it includes: a first node and a memory controller, wherein the first node is configured to: receive a first message and a second message from a second node; the first message is configured to request read / write operations on a first address managed by the memory controller; the second message is configured to request read / write operations on a second address managed by the memory controller; the execution order constraints of the read / write operations of the second node are stricter than the execution order constraints of the read / write operations of the memory controller; obtain operation permissions for the first address and the second address from the memory controller; and perform read / write operations on the first address and the second address.

[0022] In one possible implementation, the first node is specifically used to perform read and write operations on the first address and the second address in parallel.

[0023] In one possible implementation, the first node is specifically used to: perform read and write operations on the first address and the second address in parallel according to the order in which the first message and the second message are received.

[0024] In one possible implementation, the second node follows a strict order SO constraint, while the memory controller follows a loose order RO constraint.

[0025] In one possible implementation, the first node is further configured to: release the access permission of the first address to the memory controller after completing the read / write operation on the first address; and release the access permission of the second address to the memory controller after completing the read / write operation on the second address.

[0026] In one possible implementation, the first node is specifically used to: obtain the E-state of a first address and the E-state of a second address from the memory controller.

[0027] In one possible implementation, the first node is further configured to: when requesting operation permission for a first address but not obtaining operation permission for the first address, receive a request from the memory controller to perform a read / write operation requiring operation permission on the first address, or, if requesting operation permission for the first address, indicate to the memory controller that operation permission for the first address has not been obtained; when requesting operation permission for a second address but not obtaining operation permission for the second address, receive a request from the memory controller to perform a read / write operation requiring operation permission on the second address, or, if requesting operation permission for the second address, indicate to the memory controller that operation permission for the second address has not been obtained.

[0028] In one possible implementation, after obtaining operation permissions for the first address and the second address from the memory controller, the first node is further configured to: release the operation permissions for the first address and the second address to the memory controller when preset conditions are met.

[0029] In one possible implementation, the preset condition is that the memory controller requests access permissions to the first address and the second address.

[0030] In one possible implementation, the preset conditions are that the time for the first node to obtain the operation permission of the first address from the memory controller is greater than or equal to a first preset time, and the time for the first node to obtain the operation permission of the second address from the memory controller is greater than or equal to a second preset time.

[0031] In one possible implementation, the second node is an input / output I / O device outside the SoC chip, and the first node is the memory management unit (MMU) in the SoC chip.

[0032] In one possible implementation, the second node is a processor in the SoC chip, and the first node is an on-chip interconnect network (NOC) in the SoC chip or an interface module of the processor.

[0033] In one possible implementation, the first node includes a sequence processing module, an operation permission judgment module, and a data cache judgment module; the sequence processing module is used to record the order in which the first message and the second message are received; the operation permission judgment module is used to record whether the operation permission of the first address and the operation permission of the second address are received, and to determine the order in which read and write operations are performed on the first address and the second address according to the sequence; the data cache judgment module is used to record whether the identifier of the cache address corresponding to the first address and the identifier of the cache address corresponding to the second address are received, thereby determining whether to send data.

[0034] The technical effects of the second aspect are the same as those described in the first aspect and any of its embodiments, and will not be repeated here. Attached Figure Description

[0035] Figure 1 This application provides a schematic diagram of the structure of a chip system for communication between an I / O device and a SoC chip, as illustrated in an embodiment of the present application.

[0036] Figure 2 This application provides a schematic diagram of the structure of an SMMU.

[0037] Figure 3 A schematic diagram illustrating RO and SO constraints for different storage consistency models provided in this application embodiment;

[0038] Figure 4This application provides an embodiment of a method for achieving globally visible execution results in a weakly ordered model while adhering to the requirements of a strongly ordered model. Figure 1 ;

[0039] Figure 5 This application provides an embodiment of a method for achieving globally visible execution results in a weakly ordered model while adhering to the requirements of a strongly ordered model. Figure 2 ;

[0040] Figure 6 A schematic diagram illustrating communication between different modules within the same storage consistency model, provided as an embodiment of this application;

[0041] Figure 7 A schematic diagram illustrating an improvement to the weak order model provided in an embodiment of this application;

[0042] Figure 8 A schematic diagram illustrating an improvement to the same storage consistency model provided in an embodiment of this application;

[0043] Figure 9 A flowchart illustrating a read / write operation execution method provided in this application embodiment. Figure 1 ;

[0044] Figure 10 A flowchart illustrating a read / write operation execution method provided in this application embodiment. Figure 2 ;

[0045] Figure 11 A flowchart illustrating a read / write operation execution method provided in this application embodiment. Figure 3 ;

[0046] Figure 12 A flowchart illustrating a read / write operation execution method provided in this application embodiment. Figure 4 ;

[0047] Figure 13 A flowchart illustrating a read / write operation execution method provided in this application embodiment. Figure 5 ;

[0048] Figure 14 A flowchart illustrating a read / write operation execution method provided in this application embodiment. Figure 6 ;

[0049] Figure 15 A flowchart illustrating a read / write operation execution method provided in this application embodiment. Figure 7 ;

[0050] Figure 16 A flowchart illustrating a read / write operation execution method provided in this application embodiment. Figure 8 ;

[0051] Figure 17 A flowchart illustrating a read / write operation execution method provided in this application embodiment. Figure 9 ;

[0052] Figure 18 A flowchart illustrating a read / write operation execution method provided in this application embodiment. Figure 10 ;

[0053] Figure 19 A flowchart illustrating a read / write operation execution method provided in this application embodiment. Figure 10 one. Detailed Implementation

[0054] First, let me describe some of the concepts involved in this application:

[0055] Storage consistency refers to the requirement that the order in which the results of read and write operations (whether or not a read / write operation was performed) are globally visible to other nodes must meet certain requirements. For example, if a node performs a read and write operation on two addresses sequentially (equivalent to performing two read and write operations), or if a node performs two read and write operations on the same address sequentially, other nodes must not only know that two read and write operations have been performed, but also know (i.e., globally visible) that the order of the results of these two read and write operations conforms to the software's expectations. This satisfies the requirement of storage consistency. For example, when there are requirements for the execution order of read and write operations, if write operations are performed on the first address and the second address sequentially, the globally visible correct order of execution results includes: write operations were performed on both the first and second addresses, write operations were performed only on the first address, or no write operations were performed on either the first or the second address. The globally visible incorrect order of execution results includes: write operations were performed only on the second address.

[0056] Cache coherence: The processor is a faster operating device than memory. When the processor performs read / write operations on memory, waiting for the operation to complete before processing other tasks will cause processor blocking and reduce efficiency. Therefore, a cache (which is much faster than memory but has a smaller capacity) can be configured for each processor. When the processor writes data to memory, the data can be written to the cache first, allowing other tasks to be processed. Direct memory access (DMA) devices handle the data storage to memory. Similarly, when the processor reads data from memory, the DMA device first stores the data from memory to the cache, and then the processor reads the data from the cache. When different processors perform read / write operations on the same address in memory through the cache, the execution order of the read / write operations is strictly required. The next read / write operation must be blocked until the previous one is completed to prevent inconsistencies between the data in the cache and memory caused by simultaneous read / write operations.

[0057] Cache-coherent devices adhere to the MESI protocol, which defines four exclusive states for a cache line (the smallest unit of cache): E (Exclusive), M (Modified), S (Shared), and I (Invalid). Specifically, the E state indicates that the cache line is valid, the data in the cache is consistent with the data in memory, and the data exists only in this cache; the M state indicates that the cache line is valid, the data has been modified, the data in the cache is inconsistent with the data in memory, and the data exists only in this cache; the S state indicates that the cache line is valid, the data in the cache is consistent with the data in memory, and the data exists in multiple caches; and the I state indicates that the cache line is invalid.

[0058] Storage consistency models, ranked from strongest to weakest in terms of the required execution order, include: sequential consistency (SC), total store order (TSO), and relaxed model (RM). The SC model requires that the order of read and write operations on shared memory in hardware strictly match the order of operations required by software instructions. The TSO model, building upon the SC model, introduces a caching mechanism, relaxing the order constraint on write-read (write-then-read) operations, meaning that read operations can complete before write operations. The RM model is the most relaxed, imposing no order constraint on any read or write operations, simplifying hardware implementation. It only ensures execution order through software means, such as fencing subsequent operations, when needed.

[0059] When a device using a strong-order model sends read / write requests to a device using a weak-order model, there may be situations where the strong-order model has an order constraint for a certain read / write combination (e.g., write-write (write first, then write), write-read (write first, then read), read-write (read first, then write), read-read (read first, then read)), while the weak-order model does not have this order constraint. Therefore, for parallel read / write requests within a strong-order model, they must be executed sequentially within the weak-order model according to the execution order of the strong-order model to ensure that the globally visible execution results conform to the requirements of the strong-order model.

[0060] Firstly Figure 1 Taking a chip system as an example, this illustrates a typical application scenario where a device with a strong order model sends read / write requests to a device with a weak order model.

[0061] like Figure 1As shown in the illustration, an embodiment of this application provides a chip system including an input / output (I / O) device 11 and an SoC chip 12, both separate from the SoC chip. When the I / O device 11 and the SoC chip 12 are connected via a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe), the I / O device 11 can be a PCIe board. When the I / O device 11 and the SoC chip 12 are connected via a network transmission protocol, the I / O device 11 can be an Ethernet interface.

[0062] I / O device 11 uses the x86 architecture, and its corresponding strong sequential model is the TSO model. SoC chip 12 uses the ARM architecture, and its corresponding weak sequential model is the RM model.

[0063] For example, the SoC chip 12 may include a graphics processing unit (GPU) 120, a central processing unit (CPU) 121, a neural network processing unit (NPU) 122, a system memory management unit (SMMU) 123, a memory controller 124, and a memory 125. Optionally, it may also include a network on chip (NOC) 126. The GPU 120, CPU 121, NPU 122, SMMU 123, and memory controller 124 are interconnected via the NOC 126.

[0064] Among them, GPU 120 is the graphics processing core; CPU 121 is the general-purpose processor core; NPU 122 is the artificial intelligence (AI) dedicated processor core; SMMU 123 is the system memory management unit, used to provide address translation functions based on page tables. For example, SMMU 123 provides address translation functions between I / O device 11 and SoC chip 12; memory controller 124 is used to manage data read and write operations in memory 125; memory controller 124 may also include a home agent (HA), which is responsible for cache coherency management of SoC chip. It can be incorporated into memory controller 124 or mounted independently on NOC 126; memory 125 can be memory or on-chip memory.

[0065] Furthermore, such as Figure 2As shown, SMMU 123 may include a translation lookaside buffer (TLB) 211 and an address translation circuit 212. The TLB 211 reduces the time spent accessing user memory locations; it stores the latest translations from virtual memory to physical memory and can be referred to as an address translation cache. The address translation circuit 212 performs the translation from virtual address to physical address.

[0066] like Figure 3 As shown, the I / O device (hereinafter referred to as the second node) sends read / write requests to the memory controller (hereinafter referred to as the third node) in the SoC chip through the SMMU (hereinafter referred to as the first node). This represents a strong-sequence model device sending read / write requests to a weak-sequence model device. For I / O device read / write requests with RO constraints, both models allow out-of-order write-read requests (i.e., write first, then read), and these requests can be processed in parallel in both models. Therefore, there is no impact on the transmission bandwidth and interaction efficiency between the two models. However, for I / O device read / write requests with SO constraints, after entering the SoC chip, the corresponding read / write operations must still be executed in sequence to ensure that the globally visible execution results conform to the requirements of the strong-sequence model.

[0067] For example, taking a write operation as an example, such as Figure 4 As shown, the SMMU acts as an interface between different storage consistency models. In the strong-sequential model, I / O devices send write request 1 and write request 2 to the SMMU in parallel order. After two handshakes, the SMMU sends write request 1 and write request 2 to the memory controller in the weak-sequential model in serial order. That is, in the first handshake, the SMMU sends write request 1 and the corresponding data to the memory controller, and after completion, it sends write request 2 and the corresponding data to the memory controller in the second handshake.

[0068] Write Request 1 and Write Request 2 indicate that a write operation is to be performed; Write Response 1 and Write Response 2 indicate the data that can be received and the location where the data is stored; Write Data 1 and Write Data 2 include the data to be written and the location where the data is stored; Write Complete 1 and Write Complete 2 indicate that the write operation is complete; Acknowledge (ACK) 1 and ACK 2 indicate that the write completion has been received.

[0069] This approach means that in a weakly sequential model, multiple read / write requests with order constraints can only be executed serially. Furthermore, the SMMU and memory controller need to repeatedly handshake to ensure the execution order within the weakly sequential model, reducing transmission bandwidth and interaction efficiency between devices with different storage consistency models. It also suffers from poor versatility and scalability; when the memory controller changes, the SMMU must re-establish the sequential processing mechanism with the new node.

[0070] For example, such as Figure 5 As shown, in order to reduce the handshake time between the SMMU and the memory controller, the following measures are taken: Figure 3 The processing flow has been improved as follows: The SMMU sends write request 1 to the memory controller and receives write response 1. It does not need to wait for write request 1 to complete; it can first send write request 2 and receive write response 2. Then, the SMMU sends write data 1 and write data 2 in parallel, receives write completion 1 and write completion 2 in parallel, and sends ACK1 and ACK2 in parallel. ACK1 is sent earlier than ACK2, informing the memory controller that the execution result of the write request is now globally visible.

[0071] In this approach, the latency of the SMMU waiting for the memory controller to return a write response remains significant in certain scenarios (such as cross-chip scenarios), which still reduces the transmission bandwidth and interaction efficiency between devices with different memory consistency models. Furthermore, the SMMU and the memory controller still require at least one handshake, making the sequential processing mechanism more cumbersome.

[0072] In addition, for communication between different modules within the same storage consistency model, when the storage consistency model (such as the TSO model or SC model) requires the order in which execution results are globally visible, the transmission bandwidth and interaction efficiency within the model will also be reduced when the module that conforms to the SO constraint sends read and write requests to the module that conforms to the RO constraint.

[0073] The following is based on Figure 1 Taking the example of a processor (such as GPU 120, CPU 121, NPU 122, etc.) (hereinafter referred to as the second node) in a SOC chip belonging to the weak sequential model sending read and write requests to the memory controller 124 (hereinafter referred to as the third node) through an interface (such as NOC 126, interface modules in the processor, etc.) (hereinafter referred to as the first node) to illustrate a typical application scenario of sending read and write requests between different modules within the same storage consistency model.

[0074] For example, such as Figure 6 As shown, when a processor adhering to SO constraints issues multiple read / write requests in parallel (e.g., stream-write requests), the execution order is guaranteed by the model itself before these requests enter the out-of-order bus adhering to RO constraints. When these requests enter the out-of-order bus through the interface with the out-of-order bus and are sent to the memory controller, a similar approach is used to ensure that the globally visible order of execution results conforms to the requirements of the strong order model. Figure 4 Serial execution mode or Figure 5 Partial serial execution method ( Figure 6 (not shown in the image), which will reduce the transmission bandwidth and interaction efficiency within the model.

[0075] Therefore, this application provides a read / write operation execution method that can be applied to communication between different storage consistency models, as well as to communication between different modules within the same storage consistency model, in order to optimize the transmission bandwidth and interaction efficiency within the model.

[0076] For communication between different storage consistency models, such as Figure 7 As shown, by extending the cache coherence (CC) domain of the weak-sequential model to include the SMMU (Memory Management Unit) interface node between different models, sequential processing is completed at the SMMU. This allows parallel read / write requests from the strong-sequential model to be processed in parallel within the weak-sequential model, improving transmission bandwidth and interaction efficiency between devices adhering to SO (Sequential Execution) and RO (Restricted Execution) constraints. Furthermore, since sequential processing is completed at the SMMU, the memory controller of the weak-sequential model does not require a sequential processing mechanism. When the memory controller changes, the sequential processing mechanism does not need to be re-established, thus enhancing its versatility and extensibility.

[0077] Because read and write requests have a clear order in the software, and the strong ordering model of the I / O device constrains the order between these read and write requests, read and write requests can be processed in parallel efficiently after being issued in sequence within the strong ordering model.

[0078] When read / write requests reach the SMMU (Memory Management Unit) at the interface between the two models, to ensure execution order in the weak-order model, before adopting the solution provided in this application, cache consistency was handled by the memory controller within the weak-order model. The SMMU did not participate in cache consistency management, therefore, cache consistency processing could not be performed at the SMMU to ensure that the globally visible order of execution results in the weak-order model met the requirements of the strong-order model. Cache consistency could only be achieved by the memory controller through a handshake process, leading to reduced transmission bandwidth and interaction efficiency between devices with different storage consistency models. This application extends the cache consistency domain of the weak-order model, moving the cache consistency handling authority from the internal memory controller to the SMMU. Upon receiving read / write requests from the strong-order model, the SMMU can complete the order processing, ensuring that the globally visible order of execution results in the weak-order model meets the requirements of the strong-order model.

[0079] After the SMMU completes sequential processing, serial handshakes with I / O devices can be avoided, and read and write requests can be processed in parallel in a weak sequential model, improving parallel processing efficiency.

[0080] For communication between different modules within the same storage consistency model, such as Figure 8As shown, the CC scope that conforms to RO constraints can be extended to include the interface between modules that conform to SO constraints (e.g., processors) and modules that conform to RO constraints (e.g., memory controllers) within the model. This allows read and write requests from modules that conform to SO constraints to be processed in parallel at the interface and modules that conform to RO constraints, thereby optimizing the transmission bandwidth and interaction efficiency within the model.

[0081] In addition, this application extends the cache coherency domain of the weak ordering model, moving the processing authority for cache coherency from the memory controller to the interface between the processor and the memory controller. This interface can complete the sequential processing after receiving read and write requests from the processor, ensuring that the execution results are globally visible to modules that comply with RO constraints in an order that meets the requirements of modules that strongly comply with RO constraints.

[0082] like Figure 9 As shown in the embodiments of this application, the read / write operation execution method includes:

[0083] S901, The first node receives the first message and the second message from the second node.

[0084] The first message requests read and write operations on the first address managed by the third node, and the second message requests read and write operations on the second address managed by the third node. The execution order constraints for the read and write operations on the second node are stricter than those on the third node; that is, the second node adheres to the SO constraint, and the third node adheres to the RO constraint. Because the second node adheres to the SO constraint, in practice, the first message requests read and write operations on the first address managed by the third node in a strictly ordered manner, and the second message requests read and write operations on the second address managed by the third node in a strictly ordered manner.

[0085] For communication between different storage consistency models, the second node refers to the device that adheres to SO constraints in the strong ordering model, and the third node refers to the device that adheres to RO constraints in the weak ordering model. The first node refers to the interface node located between the strong ordering model and the weak ordering model. The first node can be an independent device, or it can be an interface module in the second or third node.

[0086] For example, the second node can be Figure 1 The I / O device 11 located outside the SoC chip 12 is used to send read and write requests; the third node can be Figure 1 The memory controller 124 or the HA in the SoC chip 12 is used for cache coherency management, such as managing the directory of the storage space; the first node can be the MMU, for example, it can be... Figure 1 The SMMU 123 in the SoC chip 12 or such Figure 10The read / write operation execution circuit 213 in the SMMU 123 shown is in Figure 2 The SMMU 123 shown is newly added to execute the read / write operation execution method provided in this application.

[0087] further, Figure 10 A schematic diagram of a read / write operation execution circuit 213 is provided. The read / write operation execution circuit 213 includes a sequential processing module 2131, an operation permission judgment module 2132, and a data cache judgment module 2133.

[0088] The sequence processing module 2131 is used to record the order in which the first message and the second message are received, and is used by the access control module 2132 to perform read and write operations in the order.

[0089] The operation permission determination module 2132 records whether operation permissions (e.g., E-state) for the first address and the second address (e.g., E-state) have been received. Based on the order of the first and second messages recorded by the sequence processing module 2131, it determines the order of read and write operations on the first and second addresses. For example, if the sequence processing module 2131 records that the first message was received before the second message, then the sequence processing module 2131 will first send a writeback message for the first address, and then send a writeback message for the second address. For write operations, the writeback message may include the write operation type and the target address (first address or second address); for read operations, the writeback message may include the read operation type and the target address.

[0090] The data cache determination module 2133 is used to record whether the identifier of the cache address corresponding to the first address returned by the memory controller (e.g., data buffer ID (DBID) and the identifier of the cache address corresponding to the first address (e.g., DBID) are received, so as to determine whether data needs to be sent.

[0091] It should be noted that in scenarios where I / O devices access SoC on-chip storage, i.e., communication between different storage consistency models, the read / write operation execution circuit 214, as the first node, can be located in the SMMU; similarly, in scenarios where on-chip processors access on-chip storage, i.e., communication between different modules within the same storage consistency model, the read / write operation execution circuit 214, as the first node, can be located in the NOC or the on-chip processor.

[0092] It should also be noted that this application describes a communication scenario between different storage consistency models as an example, but it is not intended to be limited thereto.

[0093] For communication between modules within the same storage consistency model, the first node refers to the module that conforms to the SO constraint in the storage consistency model, the third node refers to the module that conforms to the RO constraint in the storage consistency model, and the second node refers to the interface module in the storage consistency model used for interaction between the first node and the third node.

[0094] For example, the second node is Figure 1 The first node is the processor in the SoC chip (e.g., GPU 120, CPU 121, NPU 122, etc.), the second node is the on-chip NOC 126 in the SoC chip or the processor's interface module (this module is a hardware circuit), and the third node is the memory controller 124 in the SoC chip or the HA in the memory controller 124. Alternatively, the first, second, and third nodes can be different hardware modules inside the processor.

[0095] The read and write operations involved in this application can support write-write (write first, then write), write-read (write first, then read), read-write (read first, then write), and read-read (read first, then read). The first message or the second message can be a write request, corresponding to a write operation, or it can be a read request, corresponding to a read operation. There is no limitation to one first message or second message; there can be multiple messages. Furthermore, the message types of the first message and the second message can be the same, for example, both being write requests (i.e., write-write requests) or read requests (i.e., read-read requests), or they can be different, for example, one being a write request and the other a read request (i.e., write-read requests or read-write requests). The first address of the first message and the second address of the second message can be the same or different.

[0096] For example, such as Figure 11 As shown, the second node can send a first message and a second message to the first node. Both messages can be write request messages. The first message requests write operations on the first address managed by the third node in strict order, and the second message requests write operations on the second address managed by the third node in strict order.

[0097] S902, The first node obtains the operation permissions for the first address and the second address from the third node.

[0098] Operation permissions can refer to the E-state in cache consistency, which represents the operation permissions a node has for that address. In other words, the first node can obtain the E-state of the first address and the E-state of the second address from the third node.

[0099] After the first node acquires the operation permissions for the first address and the second address, the CC scope is extended from the third node to the first node, enabling the first node to participate in the management of cache consistency in the weak order model. Other nodes (such as the third node) cannot perform read and write operations on the first and second addresses that require operation permissions. That is, the third node's permission to process read and write requests in the order has been transferred to the first node, and the execution order of read and write operations on the first and second addresses is controlled by the first node.

[0100] The following explains in detail how the first node obtains operation permissions for the first address and the second address.

[0101] The first node can send a third message to the third node, which includes the first address. A second message is used to request access permissions for the first address. Upon receiving the second message, the third node can send a fourth message to the first node. This fourth message can be a response to the third message and indicates the access permissions granted to the first address. After receiving the fourth message, the first node can send an acknowledgment message to the third node, confirming receipt of the fourth message.

[0102] Similarly, the first node can send a third message to the third node, which includes the second address and requests access permissions for that address. Upon receiving the second message, the third node can send a fourth message to the first node. This fourth message can be a response to the third message and indicates the access permissions granted to the second address. After receiving the fourth message, the first node can send an acknowledgment message to the third node, confirming receipt of the fourth message.

[0103] This application does not limit the order in which the first node obtains the operation permission of the first address and the operation permission of the second address from the third node. For example, assuming that the first node receives the first message (including the first address) first and then receives the second message (including the second address), the first node can obtain the operation permission of the second address first and then obtain the operation permission of the first address.

[0104] The following is combined Figure 11 Explain how the first node obtains operation permissions for the first address and the second address.

[0105] For example, such as Figure 11As shown, the first node can send third message 1 and third message 2 to the third node. Third message 1 and third message 2 can be GET_E messages. Third message 1 includes the first address, and third message 2 includes the second address. Third message 1 is used to request operation permission from the first address, and third message 2 is used to request operation permission from the second address. This application does not limit the order in which the first node sends third message 1 and third message 2 to the third node.

[0106] The third node sends fourth message 1 and fourth message 2 to the first node. Fourth message 1 can be a response message to third message 1 (RSP1), and fourth message 2 can be a response message to third message 2 (RSP2). Correspondingly, the first node receives fourth message 1 and fourth message 2 from the third node. Fourth message 1 is used to instruct the first node to obtain operation permission for the first address, and fourth message 2 is used to instruct the first node to obtain operation permission for the second address.

[0107] The first node sends ACK1 (acknowledgment message 1) and ACK2 (acknowledgment message 2) of the fourth message 1 to the third node. These two acknowledgment messages are used to indicate that the first node has received the fourth message.

[0108] Steps S901 and S902 can be executed in any order. For example, step S901 can be executed first and then step S902, or step S902 can be executed first and then step S901.

[0109] S903, The first node performs read and write operations on the first address and the second address.

[0110] This application does not limit the execution order of the first node's read and write operations on the first address and the second address. In one possible implementation, the first node can perform read and write operations on the first address and the second address in parallel. Parallel means that the next read and write operation is performed before the previous read and write operation is completed, thereby realizing the parallel processing of multiple read and write operations in a weakly sequential model.

[0111] By performing read and write operations on the first and second addresses in parallel on the first node, requests from the strong order model can be processed in parallel, thereby improving the transmission bandwidth and interaction efficiency between the node that conforms to the SO constraint (the second node) and the node that conforms to the RO constraint (the third node).

[0112] The order in which the first node begins reading and writing operations on the first and second addresses can be the same as the order in which the first and second messages were received. In other words, the first node can perform read and write operations on the first and second addresses in parallel, following the order in which the first and second messages were received. For example, if the first node receives the first message first and then the second message, it can perform read and write operations on the first address first, followed by the second address. This ensures that the first node completes the sequential processing of read and write requests, thus achieving storage consistency.

[0113] The following section explains in detail how the first node performs read and write operations on the first and second addresses.

[0114] The first node can send a fifth message to the third node. This fifth message indicates a read / write operation on the first address and can be a writeback message. For a write operation, the fifth message may include the data to be written, the write operation type, and the first address; for a read operation, it may include the read operation type and the first address. Similarly, the first node can send a fifth message to the third node. This fifth message indicates a read / write operation on the second address and can be a writeback message. For a write operation, the fifth message may include the data to be written, the write operation type, and the second address; for a read operation, it may include the read operation type and the second address.

[0115] The order in which the first node sends the fifth message corresponding to the first address and the fifth message corresponding to the second address can be the same as the order in which the first message and the second message are received. For example, if the first node receives the first message first and then the second message, then the first node will send the fifth message corresponding to the first address first and then the fifth message corresponding to the second address.

[0116] After receiving the fifth message, the third node can send a sixth message to the first node. This sixth message can be a response to the fifth message and indicates the cache address corresponding to the first address. Similarly, after receiving the fifth message, the third node can send a sixth message to the first node. This sixth message can be a response to the fifth message and indicates the cache address corresponding to the second address.

[0117] After receiving the sixth message, the first node sends a seventh message to the third node. This seventh message can be a WriteData message, used to perform read and write operations on the cache address corresponding to the first address. Similarly, after receiving the sixth message, the first node sends a seventh message to the third node. This seventh message can also be a WriteData message, used to perform read and write operations on the cache address corresponding to the second address.

[0118] For example, such as Figure 11 As shown, the first node sends fifth message 1 and fifth message 2 to the third node. Fifth message 1 and fifth message 2 can be write-back messages. Fifth message 1 corresponds to the first message and indicates a write operation to the first address; fifth message 2 corresponds to the second message and indicates a write operation to the second address. Since the first node receives the first message from the second node before receiving the second message, the first node sends fifth message 1 to the third node before sending fifth message 2. Parallelism here means that the first node does not need to wait for all read and write operations corresponding to fifth message 1 to complete before sending fifth message 2.

[0119] The third node sends sixth message 1 and sixth message 2 to the first node. Sixth message 1 can be a response message to fifth message 1 (RSP3), and sixth message 2 can be a response message to fifth message 2 (RSP4). Sixth message 1 is used to indicate the cache address corresponding to the first address, and fifth message 2 is used to indicate the cache address corresponding to the second address.

[0120] The first node sends seventh message 1 and seventh message 2 to the third node. The seventh message can be a write data message. Seventh message 1 is used to write data to the cache address corresponding to the first address, and seventh message 2 is used to write data to the cache address corresponding to the second address.

[0121] After completing read / write operations on the first address, the first node can release access to that address to the third node. For example, the seventh message mentioned above can also be used to release access to the first address to the third node. This allows the third node or other nodes to continue reading and writing to the first address. Similarly, after completing read / write operations on the second address, the first node can release access to the second address to the third node. For example, the seventh message mentioned above can also be used to release access to the second address to the third node. This allows the third node or other nodes to continue reading and writing to the second address.

[0122] For example, such as Figure 11 As shown, message 1 is also used to instruct the third node to release the operation permission of the first address; message 2 is also used to instruct the third node to release the operation permission of the second address.

[0123] The read / write operation execution method provided in this application embodiment involves a first node receiving a first message and a second message from a second node. The second node adheres to SO constraints. The first message requests read / write operations on a first address managed by a third node, and the second message requests read / write operations on a second address managed by the third node. The third node adheres to RO constraints. The first node then acquires operation permissions for both the first and second addresses from the third node, enabling it to participate in cache consistency management. Other nodes are unable to perform read / write operations requiring specific permissions on the first and second addresses. In other words, the execution order of read / write operations on the first and second addresses is controlled by the first node, and consequently, the order in which the execution results are globally visible is also controlled by the first node. This ensures that the globally visible order of read / write operation results performed by nodes adhering to RO constraints meets the requirements of nodes adhering to SO constraints.

[0124] The following is combined Figures 12-19 Based on the principle of cache consistency, this paper explains how the first node will handle the following situation if, during the interaction between the first and third nodes for read and write operations, another node needs to perform read and write operations on the first address (or the second address) that require operation permissions, and the third node requests operation permissions from the first address (or the second address) or performs read and write operations on the first address (or the second address) that require operation permissions, in order to meet the storage consistency requirements and ensure that the globally visible order of execution results conforms to the requirements of the strong order model.

[0125] In one possible implementation, if a first node, while requesting but not obtaining permission to operate on a first address, receives a request from a third node for a read / write operation requiring permission on the first address, or a request for permission to operate on the first address itself, then the first node indicates to the third node that it has not obtained permission to operate on the first address. Similarly, if a first node, before requesting but not obtaining permission to operate on a second address, receives a request from a third node for a read / write operation requiring permission on the second address, or a request for permission to operate on the second address itself, then the first node indicates to the third node that it has not obtained permission to operate on the second address. Figure 12 As shown, the above read / write operation execution method also includes:

[0126] S1201. Before the first node obtains operation permission for the first address (or the second address), the first node receives the eighth message from the third node.

[0127] The eighth message is used to request read / write operations requiring permissions on the first address, or in other words, to request permission to operate on the first address. Similarly, the eighth message is used to request read / write operations requiring permissions on the second address, or in other words, to request permission to operate on the second address. For example, the eighth message could be a snoop message.

[0128] For example, such as Figure 13 As shown, before the third node sends a response message (RSP1) of the third message 1 (GET_E1) to the first node to enable the first node to obtain operation permission for the first address (or the second address), the third node sends an eighth message (sniffing message) to the first node, so that the first node receives the eighth message from the third node. The eighth message is used to request read and write operations that require operation permission on the first address (or the second address), or to request operation permission for the first address (or the second address).

[0129] S1202, The first node sends the ninth message to the third node.

[0130] The ninth message indicates that access to the first address (or second address) has not been granted. The ninth message can be a response to the eighth message; for example, it can be a sniffing response message.

[0131] For example, such as Figure 13 As shown, the first node sends the ninth message (sniffing response message) to the third node, while the eighth message is used to indicate that the operation permission for the first address (or the second address) has not been obtained.

[0132] In this implementation, if a third node requests a read / write operation requiring access to the first address before the first node acquires access to that address, or requests access to the first address in general, the first node indicates to the third node that it has not acquired access to the first address. This allows the third node or other nodes to perform read / write operations on the first address. Similarly, if a third node requests a read / write operation requiring access to the second address before the first node acquires access to that address, or requests access to the second address in general, the first node indicates to the third node that it has not acquired access to the second address. This allows the third node or other nodes to perform read / write operations on the second address.

[0133] In another possible implementation, if a third node requests a read / write operation requiring permissions on the first address, or requests permission to operate on the first address, before the first node begins writing to the first address but obtains the corresponding cache address, then the first node, after obtaining the corresponding cache address, sends the data to be written to the cache address corresponding to the first address to the third node, or indicates that permission to operate on the first address has been released. Similarly, if a third node requests a read / write operation requiring permissions on the second address, or requests permission to operate on the second address, before the first node begins writing to the second address but obtains the corresponding cache address, then the first node, after obtaining the corresponding cache address, sends the data to be written to the cache address corresponding to the second address to the third node, or indicates that permission to operate on the second address has been released. Figure 14 As shown, the above read / write operation execution method also includes:

[0134] S1401: When the first node starts writing to the first address (or the second address) but does not obtain the cache address corresponding to the first address (or the second address), the first node receives the twelfth message from the third node.

[0135] The twelfth message is used to request read or write operations that require specific permissions on the first (or second) address; in other words, it is used to request permission to operate on the first (or second) address. For example, the twelfth message could be a snoop message.

[0136] For example, such as Figure 15 As shown, before the third node sends the sixth message (including the cache address corresponding to the first address (or the second address)) to the first node, the third node sends the twelfth message (sniffing message) to the first node, so that the first node receives the twelfth message from the third node. The twelfth message is used to request read and write operations that require operation permissions on the first address (or the second address), or to request operation permissions on the first address (or the second address).

[0137] S1402. After obtaining the cache address corresponding to the first address (or the second address), the first node sends the thirteenth message to the third node.

[0138] For example, such as Figure 15 As shown, after the first node receives the sixth message 1 (including the cache address corresponding to the first address (or the second address) from the first node, it sends the thirteenth message to the third node. The thirteenth message can be a response message to the twelfth message; for example, the thirteenth message can be a sniffing response message.

[0139] In one possible implementation, the thirteenth message may include data written to the cached address corresponding to the first address (or the second address). The thirteenth message may have the functionality of the seventh message in place of the seventh message; that is, the thirteenth message may also be used to instruct the third node to release the operation permission of the first address (or the second address).

[0140] In another possible implementation, the thirteenth message can be sent after the seventh message (in which case the seventh message is used to indicate that the operation permission of the first address (or the second address) has been released to the third node), to indicate that the operation permission of the first address (or the second address) has been released.

[0141] exist Figure 14 and Figure 15 In the illustrated implementation, if a third node requests read / write operations requiring permissions on the first address, or requests permission to operate on the first address, before the first node begins writing to the first address but obtains the corresponding cache address, then after obtaining the cache address, the first node sends the data to be written to the cache address, or indicates that permission to operate on the first address has been released. Alternatively, after obtaining the cache address, the first node sends the data to be written to the cache address, allowing the third node to directly obtain the data; or, after sending the seventh message, the first node indicates that permission to operate on the first address has been released, allowing the third node or other nodes to perform read / write operations on the first address.

[0142] Similarly, if a third node requests read / write operations requiring permissions on the second address, or requests permission to operate on the second address, before the first node begins writing to the second address but before obtaining the corresponding cache address, then after obtaining the cache address, the first node sends the data to be written to the cache address, or indicates that permission to operate on the second address has been released. Alternatively, after sending the seventh message, the first node indicates that permission to operate on the second address has been released, allowing the third node or other nodes to perform read / write operations on the second address.

[0143] After the first node acquires access permissions for both the first and second addresses from the third node, it can release these permissions to the third node when preset conditions are met. This allows the third node or other nodes to perform read and write operations on both addresses.

[0144] In one possible implementation, the preset condition is that the third node requests operation permissions for the first and second addresses.

[0145] For example, if a third node requests to perform a read / write operation requiring permissions on the first address, or requests permissions for the first address in general, after the first node has acquired permission to operate on the first address but before it begins reading / writing operations on the first address, then the first node releases the permission to operate on the first address from the third node and reacquires permission for the first address from the third node. Similarly, if a third node requests to perform a read / write operation requiring permissions on the second address, or requests permissions for the second address in general, after the first node has acquired permission to operate on the second address but before it begins reading / writing operations on the second address, then the first node releases the permission to operate on the second address from the third node and reacquires permission for the second address from the third node. Figure 16 As shown, the above read / write operation execution method also includes:

[0146] S1601. After the first node obtains the operation permission for the first address (or the second address) and before it starts reading and writing operations on the first address (or the second address), the first node receives the tenth message from the third node.

[0147] The tenth message is used to request read or write operations that require specific permissions on the first (or second) address; in other words, it is used to request permission to operate on the first (or second) address. For example, the tenth message could be a snoop message.

[0148] For example, such as Figure 17 As shown, before the first node sends the fourth message 1 to the third node, the third node sends the tenth message (sniffing message) to the first node, so that the first node receives the tenth message from the third node. The tenth message is used to request read and write operations that require operation permissions on the first address (or the second address), or to request operation permissions on the first address (or the second address).

[0149] S1602. The first node sends an eleventh message to the third node and re-obtains the operation permission for the first address (or the second address) from the third node.

[0150] The eleventh message is used to instruct the release of access permissions for the first address (or the second address). The eleventh message can be a response to the tenth message; for example, the eleventh message can be a sniffing response message.

[0151] For example, such as Figure 17As shown, the first node sends an eleventh message (sniffing response message) to the third node. The eleventh message is used to indicate the release of operation permissions for the first address (or the second address), and resends the third message (GET_E) to the third node. It then receives the fourth message (RSP1 / RSP2) from the third node to obtain operation permissions for the first address (or the second address), and sends an acknowledgment message (ACK1) for the fourth message to the third node. Finally, it re-executes the read / write operation process for the first address (or the second address) and the process of releasing the operation permissions for the first address (or the second address).

[0152] In this implementation, if a third node requests read / write operations on the first address requiring specific permissions, or requests permission to access the first address, after the first node has acquired permission to access the first address but before it begins reading / writing operations on that address, then the first node releases the permission to access the first address from the third node and re-acquires permission from the third node. After the first node releases the permission to access the first address, the third node can directly perform read / write operations on the first address. Once the first node re-acquires permission from the third node, it can continue reading / writing operations on the first address.

[0153] Similarly, if, after the first node has acquired access to the second address but before it begins reading or writing to it, the third node requests access to the second address, or requests access to the second address in general, then the first node releases access to the second address from the third node and re-acquires access from the third node. After the first node releases access to the second address, the third node can directly perform read and write operations on the second address. Once the first node re-acquires access from the third node, it can continue performing read and write operations on the second address.

[0154] In another possible implementation, the preset conditions are that the time it takes for the first node to obtain operation permission for the first address from the third node is greater than or equal to a first preset time, and the time it takes for the first node to obtain operation permission for the second address from the third node is greater than or equal to a second preset time. The first preset time and the second preset time can be the same or different.

[0155] As mentioned above, steps S901 and S902 have no specific execution order. For example, if step S902 is executed before step S901, the first node pre-acquires operation permissions for the first address (or second address). Upon receiving the first message (or second message), it can quickly perform read and write operations on the first address (or second address). The first node can pre-acquire operation permissions for the first address (or second address) based on historical read and write operations.

[0156] If, within a preset time period after the first node obtains operation permissions for the first address from the third node, it does not receive the first message, then the first node releases the operation permissions for the first address to the third node. Similarly, if, within a preset time period after the first node obtains operation permissions for the second address from the third node, it does not receive the second message, then the first node releases the operation permissions for the second address to the third node.

[0157] For example, such as Figure 18 As shown, after the first node obtains operation permissions for the first address (or second address) through the third and fourth messages, if it does not receive the first message (or second message) after a preset time, the first node sends the fourteenth message to the third node to instruct the release of operation permissions for the first address (or second address). Subsequently, when the first node receives the first message (or second message) again, it re-executes the interaction process corresponding to steps S902-S903 above to complete the read / write operation.

[0158] For example, such as Figure 19 As shown, after the first node obtains the operation permission of the first address (or the second address) through the third message and the fourth message, if it receives the first message (or the second message) within a preset time, the first node will execute the interaction process corresponding to step S903 to complete the read and write operation.

[0159] In this implementation, after receiving a read / write request from the second node, the first node no longer needs to execute the process of obtaining operation permissions and can quickly perform read / write operations on the first address (or the second address).

[0160] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0161] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0162] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0163] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0164] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0165] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0166] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0167] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for performing read / write operations, characterized in that, include: The first node receives the first message and the second message from the second node; The first message is used to request read and write operations on the first address managed by the third node; The second message is used to request read and write operations on the second address managed by the third node; the execution order constraints of the read and write operations of the second node are stricter than those of the read and write operations of the third node. The first node obtains the operation permissions for the first address and the second address from the third node; The first node performs read and write operations on the first address and the second address; When the first node requests operation permission for the first address but does not obtain operation permission for the first address, and receives a request from the third node to perform a read / write operation on the first address that requires operation permission, or receives a request from the third node to obtain operation permission for the first address, the first node indicates to the third node that it has not obtained operation permission for the first address. When the first node requests operation permission for the second address but does not obtain operation permission for the second address, and receives a request from the third node to perform a read / write operation on the second address that requires operation permission, or receives a request from the third node to obtain operation permission for the second address, the first node indicates to the third node that it has not obtained operation permission for the second address.

2. The method according to claim 1, characterized in that, The first node performs read and write operations on the first address and the second address, including: The first node performs read and write operations on the first address and the second address in parallel.

3. The method according to claim 2, characterized in that, The first node performs read and write operations on the first address and the second address in parallel, including: The first node performs read and write operations on the first address and the second address in parallel according to the order in which the first message and the second message are received.

4. The method according to any one of claims 1-3, characterized in that, The second node follows the strict order SO constraint, and the third node follows the loose order RO constraint.

5. The method according to any one of claims 1-3, characterized in that, Also includes: After completing the read and write operations on the first address, the first node releases the operation permission for the first address to the third node; After completing the read and write operations on the second address, the first node releases the operation permission for the second address to the third node.

6. The method according to any one of claims 1-3, characterized in that, The first node obtains operation permissions for the first address and the second address from the third node, including: The first node obtains the exclusive state E of the first address and the E state of the second address from the third node.

7. The method according to any one of claims 1-3, characterized in that, After the first node obtains the operation permissions for the first address and the second address from the third node, the method further includes: When the preset conditions are met, the first node releases the operation permissions of the first address and the second address to the third node.

8. The method according to claim 7, characterized in that, The preset condition is that the third node requests operation permissions from the first address and the second address.

9. The method according to claim 7, characterized in that, The preset conditions are that the time for the first node to obtain the operation permission of the first address from the third node is greater than or equal to a first preset time, and the time for the first node to obtain the operation permission of the second address from the third node is greater than or equal to a second preset time.

10. The method according to any one of claims 1-3, characterized in that, The second node is an input / output I / O device outside the System-on-a-Chip (SoC) chip, the first node is the Memory Management Unit (MMU) in the SoC chip, and the third node is the Memory Controller (MCM) in the SoC chip or the Local Agent (HA) in the MCM.

11. The method according to any one of claims 1-3, characterized in that, The second node is the processor in the SoC chip, the first node is the on-chip interconnect network (NOC) in the SoC chip or the interface module of the processor, and the third node is the memory controller in the SoC chip or the HA in the memory controller.

12. A system-on-a-chip (SoC) chip, characterized in that, include: First node and memory controller, The first node is used for: Receive a first message and a second message from the second node; the first message is used to request read / write operations on a first address managed by the memory controller; the second message is used to request read / write operations on a second address managed by the memory controller; the execution order constraints of the read / write operations of the second node are stricter than those of the read / write operations of the memory controller. Obtain operation permissions for the first address and the second address from the memory controller; Perform read and write operations on the first address and the second address; The first node is also used for: When requesting access to the first address but not obtaining access to the first address, if the system receives a request from the memory controller to perform a read / write operation on the first address that requires access, or if the system receives a request from the memory controller to obtain access to the first address, the system indicates to the memory controller that access to the first address has not been obtained. When requesting access to the second address but not obtaining access to the second address, if the system receives a request from the memory controller to perform a read / write operation on the second address that requires access, or if the system receives a request from the memory controller to obtain access to the second address, the system indicates to the memory controller that access to the second address has not been obtained.

13. The SoC chip according to claim 12, characterized in that, The first node is specifically used for: Read and write operations are performed on the first address and the second address in parallel.

14. The SoC chip according to claim 13, characterized in that, The first node is specifically used for: Read and write operations are performed on the first address and the second address in parallel according to the order in which the first message and the second message are received.

15. The SoC chip according to any one of claims 12-14, characterized in that, The second node adheres to strict order SO constraints, while the memory controller adheres to loose order RO constraints.

16. The SoC chip according to any one of claims 12-14, characterized in that, The first node is also used for: After completing the read / write operation on the first address, the access permission for the first address is released to the memory controller; After completing the read / write operation on the second address, the access permission for the second address is released to the memory controller.

17. The SoC chip according to any one of claims 12-14, characterized in that, The first node is specifically used for: Obtain the exclusive E state of the first address and the E state of the second address from the memory controller.

18. The SoC chip according to any one of claims 12-14, characterized in that, After obtaining operation permissions for the first address and the second address from the memory controller, the first node is further configured to: When the preset conditions are met, the operation permissions for the first address and the second address are released to the memory controller.

19. The SoC chip according to claim 18, characterized in that, The preset condition is that the memory controller requests operation permissions for the first address and the second address.

20. The SoC chip according to claim 18, characterized in that, The preset conditions are that the time for the first node to obtain the operation permission of the first address from the memory controller is greater than or equal to a first preset time, and the time for the first node to obtain the operation permission of the second address from the memory controller is greater than or equal to a second preset time.

21. The SoC chip according to any one of claims 12-14, characterized in that, The second node is an input / output I / O device outside the SoC chip, and the first node is the memory management unit (MMU) in the SoC chip.

22. The SoC chip according to any one of claims 12-14, characterized in that, The second node is the processor in the SoC chip, and the first node is the on-chip interconnect network (NOC) in the SoC chip or the interface module of the processor.

23. The SoC chip according to any one of claims 12-14, characterized in that, The first node includes a sequential processing module, an operation permission judgment module, and a data cache judgment module; The sequence processing module is used to record the order in which the first message and the second message are received; The operation permission determination module is used to record whether operation permissions for the first address and the second address have been received, and to determine the order of reading and writing operations on the first address and the second address according to the order. The data cache determination module is used to record whether the identifier of the cache address corresponding to the first address and the identifier of the cache address corresponding to the second address are received, thereby determining whether to send data.

Images