Memory system

Abstract

Embodiments provide a memory system capable of avoiding mutual interference between cells, reducing write buffer capacity, and suppressing bit error rate deviation. In the memory system, a memory controller within the memory system: causes a nonvolatile memory to perform first programming so that a threshold region in a memory cell becomes, according to first, second, and fourth bit data, a certain threshold region among a 17th threshold region that indicates an erased state in which data has been erased and 18th to 24th threshold regions that indicate a written state in which data has been written at a voltage level higher than the 17th threshold region, causes the nonvolatile memory to perform second programming so that the threshold region in the memory cell changes, according to third bit data, from a certain threshold region among the 17th to 24th threshold regions to a certain threshold region within two threshold regions among the 1st to 16th threshold regions, and inputs, to the nonvolatile memory, the second and third bit data in a case where the nonvolatile memory is caused to perform the second programming.

Description

[0001] This application is a divisional application of the national patent application No. 202010848525.6, filed on August 21, 2020, entitled "Memory System". Technical Field

[0002] Embodiments of this disclosure relate to memory systems. Background Technology

[0003] In NAND flash memory, multi-valued data consisting of multiple bits is typically written to memory cells. Triple Level Cell (TLC) technology, which writes multi-valued data consisting of 3 bits, is currently in practical use. In the future, Quadruple Level Cell (QLC) technology, which writes multi-valued data consisting of 4 bits, will become the mainstream.

[0004] In QLC, to avoid interference between cells, the following method was studied: after writing 4 bits of data to the first memory cell, 4 bits of data are also written to the adjacent cell simultaneously. Then, another 4 bits of data are written to the first memory cell simultaneously. However, in this method, the 4 bits of data need to be held in a write buffer within the memory controller until the rewrite is complete.

[0005] In recent years, NAND flash memory has been made three-dimensional, which presents the following problems: the required write buffer memory capacity increases, and the cost of memory controllers with built-in write buffers increases. Therefore, in three-dimensional non-volatile memory, countermeasures are needed to reduce the write buffer size of the memory controller.

[0006] As a countermeasure to reduce the write buffer size of the memory controller while avoiding mutual interference between cells, the following method is known: when writing data to a memory cell, write in two stages, so that it is not necessary to rewrite all the data.

[0007] However, this method suffers from a large deviation in the bit error rate when writing data to the storage unit.

[0008] To improve the reliability of QLC technology, it is necessary to avoid mutual interference between cells, reduce the capacity of the write buffer in the memory controller, and suppress the deviation of the bit error rate when writing each bit of data. Summary of the Invention

[0009] One technical solution disclosed herein provides a memory system that can avoid inter-cell interference, reduce the capacity of the write buffer in the memory controller, and suppress the deviation of bit error rate when writing each bit of data.

[0010] According to this embodiment, a memory system is provided, comprising: a non-volatile memory having a plurality of memory cells, each of the plurality of memory cells being capable of storing 4 bits of data represented by a 1st bit to a 4th bit using 16 threshold regions, the 16 threshold regions including a first threshold region indicating an erased state, and second to 16th threshold regions having a higher voltage level than the first threshold region indicating a written state; and a memory controller, which, after causing the non-volatile memory to perform a first programming operation to write the 1st bit, the 2nd bit, and the 4th bit of data, causes the non-volatile memory to perform a second programming operation to write the 3rd bit of data, wherein the largest of the following is a list of 15 boundaries existing between adjacent threshold regions in the first to 16th threshold regions: the number of first boundaries used to determine the value of the 1st bit of data, the number of second boundaries used to determine the value of the 2nd bit of data, the number of third boundaries used to determine the value of the 3rd bit of data, and the number of fourth boundaries used to determine the value of the 4th bit of data. The first value is 5, the second largest value is 4. The memory controller is configured to perform the first programming on the non-volatile memory such that the threshold region in the memory cell becomes, based on the first bit, the second bit, and the fourth bit data, a threshold region among the following threshold regions: a 17th threshold region indicating an erased state (data has been erased), and a 18th to 24th threshold regions with a higher voltage level than the 17th threshold region indicating a written state (data has been written). The memory controller is configured to perform the second programming on the non-volatile memory such that the threshold region in the memory cell changes from a threshold region among the 17th to 24th threshold regions to a threshold region among two threshold regions among the 1st to 16th threshold regions based on the third bit data. The number of threshold regions between the lowest and highest voltage levels among the two threshold regions is two or less. The memory controller is configured to input the second bit data and the third bit data into the non-volatile memory when performing the second programming on the non-volatile memory. Attached Figure Description

[0011] Figure 1 This is a block diagram showing the general configuration of the memory system according to the first embodiment.

[0012] Figure 2 This is a block diagram illustrating an example of the internal structure of the non-volatile memory in this embodiment.

[0013] Figure 3 This is a circuit diagram representing an example of a three-dimensional NAND memory cell array.

[0014] Figure 4 It is a cross-sectional view of a portion of the NAND memory cell array of a three-dimensional NAND memory.

[0015] Figure 5 This is a diagram illustrating an example of the threshold region in the first embodiment.

[0016] Figure 6A This is a diagram illustrating an example of data coding in the first embodiment.

[0017] Figure 6B This is a diagram illustrating another example of data encoding in the first embodiment.

[0018] Figure 7 This is a diagram showing the programmed threshold region in the first embodiment.

[0019] Figure 8A This is a diagram showing the first example of the programming order in the first implementation.

[0020] Figure 8B This is a diagram showing the second example of the programming order in the first embodiment.

[0021] Figure 8C This is a diagram representing the third example of the programming order in the first implementation.

[0022] Figure 9 This is a flowchart of the first example of the writing steps (writing process) of a block as a whole in the first embodiment.

[0023] Figure 10 This is a flowchart illustrating the writing steps of the first stage of the first embodiment.

[0024] Figure 11 This is a flowchart representing the first example of the writing step in the second stage.

[0025] Figure 12 This is a diagram used to illustrate the multiple-read result processing.

[0026] Figure 13 This is a flowchart illustrating a variation of the writing step in the second stage of the first embodiment.

[0027] Figure 14A This is a diagram illustrating the amount of data written to the buffer in Foggy-Fine programming that uses 4-3-4-4 data encoding.

[0028] Figure 14B This is a diagram illustrating the amount of data written to the buffer in this embodiment.

[0029] Figure 15 This is a flowchart illustrating the processing steps of reading pages on the word line after programming has been completed up to the first stage.

[0030] Figure 16A This is a flowchart illustrating the page reading process on the word line after programming has progressed to the second stage.

[0031] Figure 16B This is a diagram representing data encoding suitable for page read processing based on a variant.

[0032] Figure 16C This is a flowchart illustrating the reading process steps of a variant example.

[0033] Figure 16D It shows the voltage waveforms of the select word line, ReadyBusy signal line, and output data line.

[0034] Figure 17 This is a diagram illustrating an example of 1-5-4-5 data encoding.

[0035] Figure 18 This is a diagram illustrating an example of 1-5-4-5 data encoding.

[0036] Figure 19 This is a diagram illustrating an example of 3-5-2-5 data encoding.

[0037] Figure 20 This is a diagram illustrating an example of 3-3-4-5 data encoding.

[0038] Figure 21 This is a diagram illustrating an example of 2-3-5-5 data encoding.

[0039] Figure 22 This is a diagram illustrating an example of 3-2-5-5 data encoding.

[0040] Figure 23 This is a diagram illustrating an example of 3-4-4-4 data encoding.

[0041] Figure 24 This is a diagram illustrating an example of 3-4-4-4 data encoding.

[0042] Figure 25This is a diagram illustrating an example of 1-4-5-5 data encoding.

[0043] Figure 26 This is a diagram illustrating an example of 2-5-3-5 data encoding.

[0044] Figure 27 This is a diagram illustrating an example of 3-4-5-3 data encoding.

[0045] Figure 28 This is a diagram illustrating an example of 3-2-5-5 data encoding.

[0046] Figure 29 This is a diagram illustrating an example of 3-2-5-5 data encoding.

[0047] Figure 30 This is a diagram illustrating an example of 1-5-5-4 data encoding.

[0048] Figure 31 This is a diagram illustrating an example of 1-5-4-5 data encoding.

[0049] Figure 32 This is a diagram illustrating an example of 1-4-5-5 data encoding.

[0050] Figure 33 This is a diagram illustrating an example of 1-5-3-6 data encoding.

[0051] Figure 34 This is a diagram illustrating an example of 1-3-6-5 data encoding.

[0052] Figure 35 This is a diagram illustrating an example of 1-2-6-6 data encoding.

[0053] Figure 36 This is a diagram illustrating an example of 1-2-6-6 data encoding.

[0054] Figure 37 This is a diagram illustrating an example of 1-2-6-6 data encoding.

[0055] Figure 38 This is a diagram illustrating an example of 1-4-6-4 data encoding.

[0056] Figure 39 This is a diagram illustrating an example of 1-4-4-6 data encoding.

[0057] Figure 40 This is a diagram illustrating an example of 1-4-6-4 data encoding.

[0058] Figure 41 This is a diagram illustrating an example of 1-4-4-6 data encoding.

[0059] Figure 42This is a diagram illustrating an example of 2-5-2-6 data encoding.

[0060] Figure 43 This is a diagram illustrating an example of 2-5-2-6 data encoding.

[0061] Figure 44 This is a diagram illustrating an example of 2-5-2-6 data encoding.

[0062] Figure 45 This is a diagram illustrating an example of 3-3-3-6 data encoding.

[0063] Figure 46 This is a diagram illustrating an example of 3-3-6-3 data encoding.

[0064] Figure 47 This is a diagram illustrating an example of 2-3-4-6 data encoding.

[0065] Figure 48 This is a diagram illustrating an example of 3-4-2-6 data encoding.

[0066] Figure 49 This is a diagram illustrating an example of 2-3-4-6 data encoding.

[0067] Figure 50 This is a diagram illustrating an example of 3-2-6-4 data encoding.

[0068] Figure 51 This is a diagram illustrating an example of 3-2-4-6 data encoding.

[0069] Figure 52 This is a diagram illustrating an example of 3-2-6-4 data encoding.

[0070] Figure 53 This is a diagram illustrating an example of 3-4-2-6 data encoding.

[0071] Figure 54 This is a diagram illustrating an example of 3-2-4-6 data encoding.

[0072] Figure 55 This is a diagram illustrating an example of 5-3-2-5 data encoding.

[0073] Figure 56 This is a diagram illustrating an example of 3-5-2-5 data encoding.

[0074] Figure 57 This is a diagram illustrating an example of 3-2-5-5 data encoding.

[0075] Figure 58 This is a diagram illustrating an example of 2-3-5-5 data encoding.

[0076] Figure 59This is a diagram illustrating an example of 2-3-5-5 data encoding.

[0077] Figure 60 This is a diagram illustrating an example of 2-3-5-5 data encoding.

[0078] Figure 61 This is a diagram illustrating an example of 5-4-2-4 data encoding.

[0079] Figure 62 This is a diagram illustrating an example of 4-5-2-4 data encoding.

[0080] Figure 63 This is a diagram illustrating an example of 5-4-2-4 data encoding.

[0081] Figure 64 This is a diagram illustrating an example of 2-4-5-4 data encoding.

[0082] Figure 65 This is a diagram illustrating an example of 2-4-5-4 data encoding.

[0083] Figure 66 This is a diagram illustrating an example of 2-5-4-4 data encoding.

[0084] Figure 67 This is a diagram illustrating an example of 2-5-4-4 data encoding.

[0085] Figure 68 This is a diagram illustrating an example of 2-5-4-4 data encoding.

[0086] Figure 69 This is a diagram illustrating an example of 1-5-4-5 data encoding.

[0087] Figure 70 This is a diagram illustrating an example of 1-4-5-5 data encoding.

[0088] Figure 71 This is a diagram illustrating an example of 1-5-5-4 data encoding.

[0089] Figure 72 This is a diagram illustrating an example of 1-4-5-5 data encoding.

[0090] Figure 73 This is a diagram illustrating an example of 1-5-5-4 data encoding.

[0091] Figure 74 This is a diagram illustrating an example of 1-5-4-5 data encoding.

[0092] Figure 75 This is a diagram illustrating an example of 1-5-5-4 data encoding.

[0093] Figure 76This is a diagram illustrating an example of 1-5-4-5 data encoding.

[0094] Figure 77 This is a diagram illustrating an example of 1-4-5-5 data encoding.

[0095] Figure 78 This is a diagram illustrating an example of 1-4-5-5 data encoding.

[0096] Figure 79 This is a diagram illustrating an example of 1-4-5-5 data encoding.

[0097] Figure 80 This is a diagram illustrating an example of 1-4-5-5 data encoding.

[0098] Figure 81 This is a diagram illustrating an example of 3-5-4-3 data encoding.

[0099] Figure 82 This is a diagram illustrating an example of 3-4-5-3 data encoding.

[0100] Figure 83 This is a diagram illustrating an example of 3-5-3-4 data encoding.

[0101] Figure 84 This is a diagram illustrating an example of 3-4-3-5 data encoding.

[0102] Figure 85 This is a diagram illustrating an example of 3-4-5-3 data encoding.

[0103] Figure 86 This is a diagram illustrating an example of 3-4-3-5 data encoding.

[0104] Figure 87 This is a diagram illustrating an example of 3-3-5-4 data encoding.

[0105] Figure 88 This is a diagram illustrating an example of 3-3-5-4 data encoding.

[0106] Figure 89 This is a diagram illustrating an example of 4-5-3-3 data encoding.

[0107] Figure 90 This is a diagram illustrating an example of 3-5-4-3 data encoding.

[0108] Figure 91 This is a diagram illustrating an example of 3-4-5-3 data encoding.

[0109] Figure 92 This is a diagram illustrating an example of 3-3-4-5 data encoding.

[0110] Figure 93This is a diagram illustrating an example of 3-3-4-5 data encoding.

[0111] Figure 94 This is a diagram illustrating an example of 3-3-4-5 data encoding.

[0112] Figure 95 This is a diagram illustrating an example of 3-4-5-3 data encoding.

[0113] Figure 96 This is a diagram illustrating an example of 3-3-5-4 data encoding.

[0114] Figure 97 This is a diagram illustrating an example of 3-3-4-5 data encoding.

[0115] Figure 98 This is a diagram illustrating an example of 4-3-4-4 data encoding.

[0116] Figure 99 This is a diagram illustrating an example of 3-4-4-4 data encoding.

[0117] Figure 100 This is a diagram illustrating an example of 3-4-4-4 data encoding.

[0118] Figure 101 This is a diagram illustrating an example of 4-3-4-4 data encoding.

[0119] Figure 102 This is a diagram illustrating an example of 3-4-4-4 data encoding.

[0120] Figure 103 This is a diagram illustrating an example of 3-4-4-4 data encoding.

[0121] Figure 104 This is a diagram illustrating an example of 3-4-4-4 data encoding.

[0122] Figure 105 This is a diagram illustrating an example of 3-4-4-4 data encoding.

[0123] Figure 106 This is a diagram illustrating an example of 4-4-3-4 data encoding.

[0124] Figure 107 This is a diagram illustrating an example of 4-4-3-4 data encoding.

[0125] Figure 108 This is a flowchart illustrating the writing steps of a block as a whole in the third embodiment.

[0126] Figure 109 This is a flowchart illustrating the writing steps in the first and second stages of the third embodiment.

[0127] Figure 110 This is a diagram illustrating the write buffer size in the programming of the third embodiment.

[0128] Label Explanation

[0129] 1. Memory system; 2. Memory controller; 3. Non-volatile memory; 4. Host processor; 5. NAND memory; 6. RAM (Random Access Memory); 7. ROM (Read-Only Memory); 8. Processor; 9. Host interface; 10. ECC circuit; 11. Memory interface; 12. Internal bus; 21. NAND I / O interface; 22. Control unit; 23. NAND memory cell array; 24. Page buffer; 31. Oscillator; 32. Sequencer; 33. Command user interface; 34. Voltage supply unit; 35. Column counter; 36. Serial access controller; 37. Row decoder; 38. Sense amplifier; 41. P-well; 42, 43, 44. Wiring layers; 45. Memory hole. 46. ​​Block insulating film; 47. Charge storage layer; 48. Gate insulating film; 49. Conductive film. Detailed Implementation

[0130] Figure 1 This is a block diagram showing the general configuration of the memory system 1 according to the first embodiment. Figure 1 The memory system 1 has a memory controller 2 and non-volatile memory 3. Figure 1 The memory system 1 can be connected to the host processor (hereinafter referred to as the host) 4. The host 4 is, for example, an electronic device such as a personal computer or a portable terminal.

[0131] The non-volatile memory 3 is a memory that stores data non-volatilely, such as a NAND flash memory (hereinafter sometimes also called NAND memory) 5. In this embodiment, the non-volatile memory 3 is described as an example of a 4-bit / cell (QLC: Quad Level Cell) NAND memory 5 having memory cells that can store 4 bits of data per memory cell. The non-volatile memory 3 of this embodiment has a three-dimensional structure in which memory cells are stacked three-dimensionally. The non-volatile memory 3 has a plurality of memory cells, each of which can store 4 bits of data represented by the 1st to 4th bits using 16 threshold regions, the 16 threshold regions including a first threshold region indicating an erased state where data has been erased, and second to 16th threshold regions with a voltage level higher than the first threshold region indicating a written state where data has been written. For example, the first bit is the lowest bit, the second bit is the middle bit, the third bit is the upper bit, and the fourth bit is the top bit.

[0132] The memory controller 2 controls the writing of data to the non-volatile memory 3 according to write commands from the host 4. Additionally, the memory controller 2 controls the reading of data from the non-volatile memory 3 according to read commands from the host 4. The memory controller 2 includes RAM (Random Access Memory) 6, ROM (Read Only Memory) 7, a processor 8, a host interface 9, ECC (Error Check and Correct) circuitry 10, and a memory interface 11. The RAM 6, processor 8, host interface 9, ECC circuitry 10, and memory interface 11 are connected via a common internal bus 12.

[0133] As described below, in this embodiment, after the memory controller 2 performs a first programming operation on the non-volatile memory 3 to write the first, second, and fourth bits of data, it performs a second programming operation on the non-volatile memory 3 to write the third bit of data. The largest value among the 15 boundaries existing between adjacent threshold regions in the first to 16th threshold regions is 5, and the second largest value is 4. The memory controller 2 is configured to perform the first programming operation on the non-volatile memory 3 such that the threshold region in the memory cell becomes, based on the first, second, and fourth bits of data, a 17th threshold region indicating an erased state (data has been erased), and a 18th to 24th threshold regions with a higher voltage level than the 17th threshold region indicating a written state (data has been written). The memory controller 2 is configured to perform a second programming of the non-volatile memory 3, such that a threshold region in the memory cell changes from one of the threshold regions 17 to 24 to one of two threshold regions 1 to 16 based on the third bit data. The number of threshold regions between the lowest voltage region and the highest voltage region among the two threshold regions is two or less. The memory controller 2 is configured to input the second bit data and the third bit data to the non-volatile memory 3 when performing the second programming.

[0134] More specifically, the memory controller 2 performs a first programming and a second programming of the non-volatile memory such that the number of boundaries between adjacent threshold regions with different values ​​for the first bit, the second bit, the third bit, and the fourth bit among the 15 boundaries of the 16 threshold regions (the first to the 16th threshold regions) is 1, 4, 5, 5, or 1, 5, 4, 5, or 3, 3, 4, 5.

[0135] Alternatively, in this embodiment, after the memory controller 2 performs a first programming operation on the non-volatile memory 3 to write the first, second, and fourth bits of data, it performs a second programming operation on the non-volatile memory 3 to write the third bit of data. The number of first boundaries used to determine the value of the first bit of data, the number of second boundaries used to determine the value of the second bit of data, the number of third boundaries used to determine the value of the third bit of data, and the number of fourth boundaries used to determine the value of the fourth bit of data among the 15 boundaries existing between adjacent threshold regions in the first to 16 threshold regions are 3, 5, 2, and 5 respectively. The memory controller 2 is configured to perform the first programming operation on the non-volatile memory 3 such that the threshold regions in the memory cells become, based on the first, second, and fourth bits of data, a 17th threshold region indicating an erased state where data has been erased, and a 18th to 24th threshold regions with a higher voltage level than the 17th threshold region indicating a written state where data has been written. The memory controller 2 is configured to perform a second programming of the non-volatile memory 3, such that a threshold region in the memory cell changes from one of the threshold regions 17 to 24 to one of two threshold regions 1 to 16 based on the third bit data. The number of threshold regions between the lowest voltage region and the highest voltage region among the two threshold regions is two or less. The memory controller 2 is configured to input the second bit data and the third bit data to the non-volatile memory 3 when performing the second programming.

[0136] The memory controller 2 can also perform a first programming of the non-volatile memory such that the voltage level difference between two threshold regions with different values ​​of the second bit data in the 17th to 24th threshold regions is smaller than the voltage level difference between two threshold regions with different values ​​of the first bit data, and smaller than the voltage level difference between two threshold regions with different values ​​of the fourth bit data.

[0137] Alternatively, the memory controller 2 may perform a second programming of the non-volatile memory such that the interval between the two threshold regions during the first programming, which differs from the value of the second bit data, is wider than the interval between adjacent threshold regions in the four threshold regions obtained by performing a second programming using the third bit data for the two threshold regions.

[0138] The host interface 9 outputs commands and user data (write data) received from the host 4 to the internal bus 12. Additionally, the host interface 9 sends user data read from the non-volatile memory 3 and responses from the processor 8 back to the host 4.

[0139] The memory interface 11 controls, based on instructions from the processor 8, the processes of writing user data to and reading from the non-volatile memory 3.

[0140] The processor 8 provides overall control over the memory controller 2. The processor 8 may be, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). Upon receiving a command from the host 4 via the host interface 9, the processor 8 performs control according to that command. For example, following a command from the host 4, the processor 8 instructs the memory interface 11 to write user data and perform parity checks to the non-volatile memory 3. Additionally, following a command from the host 4, the processor 8 instructs the memory interface 11 to read user data and perform parity checks from the non-volatile memory 3.

[0141] User data is stored in RAM 6 via internal bus 12. Processor 8 determines the storage area (memory area) on non-volatile memory 3 for the user data stored in RAM 6. Processor 8 determines the storage area on non-volatile memory 3 for data stored in pages (page data) as write units. In this specification, the user data stored in one page of non-volatile memory 3 is defined as unit data. Unit data is typically encoded and stored as codewords in non-volatile memory 3, but encoding is not mandatory. Memory controller 2 may also store unit data in non-volatile memory 3 without encoding it, but... Figure 1 The example shown illustrates the encoding configuration. When the memory controller 2 does not perform encoding, the page data and module data are identical. Furthermore, a codeword can be generated based on a single module data entry, or it can be generated based on segmented data obtained by dividing the module data. Alternatively, a codeword can be generated using multiple module data entries.

[0142] Processor 8 determines the storage area of ​​non-volatile memory 3 as the destination for writing data to each module. Physical addresses are allocated to the storage areas of non-volatile memory 3. Processor 8 uses physical addresses to manage the storage areas as the destination for writing module data. Processor 8 specifies the determined storage area (physical address) and instructs memory interface 11 to write user data to non-volatile memory 3. On the other hand, host 4 manages data using logical addresses. Therefore, processor 8 manages the mapping between logical addresses and physical addresses of user data. When processor 8 receives a read command including a logical address from host 4, it determines the physical address corresponding to the logical address, specifies the physical address, and instructs memory interface 11 to read user data.

[0143] In this specification, multiple memory cells connected together on a single word line are defined as a memory cell group (MG). A memory cell group (MG) is the unit of writing (programming). In this embodiment, the non-volatile memory 3 is a 4-bit / cell NAND memory 5, and a memory cell group (MG) has a data volume of 4 bits × number of cells. Each bit written to each memory cell corresponds to a different page. In this embodiment, the four pages of a memory cell group (MG) are referred to as the Lower page (page 1), Middle page (page 2), Upper page (page 3), and Top page (page 4).

[0144] ECC circuit 10 encodes the user data stored in RAM 6 to generate codewords. Additionally, ECC circuit 10 decodes the codewords read from non-volatile memory 3. After correcting for errors (bit errors) in the codewords read from non-volatile memory 3, ECC circuit 10 decodes them back into user data.

[0145] RAM6 temporarily stores user data received from host 4 until it is stored in non-volatile memory 3, and temporarily stores data read from non-volatile memory 3 until it is sent to host 4. RAM6 is, for example, general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0146] exist Figure 1 The diagram illustrates a configuration example where the memory controller 2 includes both an ECC circuit 10 and a memory interface 11. However, the ECC circuit 10 can also be integrated into the memory interface 11. Furthermore, the ECC circuit 10 can also be integrated into the non-volatile memory 3.

[0147] Upon receiving a write request from host 4, memory system 1 operates as follows: Processor 8 temporarily stores the write data in RAM 6. Processor 8 reads the data stored in RAM 6 and inputs it to ECC circuit 10. ECC circuit 10 encodes the input data and inputs the codeword to memory interface 11. Memory interface 11 writes the input codeword to non-volatile memory 3.

[0148] Upon receiving a read request from host 4, memory system 1 operates as follows: Memory interface 11 inputs the codeword read from non-volatile memory 3 to ECC circuit 10. ECC circuit 10 decodes the input codeword and temporarily stores the decoded data in RAM 6. Processor 8 sends the data stored in RAM 6 to host 4 via host interface 9. Alternatively, non-volatile memory 3 may be composed of multiple chips, and non-volatile memory 3 and memory interface 11 may be connected via through-silicon vias (TSVs).

[0149] also, Figure 1 The configuration of the memory controller 2 shown is one example. In addition, it can take various derivative forms, such as the internal bus 12 becoming a segmented and / or hierarchical structure, or connecting additional function blocks, etc.

[0150] Figure 2 This is a block diagram illustrating an example of the internal structure of the non-volatile memory 3 in this embodiment. The non-volatile memory 3 includes a NAND I / O interface 21, a control unit 22, a NAND memory cell array (memory cell unit) 23, and a page buffer (second memory unit) 24. The non-volatile memory 3 is formed on a semiconductor substrate (e.g., a silicon substrate) and thus chip-based.

[0151] The control unit 22 controls the operation of the non-volatile memory 3 based on commands from the memory controller 2 via the NAND I / O interface 21. Specifically, when a write request is input, the control unit 22 controls the writing of the requested data to a specified address on the NAND memory cell array 23. Conversely, when a read request is input, the control unit 22 controls the reading of the requested data from the NAND memory cell array 23 and outputs it to the memory controller 2 via the NAND I / O interface 21. The page buffer 24 is a buffer that temporarily stores data input from the memory controller 2 during writes to the NAND memory cell array 23 and temporarily stores data read from the NAND memory cell array 23.

[0152] As described below, the control unit 22 determines the threshold voltage of the bit data programmed in the second stage programming based on the data obtained by reading the data programmed through the first stage programming, the bit data repeatedly input in the first and second stages programming, and the input data of the bit programmed in the second stage programming.

[0153] The control unit 22 includes an oscillator 31, a sequencer 32, a command user interface 33, a voltage supply unit 34, a column counter 35, and a serial access controller 36. Additionally, the NAND memory cell array 23 includes a row decoder 37 and a sense amplifier 38.

[0154] NAND I / O interface 21 is a circuit used to send and receive I / O signals (input / output signals) and control signals with memory controller 2. Command user interface 33 obtains the command and address from the commands, addresses, and data received from memory controller 2 via I / O signal lines based on the control signals. Command user interface 33 then passes the obtained commands and addresses to sequencer 32.

[0155] Oscillator 31 is a circuit that generates a clock. The clock generated by oscillator 31 is supplied to various components, including sequencer 32. Sequencer 32 is a state machine driven by the clock supplied from oscillator 31. Sequencer 32 performs controls such as access to NAND memory cell array 23. For example, sequencer 32 issues instructions for controlling various internal voltages, operating timing, etc., based on commands received from command user interface 33. In addition, sequencer 32 supplies the block address and page address contained in the address received from command user interface 33 to row decoder 37. Furthermore, sequencer 32 supplies the column address contained in the address received from command user interface 33 to column counter 35.

[0156] The voltage supply unit 34 generates various internal voltages to supply to the word lines and various internal voltages to supply to the bit lines, and supplies them to the row decoder 37 and the sense amplifier 38. During programming or reading operations, the column counter 35 starts with the column address supplied by the sequencer 32 and advances the column address sequentially according to the control signal supplied by the serial access controller 36.

[0157] During programming, page buffer 24 sequentially stores the data received from serial access controller 36 into the column address area specified by column counter 35. Conversely, during reading, page buffer 24 sequentially sends the data from the stored data at the column addresses specified by the column addresses to serial access controller 36.

[0158] During programming, the serial access controller 36 serially receives data from the NAND I / O interface 21 according to the width of each I / O signal line and stores it in the page buffer 24. Conversely, during reading, the serial access controller 36 serially sends data received from the page buffer 24 according to the width of each I / O signal line to the NAND I / O interface 21.

[0159] During programming and reading operations, the line decoder 37 decodes the block address and page address, selecting the word line corresponding to the page that is the access target contained in the block BLK of the access destination. Furthermore, each line decoder 37 applies appropriate voltage to the selected word line and the non-selected word line.

[0160] During programming, the sense amplifier 38 forwards the corresponding data stored in the page buffer 24 to the memory cell transistors. Additionally, during read operations, the sense amplifier 38 senses the data read from the select word line to the bit line and stores the obtained data in the page buffer 24. The data stored in the page buffer 24 is then sent to the memory controller 2 via the serial access controller 36 and the NAND I / O interface 21.

[0161] Figure 3 This is a circuit diagram representing an example of a three-dimensional NAND memory cell array 23. Figure 3 This illustrates the circuit structure of block BLK, one of multiple blocks within a three-dimensional NAND memory cell array 23. The other blocks of the NAND memory cell array 23 also have the same circuit structure. Figure 3 The same circuit structure. Furthermore, this embodiment can also be applied to two-dimensional memory cells.

[0162] like Figure 3 As shown, the block BLK has, for example, four fingers (FNG0 to FNG3). Each finger FNG includes multiple NAND strings (NS). Each NAND string (NS) has, for example, eight cascaded memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2. In this specification, each finger FNG is sometimes referred to as a string St.

[0163] Furthermore, the number of memory cell transistors MT within the NAND string NS is not limited to 8. The memory cell transistors MT are configured between select transistors ST1 and ST2 such that their current paths are connected in series. The current path of memory cell transistor MT7 on one end of this series connection is connected to one end of the current path of select transistor ST1, and the current path of memory cell transistor MT0 on the other end is connected to one end of the current path of select transistor ST2.

[0164] The gates of the select transistors ST1 for each of FNG0 to FNG3 are shared by select gate lines SGD0 to SGD3. Conversely, the gates of select transistor ST2 are shared by multiple FNGs by the same select gate line SGS. Furthermore, the control gates of memory cell transistors MT0 to MT7 within the same block BLK are shared by word lines WL0 to WL7. That is, word lines WL0 to WL7 and select gate line SGS are shared by multiple FNG0 to FNG3s within the same block BLK. In contrast, even within the same block BLK, the select gate line SGD is independent for each of FNG0 to FNG3.

[0165] Word lines WL0 to WL7 are connected to the control gate electrodes of the memory cell transistors MT0 to MT7 that constitute the NAND string NS, respectively. In addition, the i-th memory cell transistor MTi (i = 0 to n) in each NAND string NS within the same index FNG is connected together through the same word line WLi (i = 0 to n). That is, the control gate electrodes of the memory cell transistors MTi in the same row within block BLK are connected to the same word line WLi.

[0166] Each NAND string NS is connected to the word line WLi and also to the bit line. Each memory cell within each NAND string NS can be identified by the address identified by the word line WLi and the select gates SGD0 to SGD3, and by the address identified by the bit line. As described above, the data in memory cells (memory cell transistors MT) within the same block BLK is erased together. On the other hand, data reading and writing are performed in units of physical sectors MS. A physical sector MS includes multiple memory cells connected to a word line WLi and belonging to a pointer FNG.

[0167] The memory controller 2 writes (programs) data in units of all NAND strings NS connected to a word line within a finger. Therefore, the unit of data volume for programming by the memory controller 2 is 4 bits × number of bit lines.

[0168] During read and program operations, a word line (WLi) and a select gate line (SGD) are selected based on the physical address to select the physical sector (MS). Furthermore, in this specification, the act of writing data to the memory cell as needed is referred to as programming.

[0169] Figure 4 This is a cross-sectional view of a portion of the NAND memory cell array 23 of the three-dimensional NAND memory 5. (Example) Figure 4As shown, multiple NAND strings NS are formed in the vertical direction on the p-well region 41 of the semiconductor substrate. That is, multiple wiring layers 42 that function as select gate lines SGS, multiple wiring layers 43 that function as word lines WLi, and multiple wiring layers 44 that function as select gate lines SGD are formed in the vertical direction on the p-well region 41.

[0170] Furthermore, a memory hole 45 is formed that penetrates these wiring layers 42, 43, and 44 to reach the p-well region 41. A block insulating film 46, a charge storage layer 47, and a gate insulating film 48 are sequentially formed on the side of the memory hole 45, and a conductive film 49 is also embedded within the memory hole 45. The conductive film 49 functions as a current path for the NAND string NS and forms a channel during the operation of the memory cell transistor MT and the selection transistors ST1 and ST2.

[0171] In each NAND string NS, a selection transistor ST2, multiple memory cell transistors MT, and a selection transistor ST1 are sequentially stacked on the p-type well region 41. A wiring layer that functions as a bit line BL is formed at the upper end of the conductive film 49.

[0172] Furthermore, an n+ type impurity diffusion layer and a p+ type impurity diffusion layer are formed within the surface of the p-type well region 41. A contact plug 50 is formed on the n+ type impurity diffusion layer, and a wiring layer functioning as a source line SL is formed on the contact plug 50. Additionally, a contact plug 51 is formed on the p+ type impurity diffusion layer, and a wiring layer functioning as a well wiring CPWELL is formed on the contact plug 51. The well wiring CPWELL is used to apply an erase voltage.

[0173] Figure 4 The NAND memory cell array 23 shown is in Figure 4 The paper has multiple columns arranged along its depth direction, and a pointer FNG is formed by a set of multiple NAND strings NS arranged in a single column along the depth direction. Other pointer FNGs, for example, are arranged along... Figure 4 It is formed in the left and right directions. Although in Figure 3 The diagram shows four fingers, FNG0-3, but in Figure 4 The diagram illustrates an example where three fingers are configured between contact plugs 50 and 51.

[0174] Figure 5 This is a diagram illustrating an example of the threshold region in the first embodiment. Figure 5This illustrates an example of the distribution of threshold regions in a 4-bit / cell non-volatile memory 3. In the non-volatile memory 3, information is stored using the amount of charge of electrons accumulated in the charge accumulation layer 47 of the memory cell. Each memory cell has a threshold voltage corresponding to the amount of charge of the electrons. Furthermore, multiple data values ​​to be stored in the memory cell are respectively associated with multiple regions (threshold regions) with different threshold voltages.

[0175] Figure 5 S0 to S15 represent the threshold distribution within the 16 threshold regions. Figure 5 The horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells. The threshold distribution refers to the range of threshold variation. Thus, each memory cell has 16 threshold regions separated by 15 boundaries, and each threshold region has an inherent threshold distribution.

[0176] In this embodiment, the region with a threshold voltage less than or equal to Vr1 is designated as region S0; the region with a threshold voltage greater than Vr1 and less than or equal to Vr2 is designated as region S1; the region with a threshold voltage greater than Vr2 and less than or equal to Vr3 is designated as region S2; and the region with a threshold voltage greater than Vr3 and less than or equal to Vr4 is designated as region S3. Furthermore, in this embodiment, the region with a threshold voltage greater than Vr4 and less than or equal to Vr5 is designated as region S4; the region with a threshold voltage greater than Vr5 and less than or equal to Vr6 is designated as region S5; the region with a threshold voltage greater than Vr6 and less than or equal to Vr7 is designated as region S6; and the region with a threshold voltage greater than Vr7 and less than or equal to Vr8 is designated as region S7. Additionally, in this embodiment, the region with a threshold voltage greater than Vr8 and less than or equal to Vr9 is designated as region S8; the region with a threshold voltage greater than Vr9 and less than or equal to Vr10 is designated as region S9; the region with a threshold voltage greater than Vr10 and less than or equal to Vr11 is designated as region S10; and the region with a threshold voltage greater than Vr11 and less than or equal to Vr12 is designated as region S11. In addition, in this embodiment, the region with a threshold voltage greater than Vr12 and less than or equal to Vr13 is called region S12, the region with a threshold voltage greater than Vr13 and less than or equal to Vr14 is called region S13, the region with a threshold voltage greater than Vr14 and less than or equal to Vr15 is called region S14, and the region with a threshold voltage greater than Vr15 is called region S15.

[0177] Furthermore, the threshold distributions corresponding to regions S0 to S15 are referred to as the 1st to 16th distributions. Vr1 to Vr15 are the threshold voltages that form the boundaries of each threshold region.

[0178] In the non-volatile memory 3, multiple threshold regions of a memory cell are each associated with multiple data values. This association is called data encoding. This data encoding is predetermined. During data writing (programming), charge is injected into the charge accumulation layer 47 within the memory cell to create a threshold region corresponding to the data value stored according to the data encoding. Furthermore, during reading, a read voltage is applied to the memory cell, and data logic is determined based on whether the threshold of the memory cell is lower or higher than the read voltage.

[0179] During data reading, the logic is determined by whether the threshold is lower or higher than the read level of the object being read. When the threshold is lowest, it is in the "erase" state, and all bits are defined as "1". When the threshold is higher than the "erase" state, it is in the "programmed" state, and the data is defined as either "1" or "0" according to the encoding.

[0180] Figure 6A This diagram illustrates an example of data encoding in the first embodiment, showing an example of 1-4-5-5 data encoding. In this embodiment, [the following is used]... Figure 5 The 16 threshold regions shown correspond to 16 data values ​​of 4 bits each. Figure 6A The relationship between the threshold voltage and the data values ​​of the bits corresponding to the Top, Upper, Middle, and Lower pages is shown below.

[0181] • Storage cells with threshold voltage within the S0 region are in a state where “1111” is stored.

[0182] • Storage cells with threshold voltage within the S1 region are in a state where “0111” is stored.

[0183] • Storage cells with threshold voltage within the S2 region are in a state where “0011” is stored.

[0184] • Storage cells with threshold voltage within the S3 region are in a state where “1011” is stored.

[0185] • Storage cells with threshold voltage within the S4 region are in a state where “1001” is stored.

[0186] • Storage cells with threshold voltage within the S5 region are in a state where “0001” is stored.

[0187] • Storage cells with threshold voltage within the S6 region are in a state where “0101” is stored.

[0188] • Memory cells with threshold voltage within the S7 region are in a state where “1101” is stored.

[0189] • Storage cells with threshold voltage within the S8 region are in a state where “1100” is stored.

[0190] • Storage cells with threshold voltage within the S9 region are in a state where “1110” is stored.

[0191] • Storage cells with threshold voltage within the S10 region are in a state where “1010” is stored.

[0192] • Storage cells with threshold voltage within the S11 region are in a state where “1000” is stored.

[0193] • Storage cells with threshold voltage within the S12 region are in a state where “0000” is stored.

[0194] • Storage cells with threshold voltage within the S13 region are in a state where “0100” is stored.

[0195] • Storage cells with threshold voltage within the S14 region are in a state where “0110” is stored.

[0196] • Storage cells with threshold voltage within the S15 region are in a state where “0010” is stored.

[0197] Figure 6B This is a diagram illustrating another example of data encoding in the first embodiment, showing an example of 4-3-4-4 data encoding. Figure 6B The relationship between the threshold voltage and the data values ​​of the bits corresponding to the Top, Upper, Middle, and Lower pages is shown below.

[0198] • Storage cells with threshold voltage within the S0 region are in a state where “1111” is stored.

[0199] • Storage cells with threshold voltage within the S1 region are in a state where “0111” is stored.

[0200] • Storage cells with threshold voltage within the S2 region are in a state where “0011” is stored.

[0201] • Storage cells with threshold voltage within the S3 region are in a state where “1011” is stored.

[0202] • Storage cells with threshold voltage within the S4 region are in a state where “1010” is stored.

[0203] • Storage cells with threshold voltage within the S5 region are in a state where “1110” is stored.

[0204] • Storage cells with threshold voltage within the S6 region are in a state where “1100” is stored.

[0205] • Storage cells with threshold voltage within the S7 region are in a state where “1000” is stored.

[0206] • Storage cells with threshold voltage within the S8 region are in a state where “1001” is stored.

[0207] • Storage cells with threshold voltage within the S9 region are in a state where “0001” is stored.

[0208] • Storage cells with threshold voltage within the S10 region are in a state where “0000” is stored.

[0209] • Storage cells with threshold voltage within the S11 region are in a state where “0010” is stored.

[0210] • Storage cells with threshold voltage within the S12 region are in a state where “0110” is stored.

[0211] • Storage cells with threshold voltage within the S13 region are in a state where “0100” is stored.

[0212] • Storage cells with threshold voltage within the S14 region are in a state where “0101” is stored.

[0213] • Storage cells with threshold voltage within the S15 region are in a state where “1101” is stored.

[0214] like Figure 6A and Figure 6B As shown, the logic allocates 4 bits of data to each memory cell in each region of the threshold voltage. Furthermore, in the unwritten state ("erased" state), the threshold voltage of the memory cell is within region S0. Also, regarding the code shown here, if "1111" is stored in the S0 (erased) state and "0111" is stored in the S1 state, only one bit of data changes between any two adjacent regions. Thus, Figure 6A and Figure 6B The data encoding shown is Gray code, where only one bit of data changes between any two adjacent regions.

[0215] exist Figure 6A In the encoding of this embodiment shown, the threshold voltage that serves as the boundary for determining the bit values ​​of each page is as follows.

[0216] • The threshold voltages that serve as the boundaries for determining the bit values ​​of the Top page are Vr1, Vr3, Vr5, Vr7, and Vr12.

[0217] • The threshold voltages that serve as the boundaries for determining the bit values ​​of the Upper page are Vr2, Vr6, Vr10, Vr13, and Vr15.

[0218] • The threshold voltages that serve as the boundaries for determining the bit values ​​of the Middle page are Vr4, Vr9, Vr11, and Vr14.

[0219] • The threshold voltage that serves as the boundary for determining the bit values ​​of the Lower page is Vr8.

[0220] Thus, the number of threshold voltages used to determine the bit value (hereinafter referred to as the number of boundaries) is 1, 4, 5, and 5 for the Lower, Middle, Upper, and Top pages, respectively. Hereinafter, this encoding using the respective number of boundaries for the Lower, Middle, Upper, and Top pages is referred to as 1-4-5-5 encoding.

[0221] The first feature of this embodiment is that the maximum number of boundaries where the bit value changes per page is 5. When using 4 bits to represent 16 states, the minimum maximum number of boundaries is 4. Figure 6A and Figure 6B The encoding is only one more than the first one, thus reducing the error rate deviation. Therefore, the memory system 1 of this embodiment, by possessing the first feature, can suppress the bit error rate and also suppress error rate deviation on a page-by-page basis.

[0222] The second feature of this embodiment is that the number of boundaries of the Lower page is 1, and the number of boundaries of the Middle page is 4, enabling programming in two stages: a first stage of programming that combines the Lower page and the Middle page, and a second stage of programming that combines the Upper page and the Top page.

[0223] The third feature of this embodiment is that the change range from the threshold region generated by the first stage of programming to the threshold region generated by the second stage of programming is small. That is, the change range of the threshold voltage is small. The smaller the change range of the threshold region, the less susceptible it is to interference between adjacent units. The first to third features described above will be explained in detail later.

[0224] The control unit 22 of the non-volatile memory 3 is based on Figure 6A and Figure 6B The code shown controls the programming to and reading from the NAND memory cell array 23.

[0225] Three-dimensional memory cells have not progressed as rapidly in miniaturization as two-dimensional memory cells. Therefore, in three-dimensional memory cells, if adjacent cells are spaced far apart, there is less interference between cells. In this case, a common approach is to program all bits of each cell simultaneously; for example, if the bits are allocated to different pages, all pages are programmed simultaneously.

[0226] When programming all bits of each memory cell simultaneously, the combination is not specifically considered in data encoding. Based on all the bit data, it is determined which of the 16 threshold regions to locate, and then programmed so that the region in the S0 erasing state becomes the determined threshold region. In this case, a data encoding with the minimum of the maximum number of boundaries (4-4-3-4) is typically used. In 4-4-3-4 data encoding, when allocating the 15 boundaries between the 16 threshold regions to 4 pages, 4 boundaries are allocated to the Lower page, 4 to the Middle page, 3 to the Upper page, and 4 to the Top page. With this data encoding, the deviation in the number of boundaries between pages is small, resulting in a smaller deviation in the bit error rate between pages. This is because bit errors are almost entirely caused by the shifting of the threshold to adjacent threshold regions; the more boundaries a page has, the more bit errors it will have. This relates to the fact that even if the error rate of the storage unit is the same, the correction capability of the ECC circuit 10 required to correct page data errors must be strengthened. Therefore, it is also effective in suppressing the degradation of the memory system 1's response performance, cost, and power consumption to write requests from the host 4. In addition, the deviation in read speed caused by the deviation in the number of boundaries is also reduced.

[0227] Furthermore, in a 4-bit / cell NAND memory 5, the narrower spacing between adjacent threshold regions results in a greater impact from inter-cell interference compared to 1-bit / cell or 2-bit / cell NAND memories 5. Therefore, in recent generations of NAND memories 5 that have seen miniaturization, a programming method (Foggy-Fine programming) is typically employed to suppress inter-cell interference by gradually injecting charge into the charge accumulation layer 47 of the memory cell using multiple programming stages, such as two programming stages (hereinafter sometimes simply referred to as stages). In this Foggy-Fine programming, after writing to the memory cell in the first stage (Foggy stage), writing to adjacent cells is performed, and then the second stage (Fine stage) is performed, returning to the original memory cell. In this case, each stage is a unit of programming execution, and the programming of a memory cell corresponding to a word line WLi is completed by executing two programming stages.

[0228] Both the first and second stages of programming utilize 16 threshold regions. The threshold distribution at the end of the first stage is wider than the threshold distribution in the final data encoding. That is, in the Foggy stage, a Foggy (coarse, fuzzy) write is performed. In this Foggy stage, all four pages of input data are required. The threshold distribution after the Foggy stage is an intermediate state where adjacent distributions overlap, making data reading impossible. In the Fine stage, the threshold regions from the Foggy stage are moved to the threshold regions in the final data encoding. That is, in the Fine stage, a Fine (refined) write is performed. In this Fine stage, all four pages of input data are also required. The threshold distribution after the Fine stage is a final state where adjacent distributions are separated, allowing data reading after the Fine stage.

[0229] In the case of 4-4-3-4 data encoding, the deviation in the number of boundaries is small, but in Foggy-Fine programming, 4 pages of data input are required at each stage. This leads to an increase in the time spent on data input, degrading the response performance of memory system 1 to write requests from host 4. Additionally, it increases the buffer size (write buffer size) of the write buffer (first storage section) within memory system 1 used to hold data for input to NAND memory 5. This write buffer is typically allocated to a portion of the RAM 6 within memory system 1.

[0230] As a countermeasure to these issues, in this embodiment, the memory system 1 employs 1-4-5-5 data encoding for the non-volatile memory 3 with a three-dimensional structure, and then performs page-by-page writing in two stages. Therefore, in this embodiment, not only is inter-cell interference and deviations in bit error rates between pages suppressed in the non-volatile memory 3 with a three-dimensional structure, but the write buffer size of the memory controller 2 is also reduced. The write buffer in this embodiment allows data in bits 1 to 4 (data in the Lower, Middle, Upper, and Top pages) that are repeatedly input during the first and second programming stages to be discarded or invalidated after the start of the second programming stage, and allows data in other bits to be discarded or invalidated after the start of the first programming stage.

[0231] Here, we will explain the interference between adjacent memory cells. The charge accumulated in the charge accumulation layer 47 of a certain memory cell disturbs the electric field of adjacent memory cells, resulting in noise that causes the threshold voltage to fluctuate when reading adjacent memory cells. When programming and verification are performed under certain electric field conditions, adjacent memory cells are programmed with different charges after programming, which degrades read accuracy. This interference between adjacent memory cells becomes more pronounced with the miniaturization of memory device manufacturing technology and the reduction of memory cell spacing. Moreover, this interference between adjacent memory cells mostly occurs between adjacent memory cells connected by different bit lines on the same word line WLi.

[0232] Interference between adjacent memory cells can be mitigated during programming and verification, and during reading of adjacent memory cells after programming, by reducing the difference in electric field conditions between the memory cells. As a method to reduce inter-cell interference between adjacent memory cells connected by different bit lines on the same word line WLi, one method is to divide programming into multiple stages and perform programming so that the amount of charge in the charge accumulation layer 47 does not change significantly between the stages.

[0233] In the programming sequence of this embodiment, the four bits on a word line WLi are programmed through two programming stages: a first stage and a second stage. Each programming stage is the execution unit of programming. The memory system 1 of this embodiment completes the writing of four bits of data to the memory cell by executing the two programming stages. In addition, in this embodiment, each stage of the two programming stages uses a page of data from one of the four bits. Specifically, the programming of the first stage uses data from the Lower page, Middle page, and Top page, and the programming of the second stage uses data from the Middle page, Upper page, and Top page.

[0234] Figure 7 This is a diagram showing the programmed threshold region in the first embodiment. Figure 7 In the diagram, the threshold region is represented after the first and second stages of programming of the storage unit. Figure 7 (T1) represents the threshold region of the erase state as the initial state before programming. Figure 7 (T2) represents the threshold region after the first stage of programming (first programming). Figure 7 (T3) represents the threshold region after the second stage of programming (second programming).

[0235] like Figure 7 As shown in (T1), all memory cells of the NAND memory cell array 23 are in the distributed state S0 when they are not written to ("erased" state). Figure 7As shown in (T2), during the first stage of programming, the control unit 22 of the non-volatile memory 3 either keeps the distribution S0 unchanged or injects charge to move to the distribution above the distribution S0 according to the bit value to be written (stored) to the Lower page, Middle page and Top page, per memory cell.

[0236] Specifically, the control unit 22 is programmed such that when the bit values ​​to be written to the Lower page, Middle page, and Top page are all "1", no charge is injected; and when any one of the bit values ​​to be written to the Lower page, Middle page, and Top page is "0", charge is injected, causing the threshold voltage to shift to a higher level.

[0237] That is, if the bit value to be written to the Lower, Middle, and Top pages is "011", move to distribution S1; if the bit value to be written to the Lower, Middle, and Top pages is "101", move to distribution S4; if the bit value to be written to the Lower, Middle, and Top pages is "001", move to distribution S5; if the bit value to be written to the Lower, Middle, and Top pages is "100", move to distribution S8; if the bit value to be written to the Lower, Middle, and Top pages is "110", move to distribution S9; if the bit value to be written to the Lower, Middle, and Top pages is "000", move to distribution S12; and if the bit value to be written to the Lower, Middle, and Top pages is "010", move to distribution S14.

[0238] Preferably, distributions S1, S4, S5, S8, S9, S12, and S14 increase the width of the threshold region to slightly reduce the threshold voltage for coarse programming. That is, the rise amplitude of the programming voltage pulse described later is increased. This shortens the writing time. Moreover, by programming in a way that slightly reduces the threshold voltage, the width of the threshold distribution region can be written so that it eventually becomes the predetermined width through the second stage of programming.

[0239] Preferably, the intervals between adjacent distributions S8 and S9, and between adjacent threshold distributions S12 and S14, are narrower than the intervals between other adjacent distributions. These adjacent threshold distributions with narrowed intervals have different write bit values ​​for the Middle page data. That is, the data after the first stage of programming appears as binary data, thus enabling the reading of Lower, Middle, and Top page data. By narrowing the intervals between the threshold distributions that differ in Middle page data, the intervals between the threshold distributions that differ in Lower and Top page data are ensured to be wider, increasing the margin during Lower and Top page readings. Figure 7 The threshold distribution S0 to S14 shown in (T2) corresponds to the 17th to 24th threshold regions.

[0240] Next, as Figure 7 As shown in (T3), in the second stage of programming, data writing requires both the Middle page and the Upper page. Furthermore, the control unit 22 of the non-volatile memory 3 is programmed so that the threshold distribution after the second stage of programming reaches a level (order) of 16 values ​​in the final state where adjacent distributions are separated. After the second stage of programming, all page data can be read.

[0241] In the second stage of programming, the greater the change in the threshold of the memory cell since the end of the first stage of programming, the greater the interference between adjacent cells. Therefore, it is preferable that the change in the threshold distribution with the largest change in the memory cell threshold distribution is minimized. According to this embodiment, the largest change in the threshold distribution is the amount of three threshold distributions: the case where S0 changes to S3, the case where S4 changes to S7, and the case where S8 changes to S11. Figure 7 The threshold distribution S0 to S15 shown in (T3) corresponds to the threshold regions from the 1st to the 16th.

[0242] Furthermore, programming is typically performed by applying one or more programming voltage pulses. During these multiple pulses, the voltage value increases in stages. After each pulse, a read, known as a verification read, is performed to confirm whether the memory cell has moved beyond a threshold boundary level. By repeatedly performing this application and read, the threshold of the memory cell can be moved to a range with a predetermined threshold distribution.

[0243] In addition, the control unit 22 can perform the first stage programming and the second stage programming continuously on a word line WLi. However, in order to reduce the impact of interference between adjacent memory cells, programming can also be performed in a non-contiguous order across multiple word lines WLi.

[0244] Figure 8AThis is a diagram showing the first example of the programming order in the first implementation. Figure 8B This is a diagram showing the second example of the programming order in the first embodiment. Figure 8C This is a diagram illustrating the third example of the programming order in the first embodiment. Figures 8A to 8C In order to reduce the impact of interference between adjacent memory cells, programming is performed in two programming stages. Figure 8A This illustrates an example of the programming order in a NAND memory 5 where each word line within each block is connected to a string St. Additionally, Figure 8B and Figure 8C This illustrates an example of the programming order in a NAND memory 5 where four strings St are connected to each word line within each block. Furthermore, in Figure 8B and Figure 8C In this context, the four strings St connected by each character line are denoted as strings 0 to 3.

[0245] When writing begins, the control unit 22 advances each programming stage across word lines WLi in a predetermined, non-contiguous order. That is, the first and second stages for the same word line are not executed consecutively; instead, the second stage is performed on different word lines after the first stage of programming for a particular word line.

[0246] If, after programming a word line up to the second stage is completed, programming adjacent word lines continuously in both the first and second stages, the threshold voltage variation increases. Furthermore, if the threshold voltage variation of adjacent word lines is large, the interference between adjacent memory cells increases. Therefore, to reduce interference between adjacent memory cells, reducing the threshold voltage variation of adjacent word lines after programming up to the second stage is effective. Figure 8A If the timing is such that the programming stage of the adjacent word lines after a certain word line has completed the programming up to the second stage is only the second stage.

[0247] In Figure 8A When programming the three-dimensional NAND memory 5 according to the programming order, when writing begins, the control unit 22 performs programming in the order shown in (1) to (9) below based on the instructions from the processor 8. The control unit 22 programs the NAND memory 5 based on the instructions from the processor 8, but the description of the meaning of "based on the instructions from the processor 8" is omitted below.

[0248] (1) First, the control unit 22 implements the first stage of programming ST11 for word line WL0.

[0249] (2) Next, the control unit 22 performs the first stage of programming ST12 for word line WL1.

[0250] (3) Next, the control unit 22 performs the second stage of programming ST13 for word line WL0.

[0251] (4) Next, the control unit 22 performs the first stage of programming ST14 for word line WL2.

[0252] (5) Next, the control unit 22 performs the second stage of programming ST15 for word line WL1.

[0253] (6) Next, the control unit 22 performs the first stage of programming ST16 for word line WL3.

[0254] (7) Next, the control unit 22 performs the second stage of programming ST17 for word line WL2.

[0255] (8) Next, the control unit 22 performs the first stage of programming ST18 for word line WL4.

[0256] (9) Next, the control unit 22 performs the second stage of programming ST19 for word line WL3.

[0257] Similarly, control unit 22 causes processing from Figure 8A It proceeds diagonally upwards and from the lower left to the upper right. Thus, in Figure 8A In the non-volatile memory 3, a plurality of memory cells have a plurality of first memory cells connected to a first word line and a plurality of second memory cells connected to a second word line adjacent to the first word line. After the memory controller 2 causes the plurality of first memory cells to be first programmed, it causes the plurality of second memory cells to be first programmed, and then causes the plurality of first memory cells to be second programmed after the plurality of second memory cells are first programmed.

[0258] In Figure 8B When programming the three-dimensional NAND memory 5 according to the programming order, when writing begins, the control unit 22 performs programming in the order shown in (11) to (24) below.

[0259] (11) First, the control unit 22 implements the first stage of programming ST21 for the serial St0_word line WL0.

[0260] (12) Next, the control unit 22 performs the first stage of programming ST22 for the serial word line WL0.

[0261] (13) Next, the control unit 22 performs the first stage of programming ST23 for the serial St2_word line WL0.

[0262] (14) Next, the control unit 22 performs the first stage of programming ST24 for the serial St3_word line WL0.

[0263] (15) Next, the control unit 22 performs the first stage of programming ST25 for the serial St0_word line WL1.

[0264] (16) Next, the control unit 22 performs the second stage of programming ST26 for the serial St0_word line WL0.

[0265] (17) Next, the control unit 22 performs the first stage of programming ST27 of the serial St1_word line WL1.

[0266] (18) Next, the control unit 22 performs the second stage of programming ST28 for the serial St1_word line WL0.

[0267] (19) Next, the control unit 22 performs the first stage of programming ST29 for the serial St2_word line WL1.

[0268] (20) Next, the control unit 22 performs the second stage of programming ST210 for the serial St2_word line WL0.

[0269] (21) Next, the control unit 22 performs the first stage of programming ST211 for the serial St3_word line WL1.

[0270] (22) Next, the control unit 22 implements the second stage of programming ST212 for the serial St3_word line WL0.

[0271] (23) Next, the control unit 22 performs the first stage of programming ST213 of the serial St0_ word line WL2.

[0272] (24) Next, the control unit 22 implements the second stage of programming ST214 of the serial St0_word line WL1.

[0273] Similarly, control unit 22 causes processing from Figure 8B It proceeds diagonally upwards and from the lower left to the upper right. Furthermore, in Figure 8B The text explains the case where the string St in a block has 4 characters, but the string St in a block can be 3 or less, or 5 or more.

[0274] In Figure 8C When programming the three-dimensional NAND memory 5 according to the programming order, when writing begins, the control unit 22 performs programming in the order shown in (31) to (50) below.

[0275] (31) First, the control unit 22 implements the first stage of programming ST31 of the serial St0_word line WL0.

[0276] (32) Next, the control unit 22 performs the first stage of programming ST32 for the serial word line WL0.

[0277] (33) Next, the control unit 22 performs the first stage of programming ST33 for the serial St2_word line WL0.

[0278] (34) Next, the control unit 22 performs the first stage of programming ST34 for the serial line St3_word line WL0.

[0279] (35) First, the control unit 22 implements the first stage of programming ST35 of the serial St0_word line WL1.

[0280] (36) Next, the control unit 22 performs the first stage of programming ST36 for the serial line St1_word line WL1.

[0281] (37) Next, the control unit 22 performs the first stage of programming ST37 of the serial St2_word line WL1.

[0282] (38) Next, the control unit 22 performs the first stage of programming ST38 for the serial line WL1.

[0283] (39) Next, the control unit 22 performs the second stage of programming ST39 for the serial St0_word line WL0.

[0284] (40) Next, the control unit 22 performs the second stage of programming ST310 for the serial St1_word line WL0.

[0285] (41) Next, the control unit 22 implements the second stage of programming ST311 for the serial St2_word line WL0.

[0286] (42) Next, the control unit 22 implements the second stage of programming ST312 for the serial St3_ word line WL0.

[0287] (43) Next, the control unit 22 performs the first stage of programming ST313 of the serial St0_ word line WL2.

[0288] (44) Next, the control unit 22 implements the first stage of programming ST314 of the serial line St1_word line WL2.

[0289] (45) Next, the control unit 22 implements the first stage of programming ST315 of the serial St2_word line WL2.

[0290] (46) Next, the control unit 22 implements the first stage of programming ST316 for the serial line WL2.

[0291] (47) Next, the control unit 22 performs the second stage of programming ST317 for the serial St0_word line WL1.

[0292] (48) Next, the control unit 22 implements the second stage of programming ST318 for the serial St1_word line WL1.

[0293] (49) Next, the control unit 22 implements the second stage of programming ST319 for the serial St2_word line WL1.

[0294] (50) Next, the control unit 22 performs the second stage of programming ST320 for the serial St3_word line WL1.

[0295] In addition, Figure 8C The text explains the case where the string St in a block has 4 characters, but the string St in a block can be 3 or less, or 5 or more.

[0296] Thus, even if there are multiple strings St, the programming order of each programming stage of the word line WLi within a single string St is the same as when there is only one string St. In the case of a non-volatile memory 3 with a three-dimensional structure containing multiple strings St in the block memory, the programming of the combined position of word line WLi and string St is usually done by first programming the same word line number within different strings St, and then programming the next word line number. Following this order, Figure 8A When combined by the number of strings St, for example, it would become Figure 8B or Figure 8C That order.

[0297] Here, use Figures 9-11 An example of the writing steps following the programming order of the first embodiment will be described. Figures 9-11 In the middle, it indicates that according to Figure 8B or Figure 8C The write steps are shown in the programming sequence. As previously mentioned, the memory controller 2 advances the programming phase while crossing word lines WLi in a non-contiguous order, thus performing programming by using a set of word lines WLi (in this case, a block) as the set of programming timings.

[0298] Figure 9 This is a flowchart of the first example of the writing steps for a block in the first embodiment. Here, a block has n+1 word lines WLi, from word lines WL0 to WLn (n is a natural number). Figure 10 This is a flowchart illustrating the writing steps in the first stage of the first embodiment. Figure 11 This is a flowchart illustrating the writing steps in the second stage of the first embodiment.

[0299] like Figure 9As shown, when writing begins, the control unit 22 executes the first stage of programming for string St0_word line WL0 (step S10). Next, the control unit 22 executes the first stage of programming for string St1_word line WL0 (step S20). Afterwards, the control unit 22 performs the same processing as steps S10 and S20 on each string St. Then, the control unit 22 executes the first stage of programming for string St3_word line WL0 (step S30).

[0300] Next, the control unit 22 performs the first stage of programming for string St0_word line WL1 (step S40). Then, the control unit 22 performs the second stage of programming for string St0_word line WL0 (step S50). Next, the control unit 22 performs the first stage of programming for string St1_word line WL1 (step S60). Afterwards, the control unit 22 repeatedly performs the same processing steps S40, S50, and S60 on each word line WL1 of each string St.

[0301] Then, the control unit 22 performs the first stage of programming for the string St0_word line WLn (step S70). Next, the control unit 22 performs the second stage of programming for the string St0_word line WLn-1 (step S80). After that, the control unit 22 repeatedly performs the same processing as steps S70 and S80 on each word line WLi of each string St.

[0302] Then, control unit 22 performs the second stage programming of string St3_word line WLn-1 (step S90). Next, control unit 22 performs the second stage programming of string St0_word line WLn (step S100). Next, control unit 22 performs the second stage programming of string St1_word line WLn (step S110). After that, control unit 22 performs the same processing as steps S100 and S110 on each string St. Then, control unit 22 performs the second stage programming of string St3_word line WLn (step S120).

[0303] Figure 10This is a flowchart illustrating the first example of the write step in the first stage. In the first stage of programming, firstly, an input start command for Lower page data is input from memory controller 2 to non-volatile memory 3 (step S210). Then, Lower page data is input from memory controller 2 to non-volatile memory 3 (step S215). Next, an input start command for Middle page data is input from memory controller 2 to non-volatile memory 3 (step S220). Then, Middle page data is input from memory controller 2 to non-volatile memory 3 (step S225). Next, an input start command for Top page data is input from memory controller 2 to non-volatile memory 3 (step S230). Then, Top page data is input from memory controller 2 to non-volatile memory 3 (step S235). Finally, a first-stage programming execution command is input from memory controller 2 to non-volatile memory 3 (step S240), thereby changing the chip to busy state (step S245).

[0304] During data writing, a threshold voltage Vth is determined (step S250), and one or more programming voltage pulses are applied (step S255). Then, a data read (verification) is performed to confirm whether the memory cell has moved beyond the threshold boundary level (step S260).

[0305] Next, it is confirmed whether the number of faulty bits in the data of the Lower, Middle, and Top pages is less than the standard (judgment criterion) (step S265). If the number of faulty bits is greater than the standard, the process from applying the programming pulse to judging the standard is repeated (steps S255 to S265). Moreover, if the number of faulty bits is less than the standard, the chip becomes ready (step S270). In this way, by repeatedly applying, reading, and confirming, the threshold of the memory cell can be moved to a predetermined threshold distribution range.

[0306] Furthermore, as mentioned above, the read level after the programming voltage pulse is applied during the first stage of writing can also be slightly different from the read level after the second stage of writing, preferably a level lower than the read level after the second stage of writing. That is, Vr1'≤Vr1, Vr4'≤Vr4, Vr5'≤Vr5, Vr8'≤Vr8, Vr9'≤Vr9, Vr12'≤Vr12, Vr14'≤Vr14.

[0307] In addition, during the reading after the programming voltage pulse is applied in the first stage of writing, the reading based on Vr9' and the reading based on Vr14' can be omitted. After Vr9' passes the reading of Vr8', it is set to write complete after applying a certain number of programming voltage pulses. After Vr14' passes the reading of Vr13', it is set to write complete after applying a certain number of programming voltage pulses.

[0308] This is because, as mentioned above, by narrowing the interval between the different threshold regions of the Middle page data in the data after programming in the first stage, even with simple control such as applying only a certain number of programming voltage pulses, it is possible to ensure that the interval between the different threshold regions of the Lower page and Top page data read during the second stage of writing is wide enough.

[0309] Furthermore, the readings following the application of programming voltage pulses for Vr8', Vr9', Vr12', and Vr14' can be omitted. After the reading of Vr5' has passed, the write operation is marked as complete after applying a predetermined number of programming voltage pulses for each of them. Alternatively, the readings following the application of programming voltage pulses for Vr4', Vr5', Vr8', Vr9', Vr12', and Vr14' can be further omitted. After the reading of Vr1' has passed, the write operation is marked as complete after applying a predetermined number of programming voltage pulses for each of them.

[0310] Figure 11 This is a flowchart illustrating the first example of the write step in the second stage. In the second stage of programming, firstly, an input start command for Middle page data is input from memory controller 2 to non-volatile memory 3 (step S310). Then, Middle page data is input from memory controller 2 to non-volatile memory 3 (step S320).

[0311] Next, the memory controller 2 inputs a start command for the upper page data to the non-volatile memory 3 (step S330). Then, the memory controller 2 inputs the upper page data to the non-volatile memory 3 (step S340). Next, the memory controller 2 inputs a second-stage programming execution command to the non-volatile memory 3 (step S350), thereby changing the chip to busy (step S360).

[0312] Next, the control unit 22 reads the Lower and Top pages as IDL (Internal Data Load) data (step S370). Then, based on the previously input Middle page data and the Lower and Top pages of the IDL, the Vth (threshold voltage) of the Upper page programming destination is determined (step S380). Then, using the determined Vth, data is written to the Upper page. More specifically, the voltage values ​​of multiple programming pulses are gradually increased to reach the determined threshold voltage during writing (step S390). Memory cells that have reached the target threshold voltage are excluded from the write targets.

[0313] Next, the written data is read (step S400), and it is confirmed whether the number of failed bits is less than the standard (judgment benchmark) (step S410). If the number of failed bits of the data is greater than the standard, the process from applying the programming pulse to judging the standard is repeated (steps S390 to S410). Moreover, when the number of failed bits of the data is less than the standard, the chip is ready (step S420).

[0314] This embodiment has two features. The first feature is that the Middle page data is already input in the first stage of programming, and the threshold region after the first programming is in a write state that also includes Middle page data. However, the Middle page data is input again in the second stage of programming. The second feature is that in the first stage of programming, the adjacent threshold regions where the Middle page data is switched are spaced narrower, while conversely, the adjacent threshold regions where the Lower page data and Top page data are switched are spaced wider. This improves the reliability of the Lower and Top page data read using IDL. On the other hand, if data is read using IDL, the reliability of the Middle page data might decrease. However, in this embodiment, since the Middle page data used in the first stage of programming is input again, there is no concern about reduced reliability.

[0315] Furthermore, to improve the reliability of IDL read data, the control unit 22 can perform multiple reads and retrieve the majority of the read results from the page buffer within the chip for use as subsequent write data. Of course, the control unit 22 can also perform multiple reads during normal read operations, retrieving the majority of the read results within the chip for use as read data for external transmission.

[0316] Figure 12 This is a diagram used to illustrate the multiple-read result processing. Figure 12 In the table, as a result of reading the predetermined page data, correct bits are marked with circles (○) and incorrect bits with crosses (×). Additionally, in... Figure 12 In the middle, it represents the result of selecting the most when three reads are performed.

[0317] Among the various digits, the cases where the most choices are judged as incorrect are (a) all three incorrect cases and (b) all two incorrect cases. If the probability of each digit being incorrect is set as p, then when p = 0.2, the probability of (a) all three incorrect cases is p × p × p = 0.2 × 0.2 × 0.2, and the probability of (b) all two incorrect cases is (1 - p) × p × p = (1 - 0.2) × 0.2 × 0.2.

[0318] Therefore, the result of selecting the most values ​​three times is judged to be incorrect as (p×p×p)+3×(1-p)×p×p=0.104. Thus, by performing multiple selection processes on the read results using the page buffer 24 within the chip, the control unit 22 can improve the reliability of the read data.

[0319] Furthermore, in order to improve the reliability of the read data of IDL in the second stage of word line WLn writing, the control unit 22 may change the read voltage of word line WLn in IDL according to the data or threshold voltage written in the first stage of word line WLn+1 writing and perform reading.

[0320] Furthermore, in order to improve the reliability of reading data from the IDL during the second stage of writing word line WLn, the control unit 22 can also change the non-selection voltage of word line WLn+1 in the IDL based on the data or threshold voltage written during the first stage of writing word line WLn+1. Alternatively, the reading voltage of word line WLn can be changed simultaneously for reading.

[0321] When writing data to the Upper page, one or more programming voltage pulses are applied. Furthermore, data is read from the Upper page (verification) to confirm whether the memory cell has moved beyond a threshold boundary level. The read level at this time is a predetermined level.

[0322] Furthermore, it is confirmed whether the number of invalid bits in the data of the Upper page is less than the standard. If the number of invalid bits in the data of the Upper page is greater than the standard, the process from application of the programming voltage pulse to verification is repeated. Moreover, if the number of invalid bits in the data is less than the standard, the chip becomes ready.

[0323] Here, on Figure 11 A variation of the writing step shown will be explained. Figure 13 This is a flowchart illustrating a modified example of the writing step in the second stage according to the first embodiment. Furthermore, in Figure 13 The flowchart includes the following additional step: After correcting errors in the IDL data obtained by reading the data programmed in the first stage, the process returns to the non-volatile memory 3. Specifically, firstly, a Lower page read command is input from the memory controller 2 to the non-volatile memory 3 (step S510). This causes the chip to become busy (step S512). Next, the control unit 22 reads the Lower page data using the threshold voltage Vr8'. Furthermore, based on the read result at the threshold voltage Vr8', the control unit 22 determines the value of the read data to be either "0" or "1" (step S514). Afterward, the process becomes chip ready (step S516).

[0324] When the control unit 22 outputs the read Lower page data (step S518), the Lower page data is sent to the ECC circuit 10 (step S520). Thereby, the ECC circuit 10 performs ECC correction on the Lower page data (step S522).

[0325] Next, an input start command is issued to input the data of the Lower page from the memory controller 2 to the non-volatile memory 3 (step S524). As a result, the ECC circuit 10 inputs the data of the Lower page to the non-volatile memory 3 (step S526).

[0326] Next, a read command for the Top page is input from the memory controller 2 to the non-volatile memory 3 (step S528), thereby making the chip busy (step S530). Then, the control unit 22 reads the Top page data using the threshold voltages of Vr2' and Vr10'. Then, based on the read results at the threshold voltages of Vr1', Vr4', Vr8', and Vr12', the control unit 22 determines the value of the read data to be either "0" or "1" (step S532). Afterwards, the chip becomes ready (step S534).

[0327] When the control unit 22 outputs the read Top page data (step S536), the Top page data is sent to the ECC circuit 10 (step S538). The ECC circuit 10 then performs ECC correction on the Top page data (step S540). Next, an input start command for the Top page data is sent from the memory controller 2 to the non-volatile memory 3 (step S542). The ECC circuit 10 then sends the Top page data to the non-volatile memory 3 (step S544).

[0328] Next, an input start command is sent from memory controller 2 to non-volatile memory 3 to input data for the Middle page (step S546). Subsequent steps are the same as... Figure 11 The steps are the same. Based on the Lower and Top page data from ECC circuit 10, the Middle page data that is input again, and the newly input Upper page data, the threshold voltage Vth of the programming destination is determined.

[0329] In the second stage of programming described above, only the Middle page and Upper page are input into the non-volatile memory 3. However, in this second stage, the threshold voltage Vth, the target of programming the memory cell, requires four pages of data, including the Lower page and the Top page (the threshold voltage Vth before the start of the second stage). Therefore, as preprocessing, the control unit 22 performs the following operation in this stage of programming: first, it reads the Lower page data and the Top page data, and then combines this data with the subsequently input Middle and Upper pages to determine the threshold voltage Vth of the programming target. Furthermore, the read level during verification in the second stage may be slightly different from the read level after writing in the second stage.

[0330] Here, a comparison is made between the processing steps of Foggy-Fine programming using 4-3-4-4 data encoding and the programming processing steps of this embodiment. Figure 14A This is a diagram illustrating the amount of data written to the buffer in Foggy-Fine programming using 4-3-4-4 data encoding. Figure 14B This is a diagram illustrating the amount of data written to the buffer in this embodiment. Figure 14B This illustrates an example of using 1-4-5-5 data encoding.

[0331] exist Figure 14A and Figure 14B In the diagram, the upper section represents the timeline of data input and programming execution for block writing, while the lower section represents the timeline of the period required to hold the data within the write buffer. Furthermore, in... Figure 14A and Figure 14B In this example, for simplicity, we've shown the case where there's only one string "St" within a block. When there are multiple strings "St", the amount of data written to the buffer needs to be a multiple of the number of strings "St".

[0332] In the case of Foggy-Fine programming with 4-3-4-4 data encoding, the first stage, the Foggy stage, involves inputting 4 pages of data and programming those 4 pages (Foggy stage programming). Additionally, in the case of Foggy-Fine programming with 4-3-4-4 data encoding, the second stage, the Fine stage, also involves inputting 4 pages of data and programming those 4 pages (Fine stage programming).

[0333] Furthermore, on each word line WL0, WL1, WL2, ..., until programming begins in the Fine stage, the 4-page amount of data written in the Foggy stage needs to be stored in the write buffer.

[0334] In Foggy-Fine programming, to reduce interference between adjacent memory locations, data in the four pages (Lower / Middle / Upper / Top) is not written contiguously. For example, after performing a Foggy stage to word line WL0, and before performing a Fine stage to word line WL0, a Foggy stage is performed to word line WL1, which is adjacent to word line WL0. Similarly, after performing a Foggy stage to word line WL1, and before performing a Fine stage to word line WL1, a Foggy stage is performed to word line WL2, which is adjacent to word line WL1. In this method, the four pages of data (Lower / Middle / Upper / Top) need to be kept in the write buffer until the data input for the final second Fine stage is complete. Furthermore, to reduce interference between adjacent memory locations, data on multiple word lines WL1 needs to be kept in the write buffer. For example, when performing the Foggy stage for word line WL2, four pages of data for word line WL1 and four pages of data for word line WL2 need to be kept in the write buffer. Thus, in the case of Foggy-Fine programming with 4-3-4-4 data encoding, up to eight pages of data need to be kept in the write buffer.

[0335] like Figure 14B As shown, in the programming of this embodiment, for example, two-stage programming is used in 1-4-5-5 data encoding. In the programming of this embodiment, in the first stage, three pages of data (Lower page, Middle page, and Top page) are input and the programming of these three pages is performed (first programming). In addition, in the programming of this embodiment, in the second stage, two pages of data (Middle page and Upper page) are input and one page of Upper page is programmed (second programming).

[0336] Furthermore, on each word line WL0, WL1, WL2, ..., except for the Middle page which is input in both stages, data can be stored in the write buffer during data input at each stage. When programming begins, the data can also be deleted from the write buffer. For example, if data is input in the first stage, that data is stored in the write buffer. Moreover, if programming begins in the first stage, the data on the Lower and Top pages previously stored in the write buffer can also be deleted. Similarly, if data is input in the second stage, that data is stored in the write buffer. Moreover, if programming begins in the second stage, all the data previously stored in the write buffer can be deleted. Therefore, in the programming case of this embodiment, it is necessary to pre-store a maximum of 4 pages of data in the write buffer.

[0337] In the programming of this embodiment, to reduce interference between adjacent memory cells, data in the four pages (Lower / Middle / Upper / Top) are not written contiguously. For example, after executing the first stage to word line WL0 and before executing the second stage to word line WL0, the first stage to word line WL1, which is adjacent to word line WL0, is executed. Similarly, after executing the first stage to word line WL1 and before executing the second stage to word line WL1, the first stage to word line WL2, which is adjacent to word line WL1, is executed.

[0338] Thus, in this embodiment, page data other than the Middle page is only needed during a single programming phase, so the data in the write buffer can be discarded once the data input is complete. Therefore, in this embodiment, the number of pages that need to be kept in the write buffer simultaneously can be relatively small.

[0339] Page data programmed into non-volatile memory 3 is temporarily held in a write buffer within RAM 6, and then written to non-volatile memory 3 during programming. In this embodiment, the required capacity of RAM 6 can be reduced, thus reducing costs.

[0340] Furthermore, when using Foggy-Fine programming, data forwarding of all pages must be performed twice, which incurs forwarding time and additional power consumption. In this implementation, page data, except for the Middle page, is processed through a single data forwarding for each page, thus reducing forwarding time and power consumption to approximately half.

[0341] Here, the page read process is explained. The method of page read differs depending on whether the programming of the word line WLi, which includes the page to be read, occurs before or after the second-stage write.

[0342] Before the second stage of writing, only the Lower, Middle, and Top pages are valid for recording data. Therefore, the control unit 22 reads data from the storage unit when the page being read is a Lower, Middle, or Top page, but does not read data from other pages (specifically, Upper pages), instead forcibly outputting all "1"s as read data.

[0343] On the other hand, when word lines WLi up to the second stage have been completed, the control unit 22 reads the memory cell regardless of whether the page to be read is a Top / Upper / Middle / Lower page. In this case, the required read voltage varies depending on which page is being read; therefore, the control unit 22 performs only the necessary reads according to the selected page.

[0344] The following describes the specific steps involved in page reading. Figure 15 This is a flowchart illustrating the processing steps of page reading on a word line in the memory system 1 according to the first embodiment, where programming has been completed up to the first stage (the second stage of programming has not been completed). Figure 6A The 1-4-5-5 data encoding shown has a boundary between the threshold states where the Lower page data changes. Therefore, the control unit 22 determines the data based on which of the two ranges the threshold falls within, separated by this boundary. For example, when the threshold voltage is less than Vr8', the control unit 22 controls the output of "1" as the data for the memory cell. On the other hand, when the threshold voltage is greater than Vr8', the control unit 22 controls the output of "0" as the data for the memory cell.

[0345] Furthermore, there are three boundaries between the threshold states where the data changes on the Middle page. Therefore, the control unit 22 determines the data based on which of the four ranges the threshold falls within. Similarly, there are four boundaries between the threshold states where the data changes on the Top page. Therefore, the control unit 22 determines the data based on which of the five ranges the threshold falls within.

[0346] like Figure 15 As shown, in the case of word line WLi before the second stage of writing, the control unit 22 selects the page to read (step S610). If the page to be read is a Lower page, the control unit 22 reads it using a reading voltage (step S612). As mentioned before, this voltage is Vr8, but in the case of word line before the second stage of writing, such as... Figure 7 As shown in (T2), there may also be a margin for the reading voltage and the threshold voltage, for example, Vr8'. Then, based on the reading result at the threshold voltage of Vr8, the control unit 22 determines the value of the read data as "0" or "1" (step S614).

[0347] Additionally, when the page being read is a Middle page, the control unit 22 uses three read voltages for reading (steps S616, S618, S620). As mentioned earlier, these voltages are Vr4, Vr9, and Vr14, but in the case of the word line before the second stage of writing, such as Figure 7As shown in (T2), there can also be margins for the read voltage and threshold voltage, for example, replacing them with Vr4', Vr9', and Vr14' respectively. Then, the control unit 22 determines the value of the read data as "0" or "1" based on the read results at the threshold voltage of Vr4, the threshold voltage of Vr9, and the threshold voltage of Vr14 (step S622). Here, as mentioned above, since the interval between the different threshold distributions of the data in the Middle page becomes narrower, the read margin of the Middle page becomes narrower, so there is a possibility that the reliability of the read data value is significantly worse, and the Middle page data before the second stage write can also be defined as invalid. In this case, when the read page is the Middle page, the control unit 22 can also perform forced output of all "1"s as the output data of the memory cell.

[0348] In addition, when the page being read is an Upper page, since the Upper page was not programmed in the first programming, the control unit 22 forcibly outputs all "1"s as output data (step S624).

[0349] Additionally, when the page being read is the Top page, the control unit 22 uses four read voltages for reading (steps S626, S628, S630, S632). As mentioned earlier, these voltages are Vr1, Vr4, Vr8, and Vr12, but in the case of the word line before the second stage of writing, such as Figure 7 As shown in (T2), there may also be margins for the read voltage and threshold voltage, for example, replacing them with Vr1', Vr4', Vr8', and Vr12' respectively. Then, based on the read results at the threshold voltage of Vr1, the threshold voltage of Vr4, the threshold voltage of Vr8, and the threshold voltage of Vr12, the control unit 22 determines the value of the read data as "0" or "1" (step S634).

[0350] Figure 16A This is a flowchart illustrating the processing steps for reading a page on a word line after programming has been completed to the second stage in the memory system according to the first embodiment. When programming has been completed to the second stage word line WLi, the control unit 22 selects a page to read (step S650). If the page to be read is a Lower page, the control unit 22 reads it using a threshold voltage Vr8 (step S652). Then, based on the read result at the threshold voltage Vr8, the control unit 22 determines the value of the read data to be either "0" or "1" (step S654).

[0351] Furthermore, when the page being read is a Middle page, the control unit 22 reads the data using the threshold voltages of Vr4, Vr9, Vr11, and Vr14 (steps S656, S658, S660, and S662). Then, based on the reading results at the threshold voltages of Vr4, Vr9, Vr11, and Vr14, the control unit 22 determines the value of the read data to be either "0" or "1" (step S664).

[0352] Furthermore, when the page being read is an Upper page, the control unit 22 reads the data using the threshold voltages of Vr2, Vr6, Vr10, Vr13, and Vr15 (steps S666, S668, S670, S672, and S674). Then, based on the reading results at the threshold voltages of Vr2, Vr6, Vr10, Vr13, and Vr15, the control unit 22 determines the value of the read data to be either "0" or "1" (step S676).

[0353] Furthermore, when the page being read is the Top page, the control unit 22 reads the data using the threshold voltages of Vr1, Vr3, Vr5, Vr7, and Vr12 (steps S678, S680, S682, S684, S686). Then, based on the reading results at the threshold voltages of Vr1, Vr3, Vr5, Vr7, and Vr12, the control unit 22 determines the value of the read data to be either "0" or "1" (step S688).

[0354] Furthermore, the memory controller 2 can manage and identify whether the programming of word line WLi occurs before or after the second-stage write is completed. In memory system 1, since the memory controller 2 performs programming control, it can easily refer to the programming status of which address in the non-volatile memory 3 by recording its progress. In this case, when the memory controller 2 reads from the non-volatile memory 3, it identifies the programming status of word line WLi, including the target page address, and issues a read command corresponding to the identified status. Alternatively, a flag unit can be set for word line WLi, written during the second-stage write, and the non-volatile memory 3 can manage / identify whether the second-stage write is completed before or after the write based on the data in the flag unit.

[0355] The following describes a variation of the page read processing. This variation of the page read processing can only be executed after the second stage of writing has been performed on the word line WLi that includes the page to be read. This variation of the page read processing is effective in that it speeds up the read operation when all data of the word line to be read is required.

[0356] The data encoding suitable for page read processing based on a variant is, for example, as follows: Figure 16B That kind of encoding. The following describes a variation of the read processing involved in this data encoding. In one variation of the page read processing, all pages of the Top / Upper / Middle / Lower pages are read.

[0357] Figure 16C This is a flowchart illustrating the read processing steps involved in a variant example. Additionally, Figure 16D This is a voltage waveform diagram of the select word line, ReadyBusy signal line, and output data line. The control unit 22 reads all 15 read voltages Vr15 to Vr1 sequentially. First, as... Figure 16D As shown, reading is performed at the highest voltage Vr15 (step S690), and then, reading is performed sequentially at a lower reading voltage, decreasing by one level each time (steps S691 to S707). When the reading required to determine the reading data for each page is completed, the reading data for that page can be output.

[0358] In a modified page read process, after sequentially reading from Vr15 until reading Vr8 (step S697), the data of the Lower page can be determined and output (step S698). In step S698, the data of the Lower page is determined based on the read data under the read voltage Vr8.

[0359] Next, when the reading ends up to Vr4 (step S702), the data of the Middle page is determined (step S703). In this step S703, the data of the Middle page is determined based on the reading data at reading voltages Vr4, Vr9, Vr11, and Vr14.

[0360] Next, when the reading ends up to Vr2 (step S705), the data for the Upper page is determined (step S706). In this step S706, the data for the Upper page is determined based on the read data at read voltages Vr2, Vr6, Vr10, Vr13, and Vr15.

[0361] Next, when the reading ends up to Vr1 (step S707), the final Top page data is determined (step S708). In this step S708, the Top page data is determined based on the reading data at reading voltages Vr1, Vr3, Vr5, Vr7, and Vr12.

[0362] In a modified page read process, the latency until an arbitrary page of data can be output is longer, but the total time to read all four pages is shorter than the total time in the previously described page-by-page reading scenario. For example... Figure 16D As shown, in preparation for reading, the word line only needs to be charged from zero to the high voltage Vr15 once. Furthermore, the voltage change amplitude when the reading level changes to the next voltage is small, and the voltage stabilizes quickly, thus shortening the waiting time until the reading voltage stabilizes. Therefore, when reading with all reading voltages Vr15 to Vr1, the total word line transition time is shortened, resulting in a faster overall reading time.

[0363] In addition, the above are taken Figure 16B The example given is a data encoding example, but it can be applied to virtually any data encoding. However, by changing the reading voltage sequentially from the maximum voltage to the minimum voltage, the data can be output in the order of the pages whose voltages are required to determine the data. Therefore, depending on the data encoding method, it is important to note that the reading should not be performed in the order of Lower, Middle, Upper, Top.

[0364] Thus, in the first embodiment, when programming the non-volatile memory 3 (a 4-bit / cell NAND memory with a three-dimensional or two-dimensional structure), 1-4-5-5 data encoding is used, and the programming stages are set to a two-stage system. This two-stage programming reduces the amount of data input during programming in each stage, suppressing the write buffer required by the memory controller 2. Furthermore, since the number of threshold boundaries is equal across pages, the deviation in bit error rate between pages of the non-volatile memory 3 can be reduced, and the cost of ECC can be lowered. Additionally, since data forwarding occurs only once per page except for one page, forwarding time and power consumption can be suppressed.

[0365] Furthermore, by performing each programming stage across word lines WLi, the amount of interference between adjacent cells on adjacent word lines WLi can be reduced. Additionally, due to the use of 1-4-5-5 data encoding, the variation in threshold distribution during the second programming is reduced, thus suppressing interference between adjacent cells. Moreover, by inputting data into a page (specifically the Middle page) in both stages, the IDL margin before the second stage can be increased, improving the reliability of write timing. Furthermore, due to the use of 1-4-5-5 data encoding, during the first stage programming, by setting one threshold boundary in the Lower page and two threshold boundaries in the Middle page, the programming of the first stage, i.e., the programming of the Lower and Middle pages, can be accelerated. Furthermore, the acceleration of the first stage programming can be achieved by setting the step voltage during write operations, which gradually increases the write voltage during write operations and write verification, to a value larger than that used in the second stage programming.

[0366] (Second Implementation)

[0367] The first embodiment uses a 1-4-5-5 data encoding as an example for explanation, but various data encoding variations are possible. The hardware configuration of the memory system 1 in the second embodiment is the same as that in the first embodiment. Figures 17-25 An example of data encoding for the memory system 1 of the second embodiment is shown. The memory system 1 of the second embodiment uses data encoding other than 1-4-5-5 data encoding.

[0368] Figure 17 This is a diagram illustrating an example of 1-5-4-5 data encoding. In Figure 17 In the example, the maximum number of transitions in the threshold region at the end of the second programming stage is 3. Here, although the voltage distribution ranges of the threshold regions at the end of the first and second programming stages are not entirely consistent, for convenience in this specification, the threshold region at the end of the second programming stage that has the closest associated voltage distribution range with each threshold region at the end of the first programming stage is referred to as the number of transitions in the threshold regions that changed during the second programming stage. Figure 17 In this scenario, programming is performed by inputting data from the Lower, Middle, and Upper pages in the first stage, and by inputting data from the Top and Middle pages in the second stage. The Middle page data is input repeatedly in both stages. At the completion time of the first stage, the interval between two threshold regions that can be separated by the Middle page data values ​​is narrower than the interval between other threshold regions.

[0369] Figure 18This is a diagram illustrating an example of 1-5-4-5 data encoding. In Figure 18 In the example, the maximum number of transitions in the threshold region at the end of the second programming iteration is 3. Figure 18 In this scenario, programming is performed by inputting data from the Lower, Middle, and Upper pages in the first stage, and by inputting data from the Top and Upper pages in the second stage. The Upper page data is input repeatedly in both stages. At the completion time of the first stage, the interval between two threshold regions that can be separated by the Upper page data values ​​is narrower than the interval between other threshold regions.

[0370] Figure 19 This is a diagram illustrating an example of 3-5-2-5 data encoding. In Figure 19 In the example, the maximum number of transitions in the threshold region at the end of the second programming iteration is 3. Figure 19 In this scenario, programming is performed by inputting data from the Lower, Middle, and Upper pages in the first stage, and by inputting data from the Top and Middle pages in the second stage. The Middle page data is input repeatedly in both stages. At the completion time of the first stage, the interval between two threshold regions that can be separated by the Middle page data values ​​is narrower than the interval between other threshold regions.

[0371] Figure 20 This is a diagram illustrating an example of 3-3-4-5 data encoding. In Figure 20 In the example, the maximum number of transitions in the threshold region at the end of the second programming iteration is 3. Figure 20 In the first stage, programming is performed by inputting data from the Lower, Middle, and Upper pages; in the second stage, programming is performed by inputting data from the Top and Upper pages.

[0372] Figure 21 This is a diagram illustrating an example of 2-3-5-5 data encoding. In Figure 21 In the example, the maximum number of transitions in the threshold region at the end of the second programming was 5. Figure 21 In this case, in the first stage, data from the Lower, Middle, and Top pages is input for programming; in the second stage, data from the Top and Upper pages is input for programming. The data for the Top page is input repeatedly in both stages. Figure 21 In this scenario, at the point when the first stage of programming is completed, regardless of whether the data on the Top page is 0 or 1, all three threshold regions are the same, resulting in a total of five threshold regions. This allows for a wider interval between the threshold regions, ensuring accurate data reading at the point when the first stage of programming is completed.

[0373] Figure 22 This is a diagram illustrating an example of 3-2-5-5 data encoding. In Figure 22 In the example, the maximum number of transitions in the threshold region at the end of the second programming was 5. Figure 22 In this case, in the first stage, data from the Lower, Middle, and Top pages is input for programming; in the second stage, data from the Top and Upper pages is input for programming. The data for the Top page is input repeatedly in both stages. Figure 22 In this case, at the point when the programming in the first stage is completed, regardless of whether the data on the Top page is 0 or 1, the two threshold regions are the same, and the total number of threshold regions becomes 6.

[0374] Figure 23 This is a diagram illustrating an example of 3-4-4-4 data encoding. In Figure 23 In the example, the maximum number of transitions in the threshold region at the end of the second programming was 7. Figure 23 In this scenario, programming is performed by inputting data from the Lower, Middle, and Upper pages in the first stage, and by inputting data from the Top and Upper pages in the second stage. The Upper page data is input repeatedly in both stages. At the completion time of the first stage, the interval between two threshold regions that can be separated by the Upper page data values ​​is narrower than the interval between other threshold regions.

[0375] Figure 24 This is a diagram illustrating an example of 3-4-4-4 data encoding. In Figure 24 In the example, the maximum number of transitions in the threshold region at the end of the second programming was 8. Figure 24 In this case, in the first stage, data from the Lower, Middle, and Top pages is input for programming; in the second stage, data from the Top and Upper pages is input for programming. The data for the Top page is input repeatedly in both stages. Figure 24 In this case, at the point when the programming in the first stage is completed, regardless of whether the data on the Top page is 0 or 1, the two threshold regions are the same, and the total number of threshold regions becomes 6.

[0376] Figures 17-24 This is just an example of data encoding; other data encoding methods may also be used.

[0377] For example, in the case where the maximum number of transitions in the threshold region at the end of the second programming iteration is 3, except for... Figures 17-20 In addition, there are the following Figures 25-27 . Figure 25 This is a diagram illustrating an example of 1-4-5-5 data encoding. In Figure 25 In the example, six different threshold regions are generated at the first point in time when the programming is completed. However, the threshold regions where the Top page is either 0 or 1, the Middle page is 1 and the Lower page is 1, and the Middle page is 0 and the Lower page is 1 all become the same threshold region. Therefore, instead of generating eight threshold regions, they are aggregated into six.

[0378] Figure 26 This is a diagram illustrating an example of 2-5-3-5 data encoding. In Figure 26 In the example, seven different threshold regions were generated at the point when the first programming was completed. However, the threshold regions where the Top page was either 0 or 1, the Middle page was 1, and the Lower page was 1 all became the same. Therefore, instead of eight threshold regions, seven were generated.

[0379] Figure 27 This is a diagram illustrating an example of 3-4-5-3 data encoding. In Figure 27 In the example, seven different threshold regions were generated at the point when the first programming was completed. However, the threshold regions where the Top page was either 0 or 1, the Middle page was 1, and the Lower page was 1 all became the same. Therefore, instead of eight threshold regions, seven were generated.

[0380] In addition, other examples of data encoding can be considered. Below, a diagram illustrating the code allocation for each data encoding is provided. Figure 28 This illustrates an example of 3-2-5-5 data encoding. Figure 29 This illustrates an example of 3-2-5-5 data encoding. Figure 30 This illustrates an example of 1-5-5-4 data encoding. Additionally, Figure 31 This illustrates an example of 1-5-4-5 data encoding. Figure 32 This illustrates an example of 1-4-5-5 data encoding. Figure 33 This illustrates an example of 1-5-3-6 data encoding. Additionally, Figure 34 This illustrates an example of 1-3-6-5 data encoding. Figure 35 This illustrates an example of 1-2-6-6 data encoding. Figure 36 This represents an example of 1-2-6-6 data encoding.

[0381] in addition, Figure 37 This illustrates an example of 1-2-6-6 data encoding. Figure 38 This illustrates an example of 1-4-6-4 data encoding. Figure 39 This illustrates an example of 1-4-4-6 data encoding. Additionally, Figure 40 This illustrates an example of 1-4-6-4 data encoding. Figure 41 This illustrates an example of 1-4-4-6 data encoding. Figure 42 This illustrates an example of 2-5-2-6 data encoding. Additionally, Figure 43 This illustrates an example of 2-5-2-6 data encoding. Figure 44 This illustrates an example of 2-5-2-6 data encoding. Figure 45 This illustrates an example of 3-3-3-6 data encoding. Additionally, Figure 46 This illustrates an example of 3-3-6-3 data encoding. Figure 47 This illustrates an example of 2-3-4-6 data encoding. Figure 48 This represents an example of 3-4-2-6 data encoding.

[0382] in addition, Figure 49 This illustrates an example of 2-3-4-6 data encoding. Figure 50 This illustrates an example of 3-2-6-4 data encoding. Figure 51 This illustrates an example of 3-2-4-6 data encoding. Additionally, Figure 52 This illustrates an example of 3-2-6-4 data encoding. Figure 53 This illustrates an example of 3-4-2-6 data encoding. Figure 54 This illustrates an example of 3-2-4-6 data encoding. Additionally, Figure 55 This illustrates an example of 5-3-2-5 data encoding. Figure 56 This illustrates an example of 3-5-2-5 data encoding. Figure 57 This illustrates an example of 3-2-5-5 data encoding. Additionally, Figure 58 This illustrates an example of 2-3-5-5 data encoding. Figure 59 This illustrates an example of 2-3-5-5 data encoding. Figure 60 This represents an example of 2-3-5-5 data encoding.

[0383] in addition, Figure 61 This illustrates an example of 5-4-2-4 data encoding. Figure 62 This illustrates an example of 4-5-2-4 data encoding. Figure 63 This illustrates an example of 5-4-2-4 data encoding. Additionally, Figure 64 This illustrates an example of 2-4-5-4 data encoding. Figure 65 This illustrates an example of 2-4-5-4 data encoding. Figure 66 This illustrates an example of 2-5-4-4 data encoding. Additionally, Figure 67 This illustrates an example of 2-5-4-4 data encoding. Figure 68 This illustrates an example of 2-5-4-4 data encoding. Figure 69 This illustrates an example of 1-5-4-5 data encoding. Additionally, Figure 70This illustrates an example of 1-4-5-5 data encoding. Figure 71 This illustrates an example of 1-5-5-4 data encoding. Figure 72 This represents an example of 1-4-5-5 data encoding.

[0384] in addition, Figure 73 This illustrates an example of 1-5-5-4 data encoding. Figure 74 This illustrates an example of 1-5-4-5 data encoding. Figure 75 This illustrates an example of 1-5-5-4 data encoding. Additionally, Figure 76 This illustrates an example of 1-5-4-5 data encoding. Figure 77 This illustrates an example of 1-4-5-5 data encoding. Figure 78 This illustrates an example of 1-4-5-5 data encoding. Additionally, Figure 79 This illustrates an example of 1-4-5-5 data encoding. Figure 80 This illustrates an example of 1-4-5-5 data encoding. Figure 81 This illustrates an example of 3-5-4-3 data encoding. Additionally, Figure 82 This illustrates an example of 3-4-5-3 data encoding. Figure 83 This illustrates an example of 3-5-3-4 data encoding. Figure 84 This represents an example of 3-4-3-5 data encoding.

[0385] in addition, Figure 85 This illustrates an example of 3-4-5-3 data encoding. Figure 86 This illustrates an example of 3-4-3-5 data encoding. Figure 87 This illustrates an example of 3-3-5-4 data encoding. Additionally, Figure 88 This illustrates an example of 3-3-5-4 data encoding. Figure 89 This illustrates an example of 4-5-3-3 data encoding. Figure 90 This illustrates an example of 3-5-4-3 data encoding. Additionally, Figure 91 This illustrates an example of 3-4-5-3 data encoding. Figure 92 This illustrates an example of 3-3-4-5 data encoding. Figure 93 This represents an example of 3-3-4-5 data encoding.

[0386] in addition, Figure 94 This illustrates an example of 3-3-4-5 data encoding. Figure 95 This illustrates an example of 3-4-5-3 data encoding. Figure 96 This illustrates an example of 3-3-5-4 data encoding. Additionally, Figure 97 This illustrates an example of 3-3-4-5 data encoding. Figure 98 This illustrates an example of 4-3-4-4 data encoding. Figure 99 This illustrates an example of 3-4-4-4 data encoding. Additionally, Figure 100 This illustrates an example of 3-4-4-4 data encoding. Figure 101 This illustrates an example of 4-3-4-4 data encoding. Figure 102 This illustrates an example of 3-4-4-4 data encoding. Additionally, Figure 103 This illustrates an example of 3-4-4-4 data encoding. Figure 104 This illustrates an example of 3-4-4-4 data encoding. Figure 105 This illustrates an example of 3-4-4-4 data encoding. Additionally, Figure 106 This illustrates an example of 4-4-3-4 data encoding. Figure 107 This represents an example of 4-4-3-4 data encoding.

[0387] Thus, by repeatedly inputting a portion of the page's data in the first and second stages, while programming the data for other pages only in one of the first and second stages, inter-cell interference can be reduced, the write buffer capacity can be decreased, and deviations in the bit error rate when writing each bit of data can be suppressed. In particular, in the case of 1-4-5-5, 1-5-4-5, 3-3-4-5, or 3-5-2-5 data encoding, the number of boundaries for each page of data is equal, and the number of transitions in the threshold region during programming in the second stage is less than 3, thereby suppressing deviations in the bit error rate and reducing inter-cell interference.

[0388] (Third Implementation)

[0389] The memory system 1 of the third embodiment has a reduced write buffer capacity compared to the first and second embodiments.

[0390] The hardware configuration of the memory system 1 according to the third embodiment is the same as that of the memory systems 1 according to the first and second embodiments. In the third embodiment, for page data that is repeatedly entered in the second stage of programming as in the first stage of programming, it continues to be held in the page buffer 24 inside the non-volatile memory 3 after the start of the first stage of programming. As a result, the step of entering the data for that page can be omitted in the second stage of programming, and the data entry for all pages is only done once. As a result, the capacity of the write buffer can be reduced.

[0391] Furthermore, in this embodiment, the second-stage programming of word line WLn-1 and the first-stage programming of word line WLn are performed centrally. Thus, for data of bits that are repeatedly input in the first and second-stage programming of bits 1 to 4 (Lower page, Middle page, Upper page, Top page), page buffer 24 stores the data of that bit before the start of the first-stage programming and can discard or invalidate it after the start of the second-stage programming. Hereinafter, in this embodiment, the method used in the first embodiment will also be discussed. Figure 6A The same 1-4-5-5 data encoding example described in the text will be used for illustration.

[0392] exist Figure 9 In the programming flowchart shown, the execution timing of the first and second stages of programming is offset, and each stage performs its own programming commands and inputs programming data. In contrast, in this embodiment, the programming commands and inputs for the first and second stages are performed as centrally as possible.

[0393] For example, such as Figure 8B As shown, except for the beginning and end of the block, the programming of the first stage of word line WLn and the second stage of word line WLn-1 must be performed consecutively. Therefore, in this embodiment, this part is treated as a single command input. That is, the programming data for the Lower, Middle, and Top pages of word line WLn and the Upper page of word line WLn-1 are input in a single command input. This is the same amount of data input as when using Foggy-Fine, where the data for the Lower / Middle / Upper / Top pages is input in a single programming command (but in this case, pages within the same word line WLn).

[0394] In this way, by centralizing the input of programming commands and programming data, the frequency of command input and / or polling (periodic checks to see if the chip has returned from busy to ready) in the control of the memory controller 2 is reduced, which enables the memory system 1 to be faster and the control to be simplified.

[0395] Here, use Figure 108 and Figure 109 An example of the writing steps according to the programming order involved in the third embodiment will be described. Figure 108 and Figure 109 In the middle, it indicates that according to Figure 8B The writing steps are shown in the programming order.

[0396] Figure 108This is a flowchart illustrating the writing steps of a block as a whole according to the third embodiment. Here, a block has n+1 word lines WLi, from word lines WL0 to WLn (n is a natural number). For example... Figure 108 As shown, when writing begins (step S710), the first stage of programming of the word lines WL0 of strings St0 to St3 is performed (step S712). As a result, the control unit 22 performs the first stage of programming of the word lines WL0 of strings St0 to St3 (step S714).

[0397] In addition, the control unit 22 performs the first stage of programming of the serial St0_word line WL1 and the second stage of programming of the serial St0_word line WL0 (step S716).

[0398] Next, the control unit 22 performs the first stage of programming for string St1_word line WL1 and the second stage of programming for string St1_word line WL0 (step S718). Then, the control unit 22 performs the first stage of programming for string St2_word line WL1 and the second stage of programming for string St2_word line WL0 (step S720). Afterward, the control unit 22 repeatedly performs the same processing on each word line WLi of each string.

[0399] Next, the first stage of programming for string St0_word line WLn and the second stage of programming for string St0_word line WLn-1 are performed (step S722). Then, the control unit 22 performs the first stage of programming for string St1_word line WLn and the second stage of programming for string St1_word line WLn-1 (step S724). Afterwards, the control unit 22 repeatedly performs the same processing on each word line WLi of each string.

[0400] Next, the control unit 22 performs the first stage of programming for the string St3_word line WLn and the second stage of programming for the string St3_word line WLn-1 (step S726). Next, the control unit 22 performs the second stage of programming for the word lines WLn of strings St0 to St3 (steps S728, S730, S732).

[0401] Thus, at the beginning of the block, programming in only the first stage is performed, similar to the first embodiment; and at the end of the block, programming in only the second stage is performed, similar to the first embodiment. In this case, programming in only the first stage follows... Figure 8B Perform the steps shown, only the second stage of programming follows the instructions. Figure 8C Follow the steps shown. Additionally, in Figure 108 In the flowchart, except at the beginning and end of the block, the first stage of programming for word line WLn and the second stage of programming for word line WLn-1 are performed centrally. This reduces the frequency of command input and / or polling by the memory controller 2, enabling faster processing of the memory system 1.

[0402] Figure 109 This is a flowchart illustrating the writing steps in the first and second stages of the third embodiment. For example... Figure 109 As shown, in the first and second stages of programming, the second stage of programming is executed after the first stage. Specifically, firstly, an input start command for the upper page data of word line WLn-1 is input from the memory controller 2 to the non-volatile memory 3 (step S750). Then, the upper page data of word line WLn-1 is input from the memory controller 2 to the non-volatile memory 3 (step S752).

[0403] Next, an input start command for the lower page data of word line WLn is input from memory controller 2 to non-volatile memory 3 (step S754). Then, the lower page data of word line WLn is input from memory controller 2 to non-volatile memory 3 (step S756).

[0404] Next, an input start command for the Middle page data of word line WLn is input from memory controller 2 to non-volatile memory 3 (step S758). Then, the Middle page data of word line WLn is input from memory controller 2 to non-volatile memory 3 (step S760). The Middle page data is not only input to non-volatile memory 3, but also stored in page buffer 24. After being stored in page buffer 24, the Middle data written to the buffer can be discarded or invalidated.

[0405] Next, the memory controller 2 inputs a start command for the input of the top page data of word line WLn to the non-volatile memory 3 (step S762). Then, the memory controller 2 inputs the top page data of word line WLn to the non-volatile memory 3 (step S764).

[0406] Next, the memory controller 2 inputs the first and second stage programming execution commands to the non-volatile memory 3 (step S766), thereby changing the chip to busy (step S768).

[0407] Next, one or more programming voltage pulses are applied to the Lower, Middle, and Top pages of word line WLn (step S770). Then, to confirm whether the memory cell has moved due to exceeding the threshold boundary level, data is read from the Lower and Top pages of word line WLn (step S772).

[0408] Next, it is confirmed whether the number of invalid bits in the data of the Lower page and Top page is less than the standard (step S774). If the number of invalid bits in the data of the Lower page and Top page is greater than the standard, steps S770 to S774 are repeated. Moreover, if the number of invalid bits in the data is less than the standard, the Lower page and Top page data of word line WLn-1 are read (step S776).

[0409] Then, based on the Lower and Top data of word line WLn-1 and the data of the Middle page read from page buffer 24, the threshold voltage Vth for the programming destination of the Upper page is determined (step S778). After that, data is written to the Upper page of word line WLn-1 using the determined threshold voltage Vth (step S780).

[0410] When writing data to the Upper page, one or more programming voltage pulses are applied to the Upper page of word line WLn-1. Then, data is read from the Upper page of word line WLn-1 to confirm whether the memory cell has moved beyond the threshold boundary level (step S782).

[0411] Next, a verification is performed to confirm whether the number of invalid bits in the data of the Upper page is less than the standard (step S784). If the number of invalid bits in the data of the Upper page is greater than the standard, the process of applying programming voltage pulses and reading and verifying data is repeated. Moreover, if the number of invalid bits in the data is less than the standard, the chip becomes ready (step S786).

[0412] Furthermore, in the first stage of programming for the same word line, the order of the data input start commands and page input processing for multiple pages is arbitrary; any page can be input first. Similarly, in the second stage of programming for the same word line, the order of the data input start commands and page input processing for multiple pages is also arbitrary. However, the word line numbers and the order of the programming processes in the two stages must be... Figure 109 The order shown.

[0413] Thus, in Figure 109 The text explains the case where the first stage of programming for word line WLn is performed before the second stage of programming for word line WLn-1. This is because by performing the first stage of programming for word line WLn first, the cells of word line WLn-1 that write the threshold voltage Vth of the 16-value are not affected by adjacent cells.

[0414] As described above, in this embodiment, the data of the Upper page of word line WLn-1 and the data of the Lower, Middle and Top pages of word line WLn are input continuously.

[0415] Alternatively, as another variation, after inputting the programming command, as an IDL, after first reading the data of the Lower, Middle, and Top pages of word line WLn-1, programming the Lower, Middle, and Top pages of word line WLn is performed. Then, the threshold voltage Vth for the programming destination of the Upper page of word line WLn-1 is determined, and the Upper page of word line WLn-1 is programmed using the determined threshold voltage Vth. In this way, the data of the Lower, Middle, and Top pages of word line WLn-1 of the IDL can be read before interference between adjacent cells caused by writing to word line WLn occurs.

[0416] Furthermore, the actual execution order of the programming performed by the command that summarizes the first stage of word line WLn and the second stage of word line WLn-1 in this embodiment can be changed. That is, Figure 109 The programming of the Lower, Middle, and Top pages of word line WLn, and the data reading of the Lower, Middle, and Top pages of word line WLn-1 (which serves as the IDL), can be performed either way and can be interchanged. By performing the data reading of the Lower, Middle, and Top pages of word line WLn-1 before the programming of the Lower, Middle, and Top pages of word line WLn, IDL can be performed without being affected by the programming of the Lower, Middle, and Top pages of word line WLn.

[0417] Thus, in the third embodiment, the second stage of programming for word line WLn-1 and the first stage of programming for word line WLn are performed centrally, thereby reducing the frequency of command input and / or polling. Therefore, the memory system 1 can be accelerated and control simplified.

[0418] Figure 110 This is a diagram illustrating the write buffer size (buffer data size) in the programming of the third embodiment. In this embodiment, two-stage programming is used in the 1-4-5-5 data encoding. In the programming of this embodiment, in the first stage, three pages of data (Lower page, Middle page, and Top page) are input and the programming of these three pages is performed (first programming). Furthermore, in the programming of this embodiment, in the second stage, one page of data (Upper page) is input and the programming of the Upper page is performed (second programming).

[0419] Furthermore, for each word line WL0, WL1, WL2, ..., data only needs to be stored in the write buffer during data input at each stage, and the data can be deleted from the write buffer at the start of programming. For example, if data is input in the first stage, that data is stored in the write buffer. Moreover, if programming begins in the first stage, the data of the Lower, Top, and Middle pages pre-stored in the write buffer can also be deleted. However, the data of the Middle page is also used in the second stage, so it needs to be stored in the page buffer 24 until the start of programming in the second stage. Similarly, if data is input in the second stage, that data is stored in the write buffer. Moreover, if programming begins in the second stage, all the data pre-stored in the write buffer can be deleted. Therefore, in the case of programming in this embodiment, the amount of data that needs to be pre-stored in the write buffer is at most 3 pages, which is less than in the first embodiment.

[0420] In the programming of this embodiment, to reduce interference between adjacent memory cells, data in the four pages (Lower / Middle / Upper / Top) are not written contiguously. For example, after executing the first stage to word line WL0 and before executing the second stage to word line WL0, the first stage to word line WL1, which is adjacent to word line WL0, is executed. Similarly, after executing the first stage to word line WL1 and before executing the second stage to word line WL1, the first stage to word line WL2, which is adjacent to word line WL1, is executed.

[0421] Thus, in this embodiment, all page data is only needed during a single programming phase, so the data in the write buffer can be discarded once the data input is complete. Therefore, in this embodiment, the number of pages that need to be kept in the write buffer simultaneously can be less than in the first embodiment.

[0422] Page data programmed into non-volatile memory 3 is temporarily held in a write buffer within RAM 6, and then written to non-volatile memory 3 during programming. In this embodiment, the required capacity of RAM 6 can be reduced, thus reducing costs.

[0423] In addition, in this embodiment, each page is completed through a single data forwarding, thus reducing the page data forwarding time compared to the first embodiment and reducing power consumption during forwarding.

[0424] The page read process in this embodiment is the same as the process steps described in the first embodiment, so the description is omitted.

[0425] Furthermore, in this embodiment, to maintain the data in the new, persistent page, the page buffer 24 inside the NAND flash memory needs to be increased. In such... Figure 8A As shown, in programming a NAND flash memory within a block of memory, the amount of page buffer 24 that needs to be added is equal to the amount of data in one page. In contrast, in situations such as... Figure 8B or Figure 8C As shown, programming a NAND flash memory with four strings in a block requires an additional page buffer 24 of four pages of data. This is because after executing the first stage of programming for one string, the first stage of programming for the other three strings must be executed before the second stage of programming for the same string can be executed. As a result, one page of data needs to be held for each of the four strings.

[0426] In this embodiment, the 1-4-5-5 data encoding is used as an example for explanation, but various data encoding variations can be performed, and the above-described implementation method can obviously be achieved.

[0427] In the first to third embodiments described above, the case where the non-volatile memory 3 is constructed using NAND memory 5 has been described. However, other types of non-volatile memory 3, such as ReRAM (Resistive Random Access Memory), MRAM (Magneto-Resistive Random Access Memory), PRAM (Phase Change Random Access Memory), and FeRAM (Ferroeletric Random Access Memory), may also be used.

[0428] In the first to third embodiments described above, it was explained that 3 pages of data were written in the first stage of programming and 2 pages of data were written in the second stage of programming. However, the allocation of the number of pages in the first stage of programming and the number of pages in the second stage of programming can also be changed. For example, it is also possible to write 2 pages of data in the first stage of programming and 3 pages of data in the second stage of programming.

[0429] Several embodiments of this disclosure have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and / or spirit of the invention, and are included within the scope of the invention described in the technical solution and its equivalents.

Claims

1. A memory system comprising: A non-volatile memory having multiple memory cells, each of which can store 4 bits of data represented by bits 1 through 4 using 16 threshold regions, the 16 threshold regions including a first threshold region indicating an erased state, and second to 16th threshold regions indicating a write state with a higher voltage level than the first threshold region; and The memory controller, after performing a first programming operation by writing the data of the first bit, the second bit, and the fourth bit into the non-volatile memory, then performs a second programming operation by writing the data of the third bit into the non-volatile memory. The memory controller is configured such that a threshold region in the memory cell becomes one of the following threshold regions: a 17th threshold region indicating an erased state (data has been erased) and a 18th to 24th threshold regions indicating a written state (data has been written), based on the data of the 1st bit, the 2nd bit, and the 4th bit. This allows the non-volatile memory to perform the first programming. The memory controller is configured to cause the non-volatile memory to perform the second programming in such a way that a threshold region in the memory cell changes from one of the threshold regions from the 17th to the 22nd threshold regions to one of two threshold regions from the 1st to the 12th threshold regions, and changes from one of the 23rd and 24th threshold regions to one of two threshold regions from the 13th to the 16th threshold regions, based on the data of the 3rd bit. The memory controller is configured to input the second bit of data and the third bit of data into the non-volatile memory when the non-volatile memory is programmed in the second way.

2. The memory system according to claim 1, The memory controller is configured as follows: When the non-volatile memory is programmed in the first manner, the first bit of data, the second bit of data, and the fourth bit of data are input to the non-volatile memory. When the non-volatile memory is programmed in the second way, the second bit of data and the third bit of data are input to the non-volatile memory.

3. The memory system according to claim 1, The memory controller is configured to enable the second programming of the non-volatile memory in such that a threshold region in the memory cell changes from one of the 17th and 18th threshold regions to one of the two threshold regions in the 1st to 4th threshold regions based on the data of the 3rd bit.

4. The memory system according to claim 3, The memory controller is configured to enable the second programming of the non-volatile memory in such a way that the threshold region in the memory cell changes from the 22nd threshold region to the 8th threshold region or the 9th threshold region according to the data of the 3rd bit.

5. The memory system according to claim 1, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 4, the number of boundaries with different values ​​of the third bit is 4, and the number of boundaries with different values ​​of the fourth bit is 4.

6. The memory system according to claim 1, The memory controller is configured to input the third bit data and the fourth bit data to the non-volatile memory when the non-volatile memory is programmed in the second way.

7. A memory system comprising: A non-volatile memory having multiple memory cells, each of which can store 4 bits of data represented by bits 1 through 4 using 16 threshold regions, the 16 threshold regions including a first threshold region indicating an erased state, and second to 16th threshold regions indicating a write state with a higher voltage level than the first threshold region; and A memory controller, after performing a first programming operation by writing data to the non-volatile memory based on the data in the first, second, and fourth bits, then performs a second programming operation by writing data to the non-volatile memory based on the data in the third and fourth bits. The memory controller is configured such that a threshold region in the memory cell becomes one of the following threshold regions: a 17th threshold region indicating an erased state (data has been erased) and a 18th to 21st threshold region indicating a written state (data has been written), based on the data of the 1st bit, the 2nd bit, and the 4th bit. This allows the non-volatile memory to perform the first programming. The memory controller is configured to cause the non-volatile memory to perform the second programming in such a way that a threshold region in the memory cell changes from one of the threshold regions from the 17th to the 19th threshold regions to one of the four threshold regions from the 1st to the 12th threshold regions based on the data of the 3rd bit and the data of the 4th bit, and changes from one of the threshold regions from the 20th and 21st threshold regions to one of the two threshold regions from the 13th to the 16th threshold regions. The memory controller is configured to input the third bit data and the fourth bit data to the non-volatile memory when the non-volatile memory is programmed in the second way.

8. The memory system according to claim 7, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 17th threshold region to a threshold region from the 1st threshold region to the 4th threshold region.

9. The memory system according to claim 8, The memory controller is configured to cause the non-volatile memory to be programmed in the second way such that the non-volatile memory changes from the 18th threshold region to one of the 5th threshold region, the 6th threshold region, the 9th threshold region, and the 10th threshold region.

10. The memory system according to claim 9, The memory controller is configured to cause the non-volatile memory to be programmed in the second way such that the non-volatile memory changes from the 19th threshold region to one of the 7th threshold region, the 8th threshold region, the 11th threshold region, and the 12th threshold region.

11. The memory system according to claim 10, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 20th threshold region to the 13th threshold region or the 14th threshold region.

12. The memory system according to claim 11, The memory controller causes the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 21st threshold region to the 15th threshold region or the 16th threshold region.

13. The memory system according to claim 7, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 2, the number of boundaries with different values ​​of the second bit is 3, the number of boundaries with different values ​​of the third bit is 5, and the number of boundaries with different values ​​of the fourth bit is 5.

14. A memory system comprising: A non-volatile memory having multiple memory cells, each of which can store 4 bits of data represented by bits 1 through 4 using 16 threshold regions, the 16 threshold regions including a first threshold region indicating an erased state, and second to 16th threshold regions indicating a write state with a higher voltage level than the first threshold region; and A memory controller, after performing a first programming operation by writing data to the non-volatile memory based on the data in the first, second, and fourth bits, then performs a second programming operation by writing data to the non-volatile memory based on the data in the third and fourth bits. The memory controller is configured such that a threshold region in the memory cell becomes one of the following threshold regions: a 17th threshold region indicating an erased state (data has been erased) and a 18th to 22nd threshold regions indicating a write state (data has been written), based on the data of the 1st bit, the 2nd bit, and the 4th bit. This allows the non-volatile memory to perform the first programming. The memory controller is configured to cause the non-volatile memory to undergo the second programming in such a manner that a threshold region in the memory cell changes from one of the 17th and 18th threshold regions to one of four threshold regions from the 1st to the 10th threshold regions based on the data of the 3rd bit and the 4th bit, and changes from one of the 19th to the 22nd threshold regions to one of two threshold regions from the 11th to the 16th threshold regions or one of two threshold regions from the 5th to the 8th threshold regions. The memory controller is configured to input the third bit data and the fourth bit data to the non-volatile memory when the non-volatile memory is programmed in the second way.

15. The memory system according to claim 14, The two threshold regions in the 11th threshold region to the 16th threshold region are adjacent.

16. The memory system according to claim 15, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 20th threshold region to the 11th threshold region or the 12th threshold region.

17. The memory system according to claim 16, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 21st threshold region to the 13th threshold region or the 14th threshold region.

18. The memory system according to claim 17, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 22nd threshold region to the 15th threshold region or the 16th threshold region.

19. The memory system according to claim 18, The memory controller is configured to perform the second programming on the non-volatile memory in such a way that a threshold region is changed from one of the 17th threshold region and the 18th threshold region to one of the four threshold regions from the 1st threshold region to the 10th threshold region.

20. The memory system according to claim 19, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 17th threshold region to a threshold region among the 1st to 4th threshold regions.

21. The memory system according to claim 20, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 18th threshold region to the 5th threshold region, the 6th threshold region, the 9th threshold region, or the 10th threshold region.

22. The memory system according to claim 21, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 19th threshold region to the 7th threshold region or the 8th threshold region.

23. The memory system according to claim 14, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 2, the number of boundaries with different values ​​of the third bit is 5, and the number of boundaries with different values ​​of the fourth bit is 5.

24. The memory system according to claim 19, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 17th threshold region to the 1st threshold region, the 2nd threshold region, the 7th threshold region, or the 8th threshold region.

25. The memory system according to claim 24, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 18th threshold region to the 3rd threshold region, the 4th threshold region, the 9th threshold region, or the 10th threshold region.

26. The memory system according to claim 25, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 19th threshold region to the 5th threshold region or the 6th threshold region.

27. The memory system according to claim 14, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 4, the number of boundaries with different values ​​of the third bit is 4, and the number of boundaries with different values ​​of the fourth bit is 4.

28. A memory system comprising: A non-volatile memory having multiple memory cells, each of which can store 4 bits of data represented by bits 1 through 4 using 16 threshold regions, the 16 threshold regions including a first threshold region indicating an erased state, and second to 16th threshold regions indicating a write state with a higher voltage level than the first threshold region; and A memory controller, after performing a first programming operation by writing data to the non-volatile memory based on the data in the first, second, and fourth bits, then performs a second programming operation by writing data to the non-volatile memory based on the data in the third and fourth bits. The memory controller is configured such that a threshold region in the memory cell becomes one of the following threshold regions: a 17th threshold region indicating an erased state (data has been erased) and a 18th to 22nd threshold region indicating a written state (data has been written), based on the data of the 1st bit, the 2nd bit, and the 4th bit. This allows the non-volatile memory to perform the first programming. The memory controller is configured to cause the non-volatile memory to perform the second programming in such a way that a threshold region in the memory cell changes from one of the 17th and 18th threshold regions to one of four threshold regions from the 1st to the 8th threshold regions based on the data of the 3rd bit and the data of the 4th bit, and changes from one of the 19th to the 22nd threshold regions to one of two threshold regions from the 9th to the 16th threshold regions. The memory controller is configured to input the third bit data and the fourth bit data to the non-volatile memory when the non-volatile memory is programmed in the second way.

29. The memory system according to claim 28, The number of threshold regions between the lowest voltage level threshold region and the highest voltage level threshold region among the two threshold regions in the 9th to 16th threshold regions is two or less.

30. The memory system according to claim 29, The four threshold regions in the first to eighth threshold regions are adjacent. The two threshold regions in the 13th threshold region to the 16th threshold region are adjacent.

31. The memory system according to claim 30, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 17th threshold region to a threshold region between the 1st and 4th threshold regions.

32. The memory system according to claim 31, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 18th threshold region to a threshold region between the 5th and 8th threshold regions.

33. The memory system according to claim 32, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 19th threshold region to the 9th threshold region or the 12th threshold region.

34. The memory system according to claim 33, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 20th threshold region to the 10th threshold region or the 11th threshold region.

35. The memory system according to claim 34, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 21st threshold region to the 13th threshold region or the 14th threshold region.

36. The memory system according to claim 35, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 22nd threshold region to the 15th threshold region or the 16th threshold region.

37. The memory system according to claim 28, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 1, the number of boundaries with different values ​​of the second bit is 4, the number of boundaries with different values ​​of the third bit is 5, and the number of boundaries with different values ​​of the fourth bit is 5.

38. A memory system comprising: A non-volatile memory having multiple memory cells, each of which can store 4 bits of data represented by bits 1 through 4 using 16 threshold regions, the 16 threshold regions including a first threshold region indicating an erased state, and second to 16th threshold regions indicating a write state with a higher voltage level than the first threshold region; and A memory controller, after performing a first programming operation by writing data to the non-volatile memory based on the data in the first, second, and fourth bits, then performs a second programming operation by writing data to the non-volatile memory based on the data in the third and fourth bits. The memory controller is configured such that a threshold region in the memory cell becomes one of the following threshold regions: a 17th threshold region indicating an erased state (data has been erased) and a 18th to 23rd threshold region indicating a written state (data has been written), based on the data of the 1st bit, the 2nd bit, and the 4th bit. This allows the non-volatile memory to perform the first programming. The memory controller is configured to cause the non-volatile memory to perform the second programming in such a way that a threshold region in the memory cell changes from the 17th threshold region to one of the 1st to 4th threshold regions based on the data of the 3rd bit and the data of the 4th bit, and changes from one of the 18th to 23th threshold regions to one of two threshold regions in the 5th to 16th threshold regions. The memory controller is configured to input the third bit data and the fourth bit data to the non-volatile memory when the non-volatile memory is programmed in the second way.

39. The memory system according to claim 38, The number of threshold regions between the lowest voltage level threshold region and the highest voltage level threshold region among the two threshold regions in the 5th to 16th threshold regions is no more than two.

40. The memory system according to claim 39, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 18th threshold region to the 5th threshold region or the 6th threshold region.

41. The memory system according to claim 40, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 19th threshold region to the 7th threshold region or the 10th threshold region.

42. The memory system according to claim 41, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 20th threshold region to the 8th threshold region or the 9th threshold region.

43. The memory system according to claim 42, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 21st threshold region to the 11th threshold region or the 14th threshold region.

44. The memory system according to claim 43, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 22nd threshold region to the 12th threshold region or the 13th threshold region.

45. The memory system according to claim 44, The memory controller is configured to cause the non-volatile memory to be programmed in the second way, such that the non-volatile memory changes from the 23rd threshold region to the 15th threshold region or the 16th threshold region.

46. ​​The memory system according to claim 38, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 2, the number of boundaries with different values ​​of the second bit is 5, the number of boundaries with different values ​​of the third bit is 3, and the number of boundaries with different values ​​of the fourth bit is 5.

47. The memory system according to claim 38, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 4, the number of boundaries with different values ​​of the third bit is 5, and the number of boundaries with different values ​​of the fourth bit is 3.

48. The memory system according to any one of claims 1, 7, 14, 28, and 38. The memory controller is configured to input the first bit data, the second bit data, and the fourth bit data into the non-volatile memory when the non-volatile memory is programmed in the first manner.

49. The memory system according to claim 48, The memory controller is configured to input the third bit data and the fourth bit data into the non-volatile memory when the non-volatile memory is programmed in the second way.

50. The memory system according to any one of claims 1, 7, 14, 28, and 38. The first bit is the lowest bit below the lowest bit, the second bit is the next lowest bit in the middle bit, the third bit is the next highest bit above the highest bit, and the fourth bit is the first bit of the highest bit.

51. The memory system according to any one of claims 1, 7, 14, 28, and 38. The memory system includes a volatile first storage unit that stores data from the first bit to the fourth bit. Data of bits 1 to 4 stored in the first storage unit that are repeatedly input during the first programming and the second programming can be discarded or invalidated after the second programming begins, and data of other bits can be discarded or invalidated after the first programming begins.

52. The memory system according to any one of claims 1, 7, 14, 28, and 38, The memory system includes: A volatile first storage unit that stores data from the first bit to the fourth bit; and A non-volatile second storage unit stores data of the bits 1 through 4 that were repeatedly input during the first and second programming processes. The data in bits 1 through 4 stored in the first storage unit can be discarded or invalidated after the first programming begins. The data of the first to fourth bits stored in the second storage unit that are repeatedly input during the first programming and the second programming are stored in the second storage unit before the first programming begins, and can be discarded or invalidated after the second programming begins.

53. The memory system according to claim 52, The second storage unit is configured in units of word lines.

54. The memory system according to any one of claims 1, 7, 14, 28, and 38. The plurality of memory cells in the non-volatile memory include a plurality of first memory cells connected to a first word line and a plurality of second memory cells connected to a second word line adjacent to the first word line. After the memory controller performs the first programming on the plurality of first memory cells, it performs the first programming on the plurality of second memory cells, and then performs the second programming on the plurality of first memory cells.

55. The memory system according to any one of claims 1, 7, 14, 28, and 38. The non-volatile memory has at least a first word line and a second word line for connecting two or more of the memory cells respectively. The memory controller instructs the non-volatile memory to continuously perform the first programming for the memory cell connected to the first word line and the second programming for the memory cell connected to the second word line by continuous command and data input.

56. The memory system according to any one of claims 1, 7, 14, 28, and 38. The non-volatile memory includes a control unit that determines a threshold voltage for the data of the bit programmed in the second programming based on data obtained by reading data programmed through the first programming, data of the second bit repeatedly input in the first programming and the second programming, and input data of the third bit programmed in the second programming.

57. The memory system according to claim 56, The memory system includes an error correction unit that reads the data programmed through the first programming and performs error correction. The control unit determines the threshold voltage of the data of the bit being programmed in the second programming based on the data after error correction in the error correction unit, the data of the second bit, and the input data of the third bit.

58. A memory system comprising: Non-volatile semiconductor memory devices and controllers The non-volatile semiconductor memory device has: a first string to an nth string, each of the first string to the nth string having a plurality of memory cells, the plurality of memory cells being connected in series in such a way that they can store 4 bits of data by establishing a correspondence between the first bit to the fourth bit and 16 threshold regions including a first threshold region indicating an erased state and a second threshold region to a 16th threshold region indicating a write state where the voltage level is higher than the first threshold region. The plurality of memory cells include a first memory cell to a third memory cell. The first string to the nth string have a selection transistor connected in series with the plurality of memory cells, where n is an integer greater than or equal to 2. Bit lines, which are connected to the first to the nth strings; The first to nth selection gate lines, the kth selection gate line is connected to the gate of the kth string of selection transistors, where k is an integer greater than 1 and less than n; The first word line is connected to the gate of the first memory cell in the first string to the nth string; The second word line is connected to the gate of the second memory cell of the first to nth strings; as well as The third word line is connected to the gate of the third memory cell in the first to nth strings. The controller is configured to execute write processes 1 to n, and after executing write processes 1 to n, execute write processes (n+1) to 2n. The (i+1)th write operation is executed after the i-th write operation, where i is an integer greater than 1 and less than (n-1). The (j+1)th write operation is executed after the j-th write operation, where j is an integer greater than (n+1) and less than (2n-1). The k-th write process includes: writing data to the first storage unit of the k-th string based on the 1st, 2nd, and 4th bits, and writing data to the second storage unit of the k-th string based on the 3rd or 4th bit after writing to the first storage unit of the k-th string. The (n+k)th write process includes: writing data to the third storage unit of the k-th string based on the 1st, 2nd, and 4th bits, and writing data to the first storage unit of the k-th string based on at least one of the 3rd and 4th bits after writing to the third storage unit of the k-th string. The memory controller performs the write operation such that a threshold region in the memory cell becomes one of the following threshold regions: a 17th threshold region indicating an erased state (data has been erased) based on the data of the 1st bit, the data of the 2nd bit, and the data of the 4th bit; and an 18th threshold region to a pth threshold region indicating a write state (data has been written) with a higher voltage level than the 17th threshold region. Here, p is an integer greater than 21 and less than 24. The memory controller performs the write to the memory cell in such a way that a threshold region in the memory cell changes from one of the threshold regions from the 17th to the pth threshold regions to one of the two threshold regions from the 1st to the 16th threshold regions based on the data of at least one of the 3rd and 4th bits.

59. The memory system according to claim 58, The value of p is 24. In the (n+k)th write process, the data based on the 4th bit is written to the data in the 1st storage unit of the kth string. The data written to the storage cell is based on the third bit in such a way that a threshold region from the 17th threshold region to the pth threshold region becomes a threshold region from the 1st threshold region to the 16th threshold region.

60. The memory system according to claim 58, The value of p is 21, 22, or 23. In the (n+k)th write process, data based on the 3rd and 4th bits is written to the 1st storage unit of the kth string. The data written to the storage cell is based on the 3rd and 4th bits in such a way that a threshold region from the 17th threshold region to the pth threshold region becomes a threshold region from the 1st threshold region to the 16th threshold region.

61. The memory system according to any one of claims 58 to 60, The second storage unit of the k-th string is connected in series with the first storage unit of the k-th string, and the first storage unit of the k-th string is connected in series with the third storage unit of the k-th string.

62. The memory system according to claim 61, The memory controller is configured to, when writing data corresponding to the third bit to the memory cell, input data corresponding to the second bit and data corresponding to the third bit to the non-volatile memory.

63. The memory system according to any one of claims 58 to 60, The largest value among the 15 boundaries existing between adjacent threshold regions in the first to 16th threshold regions is 5, and the second largest value is 4.

64. The memory system according to any one of claims 58 to 60, The number of threshold regions between the threshold region with the lowest voltage level and the threshold region with the highest voltage level among the two threshold regions is no more than two.

65. The memory system according to claim 59, The memory controller performs the writing of data corresponding to the 1st, 2nd, and 4th bits to the 1st storage unit of the kth string and the writing of data corresponding to the 3rd bit to the 1st storage unit of the kth string in such that the number of boundaries with different values ​​of the 1st bit, the 2nd bit, the 3rd bit, and the 4th bit among the 15 boundaries existing between adjacent threshold regions in the 1st to 16th threshold regions are 1, 4, 5, 5 or 1, 5, 4, 5 or 3, 3, 4, 5 respectively.

66. The memory system according to any one of claims 58 to 60, The data writing to the first, second, and fourth bits of the first storage unit of the k-th string is performed in such a manner that the voltage level difference between two threshold regions in the 17th to 24th threshold regions where the value of the second bit of data is different is smaller than the voltage level difference between two threshold regions where the value of the first bit of data is different, and smaller than the voltage level difference between two threshold regions where the value of the fourth bit of data is different.

67. The memory system according to any one of claims 58 to 60, The first bit is the lowest bit below the lowest bit, the second bit is the next lowest bit in the middle bit, the third bit is the next highest bit above the highest bit, and the fourth bit is the first bit of the highest bit.

68. The memory system according to any one of claims 58 to 60, The number of the first boundary used to determine the value of the first bit of data, the number of the second boundary used to determine the value of the second bit of data, the number of the third boundary used to determine the value of the third bit of data, and the number of the fourth boundary used to determine the value of the fourth bit of data, which are among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region, are 3, 5, 2, and 5 respectively. The number of threshold regions between the threshold region with the lowest voltage level and the threshold region with the highest voltage level among the two threshold regions is no more than two.

69. A memory system comprising a non-volatile semiconductor memory device and a memory controller, The non-volatile semiconductor memory device has: The first to nth strings each have a plurality of storage cells. The plurality of storage cells are connected in series in a manner capable of storing 4 bits of data by establishing a correspondence between the first to fourth bits and 16 threshold regions, including a first threshold region indicating an erased state and a second to 16th threshold regions indicating a write state with a higher voltage level than the first threshold region. The plurality of storage cells include a first to a third storage cell. The first to nth strings have selection transistors connected in series with the plurality of storage cells, where n is an integer greater than 2. Bit lines, which are connected to the first to the nth strings; The first to nth selection gate lines, the kth selection gate line is connected to the gate of the kth string of selection transistors, where k is an integer greater than 1 and less than n; The first word line is connected to the gate of the first memory cell in the first string to the nth string; The second word line is connected to the gate of the second memory cell of the first to nth strings; as well as The third word line is connected to the gate of the third memory cell in the first to nth strings. The memory controller is configured to execute write operations from the first to the nth write operation, then execute write operations from (n+1) to the 2nth write operation after executing write operations from (n+1) to the 2nth write operation, then execute write operations from (2n+1) to the 3nth write operation, then execute write operations from (3n+1) to the 4nth write operation, and finally execute write operations from (3n+1) to the 4nth write operation, and then execute write operations from (4n+1) to the 5nth write operation. The (e+1)th write operation is executed after the e-th write operation, where e is an integer greater than 1 and less than (n-1). The (f+1)th write operation is executed after the f-th write operation, where f is an integer greater than (n+1) and less than (2n-1). The (g+1)th write operation is executed after the g-th write operation, where g is an integer greater than (2n+1) and less than (3n-1). The (h+1)th write operation is executed after the h-th write operation, where h is an integer greater than (3n+1) and less than (4n-1). The (i+1)th write operation is executed after the i-th write operation, where i is an integer greater than (4n+1) and less than (5n-1). The k-th write process includes writing data corresponding to the 1st, 2nd, and 4th bits into the 1st storage unit of the k-th string. The (n+k)th write process includes writing data corresponding to the 1st, 2nd, and 4th bits into the 2nd storage unit of the kth string. The (2n+k)th write process includes writing the data corresponding to the 3rd bit into the 1st storage unit of the kth string. The (3n+k)th write process includes writing data corresponding to the 1st, 2nd, and 4th bits into the 3rd storage unit of the kth string. The (4n+k)th write process includes writing the data corresponding to the third bit to the second storage unit of the kth string. The memory controller performs the writing of data corresponding to the 1st, 2nd, and 4th bits on the memory cell in such that a threshold region in the memory cell becomes a 17th threshold region indicating an erased state (data has been erased) and a 18th to 24th threshold region with a higher voltage level than the 17th threshold region indicating a written state (data has been written). The memory controller performs the write operation on the memory cell to the data corresponding to the third bit, such that a threshold region in the memory cell changes from one of the threshold regions from the 17th to the 24th threshold regions to one of the two threshold regions from the 1st to the 16th threshold regions based on the data of the third bit.

70. The memory system according to claim 69, The second storage unit of the k-th string is connected in series with the first storage unit of the k-th string, and the first storage unit of the k-th string is connected in series with the third storage unit of the k-th string.

71. The memory system according to claim 69, The memory controller is configured to, when writing data corresponding to the third bit to the memory cell, input data corresponding to the second bit and data corresponding to the third bit to the non-volatile memory.

72. The memory system according to claim 69, The largest value among the 15 boundaries existing between adjacent threshold regions in the first to 16th threshold regions is 5, and the second largest value is 4.

73. The memory system according to claim 69, The number of threshold regions between the threshold region with the lowest voltage level and the threshold region with the highest voltage level among the two threshold regions is no more than two.

74. The memory system according to claim 69, The memory controller performs the writing of data corresponding to the 1st, 2nd, and 4th bits to the 1st storage unit of the kth string and the writing of data corresponding to the 3rd bit to the 1st storage unit of the kth string in such that the number of boundaries with different values ​​of the 1st bit, the 2nd bit, the 3rd bit, and the 4th bit among the 15 boundaries existing between adjacent threshold regions in the 1st to 16th threshold regions are 1, 4, 5, 5 or 1, 5, 4, 5 or 3, 3, 4, 5 respectively.

75. The memory system according to claim 69, The writing of data corresponding to the 1st, 2nd, and 4th bits to the first storage unit of the k-string is performed in such a manner that the voltage level difference between two threshold regions in which the data of the 2nd bit in the 17th to 24th threshold regions has different values ​​is smaller than the voltage level difference between two threshold regions in which the data of the 1st bit in the 17th to 24th threshold regions has different values, and smaller than the voltage level difference between two threshold regions in which the data of the 4th bit in the 17th to 24th threshold regions has different values.

76. The memory system according to claim 69, The first bit is the lowest bit below the lowest bit, the second bit is the next lowest bit in the middle bit, the third bit is the next highest bit above the highest bit, and the fourth bit is the first bit of the highest bit.

77. The memory system according to claim 69, The memory controller instructs the non-volatile memory to write data corresponding to the first, second, and fourth bits to the first storage unit of the k-string, and to write data corresponding to the third bit to the first storage unit of the k-string, through continuous commands and data input.

78. The memory system according to claim 69, The non-volatile memory includes a control unit that determines a threshold voltage for the data corresponding to the third bit in the first storage cell of the k-string based on data obtained by reading data written to the first storage cell of the k-string by writing data corresponding to the first, second, and fourth bits, data corresponding to the second bit that is repeatedly input by writing data corresponding to the first, second, and fourth bits in the first storage cell of the k-string and writing data corresponding to the third bit in the first storage cell of the k-string, and input data corresponding to the third bit for writing data corresponding to the third bit in the first storage cell of the k-string.

79. The memory system according to claim 78, The memory controller reads the data written by writing data corresponding to the first, second, and fourth bits to the first storage unit of the k-string and performs error correction on the read data. The control unit determines the threshold voltage of the data corresponding to the bit written by writing the data corresponding to the third bit to the first storage cell of the k-string based on the read data after the error correction has been performed, the data corresponding to the second bit, and the input data corresponding to the third bit.

80. The memory system according to claim 69, The number of first boundaries used to determine the value of the first bit of data, the number of second boundaries used to determine the value of the second bit of data, the number of third boundaries used to determine the value of the third bit of data, and the number of fourth boundaries used to determine the value of the fourth bit of data, among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region, are 3, 5, 2, and 5, respectively. In the writing of the data corresponding to the third bit, the number of threshold regions between the threshold region with the minimum voltage level and the threshold region with the maximum voltage level in the two threshold regions is 2 or less.

81. A memory system comprising: A non-volatile memory having multiple memory cells, each of which can store 4 bits of data represented by bits 1 through 4 using 16 threshold regions, the 16 threshold regions including a first threshold region indicating an erased state, and second to 16th threshold regions indicating a write state with a higher voltage level than the first threshold region; and A memory controller, after performing a first programming operation by writing data to the non-volatile memory based on the data of the first bit, the data of the second bit, and the data of the fourth bit, performs a second programming operation by writing data to the non-volatile memory based on the data of at least one of the third bit and the fourth bit. The non-volatile memory has a first word line and a second word line. The plurality of memory cells within the non-volatile memory include a plurality of first memory cells connected to the first word line and a plurality of second memory cells connected to the second word line. One of the plurality of first memories is connected in series with one of the plurality of second memory cells. After the memory controller performs the first programming on the plurality of first memory cells, it performs the first programming on the plurality of second memory cells, and after the memory controller performs the first programming on the plurality of second memory cells, it performs the second programming on the plurality of first memory cells.

82. The memory system according to claim 81, The first programming includes setting a threshold region in the storage cell to a 17th threshold region indicating an erased state (data has been erased), and a 18th to pth threshold region indicating a write state (data has been written) with a higher voltage level than the 17th threshold region. Here, p is an integer greater than 22 and less than 24. The second programming includes changing a threshold region in the storage cell from a threshold region from the 17th threshold region to the p threshold region to a threshold region from the 1st threshold region to the 16th threshold region.

83. The memory system according to claim 1 or claim 82, The first bit is the lowest bit below the lowest bit, the second bit is the next lowest bit in the middle bit, the third bit is the next highest bit above the highest bit, and the fourth bit is the first bit of the highest bit.

84. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 1, the number of boundaries with different values ​​of the second bit is 5, the number of boundaries with different values ​​of the third bit is 4, and the number of boundaries with different values ​​of the fourth bit is 5.

85. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 5, the number of boundaries with different values ​​of the third bit is 2, and the number of boundaries with different values ​​of the fourth bit is 5.

86. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 3, the number of boundaries with different values ​​of the third bit is 4, and the number of boundaries with different values ​​of the fourth bit is 5.

87. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 2, the number of boundaries with different values ​​of the second bit is 3, the number of boundaries with different values ​​of the third bit is 5, and the number of boundaries with different values ​​of the fourth bit is 5.

88. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 2, the number of boundaries with different values ​​of the third bit is 5, and the number of boundaries with different values ​​of the fourth bit is 5.

89. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 4, the number of boundaries with different values ​​of the third bit is 4, and the number of boundaries with different values ​​of the fourth bit is 4.

90. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 1, the number of boundaries with different values ​​of the second bit is 4, the number of boundaries with different values ​​of the third bit is 5, and the number of boundaries with different values ​​of the fourth bit is 5.

91. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 2, the number of boundaries with different values ​​of the second bit is 5, the number of boundaries with different values ​​of the third bit is 3, and the number of boundaries with different values ​​of the fourth bit is 5.

92. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 4, the number of boundaries with different values ​​of the third bit is 5, and the number of boundaries with different values ​​of the fourth bit is 3.

93. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 1, the number of boundaries with different values ​​of the second bit is 5, the number of boundaries with different values ​​of the third bit is 5, and the number of boundaries with different values ​​of the fourth bit is 4.

94. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 1, the number of boundaries with different values ​​of the second bit is 5, the number of boundaries with different values ​​of the third bit is 3, and the number of boundaries with different values ​​of the fourth bit is 6.

95. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 1, the number of boundaries with different values ​​of the second bit is 3, the number of boundaries with different values ​​of the third bit is 6, and the number of boundaries with different values ​​of the fourth bit is 5.

96. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 1, the number of boundaries with different values ​​of the second bit is 2, the number of boundaries with different values ​​of the third bit is 6, and the number of boundaries with different values ​​of the fourth bit is 6.

97. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 1, the number of boundaries with different values ​​of the second bit is 4, the number of boundaries with different values ​​of the third bit is 6, and the number of boundaries with different values ​​of the fourth bit is 4.

98. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 1, the number of boundaries with different values ​​of the second bit is 4, the number of boundaries with different values ​​of the third bit is 4, and the number of boundaries with different values ​​of the fourth bit is 6.

99. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 2, the number of boundaries with different values ​​of the second bit is 5, the number of boundaries with different values ​​of the third bit is 2, and the number of boundaries with different values ​​of the fourth bit is 6.

100. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 2, the number of boundaries with different values ​​of the second bit is 3, the number of boundaries with different values ​​of the third bit is 3, and the number of boundaries with different values ​​of the fourth bit is 6.

101. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 3, the number of boundaries with different values ​​of the third bit is 6, and the number of boundaries with different values ​​of the fourth bit is 3.

102. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 2, the number of boundaries with different values ​​of the second bit is 3, the number of boundaries with different values ​​of the third bit is 4, and the number of boundaries with different values ​​of the fourth bit is 6.

103. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 4, the number of boundaries with different values ​​of the third bit is 2, and the number of boundaries with different values ​​of the fourth bit is 6.

104. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 2, the number of boundaries with different values ​​of the third bit is 6, and the number of boundaries with different values ​​of the fourth bit is 4.

105. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 2, the number of boundaries with different values ​​of the third bit is 4, and the number of boundaries with different values ​​of the fourth bit is 6.

106. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 5, the number of boundaries with different values ​​of the second bit is 3, the number of boundaries with different values ​​of the third bit is 2, and the number of boundaries with different values ​​of the fourth bit is 5.

107. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 5, the number of boundaries with different values ​​of the second bit is 4, the number of boundaries with different values ​​of the third bit is 2, and the number of boundaries with different values ​​of the fourth bit is 4.

108. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 4, the number of boundaries with different values ​​of the second bit is 5, the number of boundaries with different values ​​of the third bit is 2, and the number of boundaries with different values ​​of the fourth bit is 4.

109. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 2, the number of boundaries with different values ​​of the second bit is 4, the number of boundaries with different values ​​of the third bit is 5, and the number of boundaries with different values ​​of the fourth bit is 4.

110. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 2, the number of boundaries with different values ​​of the second bit is 5, the number of boundaries with different values ​​of the third bit is 4, and the number of boundaries with different values ​​of the fourth bit is 4.

111. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 5, the number of boundaries with different values ​​of the third bit is 4, and the number of boundaries with different values ​​of the fourth bit is 3.

112. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 5, the number of boundaries with different values ​​of the third bit is 3, and the number of boundaries with different values ​​of the fourth bit is 4.

113. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 4, the number of boundaries with different values ​​of the third bit is 3, and the number of boundaries with different values ​​of the fourth bit is 5.

114. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 3, the number of boundaries with different values ​​of the second bit is 3, the number of boundaries with different values ​​of the third bit is 5, and the number of boundaries with different values ​​of the fourth bit is 4.

115. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 4, the number of boundaries with different values ​​of the second bit is 5, the number of boundaries with different values ​​of the third bit is 3, and the number of boundaries with different values ​​of the fourth bit is 3.

116. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 4, the number of boundaries with different values ​​of the second bit is 3, the number of boundaries with different values ​​of the third bit is 4, and the number of boundaries with different values ​​of the fourth bit is 4.

117. The memory system according to claim 83, The memory controller enables the non-volatile memory to perform the first programming and the second programming in such a manner that the number of boundaries with different values ​​of the first bit among the 15 boundaries existing between adjacent threshold regions in the first threshold region to the 16th threshold region is 4, the number of boundaries with different values ​​of the second bit is 4, the number of boundaries with different values ​​of the third bit is 3, and the number of boundaries with different values ​​of the fourth bit is 4.

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