Ring table updating method and module, backend device, medium, device, chip

Abstract

The application relates to a used ring updating method and module, a backend device, a medium, a device and a chip, and comprises the following steps: when receiving packet updating information of any queue, storing the packet updating information into a storage unit; if the number of the packet updating information of the queue in the storage unit is equal to n, generating a first write request and a second write request according to the n packet updating information, and sequentially sending the first write request and the second write request to a DMA processing module, so that the DMA processing module writes pointer values and data packet lengths of the n packet updating information into the used ring table according to the first write request, and writes the index of the last received packet updating information in the n packet updating information into the used ring table according to the second write request. According to the application, the data packet receiving speed is improved.

Description

Technical Field

[0001] This application relates to the field of cloud computing virtualization technology, specifically to a used ring table update method and module, backend device, computer-readable storage medium, electronic device, and chip. Background Technology

[0002] In cloud computing virtualization technology, in order to allow multiple Guest OSs to run independently of the Host OS on the same hardware, a virtualization layer is usually added, which is called VMM (Virtual Machine Monitor).

[0003] QEMU (Machine Emulator and Virtualizer), as a VMM, provides a fully virtualized environment. In a fully virtualized environment, the guest operating system is unaware that it is a virtual machine and does not require modification. However, because all operations require front-end driver emulation, frequent traps / outs during device access cause serious performance problems. To address this, the paravirtualization technology VIRTIO (Virtual I / O Device) was developed.

[0004] VIRTIO is a general-purpose paravirtualized I / O framework that the Virtual Machine emulates a series of virtualized devices. The VIRTIO framework mainly consists of three parts: the front-end driver, the back-end device, and the virtualization queue. The front-end driver is the driver for the VIRTIO emulated devices inside the virtual machine (such as common VIRTIO network devices and VIRTIO disk devices). The front-end driver receives user-mode requests, encapsulates these requests according to a preset protocol, and sends them to the back-end device. The back-end device is usually implemented in QEMU. It receives and parses I / O requests from the front-end driver, completes the send and receive operations on the actual physical device, and finally notifies the front-end driver via an interrupt mechanism. Data exchange between the front-end driver and the back-end device occurs through the Virtqueue.

[0005] According to the VIRTIO specification, a Virtqueue contains a Descriptor Table, an Available Ring, and a Used Ring. The Descriptor Table stores information such as the data buffer address, length, flags, and next-hop pointer. The Available Ring and Used Ring contain pointers to entries in the Descriptor Table. When receiving a data packet, the front-end driver fills the allocated buffer address and length information into the Descriptor Table entry, stores the pointer value of the Descriptor Table entry in the position pointed to by the current index in the Available Ring, and updates the index. The front-end driver then notifies the back-end device to send the data packet.

[0006] When a backend device receives a data packet, it reads the pointer value in the available ring table, then reads the information from the descriptor table entry based on that pointer value. It determines the buffer address and length for storing the data packet based on the descriptor table entry information, stores the data packet in the buffer address, and updates the contents of the available ring table (including the pointer value and data packet length) and its index. This notifies the frontend driver how many packets the current device has sent to the host. Furthermore, it reads the MSI-X interrupt table, initiates an interrupt, and notifies the frontend driver that a data packet has been received. Therefore, receiving a data packet requires at least four write requests: writing to the data packet buffer, writing to the used ring table, writing to the used ring table index, and writing to the interrupt. When the number of received data packets is large, the write request bandwidth becomes a bottleneck, affecting the data packet reception rate. Taking a small 64-byte packet as an example, assuming a system clock frequency of 1GHz, receiving one packet requires four clock cycles of write requests. Ideally, the maximum packet rate is 1 / 4 = 250 Mpps. Summary of the Invention

[0007] The purpose of this application is to provide a method and module for updating ring tables, a backend device, a computer-readable storage medium, an electronic device, and a chip to improve the data packet sending rate.

[0008] To achieve the above objectives, embodiments of this application provide a method for updating a used ring table, the method comprising:

[0009] When packet update information is received from any queue, the packet update information is stored in the storage unit; the packet update information includes a pointer value, data packet length, and index;

[0010] Determine whether the number of packet update information entries in the queue of the storage unit is equal to n. If so, read n packet update information entries from the queue of the storage unit; wherein, when the n packet update information entries are read, the n packet update information entries are deleted from the storage unit.

[0011] A first write request and a second write request are generated based on the n packet update information, and the first write request and the second write request are sent to the DMA processing module in sequence, so that the DMA processing module writes the pointer value and data packet length of the n packet update information into the used ring table according to the first write request, and writes the index of the last received packet update information among the n packet update information into the used ring table according to the second write request.

[0012] The first write request includes pointer values ​​and data packet lengths for the n packet update information, and the second write request includes the index of the last received packet update information among the n packet update information, where n is greater than or equal to 2.

[0013] This application provides a used ring table update module, including:

[0014] A storage unit is used to store packet update information when packet update information is received from any queue; the packet update information includes a pointer value, a data packet length, and an index.

[0015] The control unit is used to determine whether the number of packet update information in the queue in the storage unit is equal to n. If so, it reads n packet update information from the queue from the storage unit. When the n packet update information is read, the n packet update information is deleted from the storage unit.

[0016] A write request generation unit is used to generate a first write request and a second write request based on the n packet update information, and send the first write request and the second write request to the DMA processing module in sequence, so that the DMA processing module writes the pointer value and data packet length of the n packet update information into the used ring table according to the first write request, and writes the index of the last received packet update information among the n packet update information into the used ring table according to the second write request.

[0017] The first write request includes pointer values ​​and data packet lengths for the n packet update information, and the second write request includes the index of the last received packet update information among the n packet update information, where n is greater than or equal to 2.

[0018] This application also provides a VIRTIO backend device, including the used ring table update module as described above.

[0019] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the used ring table update method as described above.

[0020] This application also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the used ring table update method as described above.

[0021] This application provides a chip that includes the VIRTIO back-end device described above.

[0022] This application provides a method and module for updating a used ring table, a VIRTIO backend device, a computer-readable storage medium, an electronic device, and a chip. Traditional methods, when updating a used ring table, initiate two write requests for each received packet update information. These two write requests are used to write the pointer value, data packet length, and index of the packet update information into the available ring table, respectively. Therefore, for n packet update information, 2^n write requests (n > 1) are required. In contrast to the traditional method, this application, when updating the used ring table, initiates two write requests based on n packet update information, provided the system data bandwidth allows. One write request writes the pointer value and data packet length of the n packet update information into the available ring table, and the other writes the index into the available ring table. Compared to the traditional method requiring 2^n write requests, this application only requires two write requests to complete the update of the used ring table, reducing the number of write requests, fully utilizing system data bandwidth, and enabling the processing of n packet update information at once, greatly improving the efficiency of the used ring table update and thus increasing the packet reception rate. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings required in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a flowchart of a used ring table update method in one embodiment of this application.

[0025] Figure 2 This is a schematic diagram of the packet receiving process of a VIRTIO network device in one embodiment of this application.

[0026] Figure 3 This is a schematic diagram illustrating the principle of the ring table update module in the traditional method.

[0027] Figure 4 This is a schematic diagram illustrating the principle of a ring table update module available in one embodiment of this application.

[0028] Figure 5This is a schematic diagram of a used ring table update module in one embodiment of this application. Detailed Implementation

[0029] The detailed description of the accompanying drawings is intended to illustrate the present preferred embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functions can be achieved by different embodiments intended to be included within the spirit and scope of this application.

[0030] See Figure 1 One embodiment of this application provides a used ring table update method, which is implemented based on a used ring table update module.

[0031] like Figure 2 As shown, the packet sending process of VIRTIO network devices includes the VIRTIO front-end driver execution process and the back-end device execution process;

[0032] The VIRTIO front-end driver execution flow includes:

[0033] The first step is for the driver to prepare the buffer for receiving data packets. These data packet buffers are usually divided into two parts: one part contains 12 bytes of VIRITO network device header content; the other part contains 1522 bytes of received network data packet content. If the VIRITO MERGAEGBLE feature is successfully negotiated, the VIRITO header and data packet content will be put together and a 4096-byte buffer will be allocated.

[0034] The second step is to fill the address and length of the cache allocated in the first step into the descriptor table. For data packets that require multiple caches to occupy multiple descriptors, these descriptors are chained together through the next hop, and one chain corresponds to one network data packet.

[0035] The third step is to fill the address of the first link of the descriptor table into the position pointed to by the current index of the available ring table, and at the same time update the index value (index value + 1);

[0036] The fourth step is to write to the notification register (Notify) to notify the backend device that the cache is ready to receive the data.

[0037] It should be noted that steps one through four above are all completed in the VIRITO front-end driver.

[0038] The VIRTIO backend device execution process includes:

[0039] After receiving the Notify notification, the VIRTIO backend device performs the following steps:

[0040] The fifth step is that the descriptor table prefetching module reads the pointer values ​​in the available ring table based on the index in the available ring table, and uses these pointer values ​​to read the relevant contents in the descriptor table. This step is usually called descriptor prefetching. The specific implementation is completed by the descriptor table prefetching module. Prefetching means that the descriptor is read before the data packet is received. After the data packet is received, the previously prefetched descriptor can be used directly, which can reduce the data packet reception latency.

[0041] When a data packet received from the Ethernet packet interface module is received on the link, the descriptor prefetched in step 5 is used to send the data packet to the cache address pointed to by the descriptor for storage. At the same time, the contents of the address pointed to by the current index of the used ring table are updated (4-byte pointer + 4-byte length).

[0042] The sixth step is for the data packet update module to write the received data packets into the data packet cache, and the cache address is indicated by the corresponding descriptor content;

[0043] Step 7: The used ring table update module updates the contents of the used ring table and notifies the front-end driver how many packets the current device has sent to the host;

[0044] Step 8: The MSI-X interrupt module reads the MSI-X interrupt table, initiates an interrupt, and notifies the front-end driver that a network data packet has been received.

[0045] The method in this embodiment mainly involves the content of step seven above, see below. Figure 1 The method in this embodiment includes the following steps:

[0046] Step S10: When packet update information is received from any queue (Virtqueue), the packet update information is stored in the storage unit; the packet update information includes a pointer value, data packet length, and index;

[0047] Specifically, the packet update information includes queue information, which determines which queue the packet update information belongs to; the packet update information refers to data packet update information, and the used ring table records the cached addresses that have been used, such as... Figure 2 As shown, both the available ring table and the used ring table include a flag unit, an index unit, and a pointer unit. The index unit stores an index value, which indicates a currently available pointer unit. The pointer unit stores a pointer value, which indicates an address in the descriptor table. Each address in the descriptor table stores a descriptor table entry, such as... Figure 2Each row of the descriptor table shown is a descriptor table entry. Each descriptor table entry includes a cache address (used to store data packets), a cache length (cache resources pre-allocated to data packets), a flag (indicating whether there is a next hop), and a next hop (next hop pointer value). That is, the pointer values ​​stored in the available ring table and the used ring table correspond one-to-one with the descriptor table entries in the descriptor table. The corresponding descriptor table entry can be found based on the pointer values ​​stored in the available ring table and the used ring table. Based on the descriptor table entry, the corresponding cache address, cache length, flag, next hop, and other information can be obtained. The cache length pre-allocated to data packets recorded in the descriptor table may be different from the data packet length. The data packet length is the actual length of the data packet, and the cache length allocated to the data packet is greater than or equal to the data packet length.

[0048] After the data packet is stored in the corresponding cache address, the used ring table needs to be updated. Suppose the data packet Pac1 is stored in the cache address adr1, and the descriptor table entry corresponding to the pointer value 1 stores the cache address adr1. The index of the used ring table needs to be updated to index 3. At this time, a packet update information 1 will be received from the data packet update module. The packet update information 1 includes the pointer value 1, the length of the data packet Pac1, and the index 3.

[0049] Step S20: Determine whether the number of packet update information in the queue in the storage unit is equal to n. If so, read n packet update information from the queue in the storage unit; wherein, when the n packet update information is read, the n packet update information is deleted from the storage unit.

[0050] Step S30: Generate a first write request and a second write request based on the n packet update information, and send the first write request and the second write request to the DMA processing module in sequence, so that the DMA processing module writes the pointer value and data packet length of the n packet update information into the used ring table according to the first write request, and writes the index of the last received packet update information among the n packet update information into the used ring table according to the second write request.

[0051] Wherein, the first write request and the second write request are in PCIe TLP DMA format, the first write request includes pointer values ​​of the n packet update information and data packet length, and the second write request includes the index of the last received packet update information among the n packet update information, where n is greater than or equal to 2;

[0052] Specifically, such as Figure 3 The diagram illustrates the traditional method for updating a used ring table. Figure 3In the process, the front-end module (packet update module) sequentially sends three packet update messages (packet 1, packet 2, and packet 3) to the used ring table update module. The used ring table update module then initiates write requests for packet 1 (pointer + length), packet 1 (index), packet 2 (pointer + length), packet 2 (index), and packet 3 (pointer + length) and packet 3 (index) respectively. This means that six write requests are required for these three packet update messages, and each write request involves a relatively small number of bytes. Writing "pointer + length" takes 8 bytes, and writing the index takes 2 bytes. However, the system PCIe bandwidth is far greater than 8 bytes, resulting in significant waste of system PCIe bandwidth. To address this, since these write requests are consecutive within the same queue, they can be merged. The optimized principle for write request merging is as follows: Figure 4 As shown, the used ring table update module no longer immediately issues an update write request for a packet upon receiving update information. Instead, it waits until multiple packet update information is gathered before initiating a write request to the used ring table. For example, previously, upon receiving packet 1, two DMA write requests were immediately issued, with the write pointer + length being 8 bytes and the write index being 2 bytes. After optimization, assuming a system bandwidth of 64 bytes, let n equal 8. After collecting 8 packet update information, these 8 packet information are concatenated together and sent as a single DMA write request (8 bytes * 8 = 64 bytes). Finally, a write request is initiated to notify the software that the current index has been updated to 8. Through this optimization, for every 8 packets, previously 16 write requests were required, occupying 16 cycles of PCIe bandwidth. Using the method in this embodiment, only 2 write requests are required, occupying 2 cycles of PCIe bandwidth, resulting in a significant optimization effect.

[0053] The DMA processing module is used to perform DMA (Direct Memory Access) processing on data. DMA processing is a computer technology that allows external devices to directly access computer memory without the intervention of the central processing unit, which can greatly improve the efficiency of data transmission.

[0054] The following analysis examines the benefits of the optimizations made in this embodiment. Using a 64-byte packet as an example, and assuming a system clock speed of 1GHz, we obtain the following table:

[0055] Table 1 Optimization Benefits Table

[0056] No optimization Optimization (aggregation granularity of 8) bandwidth Mpps 1000 / (1+1+1+1)＝250 1000 / (1+0.125+1+1)＝320 Bandwidth increase % 1 (320-250) / 250＝28

[0057] As shown in Table 1, when the convergence degree n is 8, the bandwidth performance can be improved by 28%, which is quite remarkable.

[0058] In summary, the method in this embodiment can reduce the number of PCIe write requests, make full use of system data bandwidth, process n packet update information at once, greatly improve the efficiency of used ring table updates, and thus improve the packet reception rate.

[0059] In some embodiments, step S20 further includes:

[0060] In real time, it is determined whether the time difference between the initial packet reception time of any queue and the current time is equal to a preset threshold. If so, all packet update information of that queue is read from the storage unit. The initial packet reception time of any queue is the reception time of the earliest received packet update information of that queue stored in the storage unit.

[0061] Step S30 further includes:

[0062] Based on all the packet update information, a third write request and a fourth write request are generated, and the third write request and the fourth write request are sent sequentially to the DMA processing module, so that the DMA processing module writes the pointer value and data packet length of all the packet update information into the used ring table according to the third write request, and writes the index of the last received packet update information among all the packet update information into the used ring table according to the fourth write request.

[0063] The third write request includes pointer values ​​and data packet lengths for all packet update information, and the fourth write request includes the index of the last received packet update information among all packet update information.

[0064] Specifically, in practical applications, there may be instances where a certain queue fails to accumulate the required number of packets for aggregation granularity, meaning the number of received packet update information is less than n. To address this situation, this embodiment monitors the initial packet reception time of each queue in real time and compares it with the current time. If the time difference between the initial packet reception time and the current time equals a preset threshold, then even if the aggregation granularity is insufficient, all packet update information for that particular queue is read from the storage unit. Based on all the packet update information, the corresponding third and fourth write requests are output to the DMA processing module to perform write operations on the used ring table to update it, thereby avoiding packet congestion issues.

[0065] In some embodiments, the storage unit is a linked list storage structure;

[0066] Step S10 specifically includes:

[0067] When a packet update message is received from any queue, it is determined whether a linked list corresponding to that queue exists in the linked list storage structure. The linked list includes a head unit, a tail unit, a timestamp unit, multiple data units, and multiple pointer units corresponding to each data unit. The head unit stores the address of the data unit for the first packet update message of that queue, the tail unit stores the address of the data unit for the last packet update message of that queue, the timestamp unit stores the initial packet reception time, the data units store the packet update message of that queue, and the pointer units store the address of the data unit for the next packet update message of that queue.

[0068] If no linked list exists corresponding to any of the queues, then a linked list corresponding to any of the queues is created, and the update information of the packet is stored in the linked list.

[0069] If a linked list exists corresponding to any of the queues, then the update information for that packet is stored in that linked list.

[0070] Specifically, this embodiment uses a linked list structure to store the packet update information of the queues. Each queue corresponds to a linked list, and the packet update information of different queues will enter different linked lists and record the corresponding initial packet reception time. In this way, although the incoming packets may be interleaved according to the queues, they are aggregated using linked lists. When a queue has accumulated n packets, these n packets are aggregated and concatenated to generate a corresponding write request and output to the DMA processing module. Alternatively, when the difference between the initial packet reception time of the queue and the current time is equal to a preset threshold, a corresponding write request is generated based on all the packet update information of the queue and output to the DMA processing module.

[0071] In some embodiments, the method further includes:

[0072] Step S40: After reading all the package update information of any linked list, clear the contents stored in the head unit, tail unit, timestamp unit, multiple data units, and multiple pointer units of that linked list.

[0073] Specifically, in this embodiment, the linked lists of different queues share the same cache space. In order to improve the resource utilization of the cache space, after writing all the packet update information of the linked list into the used ring list, it is not necessary to cache all the packet update information again. Therefore, the contents stored in the head unit, tail unit, timestamp unit, multiple data units, and multiple pointer units of the linked list are cleared. When new packet update information is received, the contents stored in the head unit, tail unit, timestamp unit, multiple data units, and multiple pointer units are updated again.

[0074] In some embodiments, the method further includes:

[0075] After reading all packet update information of any linked list, if no new packet update information is received from the queue corresponding to the linked list within a preset time, the linked list is deleted.

[0076] Specifically, if no new packet update information is received from the queue corresponding to the linked list within a preset time, the linked list remains empty. Therefore, the linked list is deleted, and cache resources are reclaimed to facilitate the storage and use of packet update information from other queues.

[0077] In some embodiments, the method is implemented based on a used ring table update module, and the length of the first write request is equal to the PCIE bandwidth of the system where the used ring table update module is located.

[0078] Specifically, assuming the system bandwidth is 64 bytes, let n equal 8. After collecting 8 packet update information, concatenate these 8 packet information together and send out a DMA write request of 8 bytes * 8 = 64 bytes.

[0079] Corresponding to the used ring table update method described in the above embodiments, see [link to relevant documentation]. Figure 5 Another embodiment of this application also provides a used ring table update module, including:

[0080] A storage unit is used to store packet update information when packet update information is received from any queue; the packet update information includes a pointer value, a data packet length, and an index.

[0081] The control unit is used to determine whether the number of packet update information in the queue in the storage unit is equal to n. If so, it reads n packet update information from the queue from the storage unit. When the n packet update information is read, the n packet update information is deleted from the storage unit.

[0082] A write request generation unit is used to generate a first write request and a second write request based on the n packet update information, and send the first write request and the second write request to the DMA processing module in sequence, so that the DMA processing module writes the pointer value and data packet length of the n packet update information into the used ring table according to the first write request, and writes the index of the last received packet update information among the n packet update information into the used ring table according to the second write request.

[0083] The first write request includes pointer values ​​and data packet lengths for the n packet update information, and the second write request includes the index of the last received packet update information among the n packet update information, where n is greater than or equal to 2.

[0084] In some embodiments, the control unit is further configured to determine whether the time difference between the initial packet reception time of any queue and the current time is equal to a preset threshold; if so, it reads all packet update information of the queue from the storage unit; the initial packet reception time of the queue is the reception time of the earliest received packet update information of the queue stored in the storage unit.

[0085] The write request generation unit is further configured to generate a third write request and a fourth write request based on all packet update information, and send the third write request and the fourth write request to the DMA processing module in sequence, so that the DMA processing module writes the pointer value and data packet length of all packet update information into the used ring table according to the third write request, and writes the index of the last received packet update information among all packet update information into the used ring table according to the fourth write request;

[0086] The third write request includes pointer values ​​and data packet lengths for all packet update information, and the fourth write request includes the index of the last received packet update information among all packet update information.

[0087] In some embodiments, the storage unit is a linked list storage structure;

[0088] The storage unit is further configured to determine whether a linked list corresponding to any queue exists in the linked list storage structure when a packet update information of any queue is received; wherein, the linked list includes a head unit, a tail unit, a timestamp unit, multiple data units, and multiple pointer units corresponding one-to-one with the multiple data units. The head unit is used to store the data unit address of the first packet update information of any queue, the tail unit is used to store the data unit address of the last packet update information of any queue, the timestamp unit is used to store the initial packet reception time, the data units are used to store the packet update information of any queue, and the pointer units are used to store the data unit address of the next packet update information of any queue.

[0089] If no linked list exists corresponding to any of the queues, the storage unit creates a linked list corresponding to the queue and stores the packet update information in the linked list.

[0090] If a linked list exists corresponding to any of the queues, the storage unit stores the packet update information into that linked list.

[0091] In some embodiments, the storage unit is further configured to clear the contents stored in the head unit, tail unit, timestamp unit, multiple data units, and multiple pointer units of any linked list after reading all the package update information of any linked list.

[0092] In some embodiments, the storage unit is further configured to delete the linked list if, after reading all packet update information of any linked list, no new packet update information is received from the queue corresponding to the linked list within a preset time.

[0093] In some embodiments, the length of the first write request is equal to the PCIE bandwidth of the system where the used ring table update module is located.

[0094] It should be noted that the used ring table update module described in this embodiment corresponds to the used ring table update method described in the above embodiments. The function implemented by the used ring table update module described in this embodiment has been described in detail in the methods of the above embodiments, so it will not be repeated in this embodiment.

[0095] The used ring table update module of the embodiments described above is merely illustrative. The modules described as separate components may or may not be physically separate. The components of a module may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the used ring table update module scheme of the embodiments, depending on actual needs.

[0096] Another embodiment of this application provides a VIRTIO backend device, including the used ring table update module described in the above embodiments.

[0097] Another embodiment of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the used ring table update method as described in the above embodiments.

[0098] Specifically, the computer-readable storage medium may include any entity or recording medium capable of carrying the computer program instructions, such as a USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and front-end drive distribution media.

[0099] Another embodiment of this application provides an electronic device including a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the used ring table update method described in the above embodiments.

[0100] The electronic device may also include a bus connecting different components, including memory and processor. The memory may include a computer-readable medium in the form of volatile memory, such as random access memory (RAM) and / or cache memory. The memory may also include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of this application. The electronic device may also communicate with one or more external devices (e.g., keyboard, pointing device, display, etc.), and with one or more devices that enable a user to interact with the electronic device, and / or with any device (e.g., a network interface card) that enables the electronic device to communicate with one or more other computing devices, such communication may be performed via an input / output (I / O) interface, and the electronic device may also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via a network adapter.

[0101] Another embodiment of this application provides a chip that includes the VIRTIO back-end device described in the above embodiments.

[0102] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for updating a used ring table, characterized in that, The method includes: When packet update information is received from any queue, the packet update information is stored in a linked list corresponding to the queue in the storage unit. The packet update information includes a pointer value, packet length, and index. The linked list includes a head unit, a tail unit, a timestamp unit, multiple data units, and multiple pointer units corresponding one-to-one with the multiple data units. The head unit stores the data unit address of the first packet update information of the queue, the tail unit stores the data unit address of the last packet update information of the queue, the timestamp unit stores the initial packet reception time, the data units store the packet update information of the queue, and the pointer units store the data unit address of the next packet update information of the queue. Based on the linked list, determine whether the number of packet update information entries in the queue of the storage unit is equal to n. If so, read n packet update information entries from the queue of the storage unit based on the linked list. A first write request and a second write request are generated based on the n packet update information, and the first write request and the second write request are sent to the DMA processing module in sequence, so that the DMA processing module writes the pointer value and data packet length of the n packet update information into the used ring table according to the first write request, and writes the index of the last received packet update information among the n packet update information into the used ring table according to the second write request. The first write request includes pointer values ​​and data packet lengths for the n packet update information, and the second write request includes the index of the last received packet update information among the n packet update information, where n is greater than or equal to 2.

2. The method according to claim 1, characterized in that, The method includes: Determine whether the time difference between the initial packet reception time of any queue and the current time is equal to a preset threshold. If so, read all packet update information of that queue from the storage unit. The initial packet reception time of any queue is the reception time of the earliest received packet update information of that queue stored in the storage unit. A third write request and a fourth write request are generated based on all the packet update information, and the third write request and the fourth write request are sent to the DMA processing module in sequence, so that the DMA processing module writes the pointer value and data packet length of all the packet update information into the used ring table according to the third write request, and writes the index of the last received packet update information in all the packet update information into the used ring table according to the fourth write request. The third write request includes pointer values ​​and data packet lengths for all packet update information, and the fourth write request includes the index of the last received packet update information among all packet update information.

3. The method according to claim 2, characterized in that, The storage unit is a linked list storage structure; The method further includes: When a packet update message is received from any queue, it is determined whether a linked list corresponding to that queue exists in the linked list storage structure; If no linked list exists corresponding to any of the queues, then a linked list corresponding to any of the queues is created, and the update information of the packet is stored in the linked list. If a linked list exists corresponding to any of the queues, then the update information for that packet is stored in that linked list.

4. The method according to claim 3, characterized in that, The method further includes: After reading all the package update information of any linked list, clear the contents stored in the head unit, tail unit, timestamp unit, multiple data units, and multiple pointer units of that linked list.

5. The method according to claim 4, characterized in that, The method further includes: After reading all packet update information of any linked list, if no new packet update information is received from the queue corresponding to the linked list within a preset time, the linked list is deleted.

6. The method according to any one of claims 1 to 5, characterized in that, The method is implemented based on the used ring table update module, and the length of the first write request is equal to the PCIE bandwidth of the system where the used ring table update module is located.

7. A used ring table update module, characterized in that, include: A storage unit is used to store the packet update information to the linked list corresponding to the queue when packet update information is received from any queue. The packet update information includes a pointer value, a data packet length, and an index; the linked list includes a head unit, a tail unit, a timestamp unit, multiple data units, and multiple pointer units corresponding one-to-one with the multiple data units. The head unit stores the data unit address of the first packet update information of the queue, the tail unit stores the data unit address of the last packet update information of the queue, the timestamp unit stores the initial packet reception time, the data units store the packet update information of the queue, and the pointer units store the data unit address of the next packet update information of the queue. The control unit is configured to determine whether the number of packet update information entries in the queue of the storage unit is equal to n based on the linked list. If so, it reads n packet update information entries from the queue of the storage unit based on the linked list. When the n packet update information entries are read, the n packet update information entries are deleted from the storage unit. A write request generation unit is used to generate a first write request and a second write request based on the n packet update information, and send the first write request and the second write request to the DMA processing module in sequence, so that the DMA processing module writes the pointer value and data packet length of the n packet update information into the used ring table according to the first write request, and writes the index of the last received packet update information among the n packet update information into the used ring table according to the second write request. The first write request includes pointer values ​​and data packet lengths for the n packet update information, and the second write request includes the index of the last received packet update information among the n packet update information, where n is greater than or equal to 2.

8. The used ring table update module according to claim 7, characterized in that, The control unit is also used to determine whether the time difference between the initial packet reception time of any queue and the current time is equal to a preset threshold. If so, it reads all packet update information of the queue from the storage unit. The initial packet reception time of any queue is the reception time of the earliest received packet update information of the queue stored in the storage unit. The write request generation unit is further configured to generate a third write request and a fourth write request based on all packet update information, and send the third write request and the fourth write request to the DMA processing module in sequence, so that the DMA processing module writes the pointer value and data packet length of all packet update information into the used ring table according to the third write request, and writes the index of the last received packet update information among all packet update information into the used ring table according to the fourth write request; The third write request includes pointer values ​​and data packet lengths for all packet update information, and the fourth write request includes the index of the last received packet update information among all packet update information.

9. The used ring table update module according to claim 8, characterized in that, The storage unit is a linked list storage structure; The storage unit is also used to determine whether there is a linked list corresponding to any queue in the linked list storage structure when a packet update information is received from any queue. If no linked list exists corresponding to any of the queues, the storage unit creates a linked list corresponding to the queue and stores the packet update information in the linked list. If a linked list exists corresponding to any of the queues, the storage unit stores the packet update information into that linked list.

10. The used ring table update module according to claim 9, characterized in that, The storage unit is also used to clear the contents stored in the head unit, tail unit, timestamp unit, multiple data units, and multiple pointer units of any linked list after reading all the package update information of any linked list.

11. The used ring table update module according to claim 10, characterized in that, The storage unit is also configured to delete the linked list if, after reading all packet update information of any linked list, no new packet update information is received from the queue corresponding to the linked list within a preset time.

12. The used ring table update module according to any one of claims 7 to 11, characterized in that, The length of the first write request is equal to the PCIE bandwidth of the system where the used ring table update module is located.

13. A VIRTIO backend device, characterized in that, Includes the used ring table update module as described in any one of claims 7 to 12.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the used ring table update method as described in any one of claims 1 to 6.

15. An electronic device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the used ring table update method as described in any one of claims 1 to 6.

16. A chip, characterized in that, Includes the VIRTIO back-end device as described in claim 13.

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