A data processing method, an electronic device, and a storage medium

Abstract

This application relates to the field of artificial intelligence technology and discloses a data processing method, electronic device, and storage medium. In the data processing method, by setting the segmentation of parameters and data for nodes in the model—for example, dividing the parameters and input data of each node into multiple data sets—a multi-core NPU can read the segmentation from memory during data processing. Based on the segmentation, multiple cores in the multi-core NPU simultaneously load different parameters corresponding to the same node, process a portion of the node's data, and store it in the internal storage space of the corresponding core. This alleviates the storage pressure on a single core.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence technology, and in particular to a data processing method, electronic device, and storage medium. Background Technology

[0002] Generally speaking, by deploying the model on a multi-core embedded neural network processing unit (NPU), the kernels in the multi-core NPU can process the input data and obtain the output data by loading the parameters corresponding to each node (i.e., each layer in the model). Figure 1 A partial structural diagram of a recurrent neural network model is shown, such as... Figure 1 As shown, the recurrent neural network model may include an input layer 110, a hidden layer 120, an output layer 130, etc., wherein the input layer 110, the hidden layer 120, and the output layer 130 can all be considered as nodes.

[0003] like Figure 2 As shown, in some data processing schemes, for any node in the model (i.e., any layer), a single core in the multi-core NPU210 (such as...) Figure 2 Any one of 210-1 to 210-N in the memory can load the parameters corresponding to the node, process the data corresponding to the node (such as input data, output data, etc.) based on the parameters, and first store the data corresponding to the node in external memory 220, such as Double Data Rate (DDR) memory, and then store it in the internal memory space 230 of a single core (such as... Figure 2 The previously stored data in 230-1 to 230-N is deleted, and the data corresponding to that node is read from the external memory 220 via the bus 240 and stored in the internal storage space 230 of a single core (e.g., ...). Figure 2 (230-1 to 230-N in the original text). However, reading data corresponding to a node from external memory via the bus is not only inefficient but also has high latency.

[0004] Therefore, in some data processing schemes, a single kernel can process the data corresponding to all nodes and store the data of all nodes in the kernel's internal storage space. However, the internal storage space of a single kernel is often small. For models that require a large amount of storage space to process data, the internal storage space of a single kernel is far from sufficient, resulting in a large internal storage pressure on the single kernel. Summary of the Invention

[0005] To address the issue of high storage pressure on a single core, embodiments of this application provide a data processing method, an electronic device, and a storage medium.

[0006] The first aspect of this application provides a data processing method for an electronic device, characterized in that the electronic device includes a first processor, the first processor including multiple cores; and the method includes: acquiring first input data of a first model; determining a first segmentation fraction for dividing the first model based on the amount of data of the first input data and the internal storage space in the electronic device that can be used for the first model; dividing the nodes of the first model into a set of nodes of the first segmentation fraction based on the determined first segmentation fraction; processing each part of the first input data to be processed by each node using the core corresponding to each node; and storing each part of the first data to be processed by each node into the internal storage space of the core corresponding to each node.

[0007] Based on the above solution, by using multiple cores in a multi-core NPU to simultaneously load different parameters corresponding to the same node, process some of the node's data, and store it in the corresponding internal storage space, the storage pressure on a single core can be alleviated.

[0008] It can be understood that the first slice can be the segmentation information that divides the parameters and data of a node into multiple data sets, also known as the subgraph slice information, and hereinafter referred to as the target slice. For example, the first slice can refer to dividing the parameters and data of any node in the model into a predetermined number of multiple data sets. These multiple data sets are multiple data sets that can be processed in parallel.

[0009] For example, the model includes nodes A, B, C, and D. Nodes A and B are connected in parallel, meaning their input data are independent. Nodes A and C are cascaded, meaning the output data of node A is the input data of node C. Both nodes C and B are cascaded with node D, meaning their output data is the input data of node D. The input data for node A includes a1-a4, and its parameters include b1-b4. The input data for node B includes a5-a8, and its parameters include b5-b8. The parameters for node C include c1-c4, and the parameters for node D include d1-d4.

[0010] If the model's segmentation is determined to be 4, then based on the current segmentation of this node, the input data a1, a5 and parameters b1, b5, c1, d1 can be segmented into a first data set, and stored in the internal storage space of the first core in the multi-core NPU. The input data a2, a6 and parameters b2, b6, c2, d2 can be segmented into a second data set, and stored in the internal storage space of the second core in the multi-core NPU. The input data a3, a7 and parameters b3, b7, c3, d3 can be segmented into a third data set, and stored in the internal storage space of the third core in the multi-core NPU. The input data a4, a8 and parameters b4, b8, c4, d4 can be segmented into a fourth data set, and stored in the internal storage space of the fourth core in the multi-core NPU.

[0011] When processing data, the first kernel of the multi-core NPU can be used to process data a1 by loading parameters b1, c1, and d1, and to process data a5 by loading parameters b5 and d1, and the first output data e1 and e2 can be stored in the internal storage space of the first kernel. Similarly, the second kernel of the multi-core NPU can be used to process data a2 by loading parameters b2, c2, and d2, and to process data a6 by loading parameters b6 and d2, and the second output data e3 and e4 can be stored in the internal storage space of the second kernel. Specifically, the first kernel loading parameters b1, c1, and d1 to process data a1 can mean that the first kernel loads parameter b1 to process data a1, loads parameter c1 to process the output data of parameter b1, and loads parameter d1 to process the output data of parameter c1. The third kernel of the multi-core NPU is used to process data a3 using parameters b3, c3, and d3, and data a7 using parameters b7 and d3. The third output data e5 and e6 are then stored in the internal storage space of the third kernel. The fourth kernel of the multi-core NPU is used to process data a4 using parameters b4, c4, and d4, and data a8 using parameters b8 and d4. The fourth output data e7 and e8 are then stored in the internal storage space of the fourth kernel.

[0012] It is understood that the first processor can be a multi-core embedded neural network model processor. The first model is a neural network model. The first input data can include image data, text data, and audio data. Processing each sub-data can include image feature extraction from image data, text feature extraction from text data, and audio feature extraction from audio data, resulting in pixels, characters, audio signals, etc.

[0013] In one possible implementation of the first aspect described above, determining a first segmentation for dividing the first model based on the amount of data in the first input data and the internal storage space available for the first model in the electronic device includes: in the first round of determining the first segmentation, using the number of cores in the first processor as the initial segmentation; based on the initial segmentation, dividing the nodes of the first model into node sets of the initial segmentation; determining the storage space corresponding to each node set and determining a target storage space, wherein the target storage space is greater than the other storage spaces in the storage spaces corresponding to each node set; corresponding to the target storage space being less than or equal to a storage space threshold, using the initial segmentation as the first segmentation; corresponding to the target storage space being greater than the storage space threshold, adjusting the initial segmentation to obtain the first segmentation.

[0014] For example, if the number of cores in the first processor is 4, then the initial segment when determining the first segment in the first round is 4.

[0015] In one possible implementation of the first aspect above, adjusting the initial segment to obtain the first segment includes: using a multiple of the initial segment when the first segment was determined in the first round as the first segment.

[0016] For example, the first segment can be 2 or 3 times the initial segment used in the first round of determining the first segment, and the steps of obtaining the node set, determining the storage space corresponding to each node set, and determining the target storage space can be repeated until the target storage space is less than or equal to the storage space threshold and the initial segment is less than or equal to the segment threshold. The initial segment used in this round to determine the segment of the model can then be taken as the target segment.

[0017] In one possible implementation of the first aspect above, the adjusted initial segment is a multiple of the initial segment when the first segment is determined in the first round, including: determining the first segment based on the initial segment when the first segment is determined in the first round and the number of cores in the first processor.

[0018] In some optional instances, the sum of the initial slice when determining the first slice in the first round and the number of cores in the first processor can be used as the first slice. For example, if the number of cores in the first processor is 4, and the initial slice when determining the first slice in the first round is 4, then 8 can be used as the adjusted slice, i.e., the first slice.

[0019] In one possible implementation of the first aspect described above, the storage space threshold is the ratio of the internal storage space available for the first model in the electronic device to the initial segmentation.

[0020] It is understandable that the internal storage space available for the first model in an electronic device can be the high-speed local cache in a multi-core NPU, and the storage space threshold can be the ratio of the high-speed local cache in the multi-core NPU to the initial segmentation of the model.

[0021] In one possible implementation of the first aspect above, each part of the first input data to be processed by each node includes first sub-data and second sub-data, and the kernel corresponding to each node includes a first kernel and a second kernel. The kernel corresponding to each node is used to process each part of the first input data to be processed by each node, including: using the first kernel to process the first sub-data and using the second kernel to process the second sub-data.

[0022] In one possible implementation of the first aspect above, processing the first sub-data using a first kernel includes: using the first kernel to load a first subset of parameters in the node corresponding to the first sub-data for processing the first sub-data, and processing the first sub-data; and processing the second sub-data using a second kernel includes: using the second kernel to load a second subset of parameters in the node corresponding to the second sub-data for processing the second sub-data, and processing the second sub-data.

[0023] In one possible implementation of the first aspect described above, storing each part of the first input data to be processed by each node into the internal storage space of the kernel corresponding to each node includes: storing the first sub-data into the first internal storage space of the first kernel, and storing the second sub-data into the second internal storage space of the second kernel.

[0024] It is understandable that, while storing the first sub-data in the first internal storage space of the first kernel, the first output sub-data obtained by the first kernel from processing the first sub-data can also be stored in the first internal storage space of the first kernel. Similarly, while storing the second sub-data in the second internal storage space of the second kernel, the second output sub-data obtained by the second kernel from processing the second sub-data can also be stored in the second internal storage space of the second kernel.

[0025] In this embodiment, by storing the data corresponding to the first kernel in the internal storage space of the first kernel and the data corresponding to the second kernel in the internal storage space of the second kernel, compared to processing the entire first input data with a single kernel and storing it in the internal storage space of a single kernel, the storage pressure on a single kernel can be alleviated. Furthermore, compared to storing it in external memory, data can be read directly from the internal memory of the kernel without having to read data from external memory via a bus. This can alleviate the storage pressure on a single kernel while reducing the number of accesses to external memory, improving data processing efficiency, and reducing data read latency.

[0026] In a second aspect, this application provides an electronic device, including: a memory for storing instructions executed by one or more processors of the electronic device, and a processor, which is one of the one or more processors of the electronic device, for executing the data processing method mentioned in this application.

[0027] Thirdly, this application provides a readable storage medium storing instructions that, when executed on an electronic device, cause the electronic device to perform the data processing method mentioned in this application. Attached Figure Description

[0028] Figure 1 Based on some examples of this application, a partial structural schematic diagram of a recurrent neural network model is shown;

[0029] Figure 2 Based on some examples of this application, a schematic diagram of the structure of a data processing system is shown;

[0030] Figure 3 Based on some examples of this application, a schematic diagram of an application scenario is shown;

[0031] Figure 4 Based on some examples of this application, a schematic diagram of data segmentation is shown;

[0032] Figure 5 Based on some examples of this application, a flowchart of a data processing method is shown;

[0033] Figure 6 Based on some examples of this application, a flowchart illustrating a method for determining the number of segments is shown;

[0034] Figure 7 Based on some examples of this application, a schematic diagram of the hardware structure of an electronic device is shown. Detailed Implementation

[0035] The illustrative embodiments of this application include, but are not limited to, a data processing method, an electronic device, and a storage medium.

[0036] It is understood that the data processing methods mentioned in the embodiments of this application can be used in neural network models, which can be applied in many fields, such as text processing, image processing, audio processing, and autonomous driving. Figure 3 As shown, in some specific implementations, the server 310 can perform segmentation processing on the neural network model 311 and send the segmented neural network model 311 to the terminal 320, so that the terminal 320 can execute the data processing method mentioned in the embodiments of this application based on the segmented neural network model 311.

[0037] To address the aforementioned problems, this application discloses a data processing method. In this method, by setting a segmentation of the parameters and data of nodes in the model in memory—for example, dividing the parameters and input data of each node into multiple data sets—a multi-core NPU can read the segmentation in memory during data processing. Based on the segmentation, multiple cores of the multi-core NPU simultaneously load different parameters corresponding to the same node, process a portion of the node's data, and store it in the corresponding internal storage space. This alleviates the storage pressure on a single core.

[0038] It is understandable that the number of segments to be divided in the model can be determined based on the amount of input data and the internal storage space available for the model in the electronic device; this is referred to as the target number of segments.

[0039] Figure 4 This illustrates a schematic diagram of data processing, such as... Figure 4 As shown, the model includes nodes A, B, C, and D. Nodes A and B are connected in parallel, meaning their input data are independent. Nodes A and C are cascaded, meaning the output data of node A is the input data of node C. Both nodes C and B are cascaded with node D, meaning their output data is the input data of node D. The input data for node A includes a1-a4, and the parameters include b1-b4. The input data for node B includes a5-a8, and the parameters include b5-b8. The parameters for node C include c1-c4, and the parameters for node D include d1-d4.

[0040] If the model's segmentation is determined to be 4, then based on the current segmentation of this node, the input data a1, a5 and parameters b1, b5, c1, d1 can be segmented into a first data set (as shown in the dashed box), and this first data set is stored in the internal storage space of the first core in the multi-core NPU. The input data a2, a6 and parameters b2, b6, c2, d2 are segmented into a second data set, and this second data set is stored in the internal storage space of the second core in the multi-core NPU. The input data a3, a7 and parameters b3, b7, c3, d3 are segmented into a third data set, and this third data set is stored in the internal storage space of the third core in the multi-core NPU. The input data a4, a8 and parameters b4, b8, c4, d4 are segmented into a fourth data set, and this fourth data set is stored in the internal storage space of the fourth core in the multi-core NPU.

[0041] When processing data, the first kernel of the multi-core NPU can be used to process data a1 by loading parameters b1, c1, and d1, and to process data a5 by loading parameters b5 and d1, and the first output data e1 and e2 can be stored in the internal storage space of the first kernel. Similarly, the second kernel of the multi-core NPU can be used to process data a2 by loading parameters b2, c2, and d2, and to process data a6 by loading parameters b6 and d2, and the second output data e3 and e4 can be stored in the internal storage space of the second kernel. Specifically, the first kernel loading parameters b1, c1, and d1 to process data a1 can mean that the first kernel loads parameter b1 to process data a1, loads parameter c1 to process the output data of parameter b1, and loads parameter d1 to process the output data of parameter c1. The third kernel of the multi-core NPU is used to process data a3 using parameters b3, c3, and d3, and data a7 using parameters b7 and d3. The third output data e5 and e6 are then stored in the internal storage space of the third kernel. The fourth kernel of the multi-core NPU is used to process data a4 using parameters b4, c4, and d4, and data a8 using parameters b8 and d4. The fourth output data e7 and e8 are then stored in the internal storage space of the fourth kernel.

[0042] In some optional instances, the parameters and data splits for nodes in the model can be determined in the following ways:

[0043] In the first round of determining the segmentation, the number of cores in the multi-core NPU is used as the initial segmentation. Based on the initial segmentation, the parameters and data in the model are segmented to obtain multiple data sets. The storage space required to store each data set is determined, and the maximum required storage space is determined from them. When the maximum storage space is less than or equal to the storage space threshold, the initial segmentation is used as the target segmentation.

[0044] In some optional instances, when the maximum storage space is greater than the storage space threshold, the initial segmentation is used as a multiple of the initial segmentation for determining the segmentation of the model in the next round, such as 2 or 3 times the initial segmentation. The steps of obtaining multiple data sets, determining the storage space required to store the data in each data set, and determining the maximum required storage space are repeated until the maximum storage space is less than or equal to the storage space threshold and the initial segmentation is less than or equal to the segmentation threshold. The initial segmentation used to determine the segmentation of the model in this round is then used as the target segmentation.

[0045] In some optional instances, the storage threshold can be the ratio of the high-speed local cache in the multi-core NPU to the initial segment of the model in each round when determining the segmentation of the model.

[0046] The data processing methods mentioned in the embodiments of this application are described below. Figure 5 A flowchart illustrating a data processing method is shown, such as... Figure 5 As shown, the data processing method may include:

[0047] 501: Determine the target cutoff value for the model.

[0048] In some optional instances, when the model is an image recognition model that performs image recognition processing, the input image can be input into the image recognition model in the form of an n-dimensional tensor. For example, the input image can be input into the image recognition model in the form of a 3-dimensional tensor, which can include C-dimensional, H-dimensional, and W-dimensional tensors, where C can represent the number of channels in the input image, H can represent the number of pixels in the vertical direction of the input image, and W can represent the number of pixels in the horizontal direction of the input image.

[0049] Generally, if a single core in a multi-core NPU loads all the parameters corresponding to a node to process the entire image—for example, to extract image features—the amount of data that a single core needs to process is enormous, and the amount of data stored in the internal storage space of that single core is also enormous. Therefore, it is necessary to determine the model's segmentation to divide the parameters and data within the model. The specific method for determining the model's segmentation will be discussed later. Figure 6 This will be discussed in detail later.

[0050] 502: Based on the target segmentation of the model, the parameters and data of each node are segmented to obtain multiple datasets.

[0051] It is understandable that after determining the target segmentation of the model, the partial input data, partial parameters, and partial output data of each node in the model can be segmented into a data set, i.e., a slice subgraph.

[0052] 503: Multiple kernels are used to load parameters from different datasets, and data processing is performed on the data in each dataset based on the parameters to obtain the output data.

[0053] It is understandable that after obtaining multiple datasets, a kernel can load the parameters of one dataset and perform data processing on the data in that dataset, such as image feature extraction, text feature extraction, and audio feature extraction, and output the corresponding output data. This output data is also included in the dataset and stored in the kernel's internal storage space.

[0054] The method for determining the segmented data mentioned in the embodiments of this application is described below. Figure 6A flowchart illustrating a method for determining the segmentation fraction is shown, as follows: Figure 6 As shown, the method for determining the segmentation number may include:

[0055] 601: Initialize the segmentation of the model to obtain the initial segmentation.

[0056] It is understandable that when splitting data, the number of cores in a multi-core NPU, i.e. the number of parallel execution units in a multi-core NPU, can be denoted as corenum, the size of the high-speed local cache in a multi-core NPU can be denoted as sramsize, and the maximum allowed splitting fraction, i.e. the splitting fraction threshold, can be denoted as tile_num_up_limit.

[0057] Understandably, in some optional instances, the model's segmentation can be initialized based on the number of cores in a multi-core NPU to obtain an initial segmentation. For example, the model's segmentation can be denoted as `tilenum`, and the model's segmentation `tilenum` can be initialized as `corenum`.

[0058] 602: Based on the initial segmentation of the model, the parameters and data in the model are segmented to obtain multiple datasets.

[0059] It is understandable that after initializing the model's initial segmentation to obtain the current initial segmentation, it is possible to evaluate whether the current initial segmentation is the optimal segmentation, i.e., whether it is the target segmentation. In some specific implementations, the parameters and data in the model can be segmented based on the model's initial segmentation, i.e., the parameters and data of each node can be segmented.

[0060] In some optional instances, the parameters and data in the model can be segmented based on the initial segmentation number tilenum, so that the parameters and data in the model become tilenum data sets. Each data set can include part of the input data, part of the parameters and part of the output data of each node in multiple cascaded nodes. Each data set can be called a slice subgraph.

[0061] 603: Allocate storage space for each data set in the dataset and identify candidate storage spaces.

[0062] It is understandable that for each data set, i.e., each slice subgraph, the memory allocator can be called to allocate storage space for each data set, i.e., each slice subgraph. For example, the storage space required for each data set, i.e., each slice subgraph, can be denoted as buffer_size_i, and the storage space required for all data sets, i.e., all slice subgraphs, buffer_size_i can be compared to obtain the maximum storage space as a candidate storage space, and denoted as buffer_size_max.

[0063] 604: Determine whether the candidate storage space is less than or equal to the storage space threshold. If the result is yes, proceed to step 605; otherwise, proceed to step 606.

[0064] It is understandable that the storage space threshold can be determined based on the ratio of the high-speed local cache in the multi-core NPU to the initial segmentation of the model. In some optional instances, the storage space threshold can be based on the ratio of the high-speed local cache in the multi-core NPU to the initial segmentation of the model, i.e., sramsize / tilenum.

[0065] It is understandable that after determining the candidate storage space, it can be determined whether the candidate storage space is less than or equal to the storage space threshold, i.e., whether buffer_size_max ≤ sramsize / tilenum. In some optional instances, when the maximum storage space required by all data sets (i.e., all tile subgraphs) is less than or equal to the storage space threshold, the process can proceed to step 605, which uses the initial segmentation as the target segmentation, i.e., determines the current initial segmentation as the optimal segmentation. When the maximum storage space required by all data sets (i.e., all tile subgraphs) is greater than the storage space threshold, the process can proceed to step 606, which adjusts the initial segmentation.

[0066] 605: Use the initial segmentation as the target segmentation.

[0067] It is understandable that when the maximum storage space required for all data sets, i.e. all slice subgraphs, is less than or equal to the storage space threshold, the current initial slice number tilenum can be determined as the optimal slice number.

[0068] 606: Adjust the initial segmentation and proceed to step 601.

[0069] In some optional instances, a multiple of the current initial slice can be used as the initial slice of the adjusted model, such as 2 or 3 times the initial slice. Specifically, 2 times the current initial slice can be used as the initial slice of the adjusted model. For example, the sum of the current initial slice and the number of cores in the multi-core NPU can be used as the initial slice of the adjusted model, i.e., tile_num = tile_num + corenum. Then, steps 601 to 604 above can be repeated until the initial slice of the model is less than or equal to the maximum allowed slice, i.e., the slice threshold denoted as tile_num_up_limit, i.e., corenum ≤ tile_num_up_limit. That is, during the process of adjusting the initial slice, when the initial slice of the model is less than or equal to the maximum allowed slice, i.e., the slice threshold, the steps of adjusting the initial slice can be repeated until the optimal slice is found. When the initial slice of the model is greater than the maximum allowed slice, i.e., the slice threshold, the process of determining the target slice can be exited, and it is determined that the optimal slice cannot be found.

[0070] The hardware structure of electronic devices is described below. Figure 7 The diagram shows a hardware structure of an electronic device. It is understood that the electronic device of this application can be a server, desktop computer, handheld computer, laptop computer, or other electronic device. The structure of the electronic device will be described below using a server as an example.

[0071] In one embodiment, the server may include one or more processors 701, system control logic 702 connected to at least one of the processors 701, system memory 703 connected to the system control logic 702, non-volatile memory (NVM) 704 connected to the system control logic 702, and input / output (I / O) devices 705 and network interfaces 706 connected to the system control logic 702.

[0072] In some embodiments, processor 701 may include one or more single-core or multi-core processors. In some embodiments, processor 701 may include any combination of general-purpose processors and special-purpose processors (e.g., graphics processors, application processors, baseband processors, etc.). In embodiments where the server employs an eNB (Evolved Node B) or RAN (Radio Access Network) controller, processor 701 may be configured to perform various conforming embodiments.

[0073] In some embodiments, system control logic 702 may include any suitable interface controller to provide any suitable interface to at least one of the processors 701 and / or any suitable device or component communicating with system control logic 702.

[0074] In some embodiments, system control logic 702 may include one or more memory controllers to provide an interface to system memory 703. System memory 703 may be used to load and store data and / or instructions 7031. In some embodiments, the server's memory may include any suitable volatile memory, such as suitable dynamic random access memory (DRAM).

[0075] The non-volatile memory (NVM) 704 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, the non-volatile memory (NVM) 704 may include any suitable non-volatile memory such as flash memory and / or any suitable non-volatile storage device, such as at least one of an HDD (Hard Disk Drive), a CD (Compact Disc) drive, and a DVD (Digital Versatile Disc) drive.

[0076] Non-volatile memory (NVM) 704 may include a portion of storage resources on the device on which the server is installed, or it may be accessible by the device, but is not necessarily part of the device. For example, non-volatile memory (NVM) 704 may be accessed over a network via network interface 706.

[0077] Specifically, system memory 703 and non-volatile memory (NVM) 704 may each include temporary copies and permanent copies of instructions. Instructions may include instructions that, when executed by at least one of the processors 701, cause the server to implement the data processing methods mentioned in the embodiments of this application. In some embodiments, instructions, hardware, firmware, and / or their software components may additionally / alternatively be located in system control logic 702, network interface 706, and / or processor 701.

[0078] Network interface 706 may include a transceiver for providing a radio interface to the server, thereby enabling communication with any other suitable device (such as a front-end module, antenna, etc.) via one or more networks. In some embodiments, network interface 706 may be integrated into other components of the server. For example, network interface 706 may be integrated into at least one of processor 701, system memory 703, non-volatile memory (NVM) 704, and firmware device (not shown) with instructions, which, when executed by at least one of processor 701, enable the server to implement the data processing methods mentioned in the embodiments of this application.

[0079] The network interface 706 may further include any suitable hardware and / or firmware to provide a multiple-input multiple-output radio interface. For example, the network interface 706 may be a network adapter, a wireless network adapter, a telephone modem, and / or a wireless modem.

[0080] In one embodiment, at least one of the processors 701 may be packaged together with the logic of one or more controllers for system control logic 702 to form a system-in-package (SiP). In another embodiment, at least one of the processors 701 may be integrated on the same die with the logic of one or more controllers for system control logic 702 to form a system-on-a-chip (SoC).

[0081] The server may further include an input / output (I / O) device 705. The I / O device 705 may include a user interface enabling users to interact with the server; the peripheral component interface is designed to allow peripheral components to also interact with the server. In some embodiments, the server further includes sensors for determining at least one type of environmental condition and location information related to the server.

[0082] In some embodiments, the user interface may include, but is not limited to, a display (e.g., a liquid crystal display, a touch screen display, etc.), a speaker, a microphone, one or more cameras (e.g., a still image camera and / or a video camera), a flashlight (e.g., a light-emitting diode flash), and a keyboard.

[0083] In some embodiments, the peripheral component interface may include, but is not limited to, a non-volatile memory port, an audio jack, and a power interface.

[0084] In some embodiments, the sensor may include, but is not limited to, a gyroscope sensor, an accelerometer, a proximity sensor, an ambient light sensor, and a positioning unit. The positioning unit may also be part of or interact with the network interface 706 to communicate with components of the positioning network, such as Global Positioning System (GPS) satellites.

[0085] The above describes the possible hardware structures of electronic devices. It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components than illustrated, or combine certain components, or split certain components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of both.

[0086] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0087] The various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0088] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0089] The program code can be implemented using a high-level procedural language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used when needed. In fact, the mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0090] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other propagation signals. Therefore, machine-readable media include any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0091] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0092] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0093] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made thereto without departing from the scope of this application.

Claims

1. A data processing method for electronic devices, characterized in that, The electronic device includes a first processor, which includes multiple cores; And the method includes: Obtain the first input data for the first model; Based on the amount of the first input data and the internal storage space in the electronic device that can be used for the first model, a first segmentation of the first model is determined. Based on the determined first segment, the parameters and input data of different nodes of the first model are divided into data sets with a number equal to the first segment, and each data set includes parameters and input data corresponding to multiple different nodes; The input data in the different data sets is processed by synchronously loading parameters from different data sets in different kernels among the multiple kernels; The data sets that each node needs to process are stored in the internal storage space of the corresponding kernel. The determination of a first segmentation for dividing the first model based on the amount of the first input data and the internal storage space available for the first model in the electronic device includes: In the first round of determining the first segment, the number of cores in the first processor is used as the initial segment; Based on the initial segmentation, the nodes of the first model are segmented into a set of nodes based on the initial segmentation. Determine the storage space corresponding to each node set and determine the target storage space, wherein the target storage space is larger than the other storage spaces in the storage space corresponding to each node set; If the target storage space is less than or equal to the storage space threshold, the initial segmentation is taken as the first segmentation. If the target storage space is greater than the storage space threshold, the initial segmentation is adjusted to obtain the first segmentation.

2. The method according to claim 1, characterized in that, The step of adjusting the initial segment to obtain the first segment includes: The first segment is a multiple of the initial segment used when determining the first segment in the first round.

3. The method according to claim 2, characterized in that, The step of using a multiple of the initial segment when determining the first segment in the first round as the first segment includes: The first segment is determined based on the initial segment when the first segment is determined in the first round and the number of cores in the first processor.

4. The method according to claim 1, characterized in that, The storage space threshold is the ratio of the internal storage space available for the first model in the electronic device to the initial segmentation.

5. The method according to claim 1, characterized in that, The data set that each node needs to process includes a first sub-data set and a second sub-data set, and the multiple kernels include a first kernel and a second kernel. Using the aforementioned multiple kernels, different data sets that need to be processed by each node in the first model are processed synchronously, including: The first kernel is used to process the first sub-data, and The second kernel is used to process the second sub-data.

6. The method according to claim 5, characterized in that, The process of using the first kernel to process the first sub-data includes: The first kernel loads the first parameter subset from the node corresponding to the first sub-data, which is used to process the first sub-data, and processes the first sub-data; and The process of using the second kernel to process the second sub-data includes: The second kernel loads the second parameter subset from the node corresponding to the second sub-data, which is used to process the second sub-data, and then processes the second sub-data.

7. The method according to claim 6, characterized in that, The step of storing the data sets to be processed by each node into the internal storage space of the corresponding kernel includes: The first sub-data is stored in the first internal storage space of the first kernel, and The second sub-data is stored in the second internal storage space of the second kernel.

8. An electronic device, characterized in that, include: A memory for storing instructions executed by one or more processors of the electronic device, and a processor, being one of one or more processors of the electronic device, for performing the data processing method according to any one of claims 1-7.

9. A readable storage medium, characterized in that, The readable storage medium stores instructions that, when executed on an electronic device, cause the electronic device to perform the data processing method according to any one of claims 1-7.

Images