Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region and a second region; forming a dielectric layer, a first sidewall, a second sidewall, a first gate dielectric layer and a second gate dielectric layer on the substrate; forming a sacrificial layer exposing a second gate opening on the dielectric layer and in the first gate opening; and performing a compensation process on the second sidewall, doping compensation ions in each of the second sidewalls so that an etching rate difference of each of the second sidewalls by an etching process is within a preset range. By doping compensation ions in each of the second sidewalls, material differences of some of the second sidewalls caused by previous processes are compensated, etching uniformity of each of the second sidewalls when etching the second gate dielectric layer is improved, and then a height of each of the second sidewalls to be removed is kept balanced, a height of a second gate layer to be formed subsequently is kept balanced, and thus performance differences of each of transistor structures formed on the second region are reduced, and performance of a semiconductor structure to be finally formed is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] MOS (Metal-Oxide-Semiconductor) transistors are among the most important components in modern integrated circuits. The basic structure of a MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, the gate structure including: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; lightly doped regions located on the semiconductor substrate on both sides of the gate structure and source / drain regions located on the semiconductor substrate on both sides of the gate structure.

[0003] The method for forming the MOS transistor is as follows: providing a semiconductor substrate, forming a gate structure on the surface of the semiconductor substrate, the gate structure including a gate dielectric layer on the surface of the semiconductor substrate and a gate electrode layer on the surface of the gate dielectric layer; forming an offset sidewall on the sidewall surface of the gate structure, using the offset sidewall and the gate structure as masks, performing lightly doped drain (LDD) implantation on the semiconductor substrate on both sides of the gate structure to form a lightly doped region; forming a gap sidewall on the offset sidewall surface; using the gate structure, the offset sidewall, and the gap sidewall as masks, performing a source / drain region implantation process on the semiconductor substrate on both sides of the gate structure to form source / drain regions.

[0004] However, the performance and reliability of MOS transistors formed in the prior art are poor. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region; forming a dielectric layer on the substrate, the dielectric layer having a first gate opening located on the first region and a second gate opening located on the second region, the first gate opening having a first sidewall, the second gate opening having a second sidewall, the bottom of the first gate opening having a first gate dielectric layer, and the bottom of the second gate opening having a second gate dielectric layer; forming an initial sacrificial layer on the dielectric layer, within the first gate opening, and within the second gate opening; patterning the initial sacrificial layer to form a sacrificial layer exposing the second gate opening on the dielectric layer and within the first gate opening; using the sacrificial layer as a mask to perform compensation processing on the second sidewalls, doping each of the second sidewalls with compensation ions; and after the compensation processing, etching the second gate dielectric layer, wherein the etching rate difference of each of the second sidewalls is within a preset range.

[0007] Optionally, the patterning process of the initial sacrificial layer includes: forming a patterned layer on the initial sacrificial layer, the patterned layer exposing the top surface of the initial sacrificial layer located on the second region; using the patterned layer as a mask, using plasma etching to remove the initial sacrificial layer located on the second region to form the sacrificial layer.

[0008] Optionally, after the plasma etching process, the ions remaining in the second sidewall include one or more of nitrogen ions and hydrogen ions.

[0009] Optionally, the compensation ions doped within each of the second sidewalls include one or more of nitrogen ions and hydrogen ions.

[0010] Optionally, after the compensation treatment, the concentration range of residual plasma and doped compensation ions in each of the second sidewalls is 0% to 80%.

[0011] Optionally, the plasma in the plasma etching process includes one or more of NH3, NF3, N2, and H2; the inert gas in the plasma etching process includes one or more of He and Ar.

[0012] Optionally, the plasma in the compensation process includes one or more of NH3, NF3, N2, and H2; the inert gas in the plasma etching process includes one or more of He and Ar.

[0013] Optionally, the materials of the first sidewall and the second sidewall include: low-K materials; the low-K materials include: SiOC, SiOCN or SiBCN.

[0014] Optionally, the method for forming the dielectric layer, the first sidewall, the second sidewall, the first gate dielectric layer, the second gate dielectric layer, the first gate opening, and the second gate opening includes: forming a plurality of first gate dielectric layers and a plurality of second gate dielectric layers on the substrate, wherein the plurality of first gate dielectric layers are located in the first region and the plurality of second gate dielectric layers are located in the second region; forming a first dummy gate layer on the first gate dielectric layer and forming a second dummy gate layer on the second gate dielectric layer; forming a first sidewall on the sidewall of the first gate dielectric layer and the first dummy gate layer, and forming a second sidewall on the sidewall of the second gate dielectric layer and the second dummy gate layer; forming the dielectric layer on the substrate, wherein the dielectric layer covers the sidewall of the first dummy gate layer and the second dummy gate layer; removing the plurality of first dummy gate layers and the plurality of second dummy gate layers, and forming a plurality of first gate openings and a plurality of second gate openings within the dielectric layer.

[0015] Optionally, the process of forming the dielectric layer, the first sidewall, the second sidewall, the first gate dielectric layer, and the second gate dielectric layer further includes: using the first sidewall, the second sidewall, the first dummy gate layer, and the second dummy gate layer as masks, etching the first region and the second region respectively, forming a first source / drain opening in the first region, and forming a second source / drain opening in the second region; forming a first source / drain doped layer in the first source / drain opening, and forming a second source / drain doped layer in the second source / drain opening.

[0016] Optionally, the material of the initial sacrificial layer includes photoresist.

[0017] Optionally, after removing the second gate dielectric layer, the method further includes: removing the sacrificial layer; after removing the sacrificial layer, forming a first gate layer in the first gate opening, wherein the first gate dielectric layer, the first sidewall, and the first gate layer constitute a first gate structure; and forming a second gate layer in the second gate opening, wherein the second sidewall and the second gate layer constitute a second gate structure.

[0018] Optionally, the process for removing the sacrificial layer includes an ashing process.

[0019] Optionally, the substrate includes a base.

[0020] Optionally, the substrate includes a base and a fin structure located on the base, the fin structure spanning the first region and the second region.

[0021] Optionally, after forming the fin structure, the method further includes: forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewalls of the fin structure, and the top surface of the isolation layer being lower than the top surface of the fin structure.

[0022] Optionally, the fin structure is a single-layer structure.

[0023] Optionally, the fin structure includes: a plurality of channel layers overlapping along the normal direction of the substrate surface.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the semiconductor structure formation method of the present invention, the second sidewall is compensated by using the sacrificial layer as a mask and doping each second sidewall with compensating ions to compensate for the material differences of some second sidewalls caused by the previous process. This improves the etching uniformity of each second sidewall when etching the second gate dielectric layer, thereby ensuring that the height of each removed second sidewall remains balanced, so that the height of the subsequently formed second gate layer remains balanced. This reduces the performance differences of each transistor structure formed on the second region, thereby improving the performance of the final semiconductor structure. Attached Figure Description

[0026] Figure 1 and Figure 2 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0027] Figures 3 to 14 This is a schematic diagram of the steps in the method for forming a semiconductor structure in an embodiment of the present invention. Detailed Implementation

[0028] As described in the background section, the performance and reliability of MOS transistors manufactured in the prior art are poor. This will be explained in detail below with reference to the accompanying drawings.

[0029] Figure 1 and Figure 2 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0030] Please refer to Figure 1A substrate 100 is provided, the substrate 100 including a first region I and a second region II, the first region I having a first fin 101 and the second region II having a second fin 102; a dielectric layer 103, a plurality of first sidewalls 104 and a plurality of second sidewalls 105 are formed on the substrate 100, the plurality of first sidewalls 104 spanning the first fins 101 and the plurality of second sidewalls 105 spanning the second fins 102, the dielectric layer 103 covering the sidewalls of the first sidewalls 104 and the second sidewalls 105, and the dielectric layer 103 having a first gate opening and a second gate opening. A first gate opening (not shown) exposes the first sidewall 104, a second gate opening exposes the second sidewall 105, and the bottom surface of the first gate opening has a first gate dielectric layer 106, and the bottom surface of the second gate opening has a second gate dielectric layer 107; an initial sacrificial layer (not shown) is formed on the substrate 100, the initial sacrificial layer covering the dielectric layer 103, a plurality of the first sidewalls 104 and a plurality of the second sidewalls 105; the initial sacrificial layer located on the second region II is removed by plasma etching to form a sacrificial layer 108;

[0031] Please refer to Figure 2 Using the sacrificial layer 108 as a mask, the second gate dielectric layer 107 is removed; after removing the second gate dielectric layer 107, the sacrificial layer 108 is removed; after removing the sacrificial layer 108, a first gate layer 109 is formed in the first gate opening, and a second gate layer 110 is formed in the second gate opening.

[0032] In this embodiment, according to the design requirements of the electrical structure, the threshold voltages of the transistor structures formed on the first region I and the second region II are different. Therefore, by removing the second gate dielectric layer 107, the threshold voltages of the transistor structures formed on the first region I and the second region II are different.

[0033] Because plasma etching is used to remove the initial sacrificial layer, some plasma is injected into the second sidewall 105 during the removal process, thereby modifying the second sidewall 105. When removing the second gate dielectric layer 107, the modified second sidewall 105 is also partially removed. However, during the plasma etching process, the plasma concentration distribution is uneven, resulting in different plasma concentrations within each second sidewall 105. Consequently, the height to which each second sidewall 105 is removed varies, leading to different heights of the formed second gate layer 110. This results in significant differences in the performance of the transistor structures formed on the second region II, affecting the performance of the final semiconductor structure.

[0034] Based on this, the present invention provides a method for forming a semiconductor structure. By using the sacrificial layer as a mask, the second sidewall is compensated by doping each of the second sidewalls with compensating ions to make up for the material differences of some of the second sidewalls caused by the previous process. This improves the etching uniformity of each of the second sidewalls when etching the second gate dielectric layer, thereby ensuring that the height of each of the removed second sidewalls remains balanced, so that the height of the subsequently formed second gate layer remains balanced. This reduces the performance differences of the transistor structures formed on the second region, thereby improving the performance of the final semiconductor structure.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figures 3 to 14 This is a schematic diagram of the steps in the method for forming a semiconductor structure in an embodiment of the present invention.

[0037] Please refer to Figure 3 A substrate is provided, the substrate comprising a first region I and a second region II.

[0038] In this embodiment, the substrate includes a base 200 and a fin structure 201 located on the base 200, the fin structure 201 spanning the first region I and the second region II. In other embodiments, the substrate may consist only of a base.

[0039] In this embodiment, the fin structure 201 is a single-layer structure. In other embodiments, the fin structure may also be: a plurality of channel layers overlapping along the normal direction of the substrate surface.

[0040] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0041] In this embodiment, the fin structure 201 is made of silicon; in other embodiments, the fin structure may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0042] In this embodiment, the method for forming the substrate may include: providing an initial substrate (not shown), forming a patterned layer (not shown) on the substrate, the patterned layer exposing the top surface of the initial substrate; etching the initial substrate using the patterned layer as a mask to form the substrate, and the substrate includes a substrate 200 and a fin structure 201 located on the substrate 200.

[0043] Please refer to Figure 4An isolation layer 202 is formed on the substrate, the isolation layer 202 covers part of the sidewall of the fin structure 201, and the top surface of the isolation layer 202 is lower than the top surface of the fin structure 201.

[0044] In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate; etching away a portion of the initial isolation layer to form the isolation layer 202, wherein the top surface of the isolation layer 202 is lower than the top surface of the fin structure 201.

[0045] The insulating layer 202 is made of an insulating material, including silicon oxide or silicon oxynitride; in this embodiment, the insulating layer 202 is made of silicon oxide.

[0046] In this embodiment, after forming the isolation layer 202, the method further includes: forming a dielectric layer on the substrate, the dielectric layer having a first gate opening located on the first region and a second gate opening located on the second region, the first gate opening having a first sidewall, the second gate opening having a second sidewall, the bottom of the first gate opening having a first gate dielectric layer, and the bottom of the second gate opening having a second gate dielectric layer. For a detailed formation process, please refer to [reference needed]. Figures 5 to 9 .

[0047] Please refer to Figure 5 A plurality of first gate dielectric layers 203 and a plurality of second gate dielectric layers 204 are formed on the substrate, wherein the plurality of first gate dielectric layers 203 are located in the first region I and the plurality of second gate dielectric layers 204 are located in the second region II; a first dummy gate layer 205 is formed on the first gate dielectric layer 203 and a second dummy gate layer 206 is formed on the second gate dielectric layer 204.

[0048] In this embodiment, the method for forming the first gate dielectric layer 203, the second gate dielectric layer 204, the first dummy gate layer 205, and the second dummy gate layer 206 includes: forming a gate dielectric material layer (not shown) on a substrate, the gate dielectric material layer covering the sidewalls and top surface of the fin structure 201; forming a dummy gate material layer (not shown) on the gate dielectric material layer; and performing patterning processing on the gate dielectric material layer and the dummy gate material layer to form the first gate dielectric layer 203, the second gate dielectric layer 204, the first dummy gate layer 205, and the second dummy gate layer 206.

[0049] In this embodiment, the first gate dielectric layer 203 and the second gate dielectric layer 204 are made of silicon oxide; in other embodiments, the first gate dielectric layer and the second gate dielectric layer may also be made of silicon oxynitride.

[0050] In this embodiment, the first pseudo-gate layer 205 and the second pseudo-gate layer 206 are made of polycrystalline silicon.

[0051] Please refer to Figure 6 The first sidewall 207 is formed on the sidewalls of the first gate dielectric layer 203 and the first dummy gate layer 205, and the second sidewall 208 is formed on the sidewalls of the second gate dielectric layer 204 and the second dummy gate layer 206.

[0052] In this embodiment, the method for forming the first sidewall 207 and the second sidewall 208 includes: forming a sidewall material layer (not shown) on the isolation layer 202, the first dummy gate layer 205, the second dummy gate layer 206, the sidewalls of the first dummy gate layer 205 and the first gate dielectric layer 203, and the sidewalls of the second dummy gate layer 206 and the second gate dielectric layer 204; and etching the sidewall material layer back until the top surfaces of the isolation layer 202, the first dummy gate layer 205, and the second dummy gate layer 206 are exposed, thereby forming the first sidewall 207 and the second sidewall 208.

[0053] In this embodiment, the sidewall material layer is formed using atomic layer deposition (ALD).

[0054] The materials of the first sidewall 207 and the second sidewall 208 include low-k materials; the low-k materials include SiOC, SiOCN, or SiBCN. In this embodiment, the materials of the first sidewall 207 and the second sidewall 208 are SiOC.

[0055] Please refer to Figure 7 Using the first sidewall 207, the second sidewall 208, the first dummy gate layer 205, and the second dummy gate layer 206 as masks, the first region I and the second region II are etched respectively. A first source / drain opening (not shown) is formed in the first region I, and a second source / drain opening (not shown) is formed in the second region II. A first source / drain doped layer 209 is formed in the first source / drain opening, and a second source / drain doped layer 210 is formed in the second source / drain opening.

[0056] In this embodiment, the method for forming the first source / drain doped layer 209 and the second source / drain doped layer 210 includes: forming a first epitaxial layer (not shown) in the first source / drain opening using an epitaxial growth process, and forming a second epitaxial layer (not shown) in the second source / drain opening; during the formation of the first epitaxial layer and the second epitaxial layer, an in-situ doping process is used to dope the first source / drain ions into the first epitaxial layer to form the first source / drain doped layer 209, and doping the second source / drain ions into the second epitaxial layer to form the second source / drain doped layer 210.

[0057] The first source / drain ion includes N-type ions or P-type ions; the second source / drain ion includes P-type ions or N-type ions. In this embodiment, the first source / drain ion is an N-type ion, and the second source / drain ion is a P-type ion.

[0058] Please refer to Figure 8 The dielectric layer 211 is formed on the substrate, and the dielectric layer 211 covers the sidewalls of the first pseudo gate layer 205 and the second pseudo gate layer 206.

[0059] In this embodiment, the method for forming the dielectric layer 211 includes: forming an initial dielectric layer (not shown) on the substrate, the initial dielectric layer covering the first source / drain doped layer 209, the second source / drain doped layer 210, the first dummy gate layer 205, and the second dummy gate layer 206; and planarizing the initial dielectric layer until the top surfaces of the first dummy gate layer 205 and the second dummy gate layer 206 are exposed, thereby forming the dielectric layer 211.

[0060] In this embodiment, the dielectric layer 211 is made of silicon oxide; in other embodiments, the dielectric layer may also be made of low-K dielectric material (low-K dielectric material refers to dielectric material with a relative permittivity of less than 3.9) or ultra-low-K dielectric material (ultra-low-K dielectric material refers to dielectric material with a relative permittivity of less than 2.5).

[0061] Please refer to Figure 9 A plurality of the first dummy gate layers 205 and a plurality of the second dummy gate layers 206 are removed, and a plurality of the first gate openings 212 and a plurality of the second gate openings 213 are formed in the dielectric layer 211.

[0062] In this embodiment, the process of removing the first dummy gate layer 205 and the second dummy gate layer 206 employs a wet etching process. In other embodiments, the process of removing the first dummy gate layer and the second dummy gate layer may also employ a dry etching process.

[0063] Please refer to Figure 10 An initial sacrificial layer 214 is formed on the dielectric layer 211, within the first gate opening 212, and within the second gate opening 213.

[0064] In this embodiment, the initial sacrificial layer 214 is made of photoresist.

[0065] Please refer to Figure 11 The initial sacrificial layer 214 is patterned, and a sacrificial layer 215 exposing the second gate opening 213 is formed on the dielectric layer 211 and within the first gate opening 212.

[0066] In this embodiment, the method for patterning the initial sacrificial layer 214 includes: forming a patterned layer (not shown) on the initial sacrificial layer 214, the patterned layer exposing the top surface of the initial sacrificial layer 214 located on the second region II; using the patterned layer as a mask, using plasma etching to remove the initial sacrificial layer 214 located on the second region II to form the sacrificial layer 215.

[0067] In this embodiment, after the plasma etching process, the ions remaining in the second sidewall 208 include one or more of nitrogen ions and hydrogen ions.

[0068] In this embodiment, the plasma in the plasma etching process includes one or more of NH3, NF3, N2 and H2; the inert gas in the plasma etching process includes one or more of He and Ar.

[0069] Please refer to Figure 12 Using the sacrificial layer as a mask, the second sidewall 208 is compensated by doping compensation ions into each of the second sidewalls 208.

[0070] In this embodiment, the compensation ions doped within each of the second sidewalls 208 include one or more of nitrogen ions and hydrogen ions.

[0071] In this embodiment, after the compensation treatment, the concentration range of residual plasma and doped compensation ions in each of the second sidewalls 208 is 0% to 80%.

[0072] In this embodiment, the plasma in the compensation process includes one or more of NH3, NF3, N2, and H2; the inert gas in the plasma etching process includes one or more of He and Ar.

[0073] Please refer to Figure 13 After the compensation process, the second gate dielectric layer 204 is etched, and the etching rate difference of each of the second sidewalls 208 is within a preset range.

[0074] In this embodiment, by using the sacrificial layer 215 as a mask, the second sidewall 208 is compensated by doping each of the second sidewalls 208 with compensating ions to make up for the material differences in some of the second sidewalls 208 caused by the previous process. This improves the etching uniformity of each of the second sidewalls 208 when etching the second gate dielectric layer 204, thereby ensuring that the height of each of the removed second sidewalls 208 remains balanced, so that the height of the subsequently formed second gate layer remains balanced. This reduces the performance differences of each transistor structure formed on the second region II, thereby improving the performance of the final semiconductor structure.

[0075] In this embodiment, by removing the second gate dielectric layer 204, the threshold voltages of the transistor structures finally formed on the first region I and the second region II are different, thereby meeting the requirements of circuit design.

[0076] Please refer to Figure 14 After removing the second gate dielectric layer 204, the method further includes: removing the sacrificial layer 215; after removing the sacrificial layer 215, forming a first gate layer 216 in the first gate opening 212, wherein the first gate dielectric layer 203, the first sidewall 207 and the first gate layer 216 constitute a first gate structure; and forming a second gate layer 217 in the second gate opening 213, wherein the second sidewall 208 and the second gate layer 217 constitute a second gate structure.

[0077] In this embodiment, the process of removing the sacrificial layer 215 is an ashing process.

[0078] The materials of the first gate layer 216 and the second gate layer 217 include metals, such as tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the material of the first gate layer 216 and the second gate layer 217 is tungsten.

[0079] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A dielectric layer is formed on the substrate, the dielectric layer having a first gate opening located on the first region and a second gate opening located on the second region, the first gate opening having a first sidewall, the second gate opening having a second sidewall, the bottom of the first gate opening having a first gate dielectric layer, and the bottom of the second gate opening having a second gate dielectric layer. An initial sacrificial layer is formed on the dielectric layer, inside the first gate opening, and inside the second gate opening; The initial sacrificial layer is patterned to form a sacrificial layer that exposes the second gate opening on the dielectric layer and within the first gate opening; Using the sacrificial layer as a mask, the second sidewall is compensated by doping each second sidewall with compensation ions. After the compensation process, the second gate dielectric layer is etched, and the etching rate difference of each second sidewall is within a preset range.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The patterning process for the initial sacrificial layer includes: forming a patterned layer on the initial sacrificial layer, the patterned layer exposing the top surface of the initial sacrificial layer located on the second region; using the patterned layer as a mask, using plasma etching to remove the initial sacrificial layer located on the second region to form the sacrificial layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, After the plasma etching process, the ions remaining in the second sidewall include one or more of nitrogen ions and hydrogen ions.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The compensating ions doped within each of the second sidewalls include one or more of nitrogen ions and hydrogen ions.

5. The method for forming a semiconductor structure as described in claim 3, characterized in that, After the compensation treatment, the concentration range of residual plasma and doped compensation ions in each of the second sidewalls is 0% to 80%.

6. The method for forming a semiconductor structure as described in claim 2, characterized in that, The plasma used in the plasma etching process includes one or more of NH3, NF3, N2, and H2; the inert gas used in the plasma etching process includes one or more of He and Ar.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The plasma used in the compensation process includes one or more of NH3, NF3, N2, and H2; the inert gas used in the plasma etching process includes one or more of He and Ar.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The materials of the first sidewall and the second sidewall include: low-K materials; the low-K materials include: SiOC, SiOCN or SiBCN.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the dielectric layer, the first sidewall, the second sidewall, the first gate dielectric layer, the second gate dielectric layer, the first gate opening, and the second gate opening includes: forming a plurality of first gate dielectric layers and a plurality of second gate dielectric layers on the substrate, wherein the plurality of first gate dielectric layers are located in a first region and the plurality of second gate dielectric layers are located in a second region; forming a first dummy gate layer on the first gate dielectric layer and forming a second dummy gate layer on the second gate dielectric layer; forming a first sidewall on the sidewall of the first gate dielectric layer and the first dummy gate layer, and forming a second sidewall on the sidewall of the second gate dielectric layer and the second dummy gate layer; forming the dielectric layer on the substrate, wherein the dielectric layer covers the sidewall of the first dummy gate layer and the second dummy gate layer; removing the plurality of first dummy gate layers and the plurality of second dummy gate layers, and forming a plurality of first gate openings and a plurality of second gate openings within the dielectric layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process of forming the dielectric layer, the first sidewall, the second sidewall, the first gate dielectric layer, and the second gate dielectric layer further includes: using the first sidewall, the second sidewall, the first dummy gate layer, and the second dummy gate layer as masks, etching the first region and the second region respectively, forming a first source / drain opening in the first region, and forming a second source / drain opening in the second region; forming a first source / drain doped layer in the first source / drain opening, and forming a second source / drain doped layer in the second source / drain opening.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the initial sacrificial layer includes photoresist.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, After removing the second gate dielectric layer, the method further includes: removing the sacrificial layer; after removing the sacrificial layer, forming a first gate layer in the first gate opening, wherein the first gate dielectric layer, the first sidewall, and the first gate layer constitute a first gate structure; and forming a second gate layer in the second gate opening, wherein the second sidewall and the second gate layer constitute a second gate structure.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process for removing the sacrificial layer includes: an ashing process.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate includes a base.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate includes a base and a fin structure located on the base, the fin structure spanning the first region and the second region.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, After forming the fin structure, the method further includes: forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewalls of the fin structure, and the top surface of the isolation layer being lower than the top surface of the fin structure.

17. The method for forming a semiconductor structure as described in claim 15, characterized in that, The fin structure is a single-layer structure.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The fin structure includes: several layers of channel layers that overlap along the normal direction of the substrate surface.

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