ZVS auxiliary buffer for switching converters

Abstract

A voltage converter includes: a voltage input; a transformer including a primary winding coupled to the voltage input; a main switch coupled to the primary winding at a node; and a buffer circuit coupled to the voltage input and the node, the buffer circuit including a controllable switch having a gate and a source. A control circuit coupled to the main switch and configured to turn the main switch on and off to convert an input voltage supplied to the voltage input into an output voltage different from the input voltage. The gate is coupled to the source to prevent the controllable switch from turning on.

Description

Technical Field

[0001] This disclosure relates to various aspects of output power distribution, and more specifically to switching converters with snubbers. Background Technology

[0002] A voltage converter is a power converter in which an input direct current (DC) voltage is increased or decreased to a desired DC voltage level at the converter's output. An example of a typical prior art voltage converter 100 (shown as a flyback converter topology) is illustrated in the figure. The voltage converter 100 has an input terminal 101 for coupling an input voltage Vin to the voltage converter 100. The voltage converter 100 includes a transformer 102 and a controllable switch 104, the transformer 102 having a primary winding 103 coupled to the input terminal 101. The switch 104 is typically a metal-oxide-semiconductor field-effect transistor (MOSFET) with a control input, drain, and source terminals. Control circuitry (not shown) is coupled to this control input to provide control signals for controlling the timing of the on and off switching of the switch 104. This control circuitry typically includes pulse width modulation (PWM) circuitry. In operation, when the switch 104 is turned on, the inductor current in the primary winding 103 increases, thereby storing energy in its magnetic field. When transistor switch 104 is open, this energy is transferred via the secondary winding 105 of transformer 102 to output capacitor 106 and load (not shown). Disadvantages of such conventional voltage converter circuits include the generation of switching voltage and current stress, which leads to inefficient power conversion.

[0003] Therefore, a buffer or clamping circuit 107, including a buffer diode 108 connected in series with the buffer capacitor 109, is added to the voltage converter 100. The buffer circuit 107 may also include a buffer resistor (not shown) coupled in parallel with the buffer capacitor 109, and may also be referred to as an RCD clamp. The buffer circuit 107 is designed to suppress spikes generated at the drain of the MOSFET 104 caused by large current pulses and leakage (parasitic) inductance in the circuit when the MOSFET 107 is turned off.

[0004] Referring to Figures 2-4, the equivalent circuits for the voltage converter 100 of Figure 1 during time periods t0-t4 (Figure 4) are illustrated, showing the equivalent circuits during time periods t0-t2 (Figure 2) and t2-t4 (Figure 3). The equivalent circuit 200 illustrated in Figure 2 shows parasitic capacitances, including an equivalent capacitor 201 connected from node 202 that couples switch 104 to the primary winding 103. Furthermore, the parasitic capacitance indicated by diode capacitor 203 is illustrated as being connected in parallel with buffer diode 108. Referring to Figure 4, switch 104 is turned on at the beginning of time interval t0-t1. Therefore, Vin is applied across the primary winding 103, and when switch 104 is turned on, the primary current Ipri through the primary winding 103 increases linearly. Additionally, buffer diode 108 is reverse biased. At t1, switch 104 is turned off, and the energy stored in the form of current through the magnetizing inductance and leakage inductance pushes up the drain voltage Vds of switch 104, charging all associated node capacitors until D1 and D2 become forward biased. C1 is large enough to capture the energy associated with the leakage inductance and control the peak voltage on switch 104. A buffer resistor can be used to remove charge from C1 each cycle, unless parasitic C2 is used. In response to the primary current Ipri reaching 0A, the voltage on the primary is the reflected voltage of the secondary on the transformer according to the primary to secondary turns ratio n. This reflected voltage is maintained until the secondary current Isec reaches 0A at t2 and transformer 102 is discharged.

[0005] Referring to Figures 3 and 4, at t2, the drain of the node capacitor (Ceq) of Q1 is charged to Vin + Vrefl, which places the reflected voltage Vrefl across the primary inductor L1. This node capacitor and the primary inductor L1 form a natural resonant LC oscillating circuit (tank). The natural resonance with a linear component limits the voltage swing to the initial conditions. That is, the node capacitor only discharges to Vin - Vrefl. It should be noted that at t2, the resonant oscillating circuit has 0 A, no magnetic energy, and maximum voltage electric field energy. At t3, the resonant oscillating circuit has maximum magnetic energy and 0 electric field energy (effectively, VL1 = 0). At t4, the resonant oscillating circuit has 0 A, no magnetic energy, and maximum electric field energy. Point t4 is the point where the quasi-resonant controller will turn on Q1 at the minimum drain voltage to reduce switching losses. As is done in quasi-resonant mode control, switching Q1 is turned on at or near the minimum value of the first ringing valley in an attempt to turn on switch 104 at the lowest available voltage during ringing. However, even if the minimum voltage occurs at the first valley, switch 104 still experiences a significant voltage 400, which is sufficient to produce low efficiency in voltage switching, stray EMI, etc., compared to zero-voltage switching (ZVS).

[0006] Figure 5 illustrates an example timing diagram showing the drain-source voltage and primary current waveforms at various points for the switch 104 of the flyback converter in Figure 1, where the switch turn-on occurs during the second valley.

[0007] Therefore, there is a need to address the shortcomings described above in order to provide improved efficiency through reduced conduction losses in buffer circuits and power converter topologies. Summary of the Invention

[0008] According to one aspect of this disclosure, a voltage converter includes: a voltage input; a transformer including a primary winding coupled to the voltage input; a main switch coupled to the primary winding at a node; and a buffer circuit coupled to the voltage input and the node, the buffer circuit including a controllable switch having a gate and a source. A control circuit is coupled to the main switch and configured to turn the main switch on and off to convert an input voltage supplied to the voltage input into an output voltage different from the input voltage. The gate is coupled to the source to prevent the controllable switch from turning on.

[0009] According to another aspect of this disclosure, a method of manufacturing a voltage converter includes: coupling a transformer including a primary winding coupled to a voltage input; coupling a main switch to the primary winding at a node; and coupling a buffer circuit to the voltage input and the node. The buffer circuit includes a controllable switch having a gate and a source. The method further includes: coupling control circuitry coupled to the main switch, and configuring the voltage input to turn the main switch on and off to convert an input voltage supplied to the voltage input into an output voltage different from the input voltage. The gate is coupled to the source to prevent the controllable switch from turning on. Attached Figure Description

[0010] The accompanying drawings illustrate embodiments currently conceived for carrying out the present invention.

[0011] In the attached diagram:

[0012] Figure 1 is a schematic diagram of a DC / DC flyback voltage converter known in the art.

[0013] Figure 2 is an equivalent schematic diagram of the flyback converter in Figure 1.

[0014] Figure 3 is an equivalent schematic diagram during a portion of one operating cycle of the flyback converter in Figure 1.

[0015] Figure 4 is a timing diagram illustrating the voltage and current waveforms at various points for the flyback converter of Figure 1 during one operating cycle, according to an example.

[0016] Figure 5 is a timing diagram illustrating the voltage and current waveforms at various points for the flyback converter of Figure 1 during one operating cycle, according to another example.

[0017] Figure 6 This is a schematic diagram of a DC / DC flyback voltage converter according to one embodiment of the present invention.

[0018] Figure 7 yes Figure 6 The equivalent schematic diagram of the flyback converter.

[0019] Figure 8 is Figure 6 An equivalent schematic diagram during a portion of the operating cycle of a flyback converter.

[0020] Figure 9 This is a sequence diagram that illustrates, based on an example, the sequence of events during a single running cycle. Figure 6 The voltage and current waveforms of the flyback converter at various points.

[0021] Figure 10 This is a sequence diagram that illustrates, according to another example, the timing during a running cycle for Figure 6 The voltage and current waveforms of the flyback converter at various points.

[0022] Figure 11 This illustrates the process during a running loop, based on another example. Figure 6 The waveform of the flyback converter.

[0023] Figure 12 Examples of the same Figure 6 The nonlinear circuit resonant response of the circuit is compared with the simulated superposition of the linear circuit resonant response from the circuit in Figure 1.

[0024] While this disclosure allows for various modifications and alternatives, specific embodiments thereof have been illustrated by way of example in the accompanying drawings and described in detail herein. However, it should be understood that the description of specific embodiments herein is not intended to limit this disclosure to the particular forms disclosed, but rather, the invention is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure. It should be noted that in all the views of the accompanying drawings, corresponding reference numerals indicate corresponding portions. Detailed Implementation

[0025] Examples of this disclosure will now be described more fully with reference to the accompanying drawings. The following description is exemplary in nature only and is not intended to limit the disclosure, its application, or its uses.

[0026] The provision of exemplary embodiments makes this disclosure thorough and will fully communicate the scope to those skilled in the art. Numerous specific details, such as examples of particular components, apparatus, and methods, are set forth to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that specific details are not required, exemplary embodiments may be embodied in many different forms, and none should be construed as limiting the scope of this disclosure. In some exemplary embodiments, well-known processes, well-known apparatus structures, and well-known techniques are not described in detail.

[0027] Although the disclosure herein is detailed and precise to enable those skilled in the art to practice the invention, the physical embodiments disclosed herein are merely illustrative, and the invention may be embodied in other specific structures. While preferred embodiments have been described, changes in detail may be made without departing from the invention as defined by the claims.

[0028] A schematic diagram of a DC / DC voltage converter 600 that overcomes the above-mentioned drawbacks is illustrated in Figure 6 The voltage converter 600 has an input terminal 601 for coupling an input voltage Vin to the voltage converter 600. The voltage converter 600 includes a transformer 602 and a controllable switch 604, the transformer 602 having a primary winding 603 coupled to the input terminal 601. The switch 604 is typically a MOSFET having a control input (e.g., a gate terminal), a drain terminal, and a source terminal. Control circuitry 605 is coupled to the control input to provide a control signal for timing the on and off transitions of the switch 604. Control circuitry 605 typically includes a pulse width modulation (PWM) circuit that generates a PWM signal for turning the switch 604 on and off. In operation, when the switch 604 is on, the inductor current in the primary winding 603 increases, thereby storing energy in its magnetic field. When the transistor switch 604 is off, this energy is transferred via the secondary winding 606 of the transformer 602 to the output capacitor 607 and the load (not shown).

[0029] The improved buffer or clamping circuit 608 is coupled in parallel with the primary winding 603 of the transformer 602 and is designed to reduce the voltage Vds at the drain of the MOSFET 604. The buffer circuit 608 includes a buffer capacitor 609 coupled in series with a buffer switch 610. According to an embodiment, the buffer switch 610 is a superjunction MOSFET with a nonlinear capacitance responsive to the magnitude of the drain-source voltage Vds on the FET 610. The main switch 604 can be a superjunction FET or a non-superjunction FET.

[0030] refer to Figures 7-9 ,against Figure 6The voltage converter 600 is designed for the time period t0-t4. Figure 9 The time series diagram illustrates the time period t0-t2. Figure 7 ) and time period t2-t4 ( Figure 8 The equivalent circuit during the period. Figure 7 The equivalent circuit 700 illustrated shows the parasitic capacitance including an equivalent capacitor (Ceq) 701 connected from node 702 that couples switch 604 to primary winding 603. Furthermore, the parasitic capacitance of buffer switch 610 is indicated by capacitor (C2) 703, shown as being connected in parallel with the body diode (D2) 704 of buffer FET 610. Reference Figure 9 Switch 604 is turned on at the start of time interval t0-t1. Therefore, Vin is applied across the primary winding 603, and the primary current Ipri through the primary winding 603 increases linearly when switch 604 is turned on. Additionally, buffer diode 610 is reverse-biased. At t1, switch 604 is turned off, and the energy stored in the magnetizing inductance and leakage inductance in the form of current pushes up the drain voltage Vds of switch 604 and charges all associated node capacitors until D1 and D2 become forward-biased. C1 is large enough to capture the energy associated with the leakage inductance and control the peak voltage on switch 604. Buffer resistors can be used to remove charge from C1 each cycle unless parasitic C2 is used. In response to the primary current Ipri reaching 0A, the voltage on the primary is the reflected voltage of the secondary winding on the transformer, according to the primary to secondary turns ratio n. This reflected voltage is maintained until the secondary current Isec reaches 0A at t2 and transformer 602 is discharged.

[0031] During the time period t2-t4 Figure 8The equivalent circuit 800 illustrated emphasizes the nonlinear capacitance (C2) of the superjunction FET 610. The nonlinear capacitance of the superjunction FET 604 acts against the magnetizing inductor to force the drain voltage of the main switch to zero volts or near zero volts. In response to the transformer depleting its energy (e.g., when the voltage across the drain of switch 604 begins to shift downwards), the buffer FET 610 starts at 0Vds. Therefore, its Coss capacitance is large and remains so until it forms a higher Vds voltage (e.g., ~40Vds). Meanwhile, switch 604 is at its peak voltage and has a small associated Coss capacitance until its Vds drops below, for example, ~40Vds. The Coss capacitance of the buffer FET 610 can, for example, be two orders of magnitude larger at 0V than at 40V. This larger capacitance of the buffer FET 610 sustains a longer buffer voltage across the magnetizing inductor, which causes the "reverse" current ramp in the magnetizing inductor to rise. This reverse magnetizing current gradually builds up until the drain voltage Vds of the main switch 604 decreases to the input voltage. At this point, the buffer FET 610 has a buffer voltage across it, and the effective Coss is therefore small. However, the gradually increasing reverse magnetizing current reflects a much larger Coss of the buffer FET 610 starting at 0Vds, resulting in the primary magnetizing inductor 603 having energy to swing the main switch node 702 further than the natural resonance of a constant capacitor. As the magnetizing current decreases and the Coss of switch 604 increases significantly below 40V, especially if switch 604 is a superjunction FET, this voltage swing slows down as the main switch drain voltage Vds approaches zero volts.

[0032] like Figure 6 As illustrated and discussed above, the buffer switch 610 can be a controllable switch (e.g., a MOSFET), and more specifically, a superjunction MOSFET. While the buffer switch 610 can be used in a controlled manner by controlling the gate-source voltage Vgs in some circuit applications and configurations, according to the embodiments disclosed herein, the buffer switch 610 is not controlled to be in an on-state or off-state. Instead, its gate is attached to a node (e.g., to the source node) such that it is kept in an off-state (e.g., Vgs = 0V). Therefore, the buffer circuit 608 is not an actively controlled circuit causing current flow through the FET, which bypasses the body diode 704 in response to being controlled into conduction mode. Thus, the nonlinear and non-constant capacitance of the superjunction FET 610 is used to swing the drain voltage Vds of switch 604 toward zero. In this way, no control circuitry is required in the circuit design of the voltage converter 600 to switch the buffer switch 610 between the on-state and off-state.

[0033] refer to Figure 8 and Figure 9 At t2, the drain of the node capacitor Q1 (e.g., switch 604) is charged to Vin + Vrefl, which places Vrefl across the primary inductor L1 (e.g., primary winding 603). This node capacitor and the primary inductor L1 form a natural resonant LC oscillating circuit. C2 is large and makes a significant contribution to the resonance. In one example, C2 is several orders of magnitude larger than Ceq until approximately 40V is formed across C2, causing the capacitance of C2 to become very small again. This nonlinearity of C2 gradually increases the magnetization energy in the oscillating circuit to the level of a large capacitor at the beginning of the cycle, but then decreases by several orders of magnitude as a voltage is formed across it. As the resonance continues, the gradually increasing magnetic energy allows Ceq to swing much further than a linear resonant oscillating circuit. The proper selection of the superjunction FET 610 allows for ZVS without requiring the control of the on-state of the clamped FET Q2. This resonance also removes charge from C1, eliminating the need for a bleed resistor. Note that at t2, the resonant oscillation circuit has 0 A, no magnetic energy, and maximum voltage electric field energy. At t3, the resonant oscillation circuit has maximum magnetic energy and 0 electric field energy (VL1 = 0 effectively). At t4, the resonant oscillation circuit has 0 A, no magnetic energy, and maximum electric field energy. Point t4 is the optimal point to turn on Q1 604 at the minimum drain voltage during quasi-resonant control to reduce switching losses. Figure 9 As illustrated, the voltage swing caused by the buffer FET 610 reduces Vds to 0V900 or close to 0V900 to achieve ZVS.

[0034] Figure 10 An example of a timing diagram is shown, which illustrates the relationship between timing and timing. Figure 6 The drain-source voltage and primary current waveforms at various points of the flyback converter's switch 604, wherein the switch-on occurs during the first valley (e.g., in quasi-resonant control mode).

[0035] Figure 11 An example of a timing diagram is shown, which illustrates the relationship between timing and timing. Figure 6 The drain-source voltage and primary current waveforms of switch 604 in the flyback converter are shown, with switch turn-on occurring during the second valley. As illustrated, the drain voltage Vds experienced by switch 604 when it is turned on is low, thus reducing or eliminating damage to switch 604 caused by higher voltages even during the valley of the ringing cycle following the first valley. Therefore, ZVS can be maintained on subsequent valley switching. Furthermore, ZVS is maintained even if the output voltage is changed.

[0036] Figure 12 Examples of the same Figure 6The nonlinear circuit resonant response of the circuit is compared with the simulated superposition of the linear circuit resonant response of the circuit from Figure 1. The Ipri response 1200 and Vds response 1201 from the circuit from Figure 1 are shown as dashed lines, and from... Figure 6 The Ipri response 1202 and Vds response 1203 of the circuit are shown as solid lines. The voltage 1200 of the linear circuit can only cause the capacitor voltage Vrefl to swing by approximately Vin. Therefore, the minimum valley voltage produced by the linear circuit is Vin - Vrefl. However, the voltage 1202 of the nonlinear circuit can cause the voltage to swing down to 0V or close to 0V.

[0037] For most of t2, almost all of Vrefl is held across the magnetizing inductor, which causes the magnetizing current to gradually increase to the level of a resonant oscillating circuit with significantly greater energy (Cres). At t2b, the effective resonant capacitance drops by several orders of magnitude, so the gradually increasing magnetizing energy can drive the capacitor voltage much further than Vref1. At t2, the inductor current is 0 A, and Vds = Vin + Vrefl. At t2b, the voltage across C2 reaches the capacitor threshold voltage (e.g., 25 V), which causes the capacitance to drop by several orders of magnitude. At t3, the inductor current is at its maximum, Vds = Vin, and the voltage across inductor L1 is 0 V. At t4, the inductor current is 0 A, and the oscillating circuit energy is entirely capacitive.

[0038] The implementation of this disclosure allows Figure 6 The converter features a ZVS created by a nonlinear capacitor. Similar to a known RCD circuit, the leakage energy offset of the drain voltage of Q1 is effectively clamped. However, the bleed resistor of a typical RCD circuit coupled in parallel with capacitor C1 is not required because the charge resulting from the capture of leakage energy from the clamped capacitor is removed. Furthermore, the complex control of the active FET implementing the ZVS and its associated circuitry is avoided, thus eliminating the need for an isolated gate drive.

[0039] Although the invention has been described in detail with reference to only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, substitutions, alternatives, or equivalent arrangements not previously described but commensurate with the spirit and scope of this disclosure. Furthermore, while various embodiments of this disclosure have been described, it should be understood that aspects of this disclosure may include only some of the described embodiments. Therefore, the invention should not be considered limited by the foregoing description, but only by the scope of the appended claims.

Claims

1. A voltage converter, comprising: Voltage input; A transformer, the transformer including a primary winding coupled to the voltage input; A main switch, which is coupled to the primary winding at a node; A buffer circuit coupled to the voltage input and the node, the buffer circuit including a controllable switch having a gate and a source; and A control circuit coupled to the main switch and configured to turn the main switch on and off to convert an input voltage supplied to the voltage input into an output voltage different from the input voltage; The gate is coupled to the source to prevent the controllable switch from being turned on; The voltage converter mentioned above is a flyback voltage converter; The controllable switch includes a superjunction metal-oxide-semiconductor field-effect transistor (MOSFET) having a nonlinear capacitance that responds to the magnitude of the drain-source voltage on the controllable switch. and The control circuit is configured to turn on the main switch near the minimum value of the valley of the ringing cycle to achieve zero-voltage switching (ZVS).

2. The voltage converter of claim 1, wherein the main switch comprises a non-superjunction MOSFET.

3. The voltage converter of claim 1, wherein the buffer circuit further comprises a capacitor coupled between the controllable switch and the voltage input.

4. The voltage converter of claim 3, wherein the buffer circuit lacks a discharge resistor coupled in parallel with the capacitor for removing charge from the capacitor.

5. The voltage converter according to claim 1, wherein the valley is a first ringing valley.

6. The voltage converter of claim 1, wherein the minimum value is zero volts.

7. The voltage converter of claim 6, wherein the transformer further comprises a secondary winding; and The voltage converter mentioned above includes: Voltage output; and A diode coupled between the secondary winding and the first terminal of the voltage output.

8. A method of manufacturing a voltage converter, comprising: Coupling includes a transformer whose primary winding is coupled to the voltage input; The main switch is coupled to the primary winding at one node; The buffer circuit is coupled to the voltage input and the node, and the buffer circuit includes a controllable switch having a gate and a source. A control circuit coupled to the main switch is configured to turn the voltage input on and off the main switch to convert the input voltage supplied to the voltage input into an output voltage different from the input voltage. as well as The control circuit is configured to turn on the main switch near the minimum value of the valley in the ringing cycle to achieve zero-voltage switching (ZVS). The gate is coupled to the source to prevent the controllable switch from being turned on; The voltage converter mentioned above is a flyback voltage converter; and The controllable switch includes a superjunction metal-oxide-semiconductor field-effect transistor (MOSFET) having a nonlinear capacitance that responds to the magnitude of the drain-source voltage on the controllable switch.

9. The method of claim 8, wherein the main switch comprises a non-superjunction MOSFET.

10. The method of claim 8, wherein the buffer circuit further comprises a capacitor coupled between the controllable switch and the voltage input.

11. The method of claim 10, wherein the buffer circuit lacks a discharge resistor coupled in parallel with the capacitor for removing charge from the capacitor.

12. The method of claim 8, wherein the valley is a first ringing valley.

13. The method of claim 8, wherein the minimum value is zero volts.

14. The method of claim 13, wherein the transformer further comprises a secondary winding; and The method further includes: A diode coupled between the secondary winding and the first terminal of the voltage output.

Images