Circuit board processing method with extremely narrow line pattern

Abstract

This application provides a method for processing a circuit board with an extremely narrow circuit pattern, comprising the following steps: providing a substrate, including a substrate layer, the substrate layer being divided into a circuit area and a lead area excluding the circuit area; providing a conductive lead layer in the lead area; providing a first mask in the circuit area, the first mask having multiple wire-forming grooves extending through it, with a portion of the substrate layer exposed at the bottom of the wire-forming grooves, and the ends of the conductive lead layers connected to the wire-forming grooves; plating copper at the bottom of the wire-forming grooves to form a base copper layer, the thickness of the base copper layer being less than the depth of the wire-forming grooves, and the base copper layer being connected to the conductive lead layer; electroplating on the base copper layer to form an electroplated layer, the electroplated layer and the base copper layer forming an extremely narrow circuit pattern, the extremely narrow circuit pattern being disposed within the wire-forming grooves; removing the first mask; providing a second mask in the circuit area, the second mask covering the extremely narrow circuit pattern; etching to remove the conductive lead layer and removing the second mask, thereby obtaining a circuit board with an extremely narrow circuit pattern.

Description

Technical Field

[0001] This application relates to a method for fabricating a circuit board with an extremely narrow circuit pattern. Background Technology

[0002] Semi-additive process (SAP) is a common process for fabricating circuits on copper-clad laminates. The semi-additive process mainly includes the following steps: First, a mask is placed on the copper foil layer of the copper-clad laminate; next, the mask is exposed and developed to form a photosensitive pattern, which has multiple plating grooves, with a portion of the copper foil layer exposed at the bottom of the plating grooves; next, copper is deposited within the plating grooves to form conductive lines; next, the photosensitive pattern is removed; finally, a portion of the copper foil layer is rapidly etched away.

[0003] However, for fine lines with narrow linewidths (e.g., less than 10 micrometers), the rapid etching process in the semi-additive process is prone to lateral etching, which weakens the adhesion between the remaining copper foil layer and the substrate layer of the copper clad laminate, ultimately leading to the peeling off of the fine lines. Summary of the Invention

[0004] In view of the above, it is necessary to provide a circuit board manufacturing method with extremely narrow circuit patterns to solve the above problems.

[0005] A method for fabricating a circuit board with an extremely narrow circuit pattern includes the following steps: providing a substrate, the substrate including a substrate layer, the substrate layer being divided into a circuit area and a lead area excluding the circuit area, the substrate layer being ABF. A conductive lead layer is disposed in the lead area. A first mask is disposed in the circuit area, the first mask having multiple through-holes, a portion of the substrate layer being exposed at the bottom of the through-holes, the ends of the conductive lead layers being connected to the through-holes. Copper is applied to the bottom of the through-holes to form a base copper layer, the thickness of the base copper layer being less than the depth of the through-holes, the base copper layer being connected to the conductive lead layer. Electroplating is performed on the base copper layer to form an electroplated layer, the electroplated layer and the base copper layer forming an extremely narrow circuit pattern, the extremely narrow circuit pattern being disposed within the through-holes. The first mask is removed. A second mask is disposed in the circuit area, the second mask covering the extremely narrow circuit pattern. The conductive lead layer and the second mask are etched away to obtain the circuit board with the extremely narrow circuit pattern.

[0006] Further, the substrate also includes a copper foil layer disposed on one side of the substrate layer; the ultra-narrow circuit pattern includes multiple conductive pads and ultra-narrow lines connecting each adjacent pair of conductive pads. Before the step "depositing a conductive lead layer in the lead area", the method further includes: creating an opening in the circuit area, with a portion of the copper foil layer exposed at the bottom of the opening. The step "plating copper at the bottom of the wire groove to form a base copper layer" further includes: filling a portion of the base copper layer into the inner circumference of the opening to form a hollow base pad, the base pad connecting the conductive lead layer. The step "depositing an electroplated layer on the base copper layer" further includes: filling a portion of the electroplated layer into the hollow base pad, the base pad and the portion of the electroplated layer filled into the hollow base pad forming a conductor, the conductor connecting the copper foil layer and the conductive pad.

[0007] Further, the forming groove includes a fine wire groove and a coarse wire groove connecting the fine wire groove, the coarse wire groove being provided corresponding to the opening. The step of "applying copper at the bottom of the forming groove to form a base copper layer" further includes: filling a portion of the base copper layer at the bottom of the fine wire groove to form a fine wire base copper layer. The step of "applying an electroplating layer on the base copper layer" further includes: electroplating the electroplating layer on the fine wire base copper layer to form the electroplating layer, the fine wire base copper layer and the portion of the electroplating layer disposed on the fine wire base copper layer constituting the ultra-narrow line.

[0008] Furthermore, the linewidth of the extremely narrow line is less than 10 micrometers.

[0009] Furthermore, the thickness of the conductive lead layer is the same as that of the base copper layer.

[0010] Further, the step "depositing a conductive lead layer in the lead area" includes: depositing a first dry film on the substrate layer; exposing and developing the first dry film to form a photosensitive pattern, the photosensitive pattern having a first opening through it, the first opening corresponding to the lead area, with a portion of the substrate layer exposed at the bottom of the first opening; plating copper within the first opening to form the conductive lead layer; and removing the first dry film.

[0011] Further, the step "setting a first mask in the circuit area" includes: setting a second dry film on the conductive lead layer, the second dry film covering the circuit area and the lead area, and exposing and developing the second dry film to form the first mask.

[0012] Further, the step "setting a second mask in the circuit area" includes: setting a third dry film on the ultra-narrow circuit pattern, the third dry film covering the circuit area and the lead area, and exposing and developing the third dry film to form the second mask, the second mask having a second opening through it, and the conductive lead layer being exposed at the bottom of the second opening.

[0013] Furthermore, it also includes the step of: setting a solder resist layer on the extremely narrow circuit pattern.

[0014] Furthermore, before the step of "electroplated on the base copper layer to form an electroplated layer", the method further includes: forming a copper oxide layer on the first mask, partially filling the wire forming groove with the copper oxide layer to form the base copper layer, and etching away the copper oxide layer formed on the first mask.

[0015] Compared to existing technologies, the processing method for a circuit board with an extremely narrow circuit pattern provided in this application forms a conductive lead layer and an extremely narrow circuit pattern in stages, then sets a second mask to cover the extremely narrow circuit pattern, and finally etches away the conductive lead layer, thereby reducing the etching of the extremely narrow circuit pattern during the etching process and reducing the floating line problem caused by side etching to the extremely narrow circuit. Attached Figure Description

[0016] Figure 1 This is a cross-sectional schematic diagram of a substrate provided in an embodiment of this application.

[0017] Figure 2 for Figure 1 The diagram shows a cross-section of the substrate after the opening is provided. Figure 3 (Cross-section view along line II-II).

[0018] Figure 3 for Figure 2 The top view of the substrate shown.

[0019] Figure 4 for Figure 2 The diagram shows a cross-sectional view of the substrate after the first dry film has been applied.

[0020] Figure 5 For exposure and development Figure 4 The diagram shows a cross-section of the first dry film after a photosensitive pattern has been formed.

[0021] Figure 6 for Figure 5 The diagram shows a cross-sectional view of the substrate after the conductive lead layer has been installed.

[0022] Figure 7 To remove Figure 6 A schematic diagram of the cross-section after the photosensitive pattern is shown. Figure 8 (Cross-section view along VII-VII).

[0023] Figure 8 for Figure 7 The top view of the conductive lead layer shown.

[0024] Figure 9 for Figure 8The diagram shows a cross-sectional view of the conductive lead layer after the second dry film has been applied.

[0025] Figure 10 For exposure and development Figure 9 The diagram shows a cross-sectional view of the second dry film after it has formed the first mask.

[0026] Figure 11 for Figure 10 The diagram shows a cross-sectional view of the first mask after the base copper layer is placed in the groove.

[0027] Figure 12 for Figure 11 The diagram shows a cross-section of the base copper layer after electroplating.

[0028] Figure 13 To remove Figure 12 The diagram shows a cross-section behind the first mask. Figure 14 (Cross-section view along XIII-XIII).

[0029] Figure 14 for Figure 13 A top view of the extremely narrow circuit diagram shown.

[0030] Figure 15 for Figure 14 The diagram shown is a cross-sectional view of the extremely narrow circuit pattern after the third dry film is installed.

[0031] Figure 16 For exposure and development Figure 15 The diagram shows a cross-section of the second mask formed after the third dry film is produced.

[0032] Figure 17 To remove Figure 16 The diagram shows a cross-section of the conductive lead layer shown.

[0033] Figure 18 This is a cross-sectional schematic diagram of a circuit board provided in an embodiment of this application.

[0034] Explanation of main component symbols

[0035] Circuit board 100

[0036] Extremely narrow circuit diagram 10

[0037] Conductive pad 11

[0038] Extremely narrow line 12

[0039] Conductive lead layer 30

[0040] Substrate 20

[0041] 201 opening

[0042] Substrate layer 21

[0043] Copper foil layer 22

[0044] Line 23

[0045] Lead area 24

[0046] First dry film 41

[0047] Photosensitive pattern 42

[0048] First window opening 421

[0049] First mask 43

[0050] 431

[0051] Fine groove 432

[0052] 433 coarse wire groove

[0053] Second dry film 434

[0054] Second mask 44

[0055] Second window 441

[0056] Third dry film 45

[0057] Base copper layer 51

[0058] Base pad 511

[0059] Fine-line base copper layer 512

[0060] Electroplating layer 61

[0061] Conductor 71

[0062] Thickness direction X

[0063] Width W

[0064] Depth D

[0065] Thickness H1, H2, H3

[0066] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0067] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0068] Please see Figure 18This application provides a method for processing a circuit board 100 with an ultra-narrow circuit pattern 10. The ultra-narrow circuit pattern 10 includes a plurality of conductive pads 11 and a plurality of ultra-narrow lines 12. The conductive pads 11 are spaced apart, and an ultra-narrow line 12 is disposed between every two adjacent conductive pads 11. The width W of the ultra-narrow line 12 is less than 10 micrometers.

[0069] Please see Figures 1 to 18 The processing method of the circuit board 100 includes the following steps:

[0070] S1: Please see Figure 1 A substrate 20 is provided, the substrate 20 including a substrate layer 21 and a copper foil layer 22 disposed on one side of the substrate layer 21. The substrate 20 has a thickness direction X, and along the thickness direction X, the substrate 20 is divided into a circuit region 23 and a lead region 24 other than the circuit region 23. The substrate layer 21 is ABF (Ajinomoto Build-up Film).

[0071] In this embodiment, please refer to Figure 2 Before step S2, the following are also included:

[0072] S 11: An opening 201 is provided in the circuit area 23. The opening 201 penetrates the substrate layer 21 along the thickness direction X. A portion of the copper foil layer 22 is exposed at the bottom of the opening 201. The opening 201 is adjacent to the lead area 24.

[0073] S2: Please see Figure 7 A conductive lead layer 30 is formed on the substrate layer 21 corresponding to the lead area 24 by copper plating (i.e., the conductive lead layer 30 and the copper foil layer 22 are respectively formed on opposite sides of the substrate layer 21). The conductive lead layer 30 can be used to connect to an electroplating electrode (not shown).

[0074] In this embodiment, please refer to Figures 4 to 7 In step S2, setting the conductive lead layer 30 specifically includes:

[0075] S21: Please see Figure 4 A first dry film 41 is disposed on the side of the substrate layer 21 opposite to the copper foil layer 22, and the first dry film 41 covers the opening 201.

[0076] S22: Please see Figure 5 The first dry film 41 is exposed and developed to form a photosensitive pattern 42, the photosensitive pattern 42 having a first window 421, and a portion of the substrate layer 21 within the lead area 24 is exposed at the bottom of the first window 421.

[0077] S22: Please see Figure 6 Copper is applied to the bottom of the first window 421 to form the conductive lead layer 30, which is disposed on the substrate layer 21 within the lead area 24.

[0078] S23: Please see Figure 7 and Figure 8 Remove the photosensitive pattern 42.

[0079] S3: Please see Figure 10 A first mask 43 is provided on the substrate layer 21 within the circuit area 23. The first mask 43 is provided with a plurality of wire forming grooves 431, and part of the substrate layer 21 is exposed at the bottom of the wire forming grooves 431.

[0080] In this embodiment, please refer to Figure 10 In step S3, the forming groove 431 includes a fine groove 432 and a coarse groove 433 connecting the fine groove 432. The coarse groove 433 is provided corresponding to the opening 201, and the end of the coarse groove 433 is exposed at the bottom of the opening 201. The cross-sectional width (not shown) of the coarse groove 433 is greater than the cross-sectional width (not shown) of the fine groove 432.

[0081] In the embodiments, please refer to Figures 9 to 10 In step S3, the specific steps for setting the first mask 43 include:

[0082] S31: Please see Figure 9 Please refer to the figure. A second dry film 434 is provided on the substrate layer 21. The second dry film 434 covers the conductive lead layer 30 and the opening 201.

[0083] S32: Please refer to Figure 10 The second dry film 434 is exposed and developed to form the first mask 43.

[0084] S4: Please see Figure 11 Copper is applied to the first mask 43 to form a copper layer (not shown). Part of the copper layer is filled into the bottom of the wire forming groove 431 to form a base copper layer 51. The thickness (not shown) of the base copper layer 51 is less than the depth D of the wire forming groove 431. The base copper layer 51 is connected to the conductive lead layer 30. The base copper layer 51 can be used as a seed layer during electroplating. The base copper layer 51 is connected to the substrate layer 21.

[0085] In this embodiment, please refer to Figure 11 The base copper layer 51 includes a hollow base pad 511 and a fine wire base copper layer 512. Step S4 includes the following steps:

[0086] S41: A portion of the copper plating layer is filled into the opening 201 and the coarse wire groove 433 to form a hollow base pad 511. The hollow base pad 511 is electrically connected to the conductive lead layer 30. The hollow base pad 511 is electrically connected to the copper foil layer 22. The thickness of the hollow base pad 511 (not indicated) is approximately the same as the thickness H1 of the conductive lead layer 30.

[0087] S42: A portion of the copper layer is filled into the bottom of the fine wire groove 432 to form a fine wire base copper layer 512. The thickness H2 of the fine wire base copper layer 512 is approximately the same as the thickness H1 of the conductive lead layer 30. The conductive lead layer 30 is electrically connected to the fine wire base copper layer 512.

[0088] In this embodiment, step S4 further includes:

[0089] S43: A portion of the copper plating layer on the first mask 43 is removed by micro-etching. Since the bonding force between the first mask 43 and the copper plating layer is weaker than the bonding force between the base copper layer 51 and the substrate layer 21, micro-etching can both retain the base copper layer 51 on the substrate layer 21 and remove a portion of the copper plating layer on the first mask 43. Removing a portion of the copper plating layer can avoid the waste of subsequent electroplating solution and facilitate electroplating in a predetermined area (i.e., within the wire forming groove 431).

[0090] S5: Please see Figure 12 Electroplating is performed on the base copper layer 51 to form an electroplated layer 61. The electroplated layer 61 and the layer disposed on the base copper layer 51 constitute the ultra-narrow circuit pattern 10. The thickness H3 of the ultra-narrow circuit pattern 10 is related to the depth D of the forming groove 431 (see [reference]). Figure 11 The same applies. Specifically, the base pad 511 and a portion of the electroplated layer 61 disposed on the base pad 511 constitute the conductive pad 11; the fine wire base copper layer 512 and a portion of the electroplated layer 61 disposed on the fine wire base copper layer 512 constitute the ultra-narrow line 12. In the electroplating process, since the conductive lead layer 30 electrically connects the base pad 511 and the fine wire base copper layer 512, after the conductive lead layer 30 is electrically connected to the electroplating cathode, the wire forming groove 432 is immersed in a copper-containing electroplating liquid. Under the action of current, copper ions in the electroplating liquid are deposited on the base pad 511 and the fine wire base copper layer 512, thereby forming the electroplated layer 61.

[0091] In this embodiment, step S5 further includes the following step:

[0092] S51: Please see Figure 12A portion of the electroplated layer 61 is filled into the hollow base pad 511. The portion of the electroplated layer 61 disposed in the opening 201 and the base pad 511 together form a conductor 71. The conductor 71 electrically connects the conductive pad 11 and the copper foil layer 22.

[0093] S6: Please see Figure 13 and Figure 14 Remove the first mask 43.

[0094] S7: Please see Figure 16 A second mask 44 is provided in the line area 23, the second mask 44 covers the ultra-narrow line pattern 10, and the conductive lead layer 30 is exposed to the second mask 44.

[0095] In this embodiment, please refer to Figure 15 Step S7, "setting a second mask 44 in the line area 23", specifically includes:

[0096] S71: A third dry film 45 is provided on the ultra-narrow circuit pattern 10, the third dry film 45 covering the circuit area 23 and the lead area 24.

[0097] S72: Expose and develop the third dry film 45 to form the second mask 44, the second mask 44 having a second opening 441 through it, the conductive lead layer 30 being exposed at the bottom of the second opening 441.

[0098] S8: Etch away the conductive lead layer 30 exposed in the lead region 24.

[0099] S9: Remove the second mask 44 to obtain the circuit board 100 with the extremely narrow circuit pattern 10.

[0100] In other embodiments of this application, the method for processing the circuit board 100 with the extremely narrow circuit pattern 10 further includes the step of:

[0101] S 10: Etch the copper foil layer 22 to form a conductive circuit layer (not shown). And provide a solder resist layer (not shown) on the conductive circuit layer and the ultra-narrow circuit pattern 10.

[0102] Compared with the prior art, the processing method of the circuit board 100 with the ultra-narrow circuit pattern 10 provided in this application forms the conductive lead layer 30 and the ultra-narrow circuit pattern 10 in stages, then sets the second mask 44 to cover the ultra-narrow circuit pattern 10, and finally etches away the conductive lead layer 30, thereby reducing the etching of the ultra-narrow circuit pattern 10 during the etching process and reducing the floating line problem caused by the side etching of the ultra-narrow circuit 12.

[0103] In addition, those skilled in the art may make other changes within the spirit of this application. Of course, all such changes made in accordance with the spirit of this application should be included within the scope of protection claimed in this application.

Claims

1. A method of processing a circuit board having an extremely narrow line pattern, characterized by, Including the following steps: A substrate is provided, the substrate including a substrate layer, the substrate layer being divided into a circuit area and a lead area other than the circuit area, the substrate layer being ABF; A conductive lead layer is provided in the lead area; A first mask is provided in the circuit area. The first mask is provided with a plurality of wire forming grooves. Part of the substrate layer is exposed at the bottom of the wire forming grooves. The end of the conductive lead layer is connected to the wire forming groove. A base copper layer is formed at the bottom of the wire-forming groove, the thickness of which is less than the depth of the wire-forming groove, and the base copper layer is connected to the conductive lead layer. Electroplating is performed on the base copper layer to form an electroplated layer, the electroplated layer and the base copper layer forming an extremely narrow circuit pattern, the extremely narrow circuit pattern being disposed in the wire forming groove; Remove the first mask; A second mask is provided in the line area, and the second mask covers the extremely narrow line pattern; Etching removes the conductive lead layer; as well as Remove the second mask to obtain the circuit board with the extremely narrow circuit pattern.

2. The processing method as described in claim 1, characterized in that, The substrate further includes a copper foil layer disposed on one side of the substrate layer; the ultra-narrow circuit pattern includes a plurality of conductive pads and an ultra-narrow circuit connecting each pair of adjacent conductive pads, and the step of "depositing a conductive lead layer in the lead area" further includes: An opening is provided in the circuit area, and a portion of the copper foil layer is exposed at the bottom of the opening; The step "applying copper to the bottom of the wire groove to form a base copper layer" further includes: A portion of the base copper layer is filled into the inner periphery of the opening to form a hollow base pad, which is connected to the conductive lead layer; The step "to form an electroplating layer on the base copper layer" further includes: A portion of the electroplated layer is filled into the hollow base pad. The base pad and the portion of the electroplated layer filled into the hollow base pad form a conductor, which connects the copper foil layer and the conductive pad.

3. The processing method as described in claim 2, characterized in that, The wire forming groove includes a fine wire groove and a coarse wire groove connecting the fine wire groove, the coarse wire groove being provided corresponding to the opening, and the step of "applying copper to the bottom of the wire forming groove to form a base copper layer" further includes: A portion of the base copper layer is filled into the bottom of the fine wire groove to form a fine wire base copper layer; The step "to form an electroplating layer on the base copper layer" further includes: The electroplated layer is formed by electroplating on the fine-line base copper layer, and the fine-line base copper layer and the portion of the electroplated layer disposed on the fine-line base copper layer constitute the ultra-narrow line.

4. The processing method as described in claim 3, characterized in that, The linewidth of the extremely narrow line is less than 10 micrometers.

5. The processing method as described in claim 1, characterized in that, The thickness of the conductive lead layer is the same as that of the base copper layer.

6. The processing method as described in claim 1, characterized in that, The step "to form a conductive lead layer in the lead area" includes: A first dry film is formed on the substrate layer; The first dry film is exposed and developed to form a photosensitive pattern. The photosensitive pattern has a first window that extends through it. The first window is located in the lead area, and a portion of the substrate layer is exposed at the bottom of the first window. Copper plating is applied within the first window to form the conductive lead layer; and Remove the first dry film.

7. The processing method as described in claim 1, characterized in that, The step "setting a first mask in the line area" includes: A second dry film is disposed on the conductive lead layer, the second dry film covering the circuit area and the lead area; and The second dry film is exposed and developed to form the first mask.

8. The processing method as described in claim 1, characterized in that, The step "setting a second mask in the line area" includes: A third dry film is disposed on the extremely narrow circuit pattern, the third dry film covering the circuit area and the lead area; and The third dry film is exposed and developed to form the second mask, the second mask having a second opening through it, and the conductive lead layer being exposed at the bottom of the second opening.

9. The processing method as described in claim 1, characterized in that, It also includes the following steps: A solder resist layer is provided on the extremely narrow circuit pattern.

10. The processing method as described in claim 1, characterized in that, The step of "electroplating on the base copper layer to form an electroplated layer" also includes: A copper plating layer is formed on the first mask, and a portion of the copper plating layer is filled into the wire trench to form the base copper layer; and The copper oxide layer formed on the first mask is removed by etching.

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