Quantum devices with low surface loss

Abstract

Circuitry and operating methods are provided that can help reduce surface losses in quantum devices. In one example, the quantum device may include a dielectric layer, a first electrode, and a second electrode. The dielectric layer may include a recess formed in its surface that reduces the thickness of the dielectric layer from a first thickness outside a covered area of ​​the recess to a second thickness within the covered area of ​​the recess. The second thickness may be less than the first thickness. The first electrode may be located within the covered area of ​​the recess. The second electrode may be electrically isolated from the first electrode through the dielectric layer. The first and second electrodes may be located on opposite surfaces of the dielectric layer.

Description

Background Technology

[0001] One or more embodiments of this document relate to quantum devices, and more specifically, to circuits and operating methods that help reduce surface losses in quantum devices. Summary of the Invention

[0002] The following overview is provided to offer a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or essential elements, or to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, devices, systems, methods, computer-implemented methods, apparatuses, and / or computer program products that can facilitate the reduction of surface losses in quantum devices are described.

[0003] According to one embodiment, the quantum device may include a dielectric layer, a first electrode, and a second electrode. The dielectric layer may include a recess formed in a first surface of the dielectric layer. The recess may reduce the thickness of the dielectric layer from a first thickness outside a covered area of ​​the recess to a second thickness within the covered area of ​​the recess. The second thickness may be less than the first thickness. The first electrode may be located within the covered area of ​​the recess. The second electrode may be located on a second surface of the dielectric layer. The second electrode may be electrically isolated from the first electrode through the dielectric layer. The first surface and the second surface may be located on opposite surfaces of the dielectric layer.

[0004] According to another embodiment, a quantum device may include a first capacitor and a Josephson junction. The first capacitor may have first and second electrodes electrically isolated by a dielectric layer between them. The first and second electrodes may be located on opposing surfaces of the dielectric layer. The first electrode is located within a recess formed in the surface of the dielectric layer, the recess reducing the thickness of the dielectric layer from a first thickness outside the recess to a second thickness within the recess. The second thickness may be less than the first thickness. The Josephson junction may be coupled to the first electrode of the first capacitor. The Josephson junction is located on the surface of the dielectric layer in a gap between the first electrode and a third electrode of the second capacitor.

[0005] According to another embodiment, a method may include forming a recess in a first surface of a dielectric layer. The recess may reduce the thickness of the dielectric layer from a first thickness outside a covered area of ​​the recess to a second thickness within the covered area of ​​the recess. The second thickness may be less than the first thickness. The method may further include forming a first electrode positioned within the covered area of ​​the recess. The method may also include forming a second electrode located on a second surface of the dielectric layer and electrically isolated from the first electrode by the dielectric layer. The first and second surfaces may be located on opposite surfaces of the dielectric layer. Attached Figure Description

[0006] Figure 1 A top view of an exemplary non-limiting device including a transmission sub-element according to one or more embodiments described herein is shown.

[0007] Figure 2 The image shown is a cut along line AA according to one or more embodiments described herein. Figure 1 A cross-sectional view of an exemplary non-limiting device.

[0008] Figure 3 One or more embodiments described herein are illustrated. Figure 1 A close-up view of the surface of an exemplary non-limiting device.

[0009] Figure 4 An exemplary non-limiting graph is shown according to one or more embodiments described herein, depicting along... Figure 1 The calculated profile of the square of the electric field amplitude is plotted on the surface of an exemplary non-limiting device.

[0010] Figure 5 The illustrations shown are based on one or more embodiments described herein. Figure 1 An exemplary non-limiting distribution of surface losses associated with an exemplary non-limiting device.

[0011] Figure 6 A top view of an example, non-limiting device according to one or more embodiments described herein is shown, which can facilitate the reduction of surface losses in quantum devices.

[0012] Figure 7 The image shown is a cut along line BB according to one or more embodiments described herein. Figure 6 A cross-sectional view of an example non-restricted device.

[0013] Figure 8 One or more embodiments depicted according to the description herein are shown. Figure 6 A close-up view of the surface of an exemplary non-limiting device.

[0014] Figure 9 Exemplary non-limiting graphs are shown according to one or more embodiments described herein, depicting the relationship between... Figure 1 and Figure 6 The corresponding calculation profile of the square of the electric field amplitude for the exemplary non-limiting device.

[0015] Figure 10 Cross-sectional views are shown according to one or more embodiments described herein, depicting the relationship with... Figure 1 An exemplary non-limiting energy density profile associated with an exemplary non-limiting device.

[0016] Figure 11 Cross-sectional views are shown according to one or more embodiments described herein, depicting the relationship with... Figure 6 An exemplary non-limiting energy density profile associated with an exemplary non-limiting device.

[0017] Figure 12-15 A cross-sectional view of an exemplary non-limiting device having recessed electrodes according to one or more embodiments described herein is shown.

[0018] Figure 16 A cross-sectional view of an exemplary non-limiting device according to one or more embodiments described herein is shown, which can facilitate the reduction of surface losses in quantum devices.

[0019] Figure 17 The following is illustrated after the growth or formation of a dielectric layer, according to one or more embodiments described herein. Figure 16 A cross-sectional view of an exemplary non-limiting device.

[0020] Figure 18 This illustrates a process following the deposition of one or more metal layers according to one or more embodiments described herein. Figure 17 A cross-sectional view of an exemplary non-limiting device.

[0021] Figure 19 The diagram illustrates the effect after reversing or flipping the orientation of the device according to one or more embodiments described herein. Figure 18 A cross-sectional view of an exemplary non-limiting device.

[0022] Figure 20 This illustrates the process after the processing layer is bonded to one or more metal layers, according to one or more embodiments described herein. Figure 19 A cross-sectional view of an exemplary non-limiting device.

[0023] Figure 21 The following is illustrated after substrate removal, according to one or more embodiments described herein. Figure 20 A cross-sectional view of an exemplary non-limiting device.

[0024] Figure 22 The following diagram illustrates the process after removing the insulating layer, according to one or more embodiments described herein. Figure 21 A cross-sectional view of an exemplary non-limiting device.

[0025] Figure 23 The following diagram illustrates the process after forming a recess, according to one or more embodiments described herein. Figure 22 A cross-sectional view of an exemplary non-limiting device.

[0026] Figure 24 The following diagram illustrates the application of an oxidation process according to one or more embodiments described herein. Figure 23 A cross-sectional view of an exemplary non-limiting device.

[0027] Figure 25 The following is illustrated after the removal of the oxide layer, according to one or more embodiments described herein. Figure 24 A cross-sectional view of an exemplary non-limiting device.

[0028] Figure 26 This illustrates a process following the deposition of one or more metal layers according to one or more embodiments described herein. Figure 25 A cross-sectional view of an exemplary non-limiting device.

[0029] Figure 27 The image shows the portion outside the recess after removing one or more metal layers, according to one or more embodiments described herein. Figure 26 A cross-sectional view of an exemplary non-limiting device.

[0030] Figure 28 A top view of an exemplary non-limiting device according to one or more embodiments described herein is shown, which can facilitate the reduction of surface losses in quantum devices.

[0031] Figure 29 The image shows a CC cut along the line according to one or more embodiments described herein. Figure 28 A cross-sectional view of an exemplary non-limiting device.

[0032] Figure 30 A top view of another exemplary non-limiting device according to one or more embodiments described herein is shown, which can facilitate the reduction of surface losses in quantum devices.

[0033] Figure 31 A top view is shown of an exemplary non-limiting device that can help reduce crosstalk and / or decouple between qubits according to one or more embodiments described herein.

[0034] Figure 32The image shows a cut along the DD line according to one or more embodiments described herein. Figure 31 A cross-sectional view of an exemplary non-limiting device.

[0035] Figure 33 The image shows a cut along the DD line according to one or more embodiments described herein. Figure 31 Another cross-sectional view of an exemplary non-limiting device.

[0036] Figure 34 The following diagram illustrates a cut-off along the EE according to one or more embodiments described herein. Figure 31 A cross-sectional view of an exemplary non-limiting device.

[0037] Figure 35 The following diagram illustrates a cut-off along the EE according to one or more embodiments described herein. Figure 31 Another cross-sectional view of an exemplary non-limiting device.

[0038] Figure 36 Exemplary non-limiting devices that facilitate impedance matching according to one or more embodiments described herein are shown.

[0039] Figure 37 Another exemplary non-limiting device that can facilitate impedance matching according to one or more embodiments described herein is shown.

[0040] Figure 38 A flowchart of an exemplary non-limiting method according to one or more embodiments described herein is shown, which can facilitate the reduction of surface losses in quantum devices.

[0041] Figure 39 A block diagram of an exemplary, non-limiting operating environment is shown, which may facilitate the description of one or more embodiments herein. Detailed Implementation

[0042] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, it is not intended to be construed as being bound by any express or implied information presented in the foregoing Background or Summary of the Invention or Detailed Description sections.

[0043] One or more embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals are used to denote the same elements throughout. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of the one or more embodiments. However, it will be apparent in various circumstances that the one or more embodiments described may be practiced without these specific details.

[0044] Unless otherwise specifically indicated, the following definitions are used in this disclosure. "Transmon" refers to a superconducting quantum system having a capacitor and a Josephson junction in parallel, which serves as a component of a qubit. The resonant quality factor Q and T1 represent measures of quantified coherence, which is the standard for the transmon as a resonator. T1 is the approximate time the transmon remains at its first excitation energy level. Q and T1 can be correlated to T1 = Q / 2πF, where F is the resonant frequency of the transmon. Q or T1 can be measured at low temperatures and for a minimum amount of energy in the transmon that corresponds to the transition between ground and the first level (e.g., temperatures on the order of 10 milliklvin or 0.01 kJ; and / or approximately corresponding to the energy of the product hF, where h is Planck's constant and F is the transmon frequency). "Loss" refers to a physical mechanism in or around the transmon element that dissipates some of the transmon's energy and limits its time remaining at the first level. The term "surface loss" refers to a loss source typically located on the top surface of the transmon component. The term "two-level system" (TLS) refers to a two-state quantum system that can exist as a superposition of two quantum states. Unwanted TLS can act as localized discrete energy trapping sites (and loss sources) for transporters. Unwanted TLS is typically found in disordered regions of materials, far from perfectly crystalline regions, such as at surfaces or boundaries where natural atomic boundaries are stretched or broken.

[0045] Traditional computers operate on binary numbers (or bits), which store or represent information as binary states to perform computation and information processing functions. In contrast, quantum computing devices operate on qubits (or quantum bits), which store or represent information as both binary states and a superposition of binary states. To do this, quantum computing devices utilize quantum mechanical phenomena such as entanglement and interference.

[0046] Quantum computing uses qubits as its basic unit, instead of classical computing bits. A qubit (e.g., a quantum binary digit) is a quantum mechanical simulation of a classical bit. While a classical bit can be used only in one of two ground states (e.g., 0 or 1), a qubit can be used in a superposition of these ground states (e.g., α|0〉+β|1〉, where α and β are complex scalars such that |α| 2 +|β| 2=1), thus allowing multiple qubits to theoretically hold more information exponentially than the same number of classical bits. Therefore, theoretically, quantum computers (e.g., computers that use qubits instead of just classical bits) can quickly solve problems that might be extremely difficult for classical computers. A bit in a conventional computer is simply a binary digit with a value of 0 or 1. Almost any device with two distinct states can be used to represent a conventional bit: switches, valves, magnets, coins, etc. Part of the quantum mystery is that a qubit can occupy a superposition of 0 and 1 states. A qubit cannot have an intermediate value, such as 0.63; when the state of a qubit is measured, the result is either 0 or 1. However, during computation, a qubit can behave as if it were a mixture of states—for example, 63% 0 and 37% 1. General quantum programs require coordination between the quantum and classical parts of the computation. One way to think about general quantum programs is to identify the processes and abstractions involved in specifying a quantum algorithm, transforming the algorithm into an executable form, running experiments or simulations, and analyzing the results. By processing information using the laws of quantum mechanics, quantum computers offer novel ways to perform computational tasks such as molecular computation, financial risk calculation, optimization, and more.

[0047] The tansmon is considered a leading candidate for creating qubits (or quantum bits) to improve the scalability of quantum computing devices. One metric used to quantize the quality of a tansmon involves its resonant quality at low temperatures. This metric can be measured as the quality factor Q or the coherence time T1. Typically, good values ​​for Q and T1 are 5,000,000 and 0.15 milliseconds (ms), respectively, for a tansmon with a resonant frequency of approximately 5 GHz. These values ​​of Q and T1 correspond to the average number of qubits achievable in the best quantum processors produced to date, with approximately 50 qubits. However, further improvements of approximately two orders of magnitude in these Q and T1 values ​​are needed to achieve quantum computing devices with quantum advantages over classical computers.

[0048] A wide range of loss mechanisms can potentially negatively impact achievable Q and T1 values. One potential loss source for the transporter may involve defects in the material (e.g., silicon (Si) and / or silicon dioxide (SiO2)) near the top surface of the transporter. Some of these defects have been observed to act as TLS, exhibiting transitions at frequencies near the transporter frequency (e.g., the resonant frequency), thereby reducing the transporter's energy. Losses associated with such defects limit the maximum achievable Q and T1 values.

[0049] Embodiments of the techniques described herein can provide transporter element geometries and / or arrangements that facilitate reduction of transporter surface losses. Losses are typically driven by electric fields present on the transporter surface, particularly on the surface of the dielectric element comprising the transporter. Embodiments of this disclosure provide structures that can reduce the amplitude of the electric field at the transporter surface, particularly on the surface of the dielectric element comprising the transporter. The compatibility between aspects of one or more embodiments described herein and this design can facilitate the incorporation of these aspects into some current manufacturing techniques. One or more embodiments described herein can reduce the transporter footprint to facilitate increased transporter density in quantum hardware. One or more embodiments described herein can facilitate reduced transporter radiation losses by increasing the portion of the electric field residing within the dielectric comprising the transporter, thereby reducing the portion of the electric field residing outside the dielectric.

[0050] Figure 1-2 An exemplary non-limiting device 100 including a transmission sub-element is shown. Specifically, Figure 1-2 A top view of device 100 and a cross-sectional view of device 100 taken along line AA are shown respectively. Figure 1-2 As shown, device 100 includes electrodes 120 and 130 formed on surface 112 of dielectric layer 110. Dielectric layer 110 may include any material with electrically insulating properties, including but not limited to sapphire, diamond, and semiconductor elements such as Si, silicon-germanium (SiGe), silicon-germanium-carbon (SiGeC), silicon carbide (SiC), germanium (Ge) alloys, gallium arsenide (GaAs), etc. Semiconductors are known to behave as insulators at operating temperatures below 1 Kelvin. Electrodes 120 and / or 130 may include titanium nitride (TiN), aluminum (Al), niobium (Nb), rhenium (Re), tin (Sn), non-superconductors, superconductors, ferromagnetic metals, or combinations thereof. Electrodes 120 and / or 130 may include length, width, and height dimensions. For example, electrode 130 includes a length dimension 132, a width dimension 134, and a height dimension 136. In one embodiment, the length dimension 132 may be between approximately 100 micrometers (μm) and approximately 1000 μm; the width dimension 134 may be between approximately 10 μm and approximately 100 μm; and the height dimension 136 may be between approximately 20 nanometers (nm) and approximately 200 nm.

[0051] Electrodes 120 and 130 may include a transporter when coupled to a tunnel junction (not shown) located in a gap 140 between electrodes 120 and 130 on surface 112. In an embodiment, the transporter implemented using device 100 may be referred to as a standard transporter. As an example, the tunnel junction may be implemented as a Josephson junction. In this example, the tunnel junction may become a Josephson junction when the electrodes of the tunnel junction (e.g., electrodes 120 and / or 130) become superconductors (e.g., when the operating temperature is below the critical temperature of the material including the electrodes (e.g., a metal). Electrodes 120 and 130 may be formed as capacitors providing capacitance for the transporter, wherein electrodes 120 and 130 correspond to the plates of the capacitor. The tunnel junction (not shown) may form a bridge in the region within the electrodes occupied by gap 140 on surface 112. The tunnel junction may occupy a relatively small subset of the region within the electrodes occupied by gap 140 on surface 112. For example, the geometry of the region within the electrodes may be defined by multiplying the dimension (e.g., width) of gap 140 by the length dimension 132 of electrode 130. In this example, the tunnel junction can occupy a relatively small subset of this geometry. Thus, the capacitor formed by electrodes 120 and 130 can represent the largest element of the transporter.

[0052] When the transporter is electrically driven to its high energy level, a voltage can exist in the region within the electrodes between electrodes 120 and 130. When a voltage is present, an electric field can be established near (e.g., around and between) electrodes 120 and 130. Specifically, the highest amplitude of the electric field can typically be found in the region within the electrodes. More specifically, the highest amplitude of the electric field can be found along the respective edges of electrodes 120 and 130. The driving term for a lossy medium such as TLS can be expressed as εE. 2 , where ε represents the dielectric constant of the loss medium, and E represents the amplitude of the electric field. It is worth noting that the loss involves the square of the electric field amplitude.

[0053] Figure 3-5 An exemplary, non-limiting electric field distribution and the corresponding surface loss associated with device 100 are shown. Specifically, Figure 4 An exemplary non-limiting graph 400 is shown, which depicts along... Figure 3The calculated profile 410 of the square of the electric field amplitude (corresponding to the Y-axis of graph 400) is plotted by line 310 (corresponding to the X-axis of graph 400). Graph 400 shows two main peaks of the calculated profile 410 corresponding to the respective edges of electrodes 120 and 130 defining the gap 140. Graph 400 further illustrates that the electric field can be distributed in other locations within the device 100. For example, graph 400 includes two secondary peaks of the calculated profile 410, which correspond to the respective edges of electrodes 120 and 130 opposite the edges defining the gap 140. As another example, the calculated electric field amplitude value of the profile 410 associated with the inner portion of the gap 140 does not reach zero.

[0054] As mentioned above, the driving term for lossy media such as TLS can be represented as εE 2 Therefore, the distribution of electric field amplitude values ​​along line 310 depicted in graph 400 indicates that, for device 100, surface losses mainly occur in a relatively small region of surface 112 near electrodes 120 and 130. Most of these surface losses can be confined to the region within the electrodes occupied by gap 140, along the corresponding edges of electrodes 120 and 130 defining gap 140, as indicated by the positions of the two main peaks in the calculated profile depicted in graph 400. This distribution of surface losses 510 associated with device 100 is achieved through… Figure 5 The variation intensity of the surface loss 510 shown is used to illustrate this.

[0055] Figure 6-7 An exemplary non-limiting device 600 is shown that helps reduce surface losses in quantum devices. Specifically, Figure 6-7 A top view of device 600 and a cross-sectional view of device 600 along line BB are shown respectively. Figure 6-7 As shown, device 600 includes electrodes 620 and 630 formed on surface 612 of dielectric layer 610. Dielectric layer 610 may comprise any material having electrically insulating properties, including but not limited to sapphire and diamond, and semiconductor elements such as Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, etc., semiconductors are known to behave as insulators at operating temperatures below 1 Kelvin. Electrodes 620 and / or 630 may comprise titanium nitride (TiN), aluminum (Al), niobium (Nb), rhenium (Re), tin (Sn), non-superconductors, superconductors, ferromagnetic metals, or combinations thereof. Electrodes 620 and 630 may include transporters when coupled to a tunnel junction (not shown) located in a gap 640 between electrodes 620 and 630 on surface 612. In one embodiment, the transporter implemented using device 600 may be referred to as a thin dielectric transporter.

[0056] One aspect of the device 600 that facilitates reducing surface losses involves reducing one or more dimensions of electrodes 620 and 630. For example, Figure 1 and Figure 6 The comparison shows that electrode 630 has a length dimension 632 that is significantly smaller than the length dimension 132 of electrode 130. As another example, the width dimension 634 and / or height dimension 636 of electrode 630 can also be reduced. Those skilled in the art will recognize that by reducing one or more dimensions of electrodes 620 and 630, the associated capacitance provided by electrodes 620 and 630 can be reduced. Any such reduction in capacitance will negatively impact the performance of the transporters formed in part by electrodes 620 and 630.

[0057] like Figure 7 As shown, the thickness of the dielectric layer 610 can be reduced to mitigate this capacitance reduction. To this end, the device 600 includes a recess 710 formed in the surface 612 of the dielectric layer 610, which reduces the thickness of the dielectric layer 610. Specifically, the recess 710 reduces the thickness of the dielectric layer 610 from a thickness 720 outside the covered area of ​​the recess 710 to a thickness 730 within the covered area of ​​the recess 710. The thickness 730 can be less than the thickness 720. The thickness 730 can be between the electrode 630 and the electrode 650 located on the surface 614 of the dielectric layer 610. Surfaces 612 and 614 can be opposing surfaces of the dielectric layer 610. In one embodiment, the thickness 730 can be between approximately 5 μm and approximately 20 μm. The electrode 620 can be positioned within the covered area of ​​the recess 710. The electrode 630 can also be located within the covered area of ​​another recess formed in the surface 612 of the dielectric layer 610. The reduction in the thickness of the dielectric layer 610 can cause the associated capacitance provided by electrodes 620 and 630 to increase to a value substantially similar to the capacitance provided by electrodes 120 and 130.

[0058] Since the surface area of ​​electrodes 620 and 630 is reduced by decreasing one or more of their dimensions, a reduction in surface loss can be intuitively expected. However, reducing the thickness of dielectric layer 610 to increase the associated capacitance provided by electrodes 620 and 630 can increase the amplitude of the electric field present at surface 612. In particular, the increase in the amplitude of the electric field present at surface 612 can involve shifting some electric field lines from within dielectric layer 610 to surface 612 by reducing the thickness of dielectric layer 610.

[0059] Figure 9 An exemplary non-limiting graph 900 is shown, which depicts along... Figure 8 The contour 910 plots the square of the electric field amplitude (corresponding to the Y-axis of curve 900) drawn by line 810 (corresponding to the X-axis of curve 900). Figure 8The line 810 can basically correspond to Figure 3 Line 310, therefore the X-axis of curve 900 can basically correspond to the X-axis of curve 400. For example... Figure 9 As shown, the calculated profile 910 can be much larger than the calculated profile 410, approaching an order of magnitude. In some cases, the calculated profile 910 may include the ratio of the square of the electric field amplitude to the increase in the calculated profile 410, which is substantially analogous to the ratio of the decrease in the respective surface areas of electrodes 620 and 630 to electrodes 120 and 130. In this case, any reduction in surface losses expected by reducing the respective surface areas of electrodes 620 and 630 can be offset by the corresponding increase in the electric field amplitude.

[0060] Figure 10 The description and Figure 1-3 A cross-sectional view 1000 of an exemplary unrestricted energy density profile 1050 associated with device 100. Figure 10 The energy density profile 1050 can be used as εE at all points in this region. 2 The magnitude is derived (for the driving term of lossy media such as TLS). In one embodiment, the electric field E can be calculated using a finite element software package capable of decomposing the volume of interest into triangular elements. The finite element software package can also calculate the electric field at each vortex of the element. This electric field can be generated by applying a voltage to conductive electrodes (e.g., electrodes 620 and / or 630). Figure 10 As shown, the energy density profile 1050 associated with device 100 includes an energy density profile 1052 in the medium 1060 (e.g., air) above the surface 112 of dielectric layer 110 and an energy density profile 1054 within dielectric layer 110. Energy density profile 1052 may be associated with the radiation loss of device 100. Figure 10 The energy density profile 1050 is also shown to include a local maximum 1055 located within the dielectric 1060 near the surface 112, which can provide an interface between the dielectric layer 110 and the dielectric 1060.

[0061] Figure 11 A cross-sectional view 1100 is shown according to one or more embodiments described herein, depicting a... Figure 6-9 An exemplary non-limiting energy density profile 1150 associated with the device 600. Figure 11 The energy density profile 1150 can be compared with Figure 10 The energy density profile of 1050 was obtained in a similar manner. (And...) Figure 10Similar to the energy density profile 1050, the energy density profile 1150 associated with device 600 includes an energy density profile 1152 in the dielectric 1160 (e.g., air) above the surface 612 of dielectric layer 610 and an energy density profile 1154 within dielectric layer 610. However, with Figure 10 The energy density profile is different at 1050. Figure 11 The energy density profile 1150 is primarily located within the dielectric layer 610. That is, the energy density profile 1154 located within the dielectric layer 610 can substantially exceed the energy density profile 1152 located outside the dielectric layer 610. For example... Figure 11 As shown, the energy density profile 1150 includes a local maximum 1155 at a depth 1114 within the dielectric layer 610, which corresponds to the distance between the surface 612 of the dielectric layer 610 and the recessed surface 1124 of the dielectric layer 610 within the coverage area of ​​the recess 710. In one embodiment, the depth 1114 may be at least 0.3 μm. The local maximum 1155 may be located within the dielectric layer 610 between the electrodes 630 and 650.

[0062] exist Figure 11 In this embodiment, the electrode 630 of device 600 includes a rounded edge (e.g., rounded edge 1132) that engages with the sidewall 1122 of recess 710 and the recessed surface 1124 within the covered area of ​​recess 710. In one embodiment, the rounded edge 1132 may be a bottom corner of electrode 630 rounded with radius r. Figure 11 As further shown, rounded edges can facilitate the extension and / or minimization of the peak value of the energy density profile 1154 within the dielectric layer 610. In some cases, rounded edges of the electrode 630 can particularly facilitate the extension and / or minimization of the peak value of the energy density profile 1154 within the dielectric layer 610 near the metal / dielectric interface associated with the sidewalls 1122 and / or recessed surfaces 1124.

[0063] Table 1 illustrates exemplary reductions in surface loss achievable with thin dielectric transporters (e.g., transporters implemented using device 600) compared to standard transporters (e.g., transporters implemented using device 100). In exemplary Table 1, d (μm) can correspond to Figure 11 The depth is 1114. For this comparison, a standard transporter includes electrodes (e.g., Figure 1Electrodes 120 and / or 130, comprising a length dimension of 500 μm (e.g., length dimension 132) and a width dimension of 60 μm (e.g., width dimension 134). Standard transporters also include a 20 μm gap between the electrodes (e.g., gap 140). Thin dielectric transporters comprise electrodes (e.g.,...) having a length dimension of 70 μm (e.g., length dimension 632) and a width dimension of 60 μm (e.g., width dimension 634). Figure 6 Electrodes 620 and / or 630). The thin dielectric transport layer also includes a 20 μm gap between the electrodes (e.g., gap 640). The thin dielectric transporter also includes a dielectric material thickness (e.g., between electrodes 620 and / or 630) between the electrodes located on the surface of the dielectric layer (e.g., surface 612) and the electrodes located on the opposite surface of the dielectric layer (e.g., surface 614) (e.g., electrode 650). Figure 7 (Thickness 730). The thickness of the thin dielectric transport layer can be maintained at 4.5 micrometers.

[0064] d(um) Surface loss reduced 0 1.1x 1 5.0x 2 7.5x 4 10.8x 8 16.5x

[0065] Table 1

[0066] As shown in Table 1, even without creating a recess on the electrode surface of the dielectric layer, a thin dielectric transporter can still reduce surface loss compared to a standard transporter. That is, even without forming a recess on the surface of the dielectric layer, a thin dielectric transporter can increase the reduction in surface loss by a factor of 1.1 compared to a standard transporter. The calculation of the surface loss values ​​for the thin dielectric transporter and the standard transporter in Table 1 can include integrating over each transporter. One integration can be summed at εE on the dielectric layer surface corresponding to the thin dielectric transporter. 2 Another integral can be summed at the surface of the dielectric layer corresponding to the standard transporter, εE. 2 Table 1 provides the ratio of these two integrals. Table 1 also shows the ratio when these electrodes are located at a depth (e.g., depth). Figure 11 When the depth of the recess (e.g., recess 710) is 4 μm, the reduction in surface loss obtained by the thin dielectric transporter can be increased by an order of magnitude. In this example, by increasing the depth of the recess in which the electrode is placed from 0 μm to 4 μm, the reduction in surface loss relative to the standard transporter increases from 1.1X to 10.8X.

[0067] Table 2 shows the reduction in surface loss that can be achieved using standard transporters by recessing the electrodes within the corresponding dielectric layers. The comparisons in Table 2 are made only between standard transporters. For example, Table 2 shows that standard transporters can achieve approximately a 3-fold increase in surface loss reduction by recessing the electrodes 1 μm into the corresponding dielectric.

[0068] d(um) Surface loss reduced 0 1.0x 1 2.9x 2 3.3x 4 3.6x 8 3.8x

[0069] Table 2

[0070] Figure 12-15 A cross-sectional view of an exemplary non-limiting device having recessed electrodes according to one or more embodiments described herein is shown. Figure 12-15 Each electrode shown may include TiN, Al, Nb, Re, Sn, non-superconductor, superconductor, ferromagnetic metal or a combination thereof. Figure 12 An exemplary non-limiting device 1200 is shown, which includes an electrode 1230 located within a covered area of ​​a recess 710 formed in a surface 612 of a dielectric layer 610. (See example...) Figure 12 As shown, the surface 1232 of the electrode 1230 does not coincide with the surface 612 of the dielectric layer 610. Instead, the electrode 1230 only engages with a portion 1224 of the defined recess 710 of the sidewall 1122.

[0071] Figure 13 An exemplary non-limiting device 1300 is shown, which includes an electrode 1330 located within a covered area of ​​a recess 710 formed in a surface 612 of a dielectric layer 610. (See diagram below.) Figure 13 As shown, electrode 1330 does not include a solid block that completely occupies the volume of recess 710. Instead, electrode 1330 includes a film that extends continuously between the sidewalls 1122 defining recess 710. The film including electrode 1330 extends beyond the surface 612 of dielectric layer 610.

[0072] Figure 14 The device 1400 may include Figure 13 Exemplary, non-limiting alternative embodiments of device 1300. Similar to device 1300, device 1400 includes an electrode 1430 that does not include a solid that completely occupies the volume of recess 710. Similar to electrode 1330 of device 1300, electrode 1430 includes a film that extends continuously between the sidewalls 1122 defining recess 710. Unlike electrode 1330, electrode 1430 does not extend beyond the surface 612 of dielectric layer 610. Instead, electrode 1430 extends partially upward to the sidewalls 1122 defining recess 710 such that electrode 1430 does not intersect with a portion 1424 of sidewall 1122.

[0073] Figure 15 An example non-limiting device 1500 is shown, including a recess 1520 formed in a dielectric layer 610. For example... Figure 15 As shown, the recess 1520 is defined by a sidewall 1522, which undercuts the surface 1612 of the dielectric layer 610 forming the recess 1520. The device 1500 further includes electrodes 1530 positioned within the recess 1520. (The last sentence appears to be incomplete and possibly refers to a different device.) Figure 13-14 Similar to electrodes 1330 and 1430, electrode 1530 does not include a solid block that completely occupies the volume of recess 1520. Instead, electrode 1530 includes a film extending continuously between the sidewalls 1522 defining recess 1520. Similar to... Figure 14 Electrode 1430, electrode 1530 extends upward to the sidewall 1522, such that electrode 1530 does not intersect with part 1524 of sidewall 1522.

[0074] Figure 16-27 Exemplary, non-limiting, multi-step manufacturing sequences are illustrated, which can be implemented to manufacture one or more embodiments of this disclosure described herein and / or shown in the accompanying drawings. For example, they can be implemented... Figure 16-27 The non-limiting multi-step manufacturing sequence shown describes a device that helps reduce, for example, [the following text is incomplete and likely refers to a different topic:] Figure 6-8 The surface loss of the 600 quantum device.

[0075] Figure 16 A cross-sectional view of an exemplary non-limiting device 1600, which can help reduce surface losses in quantum devices according to one or more embodiments described herein, is shown. Figure 16As shown, device 1600 may include a substrate 1610. Substrate 1610 may include any material with mechanical rigidity, including but not limited to metals, glass, sapphire, and diamond, as well as semiconductor elements such as Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, and other materials with mechanical rigidity. Device 1600 may also include an intermediate layer 1620 formed on substrate 1610. Intermediate layer 1620 may include any material having at least one material property different from the corresponding material property of substrate 1610. In one embodiment, at least one material property may include: mechanical properties; chemical properties; electrical properties; or combinations thereof. In one embodiment, intermediate layer 1620 may have electrically insulating properties, including but not limited to silicon dioxide (SiO2), silicon nitride (Si3N4), hafnium oxide (HfO2), aluminum oxide (Al2O3), and other materials with electrically insulating properties. In an embodiment, intermediate layer 1620 may be a buried oxide (BOX) layer. In an embodiment, the BOX layer may be thermally grown or obtained by ion implantation. In one embodiment, the intermediate layer 1620 may be grown or formed by atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), tetraethyl orthosilicate (TEOS), etc. In another embodiment, the intermediate layer 1620 may include any combination of a BOX layer and one or more dielectric layers, said dielectric layers being grown or formed via ALD, PECVD, TEOS, etc. The device 1600 may also include a dielectric layer 1630 formed on the intermediate layer 1620. The dielectric layer 1630 may include any material having electrically insulating properties, including but not limited to sapphire and diamond, and semiconductor elements such as Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, etc., semiconductors are known to behave as insulators at operating temperatures below 1 Kelvin. In one embodiment, the substrate 1610, the intermediate layer 1620, and the dielectric layer 1630 may form a silicon-on-insulator (SOI) wafer.

[0076] Figure 17 The following is illustrated after the growth or formation of the dielectric layer 1740, according to one or more embodiments described herein. Figure 16 A cross-sectional view of an exemplary non-limiting device. Device 1700 may include exemplary non-limiting alternative embodiments of device 1600 made by growing or forming a dielectric layer 1740 on a dielectric layer 1630. The dielectric layer 1740 may include any material having electrically insulating properties, including but not limited to sapphire and diamond, and semiconductor elements such as Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, etc., semiconductors are known to behave as insulators at operating temperatures below 1 Kelvin. In one embodiment, the dielectric layer 1740 may have a density of less than 10 Kelvin. -6Or ideally less than 10 -7 The dielectric loss tangent. In one embodiment, the dielectric layer 1740 may include less than 10. 10 One of the defect densities (e.g., per 10 10 (An atom is smaller than a defect). Exemplary defects associated with defect density may include vacancies, self-interstitial atoms, antisites, unintentional impurities, etc. In one embodiment, the dielectric layer 1740 may have at least 10 4 The resistivity is measured in Ohm·cm. In one embodiment, the dielectric layer 1740 may be an epitaxial growth layer formed using an epitaxial growth process, such as metal-organic vapor phase epitaxy (MOVPE), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other epitaxial growth processes. In one embodiment, the dielectric layer 1740 may include a thickness (e.g., height) of about 1 to 10 micrometers (μm). In one embodiment, when the dielectric layer 1630 includes a resistivity of less than 1 ohm·cm... 2 At a defect density of 1000, Figure 17-27 The dielectric layer 1740 may be omitted in one or more of the devices shown. In one embodiment, the dielectric layer 1630 has a density of less than 1000 / cm. 2 With a defect density of at least 1000 Ohm·cm and a resistivity of at least 1000 Ohm·cm, dielectric layer 1740 can be obtained from... Figures 17 to 27 The components shown are omitted. In one embodiment, when the dielectric layer 1630 comprises less than 1000 / cm 2 With a defect density of at least 10 μm and a thickness of at least 10 μm, it is possible to obtain... Figure 17-27 The dielectric layer 1740 is omitted in one or more devices shown.

[0077] Figure 18 The following is illustrated after the deposition of one or more metal layers 1850, according to one or more embodiments described herein. Figure 17A cross-sectional view of an exemplary non-limiting device. Device 1800 may include exemplary non-limiting alternative embodiments of device 1700 formed by depositing one or more metal layers 1850 on dielectric layer 1740. The one or more metal layers 1850 may include TiN, Al, Nb, Re, Sn, non-superconductor, superconductor, ferromagnetic metal, or combinations thereof. In one embodiment, the one or more metal layers 1850 may be deposited on dielectric layer 1740 by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other metallization processes. In one embodiment, at least one top adhesion promoting layer (e.g., SiO2 layer and / or glass layer) may be formed on the one or more metal layers 1850. In one embodiment, the one or more metal layers 1850 may include Figure 8 Electrode 650.

[0078] Figure 19 The following is illustrated after the orientation of the inverted or flipped device 1800, according to one or more embodiments described herein. Figure 18 A cross-sectional view of an exemplary non-limiting device. (Reference) Figure 18 Device 1800 includes a substrate 1610 and an intermediate layer 1620 arranged in an orientation 1805. After the orientation 1805 of device 1800 is reversed or flipped, the substrate 1610 and the intermediate layer 1620 in device 1900 can be arranged in an orientation 1905 opposite to the orientation 1805, such as... Figure 19 As shown.

[0079] Figure 20 This illustrates the process after the processing layer 2060 is bonded to one or more metal layers 1850, according to one or more embodiments described herein. Figure 19 A cross-sectional view of an exemplary non-limiting device. Device 2000 may include exemplary non-limiting alternative embodiments of device 1900 formed by bonding a processing layer 2060 to one or more metal layers 1850. The processing layer 2060 may be any mechanically rigid material, such as a metal, dielectric material, or other mechanically rigid material. In one embodiment, the processing layer 2060 may be a carrier wafer comprising any material having semiconductor properties, including but not limited to diamond, Si, SiGe, SiGeC, SiC, Ge alloys, etc. The processing layer 2060 may be bonded to one or more metal layers 1850 via diffusion bonding, adhesive bonding, fusion bonding, or other semiconductor bonding techniques.

[0080] Figure 21 The following is illustrated after removal of substrate 1610, according to one or more embodiments described herein. Figure 20A cross-sectional view of an exemplary non-limiting device. Device 2100 may include exemplary non-limiting alternative embodiments of device 2000 formed by removing substrate 1610. Substrate 1610 may be removed by a chemical mechanical polishing (CMP) process, which involves applying a combination of chemical and mechanical forces to substrate 1610. Intermediate layer 1620 may serve as a stop layer for the CMP process to facilitate isolation of dielectric layer 1630 from the combination of chemical and mechanical forces involved in the CMP process. In one embodiment, intermediate layer 1620 may include a thickness (e.g., height) of at least 1 μm to facilitate the achievement of accuracy and / or reliability of the CMP process. It is noteworthy that available SOI wafers typically include an insulating layer of at least 1 μm.

[0081] Figure 22 The following diagram illustrates the process after removing intermediate layer 1620, according to one or more embodiments described herein. Figure 21 A cross-sectional view of an exemplary non-limiting device. Device 2200 may include exemplary non-limiting alternative embodiments of device 2100 formed by removing intermediate layer 1620. Intermediate layer 1620 may be removed by a dry etching process, a wet etching process, or other etching processes.

[0082] Figure 23 The diagram illustrates the following after the recess 2370 is formed in the dielectric layers 1630 and / or 1740 according to one or more embodiments described herein. Figure 22 A cross-sectional view of an exemplary non-limiting device. Device 2300 may include an exemplary non-limiting alternative embodiment of device 2200 created by forming a recess 2370 in dielectric layers 1630 and / or 1740. Dielectric layers 1630 and / or 1740 may be selectively etched to form the recess 2370. Figure 23 As shown, the recess 2370 can reduce the thickness of the dielectric layer 1740 from a thickness 2342 outside the coverage area of ​​the recess 2370 to a thickness 2344 within the coverage area of ​​the recess 2370. In one embodiment, the recess 2370 may include... Figure 7 In one embodiment, the recess 710, the processing layer 2060 may include a thickness (e.g., height) of approximately 750 μm to provide structural support to the dielectric layer 1740. In this embodiment, the thickness 2344 of the dielectric layer 1740 may compromise the structural integrity of the dielectric layer 1740 adjacent to the recess 2370.

[0083] Figure 24 The following diagram illustrates the application of an oxidation process according to one or more embodiments described herein. Figure 23A cross-sectional view of an exemplary non-limiting device. Device 2400 may include exemplary non-limiting alternative embodiments of device 2300 created after an oxidation process consumes a portion of dielectric layer 1630 and / or dielectric layer 1740. The application of an oxidation process (e.g., thermal oxidation and / or electrochemical oxidation) can consume a portion of dielectric layer 1630 and / or dielectric layer L740 by converting the dielectric material corresponding to dielectric layer 1630 and / or 1740 into oxide layer 2480.

[0084] Figure 25 The following is illustrated after the removal of oxide layer 2480, according to one or more embodiments described herein. Figure 24 A cross-sectional view of an exemplary non-limiting device. Device 2500 may include exemplary non-limiting alternative embodiments of device 2400 created after removing oxide layer 2480. Oxide layer 2480 may be removed by a dry etching process, a wet etching process, or other etching processes. Figure 25 As shown, the application of the oxidation process and the removal of the resulting oxide layer 2480 can form a fillet radius 2572 between the sidewall 2542 of the recess 2370 and the recessed surface 2544 of the dielectric layer 1740 within the covered area of ​​the recess 2370. In one embodiment, the fillet radius 2572 may include... Figure 11 The fillet radius is 1132.

[0085] Figure 26 This shows the process after depositing one or more metal layers 2690. Figure 25 A cross-sectional view of an exemplary, non-limiting device. Device 2600 may include exemplary, non-limiting alternative embodiments of device 2500 formed by depositing one or more metal layers 2690 on dielectric layer 1740. The one or more metal layers 2690 may include TiN, Al, Nb, Re, Sn, non-superconductors, superconductors, ferromagnetic metals, or combinations thereof. In one embodiment, the one or more metal layers 2690 may be deposited on dielectric layer 1740 via PVD, CVD, ALD, or another metallization process.

[0086] Figure 27 The image shows the portion of one or more metal layers 2690 outside the recess 2370 after removal, according to one or more embodiments described herein. Figure 26A cross-sectional view of an exemplary non-limiting device. Device 2700 may include exemplary non-limiting alternative embodiments of device 2600 created by retaining portions of one or more metal layers 2690 within a recess 2370. Portions of one or more metal layers 2690 outside the recess 2370 may be removed via a CMP process involving applying a combination of chemical and mechanical forces to one or more metal layers 2690. A dielectric layer 1740 may serve as a stop layer for the CMP process to facilitate retaining portions of one or more metal layers 2690 within the recess 2370. In one embodiment, the retained portions of one or more metal layers 2690 within the recess 2370 may form electrodes (e.g., Figures 6 to 8 Electrodes 620 and / or 630). In one embodiment, the CMP process can use a fill pattern in areas without patterned components to fine-tune polishing uniformity. In one embodiment, a spin-coating technique can be used to apply photoresist to device 2700 to facilitate additional photolithography steps. In one embodiment, the surface uniformity of the dielectric layer 1740 after the CMP process may not be sufficient to support the application of photoresist using a spin-coating technique. In this embodiment, a photoresist (e.g., polymethyl methacrylate (PMMA) and / or methyl methacrylate (MMA)) can be sprayed onto device 2700.

[0087] Figures 28-29 An exemplary non-limiting device 2800 is shown that facilitates the reduction of surface losses in quantum devices. In particular, Figures 28-29 A top view of device 2800 and a cross-sectional view of device 2800 along line CC are shown respectively. Figures 28-29 As shown, device 2800 may include an electrode 2830 located within a covered area of ​​a recess 2910 formed in the surface 2812 of dielectric layer 2810. Device 2800 may also include an electrode 2820 positioned on surface 2812. Similar to electrode 2830, electrode 2820 may be positioned within a covered area of ​​another recess (not shown) formed in surface 2812.

[0088] Reference Figure 29Device 2800 may further include an electrode 2880, which may be positioned on the surface of dielectric layer 2810 opposite to surface 2812. Electrode 2880 may be electrically isolated from electrodes 2820 and / or 2830 via dielectric layer 2810. In device 2800, electrodes 2820 and 2880 may form a first capacitor (or capacitor). Electrodes 2830 and 2880 may also form a second capacitor (or capacitor) in series with the first capacitor in device 2800. Dielectric layer 2810 may include any material having electrically insulating properties, including but not limited to sapphire and diamond, and semiconductor elements such as Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, etc., semiconductors are known to behave as insulators at operating temperatures below 1 Kelvin. Electrodes 2820, 2830 and / or 2880 may include TiN, Al, Nb, Re, Sn, non-superconductors, superconductors, ferromagnetic metals or combinations thereof.

[0089] like Figure 28 As shown, gap 2825 may be located between electrodes 2820 and 2830 in device 2800. Electrode 2820 may be coupled to Josephson junction 2850 located in gap 2825, and electrode 2830 may be coupled to Josephson junction 2850 to form qubits (e.g., transporters). Device 2800 may also include bus 2870, which couples the qubits to external devices (e.g., readout circuitry) via gap 2920. In one embodiment, bus 2870 may include a readout resonator. In one embodiment, when gap 2920 is 0.5 μm and bus 2870 includes a width dimension 2872 of 10 μm and a thickness dimension 2930 of 1 μm, a coupling capacitance of 2.2 nanofarads (fF) may exist between bus 2870 and electrode 2830.

[0090] Figure 30 The device 3000 may include Figures 28-29 Exemplary, non-limiting alternative embodiments of the device 2800. Similar to Figures 28-29 Devices 2800 and 3000 may include a bus 3010 that couples a qubit including an electrode 2830 to an external device (e.g., a readout circuit) via a gap 3020. In one embodiment, when the gap 3020 is 1 μm and the bus 3010 includes a coupling length dimension 3012 of 20 to 50 μm and a thickness dimension of 0.5 to 1 μm (not shown), a coupling capacitance of 1 to 10 fF may exist between the bus 3010 and the electrode 2830.

[0091] Figures 31-35 An example non-limiting device 3100 is shown that can facilitate crosstalk reduction and / or inter-qubit decoupling according to one or more embodiments described herein. In particular, Figure 31A top view of device 3100 is shown. Figures 32-33 A cross-sectional view of device 3100 taken along line DD is shown, while Figures 34-35 Cross-sectional views of device 3100 taken along line EE are shown. (Reference) Figure 31 Device 3100 may include a shielding structure 3110 and a through-hole structure 3120. For example... Figures 32 to 35 As shown, the shielding structure 3110 and / or the via structure 3120 can be electrically coupled to conductive elements positioned on opposite surfaces of the dielectric layer 2810. For example, the shielding structure 3110 and / or the via structure 3120 can electrically couple a conductive element 3160 positioned on surface 2812 of the dielectric layer 2810 to an electrode 2880.

[0092] To this end, the shielding structure 3110 and the via structure 3120 may respectively include sidewalls 3220 and 3420, which can provide a conductive path between the conductive element 3160 and the electrode 2880. Sidewalls 3220 and / or 3420 may include TiN, Al, Nb, Re, Sn, non-superconductors, superconductors, ferromagnetic metals, or combinations thereof. By providing a conductive path between the conductive element 3160 and the electrode 2880, the shielding structure 3110 and / or the via structure 3120 can facilitate the scalability of quantum hardware. For example, the shielding structure 3110 and / or the via structure 3120 can realize electrical connections between different layers of a multilayer quantum device, which can involve increasingly dense levels of connectivity. Figure 32 and 33 The comparison shows that the volume of the shielding structure 3110 defined by the sidewall 3220 can be filled with conductive material 3230, such as Figure 32 As shown, or the volume can remain empty, such as... Figure 33 As shown. Figure 34 and 35 The comparison shows that the volume of the through-hole structure 3120 defined by the sidewall 3420 can be as follows: Figure 34 The volume shown is filled with conductive material 3430, or the volume can be as follows: Figure 35 The diagram is left blank. In one embodiment, the conductive material 3230 and / or 3430 may include TiN, Al, Nb, Re, Sn, non-superconductor, superconductor, ferromagnetic metal, or a combination thereof.

[0093] Another aspect of the shielding structure 3110 relates to crosstalk between qubits. As described above, the Josephson junction 2850 can be coupled to electrodes 2820, 2830, and 2880 to form a qubit. The shielding structure 3110 can be positioned between this qubit and another qubit (not shown) located outside the shielding structure 3110. Figure 31In this design, shielding structure 3110 is depicted as substantially external to the qubit including the Josephson junction 2850. Thus, the sidewall 3220 of shielding structure 3110 can form a trench-like structure substantially external to the qubit including the Josephson junction 2850 to mitigate the transverse electric field generated by the qubit. In doing so, shielding structure 3110 can facilitate crosstalk reduction and / or decoupling of the qubit including the Josephson junction 2850 from other qubits (not shown) located outside shielding structure 3110. In one embodiment, the sidewall 3220 of shielding structure 3110 can resemble a curtain substantially external to the qubit including the Josephson junction 2850, extending to the extent that sidewall 3220 extends between conductive element 3160 and electrode 2880. In one embodiment, the shielding structure 3110 may resemble a moat having conductive or superconducting sidewalls substantially external to the qubits comprising the Josephson junction 2850, to the extent that the sidewalls 3220 of the shielding structure 3110 substantially external to the qubits comprising the Josephson junction 2850. In one embodiment, the conductive element 3160 may be a ground plane providing a ground potential.

[0094] Figure 36 An exemplary non-limiting device 3600 that can facilitate impedance matching according to one or more embodiments described herein is shown. Figure 36 As shown, device 3600 includes bump pads 3610 located on the surface of a dielectric layer. The bump pads 3610 can facilitate coupling of device 3600 to external devices (e.g., readout circuitry). Device 3600 may also include electrodes (not shown) located on opposite surfaces of the dielectric layer. For example, device 3600 may include electrodes, such as... Figure 29 Electrode 2880. To facilitate impedance matching between device 3600 and external devices, a portion of the electrode in region 3620 below bump pad 3610 can be removed.

[0095] Figure 37 Another example, non-limiting device 3700, which facilitates impedance matching according to one or more embodiments described herein is shown. Figure 37 As shown, device 3700 includes element 3702, which includes electrodes 3720 and 3730 located on opposite surfaces of dielectric layer 3710. Device 3700 also includes element 3704, which includes electrode 3760 located on the surface of dielectric layer 3750. Elements 3702 and 3704 can collectively form a half-wavelength (λ / 2) resonator structure. Elements 3702 and 3704 can be electrically coupled via solder 3740 that couples the bump pad 3722 of electrode 3720 to the bump pad 3762 of electrode 3760. Figure 37As shown, electrodes 3720 and 3760 can be configured as quarter-wavelength (λ / 4) resonator substructures to facilitate impedance matching.

[0096] Figure 38 A flowchart of an exemplary non-limiting method 3800 according to one or more embodiments described herein is shown, which can facilitate the reduction of surface losses in quantum devices. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. At 3810, method 3800 may include a dielectric layer (e.g., Figure 6 A recess is formed in the first surface of the dielectric layer 610 (e.g., Figure 7 The recess 710). The recess can reduce the thickness of the dielectric layer from a first thickness outside the covered area of ​​the recess to a second thickness within the covered area of ​​the recess. The second thickness can be less than the first thickness. In 3820, method 3800 can also include forming a first electrode located within the covered area of ​​the recess (e.g., Figure 6 Electrode 630). In 3830, method 3800 can also include forming a second electrode (e.g., electrode 630). Figure 7 The electrode 650 is located on the second surface of the dielectric layer and is electrically isolated from the first electrode through the dielectric layer. The first surface and the second surface may be located on opposite surfaces of the dielectric layer.

[0097] In one embodiment, method 3800 may further include forming a Josephson knot (e.g., Figure 28 Josephson junction 2850), which is coupled to the first electrode and located on the first surface of the dielectric layer in the gap between the first electrode and the third electrode (e.g., electrode 2820). Figure 28 In the gap 2825). In one embodiment, the first electrode and the second electrode may form a first capacitor. In one embodiment, the second electrode and the third electrode may form a second capacitor. In one embodiment, the second capacitor may be connected in series with the first capacitor. In one embodiment, the second electrode may be formed before the first electrode is formed. In one embodiment, method 3800 may further include processing a layer (e.g., Figures 20 to 27 The processing layer 2060 is bonded to the second electrode to provide structural support to the dielectric layer. In this embodiment, the second electrode may be located between the dielectric layer and the processing layer.

[0098] In one embodiment, method 3800 further includes oxidizing the surface of the dielectric layer to form a fillet radius between the sidewall of the recess and the recessed surface of the dielectric layer within the covered area of ​​the recess (e.g., Figure 11 The fillet radius is 1132. In one embodiment, method 3800 may further include forming a shielding structure (e.g., Figure 31A shielding structure 3110 is located between the first electrode and a first qubit adjacent to the first electrode. The shielding structure can facilitate the reduction of crosstalk. In this embodiment, the shielding structure can electrically couple the second electrode to a conductive element (e.g., conductive element 2860) positioned on the first surface to provide a ground potential. In one embodiment, the first and second electrodes may include a second qubit. In this embodiment, the shielding structure can further facilitate the decoupling of the second qubit from the first qubit.

[0099] In order to provide context for the various aspects of the disclosed topic, Figure 39 The following discussion is intended to provide a general description of the suitable environment in which the various aspects of the disclosed subject matter can be realized. Figure 39The suitable operating environment 3900 for implementing various aspects of this disclosure is shown, and may further include a computer 3912. The computer 3912 may further include a processing unit 3914, system memory 3916, and a system bus 3918. The system bus 3918 couples system components, including but not limited to the system memory 3916, to the processing unit 3914. The processing unit 3914 may be any of a variety of available processors. Dual microprocessor and other multiprocessor architectures may also be used as the processing unit 3914. The system bus 3918 may be any of several bus architectures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of available bus architectures, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronic Devices (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1094), and Small Computer System Interface (SCSI). System memory 3916 may also include volatile memory 3920 and non-volatile memory 3922. The Basic Input / Output System (BIOS), containing basic routines such as transferring information between components within computer 3912 at startup, is stored in non-volatile memory 3922. By way of illustration and not limitation, non-volatile memory 3922 may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory 3920 may also include random access memory (RAM) used as an external cache. By way of illustration and not limitation, RAM may be obtained in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct memory bus RAM (DRRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0100] Computer 3912 may also include removable / non-removable, volatile / non-volatile computer storage media. For example, Figure 39Disk storage device 3924 is shown. Disk storage device 3924 may also include, but is not limited to, devices such as disk drives, floppy disk drives, magnetic tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or Memory Sticks. Disk storage device 3924 may also include a standalone storage medium or a storage medium combined with other storage media, including but not limited to optical disc drives such as compact disc ROM devices (CD-ROM), CD recordable drives (CD-R drives), CD rewritable drives (CD-RW drives), or digital multifunction disc ROM drives (DVD-ROM). To facilitate connection of disk storage device 3924 to system bus 3918, a removable or non-removable interface, such as interface 3926, is typically used. Figure 39 Software acting as an intermediary between the user and the basic computer resources described in the suitable operating environment 3900 is also depicted. Such software may also include, for example, an operating system 3928. The operating system 3928, which can be stored on a disk storage device 3924, is used to control and allocate the resources of the computer 3912. System application program 3930 utilizes the operating system 3928 to manage resources through program modules 3932 and program data 3934, for example, stored in system memory 3916 or disk storage device 3924. It should be understood that this disclosure can be implemented with various operating systems or combinations of operating systems. The user inputs commands or information to the computer 3912 through an input device 3936. The input device 3936 includes, but is not limited to, pointing devices such as a mouse, trackball, pen, touchpad, keyboard, microphone, joystick, game pad, disc satellite dish, scanner, TV tuner card, digital camera, digital camcorder, webcam, etc. These and other input devices are connected to the processing unit 3914 via interface port 3938 through system bus 3918. Interface port 3938 includes, for example, a serial port, a parallel port, a gaming port, and a Universal Serial Bus (USB). Output device 3940 uses some of the same type of ports as input device 3936. Thus, for example, a USB port can be used to provide input to computer 3912 and output information from computer 3912 to output device 3940. Output adapter 3942 is provided to illustrate the existence of some output devices 3940, such as monitors, speakers, and printers, as well as other output devices 3940 that require dedicated adapters. By way of illustration and not limitation, output adapter 3942 includes graphics cards and sound cards that provide a means of connection between output device 3940 and system bus 3918. It can be noted that other devices and / or systems of devices provide both input and output capabilities, such as remote computer 3944.

[0101] Computer 3912 can operate in a networked environment using a logical connection to one or more remote computers, such as remote computer 3944. Remote computer 3944 can be a computer, server, router, network PC, workstation, microprocessor-based appliance, peer-to-peer device, or other common network node, and typically may also include many elements described relative to computer 3912. For simplicity, only storage device 3946 is shown with remote computer(s) 3944(s). Remote computer 3944 is logically connected to computer 3912 via network interface 3948 and then physically connected via communication connection 3950. Network interface 3948 includes wired and / or wireless communication networks, such as local area network (LAN), wide area network (WAN), cellular network, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Wire Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks like Integrated Services Digital Network (ISDN) and its variants, packet-switched networks, and Digital Subscriber Line (DSL). Communication connection 3950 refers to the hardware / software used to connect network interface 3948 to system bus 3918. Although communication connection 3950 is shown as being inside computer 3912 for clarity, it can also be external to computer 3912. For illustrative purposes only, the hardware / software used to connect to network interface 3948 may also include internal and external technologies such as modems including conventional telephone-grade modems, cable modems, and DSL modems, ISDN adapters, and Ethernet cards.

[0102] This invention can be a system, method, apparatus, and / or computer program product at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention. A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may also include: portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or recessed structures with instructions recorded thereon, and any suitable combinations of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

[0103] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network, to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device. The computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). Computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of the invention, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to personalize the electronic circuits by utilizing state information of the computer-readable program instructions.

[0104] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of manufacture comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. The computer-readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational actions to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus, or other device, implement the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0105] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may occur in a non-consecutive order as shown in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0106] Although the subject matter has been described above in the general context of computer-executable instructions of a computer program product running on one or more computers, those skilled in the art will recognize that this disclosure can also be implemented or can be combined with other program modules. Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks and / or implement specific abstract data types. Furthermore, those skilled in the art will understand that the computer implementation methods of the present invention can be implemented using other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronic products, etc. The aspects shown can also be practiced in a distributed computing environment in which tasks are performed by remote processing devices linked via a communication network. However, some, if not all, aspects of this disclosure can be practiced on a standalone computer. In a distributed computing environment, program modules can reside in local and remote memory storage devices. For example, in one or more embodiments, computer-executable components can be executed from memory that may include or consist of one or more distributed memory cells. As used herein, the terms “memory” and “memory cell” are interchangeable. Furthermore, one or more embodiments described herein can execute code of a computer executable component in a distributed manner, for example, multiple processors combined or cooperating to execute code from one or more distributed memory units. As used herein, the term "memory" can include a single memory or memory unit at one location or multiple memories or memory units at one or more locations.

[0107] As used herein, the terms “component,” “system,” “platform,” “interface,” etc., may refer to and / or include computer-related entities or entities related to an operating machine having one or more specific functions. Entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or a computer. For illustration, an application running on a server and a server itself can both be components. One or more components may reside within a process and / or a thread of execution, and components may be located on a single computer and / or distributed across two or more computers. In another example, a corresponding component may be executable from various computer-readable media on which various data structures are stored. These components may communicate via local and / or remote processes, for example, based on signals having one or more data packets (e.g., data from a component via which it interacts with a local system, another component in a distributed system, and / or with other systems via a network such as the Internet). As another example, a component can be a device having specific functions provided by mechanical parts operated by electrical or electronic circuitry, which is operated by a software or firmware application executed by a processor. In this case, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As yet another example, a component can be a device that provides specific functions through electronic parts rather than mechanical parts, wherein the electronic parts can include a processor or other device to execute software or firmware that at least partially endows the electronic parts with the functions. In one aspect, the component can be emulated via a virtual machine, for example within a cloud computing system.

[0108] Furthermore, the term "or" is intended to indicate an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X adopts A or B" is intended to indicate any natural inclusive permutation. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied under any of the foregoing examples. Furthermore, unless otherwise specified or clear from the context to refer to the singular form, the articles "a" and "an" as used in this specification and figures should generally be interpreted as meaning "one or more". As used herein, the terms "example" and / or "exemplary" are used to indicate that something is used as an example, instance, or illustration. To avoid ambiguity, the subject matter disclosed herein is not limited to these examples. Moreover, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor does it exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0109] As used herein, the term "processor" can refer to substantially any computing processing unit or device, including but not limited to a single-core processor; a single processor with software multithreading capabilities; a multi-core processor; a multi-core processor with software multithreading capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, a processor can refer to an integrated circuit, application-specific integrated circuit (ASIC), digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic controller (PLC), complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, processors can employ nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user devices. Processors can also be implemented as a combination of computing processing units. In this disclosure, terms such as "storage," "memory," "database," "database," and substantially any other information storage component related to the operation and function of a component are used to refer to a "memory component," an entity embodied in "memory," or a component that includes memory. It should be understood that the memory and / or memory components described herein may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of illustration and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM, which may be used as external cache memory. By way of illustration and not limitation, RAM may be available in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Furthermore, the memory components disclosed in the systems or computer-implemented methods of this document are intended to include, but are not limited to, these and any other suitable types of memory.

[0110] The above description includes only examples of systems and computer-implemented methods. It is certainly impossible to describe every conceivable combination of components or computer-implemented methods for the purpose of describing this disclosure; however, those skilled in the art will recognize that many further combinations and arrangements of this disclosure are possible. Furthermore, with regard to the use of the terms "comprising," "having," "possessing," etc., in the detailed description, claims, appendices, and drawings, these terms are intended to be inclusive in a similar manner to how the term "comprising" is interpreted when used as a transitional word in the claims.

[0111] Various embodiments have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to existing technologies on the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A quantum device, comprising: A dielectric layer including a recess formed in a first surface of the dielectric layer, wherein the recess reduces the thickness of the dielectric layer from a first thickness outside a covered area of ​​the recess to a second thickness within the covered area of ​​the recess, and wherein the second thickness is less than the first thickness; The first electrode is positioned within the covered area of ​​the recess; as well as A second electrode is located on a second surface of the dielectric layer and is electrically isolated from the first electrode through the dielectric layer, wherein the first surface and the second surface are opposite surfaces of the dielectric layer; A third electrode is positioned on the first surface of the dielectric, wherein a gap is inserted between the first electrode and the third electrode, wherein the first electrode is coupled to a Josephson junction located within the gap.

2. The quantum device according to claim 1, wherein, The first electrode and the second electrode form a first capacitor, and the second electrode and the third electrode form a second capacitor.

3. The quantum device according to claim 1 or 2, wherein, The first electrode includes a rounded edge that engages with the sidewall of the recess and the recessed surface of the dielectric layer within the covered area of ​​the recess.

4. The quantum device according to claim 1 or 2, wherein, The recess has a depth of at least 0.3 micrometers.

5. The quantum device according to claim 1 or 2, wherein, The sidewall of the recess is cut under the surface of the dielectric layer that forms the recess.

6. The quantum device according to claim 1 or 2, wherein, The first electrode comprises a superconducting material.

7. The quantum device according to claim 1 or 2, further comprising: A shielding structure is positioned between the first electrode and a first qubit adjacent to the first electrode, wherein the shielding structure promotes crosstalk reduction, and wherein the shielding structure electrically couples the second electrode to a conductive element positioned on the first surface that provides a ground potential.

8. The quantum device as claimed in claim 7, wherein, The first electrode and the second electrode each include a second qubit, and the shielding structure further facilitates the decoupling of the second qubit from the first qubit.

9. The quantum device according to claim 1 or 2, wherein, The dielectric layer is an epitaxial growth layer.

10. The quantum device according to claim 1 or 2, further comprising: A processing layer that provides structural support for the dielectric layer, wherein the second electrode is located between the dielectric layer and the processing layer.

11. The quantum device according to claim 1 or 2, wherein, The second thickness of the dielectric layer within the covered area of ​​the recess is less than at least one dimension of the first electrode.

12. A quantum device, comprising: A first capacitor has a first electrode and a second electrode, the first electrode and the second electrode being electrically isolated by a dielectric layer between the first electrode and the second electrode, wherein the first electrode and the second electrode are positioned on opposite surfaces of the dielectric layer, wherein the first electrode is positioned within a covered area of ​​a recess formed in a first surface of the dielectric layer, the recess reducing the thickness of the dielectric layer from a first thickness outside the covered area of ​​the recess to a second thickness within the covered area of ​​the recess, and wherein the second thickness is less than the first thickness; A third electrode is positioned on the first surface of the dielectric, wherein a gap is inserted between the first electrode and the third electrode; as well as A Josephson junction coupled to the first electrode of the first capacitor, wherein the Josephson junction is located on the surface of the dielectric layer in the gap between the first electrode and the third electrode of the second capacitor.

13. The quantum device according to claim 12, wherein, The third electrode is located in another recess formed in the surface of the dielectric layer.

14. The quantum device according to claim 12 or 13, wherein, The third electrode and the second electrode form the second capacitor.

15. The quantum device according to claim 12 or 13, wherein, The second capacitor is connected in series with the first capacitor.

16. The quantum device according to claim 12 or 13, wherein, The first electrode includes a rounded edge that engages with the sidewall of the recess and the recessed surface of the dielectric layer within the covered area of ​​the recess.

17. The quantum device according to claim 12 or 13, wherein, The sidewall of the recess is cut under the surface of the dielectric layer that forms the recess.

18. The quantum device according to claim 12 or 13, further comprising: A shielding structure is positioned between the first electrode and a first qubit adjacent to the first electrode, wherein the shielding structure promotes crosstalk reduction, and wherein the shielding structure electrically couples the second electrode to a conductive element positioned on a surface providing a ground potential.

19. The quantum device of claim 18, wherein, The first electrode and the second electrode each include a second qubit, and the shielding structure further facilitates the decoupling of the second qubit from the first qubit.

20. A method comprising: A recess is formed in a first surface of a dielectric layer, wherein the recess reduces the thickness of the dielectric layer from a first thickness outside the covered area of ​​the recess to a second thickness within the covered area of ​​the recess, and wherein the second thickness is less than the first thickness; A first electrode is formed within the coverage area of ​​the recess; as well as A second electrode is formed, which is located on a second surface of the dielectric layer and electrically isolated from the first electrode through the dielectric layer, wherein the first surface and the second surface are located on opposite surfaces of the dielectric layer; The method further includes: A Josephson junction is formed, which is coupled to the first electrode and located on the first surface of the dielectric layer, in the gap between the first electrode and the third electrode.

21. The method according to claim 20, wherein, The first electrode and the second electrode form a first capacitor, and the second electrode and the third electrode form a second capacitor.

22. The method according to claim 20 or 21, further comprising: The first surface of the dielectric layer is oxidized to form a rounded corner radius between the sidewall of the recess and the recessed surface of the dielectric layer within the covered area of ​​the recess.

23. The method according to claim 20 or 21, further comprising: A shielding structure is formed between the first electrode and a first qubit adjacent to the first electrode, wherein the shielding structure promotes crosstalk reduction, and wherein the shielding structure electrically couples the second electrode to a conductive element positioned on the first surface that provides a ground potential.

24. The method according to claim 23, wherein, The first electrode and the second electrode include a second qubit, and the shielding structure further facilitates the decoupling of the second qubit from the first qubit.

25. The method according to claim 20 or 21, wherein, The second electrode is formed before the first electrode is formed.

26. The method according to claim 20 or 21, further comprising: The processing layer is bonded to the second electrode to provide structural support to the dielectric layer, wherein the second electrode is located between the dielectric layer and the processing layer.

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