Relay control method and system based on FPGA and CPLD
The relay control method and system based on FPGA and CPLD modules solves the relay control problem of relay controllers that has not been solved in the prior art, realizes full-duplex asynchronous bus communication, improves the reliability and safety of relay control, and allows for adjustable data transmission rate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TIANJIN JINHANG COMP TECH RES INST
- Filing Date
- 2023-07-20
- Publication Date
- 2026-06-02
AI Technical Summary
Existing universal asynchronous communication buses cannot fully meet the operational requirements in some scenarios with high security and reliability requirements, such as relay control in integrated avionics systems.
The FPGA module reads the control information from the upstream module, generates a second address, and writes it to the CPLD module. After confirming that the feedback data is consistent, the CPLD module is controlled to send control data to the relay, realizing full-duplex asynchronous bus communication and increasing reliability and security.
It improves the reliability and safety of relay control, while the data transmission speed and rate are adjustable, making it suitable for scenarios with high requirements for safety and reliability.
Smart Images
Figure CN116974965B_ABST
Abstract
Description
Technical Field
[0001] This disclosure generally relates to the field of bus technology, and specifically to a relay control method and system based on FPGA and CPLD. Background Technology
[0002] With the continuous development of digital communication control systems, FPGA / CPLD has been widely used in many fields. As applications mature, developers have described some general-purpose asynchronous communication buses using hardware description languages and packaged them into dedicated bus IP cores for use by users. These include UART, CAN bus, EMIF bus, LOCALBUS bus, I2C, and SPI. These dedicated general-purpose buses have advantages, but also disadvantages and cannot be used in some situations. For example, in some integrated avionics systems, when controlling relays, the above buses cannot fully meet the working requirements in scenarios with high safety and reliability requirements. Summary of the Invention
[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a relay control method and system based on FPGA and CPLD that can solve the above-mentioned technical problems.
[0004] The first aspect of this application provides a relay control method based on FPGA and CPLD, comprising the following steps:
[0005] Read the control information sent by the upstream module, the control information including first control data and a first address;
[0006] Subtract 1 from the first address to generate the second address;
[0007] Write the first control data and the first address into the CPLD module;
[0008] Send the second address to the CPLD module and read the first feedback data corresponding to the second address sent by the CPLD module;
[0009] When it is determined that the first control data is consistent with the first feedback data, a confirmation signal is sent to the CPLD module to control the CPLD module to send the first control data to the relay.
[0010] According to the technical solution provided in this application, the following steps are also included:
[0011] The pin status information of the CPLD module was collected multiple times;
[0012] If it is determined that the pin status information collected multiple times is consistent, the pin status information is sent to the upstream module.
[0013] According to the technical solution provided in this application, the following steps are also included:
[0014] If the pin status information collected multiple times is inconsistent, the pin status information is collected repeatedly in a loop.
[0015] If the pin status information collected multiple times in a loop is inconsistent, a fault code is generated and sent to the upstream module.
[0016] According to the technical solution provided in this application, reading the control information sent by the upstream module includes the following steps:
[0017] Read the first signal sent by the upstream module;
[0018] When the first signal is high, the control information sent by the upstream module is read; the first control data is stored in the first data register, and the first address is stored in the first address register.
[0019] According to the technical solution provided in this application, writing the first control data and the first address into the CPLD module includes the following steps:
[0020] Send a write enable signal, first control data, and first address to the CPLD module;
[0021] The write enable signal is brought to a low level to start the write enable counter, and the CPLD module reads the first control data and the first address.
[0022] After determining that the write enable counter has been maintained for n clock cycles, the first address in the first address register is cleared to zero, and the write enable signal is changed to a high level.
[0023] According to the technical solution provided in this application, sending the second address to the CPLD module and reading the first feedback data corresponding to the second address sent by the CPLD module includes the following steps:
[0024] Send a read enable signal and a second address to the CPLD module, and store the second address in the second address register;
[0025] The read enable signal is controlled to go low, the read enable counter is started, and the CPLD module receives the second address, which is used to read the first feedback data in the CPLD module.
[0026] After determining that the read enable counter has been maintained for k / 2 clock cycles, the first feedback data corresponding to the second address issued by the CPLD module is read, and the first feedback data is stored in the second data register;
[0027] After determining that the read enable counter has been maintained for k clock cycles, the second address in the second address register is cleared, and the read enable signal is changed to a high level.
[0028] According to the technical solution provided in this application, before sending the second address to the CPLD module and reading the first feedback data corresponding to the second address sent by the CPLD module, the following steps are also included:
[0029] Send an interval control signal to the CPLD module;
[0030] The interval control signal is brought to a high level to start the interval counter;
[0031] After determining that the interval counter has been maintained for x clock cycles, the interval control signal is controlled to go low.
[0032] According to the technical solution provided in this application, when it is determined that the first control data is consistent with the first feedback data, a confirmation signal is sent to the CPLD module to control the CPLD module to send the first control data to the relay, including the following steps:
[0033] When it is determined that the first control data is consistent with the first feedback data;
[0034] Send an acknowledgment signal to the CPLD;
[0035] The confirmation transmission signal is brought to a high level to start the confirmation transmission counter;
[0036] The CPLD module is controlled to send the first control data to the relay;
[0037] After determining that the confirmation transmission counter has been maintained for j clock cycles, the first control data in the first data register and the first feedback data in the second data register are cleared, and the confirmation transmission signal is changed to a low level.
[0038] A second aspect of this application provides a relay control system based on FPGA and CPLD, comprising:
[0039] CPLD module, wherein the CPLD module is connected to the relay;
[0040] An FPGA module, which is connected to the upstream module and the CPLD module;
[0041] The FPGA module is configured to:
[0042] Read the control information sent by the upstream module, the control information including first control data and a first address;
[0043] Subtract 1 from the first address to generate the second address;
[0044] Write the first control data and the first address into the CPLD module;
[0045] Send the second address to the CPLD module and read the first feedback data corresponding to the second address sent by the CPLD module;
[0046] When it is determined that the first control data is consistent with the first feedback data, a confirmation signal is sent to the CPLD module to control the CPLD module to send the first control data to the relay.
[0047] The beneficial effects of this application are as follows:
[0048] This application provides a relay control method and system based on FPGA and CPLD. The control method includes the following steps: the FPGA module reads control information sent by the upstream module, the control information including first control data and a first address; the FPGA module decrements the first address by 1 to generate a second address; subsequently, the FPGA module writes the first control data and the first address into the CPLD module; the FPGA module sends the second address to the CPLD module and reads the first feedback data corresponding to the second address sent by the CPLD; when the FPGA module determines that the first control data and the first feedback data are consistent, the FPGA module sends an acknowledgment signal to the CPLD module, controlling the CPLD module to send the first control data to the relay; through the above steps, the FPGA module and the CPLD module form a full-duplex asynchronous bus communication processing system, realizing the function of reading back and confirming control information, increasing the reliability and security of relay control; at the same time, the data transmission speed of the FPGA module and the CPLD module is fast and the rate is adjustable; it can be applied to any scenario with high requirements for security and reliability. Attached Figure Description
[0049] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0050] Figure 1 This is a flowchart of a relay control method based on FPGA and CPLD in this application;
[0051] Figure 2 This is a schematic diagram of a relay control system based on FPGA and CPLD according to this application;
[0052] Figure 3 This is a timing diagram illustrating the operation of the relay controlled by the FPGA and CPLD.
[0053] Figure 4 This is a timing diagram illustrating the operation of the CPLD module for collecting pin status information.
[0054] In the diagram: 1. Upstream module; 2. FPGA module; 3. CPLD module; 4. Relay. Detailed Implementation
[0055] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.
[0056] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0057] Example 1
[0058] Please refer to Figure 1 The flowchart of a relay control method based on FPGA and CPLD provided in this application includes the following steps:
[0059] S100: Read the control information sent by the upstream module, the control information including first control data and first address;
[0060] This solution is executed through FPGA module 2. FPGA (Field-Programmable Gate Array) is a programmable logic device, a type of integrated circuit, and it possesses high flexibility and reconfigurability. Figure 2 As shown, the FPGA module 2 is connected to the upstream module 1 and the CPLD module 3 respectively, and the CPLD module 3 is connected to the relay 4; the FPGA module 2 and the CPLD module 3 constitute a full-duplex asynchronous bus communication processing system for transmitting data between the upstream module 1 and the relay 4.
[0061] In this embodiment, the upstream module 1 is the host computer in the integrated avionics system. The host computer is used to send control information to the relay 4 to control the switching of the relay 4.
[0062] The CPLD (Complex Programmable Logic Device) module 3 is a programmable logic device used to implement the functions of digital logic circuits. A CPLD consists of a series of programmable logic gates and registers, and also includes programmable internal connection routing. Unlike FPGAs, CPLDs have smaller resource footprints and are suitable for implementing medium-sized logic circuits. CPLDs are suitable for applications that do not require high logic scale but demand high reliability and real-time performance. They typically feature low power consumption, high reliability, and small size.
[0063] In this embodiment, optionally, reading the control information sent by the upstream module includes the following steps:
[0064] Read the first signal sent by the upstream module;
[0065] When the first signal is high, the control information sent by the upstream module is read; the first control data is stored in the first data register, and the first address is stored in the first address register.
[0066] In this embodiment, the FPGA module 2 and the CPLD module 3 are connected via 16-bit address lines and 16-bit data lines. The FPGA module 2 internally defines a 32-bit register. The first data register and the first address register are located within the FPGA module 2; the first data register is a 16-bit data register, and the first address register is a 16-bit address register. The upstream module 1 sends a first signal to the FPGA module 2. The first signal is high, indicating that the FPGA module 2 detects that the first signal is valid. The FPGA module 2 reads the control information sent by the upstream module 1 and stores it in the defined 32-bit register. The lower 16 bits of the data in the 32-bit register are used as the first control data and registered in the first data register. The higher 16 bits of the data in the 32-bit register are used as the first address and registered in the first address register. When transmitting data, the data and address need to be transmitted separately so that the FPGA module 2 can correctly identify and access the memory cells. Transmitting data and address separately also improves data transmission efficiency.
[0067] S200: Subtract 1 from the first address to generate the second address;
[0068] In this scheme, in order to prevent the CPLD module 3 from making erroneous operations when receiving and sending data, the first address is decremented by 1 to generate the second address, and the second address is stored in the second address register of the FPGA module 2. The second address register is a 16-bit address register.
[0069] S300: Write the first control data and the first address into the CPLD module;
[0070] In this embodiment, optionally, writing the first control data and the first address into the CPLD module includes the following steps:
[0071] Send a write enable signal, first control data, and first address to the CPLD module;
[0072] The write enable signal is brought to a low level to start the write enable counter, and the CPLD module reads the first control data and the first address.
[0073] After determining that the write enable counter has been maintained for n clock cycles, the first address in the first address register is cleared to zero, and the write enable signal is changed to a high level.
[0074] Specifically: FPGA module 2 sends a write enable signal, first control data, and a first address to CPLD module 3, controlling the write enable signal to go low. CPLD module 3 detects the write enable signal going low, reads the first control data and the first address, and stores them in its third data register and third address register, respectively. Simultaneously with the write enable signal going low, FPGA module 2 starts a write enable counter. After the write enable counter maintains its position for n clock cycles (the clock cycle of the write enable counter is determined by the connected clock signal, and the clock cycle of the write enable counter matches the clock cycle of FPGA module 2), the first control data is written into CPLD module 3. At this time, the first address in the first address register is cleared to facilitate the next transmission of control information, and the write enable signal is controlled to go high, completing the writing of the first control data to CPLD module 3.
[0075] S400: Send the second address to the CPLD module and read the first feedback data corresponding to the second address sent by the CPLD module;
[0076] In this embodiment, optionally, sending the second address to the CPLD module and reading the first feedback data corresponding to the second address sent by the CPLD module includes the following steps:
[0077] Send a read enable signal and a second address to the CPLD module, and store the second address in the second address register;
[0078] The read enable signal is controlled to go low, the read enable counter is started, and the CPLD module receives the second address, which is used to read the first feedback data in the CPLD module.
[0079] After determining that the read enable counter has been maintained for k / 2 clock cycles, the first feedback data corresponding to the second address issued by the CPLD module is read, and the first feedback data is stored in the second data register;
[0080] After determining that the read enable counter has been maintained for k clock cycles, the second address in the second address register is cleared, and the read enable signal is changed to a high level.
[0081] In this process, the FPGA module 2 sends a read enable signal and a second address to the CPLD module 3, controlling the read enable signal to go low. The CPLD module 3 detects that the read enable signal has gone low and receives the second address. Simultaneously, the FPGA module 2 starts the read enable counter. After the read enable counter maintains its position for k / 2 clock cycles (the clock cycle of the read enable counter is determined by the connected clock signal, and the clock cycle of the read enable counter matches the clock cycle of the FPGA module 2), the FPGA module 2 reads the first feedback data corresponding to the second address sent by the CPLD module 3 and stores the first feedback data in the second data register (the first feedback data is read in the middle of the clock cycle maintained by the read enable counter, and the read first feedback data is stable). The second data register is a 16-bit register. After the read enable counter maintains its position for k clock cycles, the FPGA module 2 completes the reading of the first feedback data, controls the second address in the second address register to be cleared to facilitate the next transmission of control information, and controls the read enable signal to go high.
[0082] S500: When it is determined that the first control data is consistent with the first feedback data, a confirmation signal is sent to the CPLD module to control the CPLD module to send the first control data to the relay.
[0083] In this embodiment, optionally, when it is determined that the first control data is consistent with the first feedback data, an acknowledgment signal is sent to the CPLD module, and the CPLD module is controlled to send the first control data to the relay, including the following steps:
[0084] When it is determined that the first control data is consistent with the first feedback data;
[0085] Send an acknowledgment signal to the CPLD module;
[0086] The confirmation transmission signal is brought to a high level to start the confirmation transmission counter;
[0087] The CPLD module is controlled to send the first control data to the relay;
[0088] After determining that the confirmation transmission counter has been maintained for j clock cycles, the first control data in the first data register and the first feedback data in the second data register are cleared, and the confirmation transmission signal is changed to a low level.
[0089] In this process, after receiving the first feedback data sent by the CPLD, the FPGA module 2 determines that the first control data is consistent with the first control data. Then, the FPGA module 2 sends an acknowledgment signal to the CPLD module 3, controls the acknowledgment signal to go high, and starts the acknowledgment counter, which is set within the FPGA module 2. Simultaneously, the CPLD module 3 sends the first control data to the relay 4, and the relay 4 switches according to the first control data. After the acknowledgment counter maintains its position for j clock cycles (the clock cycle of the acknowledgment counter is determined by the connected clock signal, and the clock cycle of the acknowledgment counter matches the clock cycle of the FPGA module 2), the FPGA module 2 clears the first control data in the first data register and the first feedback data in the second data register to facilitate the next transmission of control information. Simultaneously, the acknowledgment signal goes low, completing one transmission of control information.
[0090] Working principle: This application uses the FPGA module 2 and the CPLD module 3 to form a full-duplex asynchronous bus communication processing system, which realizes the function of reading back and confirming control information, and increases the reliability and safety when controlling the relay 4; at the same time, the data transmission speed of the FPGA module 2 and the CPLD module 3 is fast and the rate is adjustable; it can be applied to any scenario with high requirements for safety and reliability.
[0091] In some implementations, before sending the second address to the CPLD module and reading the first feedback data corresponding to the second address sent by the CPLD module, the following steps are further included:
[0092] Send an interval control signal to the CPLD module;
[0093] The interval control signal is brought to a high level to start the interval counter;
[0094] After determining that the interval counter has been maintained for x clock cycles, the interval control signal is controlled to go low.
[0095] Specifically, before sending the second address to the CPLD module 3 and reading the first feedback data corresponding to the second address sent by the CPLD module 3, the FPGA module 2 sends an interval control signal to the CPLD module 3. The FPGA module 2 controls the interval control signal to go high and starts the interval counter. After the FPGA module 2 determines that the interval counter has been maintained for x clock cycles (the clock cycle of the interval counter is determined by the connected clock signal, and the clock cycle of the interval counter matches the clock cycle of the FPGA module 2), it controls the interval control signal to go low. The FPGA module 2 sets a time interval between reading and writing data to prevent errors from occurring when the FPGA module 2 reads back the first feedback data from the CPLD module 3.
[0096] For ease of understanding by those skilled in the art, in this embodiment, as... Figure 3 The diagram shows the timing sequence of the FPGA and CPLD controlling relay 4. In the diagram: clk is the local clock, valid is the first signal, data is the control information, wr_data is the first data register, wr_addr is the first address register, rd_addr is the second address register, wr_en is the write enable signal, blank is the interval control signal, rd_en is the read enable signal, rd_data is the second data register, and tx_en is the confirmation signal.
[0097] The FPGA module 2 reads the first signal valid sent by the upstream module 1; when the first signal valid is high, it reads the control information data sent by the upstream module 1. The control information data includes first control data and a first address. The first control data is stored in the first data register wr_data, and the first address is stored in the first address register wr_addr.
[0098] Furthermore, the first address is subtracted by 1 to generate the second address, and the second address is stored in the second address register rd_addr of the FPGA module 2;
[0099] Furthermore, a write enable signal wr_en, first control data, and a first address are sent to the CPLD module 3; the write enable signal wr_en is controlled to go low, and a write enable counter is started. The CPLD module 3 reads the first control data and the first address; after the write enable counter is maintained for 40 clock cycles, the first address in the first address register wr_addr is cleared to zero, and the write enable signal wr_en is controlled to go high.
[0100] Furthermore, an interval control signal blank is sent to the CPLD module 3; the interval control signal blank is controlled to go high to start the interval counter; after the interval counter is maintained for 20 clock cycles, the interval control signal blank is controlled to go low.
[0101] Furthermore, a read enable signal rd_en and a second address are sent to the CPLD module 3, and the second address is registered in the second address register rd_addr; the read enable signal rd_en is controlled to go low, and a read enable counter is started, and the CPLD module 3 receives the second address; after the read enable counter is maintained for 20 clock cycles, the first feedback data corresponding to the second address sent by the CPLD module 3 is read, and the first feedback data is registered in the second data register rd_data; after the read enable counter is maintained for 40 clock cycles, the second address in the second address register rd_addr is cleared, and the read enable signal rd_en is controlled to go high.
[0102] Furthermore, when it is determined that the first control data is consistent with the first feedback data, an acknowledgment transmission signal tx_en is sent to the CPLD module 3; the acknowledgment transmission signal tx_en is controlled to go high, and an acknowledgment transmission counter is started; the CPLD module 3 is controlled to send the first control data to the relay 4; after the acknowledgment transmission counter is maintained for 20 clock cycles, the first control data in the first data register wr_data and the first feedback data in the second data register rd_data are cleared, and the acknowledgment transmission signal tx_en is controlled to go low.
[0103] In some implementations, the following steps are also included:
[0104] The pin status information of the CPLD module was collected multiple times;
[0105] If it is determined that the pin status information collected multiple times is consistent, the pin status information is sent to the upstream module.
[0106] Specifically, the pin status of the CPLD module 3 is determined by the pin status of the relay 4. Therefore, the acquisition of the pin status information of the CPLD module 3 can reflect the pin status of the relay 4 in real time.
[0107] In this embodiment, the FPGA module 2 acquires the pin status information of the CPLD module 3 using a periodic acquisition method. The FPGA module 2 detects the read data signal of the CPLD module 3 pins in real time. When the read data signal is detected as valid (i.e., the read data signal becomes low), the acquisition control signal is pulled high, and the FPGA module 2 starts the acquisition counter to perform cyclic counting. The number of cyclic counting cycles can be adjusted according to the actual acquisition situation (the clock period maintained by the acquisition counter is determined by the connected clock signal, and the clock period of the acquisition counter matches the clock period of the FPGA module 2). When the adjustable cycle is reached, the acquisition counter is cleared to zero and re-accumulated. At the same time, when the adjustable cycle number is reached, the FPGA module 2 sends three acquisition signals to the CPLD module 3 respectively, and the FPGA module 2 acquires the pin status information of the CPLD module 3 three times. The three acquired pin status information of the CPLD module 3 are further compared. When the FPGA module 2 determines that the three acquired pin status information are consistent, the pin status information is packaged and sent to the upstream module 1.
[0108] For ease of understanding by those skilled in the art, in this embodiment, as... Figure 4 The diagram shows the working timing of the pin status information of the CPLD module 3. In the diagram, clk is the local clock, en is the read data signal, flag_plus is the acquisition control signal, flag_r1 is the first acquisition signal, flag_r2 is the first acquisition signal, and flag_r3 is the first acquisition signal.
[0109] After the FPGA module 2 and the CPLD module 3 start working, the FPGA module 2 begins to detect the read data signal en. When the read data signal en is detected as a valid signal, it indicates that the pin status information of the CPLD module 3 can be acquired. At this time, the acquisition control signal flag_plus is pulled high and held, and the acquisition counter is started to count cyclically. In this embodiment, each cycle is 5µs. After the 5µs count ends, the acquisition counter is cleared and the counting starts again. At the same time, after the 5µs count ends, the first acquisition signal flag_r1 is pulled high, and the FPGA module 2 begins to acquire the pin status information of the CPLD module 3 and starts the first counter. After maintaining it for 12,000 clock cycles, the first acquisition signal flag_r1 is pulled low. When the first counter counts to 6,000, the acquisition of the pin status information of the CPLD module 3 begins. The FPGA module 2 further raises the second acquisition signal flag_r2, and starts acquiring the pin status information of the CPLD module 3, and starts the second counter. After maintaining it for 12,000 clock cycles, the second acquisition signal flag_r2 is pulled low. When the second counter counts to 6,000, the level status of the pins of the CPLD module 3 is extracted. The FPGA module 2 further raises the third acquisition signal flag_r3, and starts acquiring the pin status information of the CPLD module 3, and starts the third counter. After maintaining it for 12,000 clock cycles, the third acquisition signal flag_r3 is pulled low. When the third counter counts to 6,000, the level status of the pins of the CPLD module 3 is extracted. If the pin status information acquired in the three acquisitions is consistent, the pin status information is packetized and sent to the upstream module 1.
[0110] In some implementations, the following steps are also included:
[0111] If the pin status information collected multiple times is inconsistent, the pin status information is collected repeatedly in a loop.
[0112] If the pin status information collected multiple times in a loop is inconsistent, a fault code is generated and sent to the upstream module.
[0113] Specifically, when the FPGA module 2 determines that the pin status information collected three times is inconsistent, it repeats the cycle three times (collecting the pin status information of the CPLD module 3 three times in one cycle). When the values collected in the three cycles are inconsistent, the FPGA module 2 generates a fault code and sends it to the upstream module 1, so that the upstream module 1 can cut off the control of the relay 4.
[0114] Example 2
[0115] Please refer to Figure 2A schematic diagram of a relay 4 control system based on FPGA and CPLD provided in this application includes:
[0116] CPLD module 3, which is connected to relay 4;
[0117] FPGA module 2, which is connected to upstream module 1 and CPLD module 3;
[0118] The FPGA module 2 is configured to:
[0119] Read the control information sent by the upstream module 1, the control information including first control data and a first address;
[0120] Subtract 1 from the first address to generate the second address;
[0121] Write the first control data and the first address into CPLD module 3;
[0122] Send the second address to the CPLD module 3 and read the first feedback data corresponding to the second address sent by the CPLD module 3;
[0123] When it is determined that the first control data is consistent with the first feedback data, a confirmation signal is sent to the CPLD module 3 to control the CPLD module 3 to send the first control data to the relay 4.
[0124] Specifically, this embodiment is a specific implementation of Embodiment 1, which has been described in detail in Embodiment 1. Its implementation principle is also basically the same as that in Embodiment 1, and will not be explained in detail here.
[0125] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.
Claims
1. A relay control method based on FPGA and CPLD, characterized in that, include: CPLD module (3), the CPLD module (3) is connected to the relay (4); FPGA module (2), which is connected to upstream module (1) and CPLD module (3); The FPGA module (2) is configured to: Read the control information sent by the upstream module (1), the control information including first control data and first address; Subtract 1 from the first address to generate the second address; Write the first control data and the first address into the CPLD module (3); Send the second address to the CPLD module (3) and read the first feedback data corresponding to the second address sent by the CPLD module (3); When it is determined that the first control data is consistent with the first feedback data, a confirmation signal is sent to the CPLD module (3) to control the CPLD module (3) to send the first control data to the relay (4).
2. The relay control method based on FPGA and CPLD according to claim 1, characterized in that, It also includes the following steps: The pin status information of the CPLD module was collected multiple times; If it is determined that the pin status information collected multiple times is consistent, the pin status information is sent to the upstream module.
3. The relay control method based on FPGA and CPLD according to claim 2, characterized in that, It also includes the following steps: If the pin status information collected multiple times is inconsistent, the pin status information is collected repeatedly in a loop. If the pin status information collected multiple times in a loop is inconsistent, a fault code is generated and sent to the upstream module.
4. The relay control method based on FPGA and CPLD according to claim 1, characterized in that, Reading control information sent by the upstream module includes the following steps: Read the first signal sent by the upstream module; When the first signal is high, the control information sent by the upstream module is read; the first control data is stored in the first data register, and the first address is stored in the first address register.
5. A relay control method based on FPGA and CPLD according to claim 4, characterized in that, Writing the first control data and the first address into the CPLD module includes the following steps: Send a write enable signal, first control data, and first address to the CPLD module; The write enable signal is brought to a low level to start the write enable counter, and the CPLD module reads the first control data and the first address. After determining that the write enable counter has been maintained for n clock cycles, the first address in the first address register is cleared to zero, and the write enable signal is changed to a high level.
6. The relay control method based on FPGA and CPLD according to claim 4, characterized in that, Sending the second address to the CPLD module and reading the first feedback data corresponding to the second address sent by the CPLD module includes the following steps: Send a read enable signal and a second address to the CPLD module, and store the second address in the second address register; The read enable signal is controlled to go low, the read enable counter is started, and the CPLD module receives the second address, which is used to read the first feedback data in the CPLD module. After determining that the read enable counter has been maintained for k / 2 clock cycles, the first feedback data corresponding to the second address issued by the CPLD module is read, and the first feedback data is stored in the second data register; After determining that the read enable counter has been maintained for k clock cycles, the second address in the second address register is cleared, and the read enable signal is changed to a high level.
7. The relay control method based on FPGA and CPLD according to claim 1, characterized in that, Before sending the second address to the CPLD module and reading the first feedback data corresponding to the second address sent by the CPLD module, the following steps are also included: Send an interval control signal to the CPLD module; The interval control signal is brought to a high level to start the interval counter; After determining that the interval counter has been maintained for x clock cycles, the interval control signal is controlled to go low.
8. A relay control method based on FPGA and CPLD according to claim 6, characterized in that, When it is determined that the first control data is consistent with the first feedback data, a confirmation signal is sent to the CPLD module, controlling the CPLD module to send the first control data to the relay, including the following steps: When it is determined that the first control data is consistent with the first feedback data; Send an acknowledgment signal to the CPLD; The confirmation transmission signal is brought to a high level to start the confirmation transmission counter; The CPLD module is controlled to send the first control data to the relay; After determining that the confirmation transmission counter has been maintained for j clock cycles, the first control data in the first data register and the first feedback data in the second data register are cleared, and the confirmation transmission signal is changed to a low level.