A multi-channel TR assembly

Abstract

This invention discloses a multi-channel TR component, comprising multiple beam control chips (1) and a beam control code communication module (3) integrated internally. The front end of the beam control code communication module (3) is connected to a main control chip (2), and its rear end is connected to the multiple beam control chips (1) connected in parallel. The beam control code communication module (3) and the main control chip (2) use high-speed communication to receive beam control codes. The beam control codes are written to the multiple beam control chips (1) in parallel. The beam control code communication module (3) includes a serial communication unit (31), an instruction parsing data buffer unit (32), a data processing unit (33), an output driving circuit (34), a PLL circuit (35), a signal synchronization shaping unit (36), and first to third LVDS interfaces. The multi-channel TR component of this invention has fast data transmission and short beam control code writing time.

Description

Technical Field

[0001] This invention belongs to the technical field of phased array radar components, specifically a multi-channel TR component. Background Technology

[0002] The TR (Transmitter and Receiver) module is a core component of an active phased array radar. The TR module receives and analyzes the beam control code from the main control chip, performs level conversion and signal amplification, and then drives the radio frequency chip to achieve the transmission and reception of microwave signals.

[0003] Each active phased array radar consists of tens of thousands of microwave signal transceiver channels. Each microwave signal transceiver channel is composed of a beam control chip. The internal structure of the beam control chip is as follows: Figure 1 As shown, the system includes a beam control module connected to the main control chip at the front end and an RF chip connected to the back end of the beam control module. The beam control module typically includes a receiving circuit, a beam control code processing circuit, and a level conversion and driving circuit. The input of the receiving circuit is connected to the main control chip, and its output is connected to the input of the beam control code processing circuit. The input of the level conversion and driving circuit is connected to the output of the beam control code processing circuit, and its output is connected to the RF chip. The receiving circuit communicates with the main control chip, receiving the beam control code sent by the main control chip. The beam control code processing circuit reads the beam control code from the receiving circuit and parses it to obtain information about the control beam control code. The level conversion and driving circuit performs level conversion and signal amplification, outputting the beam control code to the RF chip to drive it. Early phased array radars integrated a single microwave signal transceiver channel, i.e., a beam control chip, into a single TR component, forming a single-channel TR component.

[0004] To achieve miniaturization and weight reduction of radar arrays, the current trend is to integrate multiple microwave signal transceiver channels, i.e., multiple beam control chips, into a single TR module, forming a multi-channel TR module, such as 4-channel, 8-channel, or 16-channel TR modules.

[0005] Figure 2 The diagram shows an example of the structural block diagram of an existing multi-channel TR module. Each beam control chip within the TR module is directly connected to the enable control signal terminal (SW) and beam control code terminal of the main control chip. The main control chip and the beam control chips communicate via serial port. Taking the common SPI format as an example, the serial communication speed is typically 10Mbps, with a maximum of 20Mbps. The main control chip writes the beam control code controlling microwave signal reception and transmission to each beam control chip in the TR module one by one. The time taken for the main control chip to write the beam control code to one TR module is the sum of the writing times of all beam control chips. The total update time of the radar array beam control data is the sum of the writing times of all TR modules.

[0006] On the one hand, the data transmission speed is low because the main control chip and the beam control chip communicate via serial port. On the other hand, the main control chip writes the beam control code to each beam control chip one by one. For a phased array radar with tens of thousands of TR components, the overall data update time is long, and the radar array beam control data update speed is slow, which seriously affects the accuracy and flexibility of phased array radar detection. Summary of the Invention

[0007] The purpose of this invention is to provide a multi-channel TR component with fast data transmission and short beam control code writing time, which can improve the update speed of radar array beam control data.

[0008] The technical solution to achieve the purpose of this invention is as follows:

[0009] A multi-channel TR component, the front end of which is connected to the main control chip 2, and multiple parallel beam control chips 1 are integrated inside;

[0010] The multi-channel TR component also includes a wave control code communication module 3;

[0011] The front end of the beam control code communication module 3 is connected to the main control chip 2, and its rear end is connected to the multiple beam control chips 1 connected in parallel.

[0012] The wave control code communication module 3 and the main control chip 2 use high-speed communication to receive wave control codes.

[0013] The beam control code communication module 3 writes beam control codes to multiple beam control chips 1 connected in parallel in a parallel manner.

[0014] Preferably, the wave control code communication module 3 includes:

[0015] The serial communication unit 31 is used to receive control commands and beam control data for each channel sent by the main control chip 2 at high speed, and to send beam control code readback data for each channel to the main control chip 2.

[0016] The instruction parsing data buffer unit 32 is used to receive and temporarily store the control instructions and beam control data of each channel output by the serial communication unit 31, and output the control instructions and beam control data to the data processing unit 33 in a first-in-first-out manner.

[0017] Data processing unit 33 is used to classify and process beam control data according to the control command; including sending the beam control code obtained from the processed beam control data to the output drive circuit 34; acquiring the beam control code status data at the output terminal of the output drive circuit 34 in real time, and sending the beam control code status data to the serial communication unit 31.

[0018] The output drive circuit 34 is used to amplify the beam control code signal to drive the subsequent beam control chips 1.

[0019] PLL circuit 35 is used to generate an 800MHz clock signal for synchronizing and shaping the SW signal based on the LVDS communication clock signal.

[0020] The signal synchronization shaping unit 36 ​​is used to synchronously sample the SW signal according to the clock signal, and to shape the sampled SW signal according to the working requirements of the TR component, and output it to each beam control chip 1.

[0021] It also includes the first to third LVDS interfaces 371, 372, and 373;

[0022] The first LVDS interface 371 is used to receive high-speed clock signals;

[0023] The second LVDS interface 372 is used to receive high-speed data signals;

[0024] The third LVDS interface 373 is used to send the wave control code readback data of each channel;

[0025] The receiving data signal port 3102 of the serial communication unit 31 is connected to the wave control data output terminal 23 of the main control chip 2 through the second LVDS interface 372, and the sending data port 3103 of the serial communication unit 31 is connected to the readback data port 24 of the main control chip 2 through the third LVDS interface 373.

[0026] The input terminal of the instruction parsing data buffer unit 32 is connected to the data output terminal 3104 of the serial communication unit 31, and its output terminal is connected to the data receiving terminal 3301 of the data processing unit 33.

[0027] The input terminal 3401 of the output driving circuit 34 is connected to the output terminal 3303 of the data processing unit 33, and its beam control code output terminal 3402 is connected to the beam control code terminal of each beam control chip 1. The beam control code state sampling output terminal 3403 of the output driving circuit 34 is connected to the data acquisition input terminal 3304 of the data processing unit 33.

[0028] The data processing unit 33's data acquisition output terminal 3302 is connected to the serial communication unit 31's data readback port 3105;

[0029] The clock signal port 3101 of the serial communication unit 31 is connected to the input terminal of the PLL circuit 35, and is also connected to the clock signal port 22 of the main control chip 2 through the first LVDS interface 371.

[0030] The clock input terminal 3601 of the signal synchronization shaping unit 36 ​​is connected to the output terminal of the PLL circuit 35, the SW signal input terminal 3602 of the signal synchronization shaping unit 36 ​​is connected to the SW signal transmission port 21 of the main control chip 2, and the TR-type signal output terminal 3603 of the signal synchronization shaping unit 36 ​​is connected to the control terminal of each beam control chip 1.

[0031] Compared with the prior art, the significant advantages of this invention are:

[0032] 1. Fast data transmission: This invention uses LVDS interface communication, with a communication speed of up to 400Mbps, which greatly improves the data transmission speed;

[0033] 2. Short beam control code writing time: This invention employs a simultaneous beam control code writing method for multiple beam control chips within the same TR component. The time it takes for the main control chip to write beam control codes to one TR component is the sum of the writing times for one beam control chip. This significantly shortens the total time for updating radar array beam control data.

[0034] This invention improves data transmission speed and wave control code writing efficiency, ensuring the timeliness of radar array wave control data updates and effectively enhancing the accuracy and flexibility of phased array radar detection.

[0035] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0036] Figure 1 This is a structural block diagram of a current single-channel TR component.

[0037] Figure 2 This is a structural block diagram of a multi-channel TR component in the prior art.

[0038] Figure 3 This is a structural block diagram of the multi-channel TR component of the present invention.

[0039] In the diagram, the front end of the beam control code communication module is connected to the main control chip, and its back end is connected to multiple beam control chips connected in parallel.

[0040] Figure 4 yes Figure 3 The diagram shows the structural block diagram of the serial communication unit in the wave control code communication module.

[0041] Figure 5 yes Figure 3 The diagram shows the structural block diagram of the data processing unit in the wave control code communication module.

[0042] Figure 6 yes Figure 3 The diagram shows the structural block diagram of the signal synchronization shaping unit in the wave control code communication module.

[0043] In the diagram, 1 is the beam control chip, and 2 is the main control chip.

[0044] 3. Waveform control code communication module; 31. Serial communication unit; 32. Instruction parsing and data buffer unit; 33. Data processing unit; 34. Output drive circuit; 35. PLL circuit; 36. Signal synchronization and shaping unit; 371, 372, 373. First to third LVDS interfaces.

[0045] 311 Shift Register, 312 Data Frame Header Parsing Circuit, 313 Data Frame Tail Parsing Circuit, 314 Data Receive Control Circuit, 315 Data Verification Circuit, 316 Data Buffer Transmission Circuit, 317 Data Frame Synthesis Circuit, 318 Data Frame Transmission Circuit.

[0046] 331 Beamcode Synthesis Circuit, 332 Beamcode Parallel Transmission Circuit, 333 Power Control Data Buffer, 334 Amplitude Attenuation Data Buffer, 335 Phase Shift Data Buffer, 336 Readback Control Circuit, 337 Beamcode Readback Sampling Circuit, 338 Readback Data Transmission Circuit, 339 Temperature Detection Circuit.

[0047] 361 Synchronous sampling circuit, 362 T1 delay circuit, 363 T2 delay circuit, 364 T3 delay circuit, 365 COM signal shaping circuit, 366 T4 delay circuit, 367 TR signal shaping circuit, 368 Signal output drive circuit. Implementation

[0048] like Figure 3 As shown, the multi-channel TR component of the present invention has its front end connected to the main control chip 2, and integrates multiple parallel beam control chips 1 inside.

[0049] As an improvement of the present invention, the multi-channel TR component further includes a wavecode communication module 3;

[0050] The front end of the beam control code communication module 3 is connected to the main control chip 2, and its rear end is connected to the multiple beam control chips 1 connected in parallel.

[0051] The wave control code communication module 3 and the main control chip 2 use high-speed communication to receive wave control codes.

[0052] The beam control code communication module 3 writes beam control codes to multiple beam control chips 1 connected in parallel in a parallel manner.

[0053] like Figure 3 As shown, the wave control code communication module 3 includes:

[0054] The serial communication unit 31 is used to receive control commands and beam control data for each channel sent by the main control chip 2 at high speed, and to send beam control code readback data for each channel to the main control chip 2.

[0055] The instruction parsing data buffer unit 32 is used to receive and temporarily store the control instructions and beam control data of each channel output by the serial communication unit 31, and output the control instructions and beam control data to the data processing unit 33 in a first-in-first-out manner.

[0056] Data processing unit 33 is used to classify and process beam control data according to the control command; the classification and processing includes: sending the beam control code obtained from the beam control data to the output drive circuit 34; acquiring the beam control code status data of the beam control code output terminal 3402 of the output drive circuit 34 in real time, and sending the beam control code status data to the serial communication unit 31.

[0057] The output drive circuit 34 is used to amplify the beam control code signal and output it to each channel to drive each beam control chip 1 in the subsequent stage.

[0058] PLL circuit 35 is used to generate an 800MHz clock signal for synchronizing and shaping the SW signal based on the LVDS communication clock signal.

[0059] The signal synchronization shaping unit 36 ​​is used to synchronously sample the SW signal according to the 800MHz clock signal, and to shape the sampled SW signal according to the working requirements of the TR component, and output it to each beam control chip 1.

[0060] It also includes the first to third LVDS interfaces 371, 372, and 373;

[0061] The first LVDS interface 371 is used to receive high-speed clock signals;

[0062] The second LVDS interface 372 is used to receive high-speed data signals;

[0063] The third LVDS interface 373 is used to send the wave control code readback data of each channel;

[0064] The receiving data signal port 3102 of the serial communication unit 31 is connected to the wave control data output terminal 23 of the main control chip 2 through the second LVDS interface 372, and the sending data port 3103 of the serial communication unit 31 is connected to the readback data port 24 of the main control chip 2 through the third LVDS interface 373.

[0065] The input terminal of the instruction parsing data buffer unit 32 is connected to the data output terminal 3104 of the serial communication unit 31, and its output terminal is connected to the data receiving terminal 3301 of the data processing unit 33.

[0066] The input terminal 3401 of the output driving circuit 34 is connected to the output terminal 3303 of the data processing unit 33, and its beam control code output terminal 3402 is connected to the beam control code terminal of each beam control chip 1. The beam control code state sampling output terminal 3403 of the output driving circuit 34 is connected to the data acquisition input terminal 3304 of the data processing unit 33.

[0067] The data processing unit 33's data acquisition output terminal 3302 is connected to the serial communication unit 31's data readback port 3105;

[0068] The clock signal port 3101 of the serial communication unit 31 is connected to the input terminal of the PLL circuit 35, and is also connected to the clock signal port 22 of the main control chip 2 through the first LVDS interface 371.

[0069] The clock input terminal 3601 of the signal synchronization shaping unit 36 ​​is connected to the output terminal of the PLL circuit 35, the SW signal input terminal 3602 of the signal synchronization shaping unit 36 ​​is connected to the SW signal transmission port 21 of the main control chip 2, and the TR-type signal output terminal 3603 of the signal synchronization shaping unit 36 ​​is connected to the control terminal of each beam control chip 1.

[0070] On the one hand, this invention changes the data transmission process of obtaining wave control codes from the main control chip 2 from low-speed SPI to high-speed LVDS, using high-speed communication to receive wave control codes, which greatly improves the wave control code transmission speed of the TR component. On the other hand, this invention changes the transmission of wave control codes to each channel from serial to parallel, significantly improving data transmission efficiency. By increasing the data transmission speed and improving the wave control code writing efficiency, the timeliness of radar array wave control data updates is ensured, effectively improving the accuracy and flexibility of phased array radar detection.

[0071] like Figure 4 As shown, the serial communication unit 31 includes a shift register 311, a data frame header parsing circuit 312, a data frame tail parsing circuit 313, a data receiving control circuit 314, a data verification circuit 315, a data buffer sending circuit 316, a data frame synthesis circuit 317, and a data frame sending circuit 318.

[0072] The clock input terminal 3111 of the shift register 311 corresponds to the clock signal port 3101 and is used to connect to the first LVDS interface 371. Its receiving data input terminal 3112 corresponds to the receiving data signal port 3102 and is used to connect to the second LVDS interface 372. The receiving data output terminal 3113 of the shift register 311 is connected to the data input terminal of the data frame header parsing circuit 312, the second data input terminal 3132 of the data frame tail parsing circuit 313, and the third data input terminal 3143 of the data receiving control circuit 314, respectively.

[0073] The output terminal of the data frame header parsing circuit 312 is connected to the first data input terminal 3131 of the data frame tail parsing circuit 313 and the first data input terminal 3141 of the data receiving control circuit 314, respectively.

[0074] The second data input terminal 3142 of the data receiving control circuit 314 is connected to the output terminal 3133 of the data frame end parsing circuit 313.

[0075] The output terminal 3146 of the data receiving control circuit 314 is connected to the input terminal of the data buffer sending circuit 316; the output terminal of the data buffer sending circuit 316 corresponds to the data output terminal 314 of the serial communication unit 31 and is used to connect to the input terminal of the instruction parsing data buffer unit 32.

[0076] The data receiving control circuit 314 and the data verification circuit 315 are bidirectionally connected;

[0077] The input terminal of the data frame synthesis circuit 317 corresponds to the readback data port 3105, which is used to connect to the data acquisition output terminal 3302 of the data processing unit 33.

[0078] The input terminal of the data frame sending circuit 318 is connected to the output terminal of the data frame combining circuit 317; its output terminal is used to connect to the third LVDS interface 373.

[0079] The clock signal port 3101, the receive data signal port 3102, and the transmit data port 3103 of the serial communication unit 31 are the three main communication ports for serial communication. The serial communication unit 31 reads data from the receive data signal port 3102 into the shift register 311 on each falling edge of the clock. When data needs to be transmitted, it sends the data in the data frame transmission circuit 318 to the previous stage circuit through the transmit data port 3103 on each rising edge of the clock.

[0080] The data in shift register 311 is read by three circuits: data frame header parsing circuit 312, data frame tail parsing circuit 313, and data receiving control circuit 314.

[0081] Data frame header parsing circuit 312: In serial communication, 0XAA is used as the data communication frame header. The data frame header parsing circuit 312 is used to identify the 0XAA data terminal and send the identification result to the data receiving control circuit 314 and the data frame tail parsing circuit 313. At the same time, after receiving the first 0XAA frame header data, the data frame header parsing circuit 312 starts counting and does not identify 0XAA data in the subsequent 7 data, to ensure that 0XAA in normal control data is not mistaken for a data frame header.

[0082] Data frame tail parsing circuit 313: In serial communication, 0X55 is used as the frame tail of data communication. After receiving the frame header recognition result sent by the data frame header parsing circuit 312, it starts counting, judges whether the seventh received data is 0X55, and sends the judgment result to the data receiving control circuit 314.

[0083] Data receiving control circuit 314: Based on the feedback results of the data frame header parsing circuit 312, the data frame tail parsing circuit 313, and the data verification circuit 315, it determines whether the received data frame is valid. If all three circuits pass the test, the received data frame is sent to the data buffer transmission circuit 316. If any one of the three circuits fails the test, the received data frame is discarded.

[0084] Data verification circuit 315: Performs algorithm verification on the received data, using a bitwise XOR operation as agreed upon in the verification algorithm. The verification result is then sent to data receiving control circuit 314.

[0085] Data buffering and transmitting circuit 316: Receives the wave control data sent by the data receiving control circuit 314 and buffers the received data according to the first-in-first-out principle. The received wave control data is then sent to the next stage circuit through the data output terminal 314.

[0086] The serial communication unit 31 also receives wave control code readback data from the data processing unit 33, integrates the readback wave control code data into a data frame of a specified format, and sends it to the next-level circuit through the serial port.

[0087] Data frame synthesis circuit 317: Receives wave control code readback data from data processing unit 33 through readback data port 315, and synthesizes the received wave control code data into a standard data frame format for serial communication according to the serial communication protocol.

[0088] Data frame sending circuit 318: Reads the standard format frame data from the data frame synthesis circuit 317 and sends it to the previous stage circuit through the data sending port 3103.

[0089] Those skilled in the art will understand that the shift register 311, data frame header parsing circuit 312, data frame tail parsing circuit 313, data receiving control circuit 314, data verification circuit 315, data buffer sending circuit 316, data frame synthesis circuit 317, and data frame sending circuit 318 described above can all be implemented by circuits, units, functional modules, or even computer programs with the same functions in the prior art.

[0090] like Figure 5As shown, the data processing unit 33 includes a wave control code synthesis circuit 331, a wave control code parallel transmission circuit 332, a power control data buffer 333, an amplitude attenuation data buffer 334, a phase offset data buffer 335, a readback control circuit 336, a wave control code readback sampling circuit 337, a readback data transmission circuit 338, and a temperature detection circuit 339.

[0091] The power control input terminal 3311 of the wave code synthesis circuit 331 is connected to the output terminal of the instruction parsing data buffer unit 32 through the power control data buffer unit 333;

[0092] The amplitude attenuation value input terminal 3312 of the wave code synthesis circuit 331 is connected to the output terminal of the instruction parsing data buffer unit 32 through the amplitude attenuation data buffer unit 334.

[0093] The phase offset input terminal 3313 of the wave code synthesis circuit 331 is connected to the output terminal of the instruction parsing data buffer unit 32 through the phase offset data buffer unit 335;

[0094] The output terminal 3314 of the wave code synthesis circuit 331 is connected to the input terminal of the wave code parallel transmission circuit 332, and the output terminal of the wave code parallel transmission circuit 332 is used to connect to the input terminal 3401 of the output driving circuit 34.

[0095] The instruction terminal 3361 of the readback control circuit 336 is connected to the output terminal of the instruction parsing data buffer unit 32, its temperature input terminal 3362 is connected to the output terminal of the temperature detection circuit 339, its status data input terminal 3363 is connected to the output terminal of the wave control code readback sampling circuit 337, and its output terminal 3364 is connected to the input terminal of the readback data sending circuit 338.

[0096] The input terminal of the wave control code readback sampling circuit 337 is used to connect to the wave control code status sampling terminal 3403 of the output driving circuit 34.

[0097] The output of the readback data transmission circuit 338 is used to connect to the readback data port 3105 of the serial communication unit 31.

[0098] The data received from the serial port by the data receiver 3301 is sent to the power control data buffer 333, amplitude attenuation data buffer 334, and phase offset data buffer 335 respectively according to the instructions.

[0099] Power control data buffer 333: Receives data related to the power control section of each channel of the TR component from the beam control data, buffers the received power control data according to the first-in-first-out principle, and sends it to the beam control code synthesis circuit 331.

[0100] Amplitude attenuation data buffer 334: Receives data on the amplitude attenuation values ​​of microwave signals of each channel of the TR component from the beam control data, buffers the received power control data according to the first-in-first-out principle, and sends it to the beam control code synthesis circuit 331.

[0101] Phase offset data buffer 335: Receives data on the phase offset of microwave signals of each channel of the TR component from the beam control data, buffers the received power control data according to the first-in-first-out principle, and sends it to the beam control code synthesis circuit 331.

[0102] Beam control code synthesis circuit 331: According to the data format requirements for communication with the subsequent beam control module, it synthesizes the beam control data in the power control data buffer 333, amplitude attenuation data buffer 334, and phase offset data buffer 335 into a communication-mode beam control code, and sends the synthesized beam control code to the beam control code parallel transmission circuit 332.

[0103] Beam control code parallel transmission circuit 332: Reads the beam control codes of each channel in the beam control code synthesis circuit 331, and sends the read beam control codes to the output drive circuit 34 of the next stage in parallel through the output terminal 3303.

[0104] Readback control circuit 336: Based on different readback commands, it reads the real-time beam control code data from the beam control code readback sampling circuit 337 or the real-time temperature value inside the TR component monitored by the temperature detection circuit 339, and sends the read data to the readback data transmission circuit 338.

[0105] Readback data transmission circuit 338: transmits the readback data sent by the readback control circuit 336 to the serial communication unit 31 for backup through the data acquisition output terminal 3302.

[0106] Wavecode readback sampling circuit 337: Real-time sampling output of wavecode data in drive circuit 34.

[0107] Temperature detection circuit 339: Real-time detection of the temperature in the TR component and storage of it in the data buffer in the form of eight-bit binary two's complement.

[0108] Those skilled in the art will understand that the waveform code synthesis circuit 331, waveform code parallel transmission circuit 332, power control data buffer 333, amplitude attenuation data buffer 334, phase offset data buffer 335, readback control circuit 336, waveform code readback sampling circuit 337, readback data transmission circuit 338, and temperature detection circuit 339 described above can all be implemented by existing circuits, units, functional modules, or even computer programs with the same functions.

[0109] like Figure 6As shown, the signal synchronization shaping unit 36 ​​includes a synchronization sampling circuit 361, a T1 delay circuit 362, a T2 delay circuit 363, a T3 delay circuit 364, a COM signal shaping circuit 365, a T4 delay circuit 366, a TR signal shaping circuit 367, and a signal output driving circuit 368.

[0110] The clock sampling terminal 3611 of the synchronous sampling circuit 361 corresponds to the clock input terminal 3601, which is used to connect to the output terminal of the PLL circuit 35. Its SW signal sampling terminal 3612 corresponds to the SW signal input terminal 3602, which is used to connect to the SW signal transmission port 21 of the main control chip 2. The output terminal of the synchronous sampling circuit 361 is connected to the input terminals of the T1 delay circuit 362 and the T4 delay circuit 366, respectively.

[0111] The output terminal of the T1 delay circuit 362 is connected to the input terminal of the T2 delay circuit 363 and the first input terminal 3671 of the TR signal shaping circuit 367, respectively.

[0112] The output terminal of the T2 delay circuit 363 is connected to the input terminal of the T3 delay circuit 364 and the second input terminal 3652 of the COM signal shaping circuit 365, respectively.

[0113] The first input terminal 3651 of the COM signal shaping circuit 365 is connected to the output terminal of the T3 delay circuit 364, and its output terminal 3653 is connected to the first input terminal 3681 of the signal output driving circuit 368.

[0114] The second input terminal 3672 of the TR signal shaping circuit 367 is connected to the output terminal of the T4 delay circuit 366, and its output terminal 3673 is connected to the second input terminal 3682 of the signal output driving circuit 368.

[0115] The output terminal 3683 of the signal output driving circuit 368 corresponds to the TR-type signal output terminal 3603, which is used to connect to the control terminal of each beam control chip 1.

[0116] The clock input terminal 3601 of the signal synchronization shaping unit 36 ​​is connected to the output terminal of the PLL circuit 35. The high-speed sampling clock (800MHz, output by the PLL circuit 35) input terminal 3601, the SW signal input terminal 3602, and the TR and COM signals after SW shaping are output to the subsequent circuit via the TR-type signal output terminal 3603.

[0117] Synchronous sampling circuit 361: Synchronously samples the SW port signal at a clock frequency of 800MHz with an accuracy of 1ns. The synchronized SW signal can achieve perfect timing matching with the beam control code data signal in the subsequent beam control module.

[0118] T1 delay circuit 362: When the sampled SW signal changes from low to high, the internal timer circuit is started. When the timer reaches T1, the internal timer circuit stops working and sends a timing end signal to the TR signal shaping circuit 367 and the T2 delay circuit 363.

[0119] T2 Delay Circuit 363: When the internal timer circuit receives the timing end signal sent by T1 delay circuit 520, the internal timer circuit stops working when the timing reaches T2, and sends the timing end signal to COM signal shaping circuit 365 and T3 delay circuit 364.

[0120] T3 Delay Circuit 364: When the internal timer circuit receives the timing end signal sent by the T2 delay circuit 550, the internal timer circuit stops working when the timing reaches T3 and sends the timing end signal to the COM signal shaping circuit 365.

[0121] COM signal shaping circuit 365: When the timing end signal is sent by the T2 delay circuit 363, the voltage of the signal output terminal 3653 is changed from logic low to logic high; when the timing end signal is sent by the T3 delay circuit 364, the voltage of the signal output terminal 3653 is changed from logic high to logic low.

[0122] T4 Delay Circuit 366: When the sampled SW signal changes from logic high to logic low, the internal timer circuit is started. When the timer reaches T4, the internal timer circuit stops working and sends a timing end signal to the TR signal shaping circuit 367.

[0123] TR signal shaping circuit 367: When the timing end signal is sent by the T1 delay circuit 361, the voltage of the signal output terminal 3673 is changed from logic low to logic high; when the timing end signal is sent by the T4 delay circuit 366, the voltage of the signal output terminal 3673 is changed from logic high to logic low.

[0124] Signal output drive circuit 368: After amplifying the driving capability of the shaped signals output by TR signal shaping circuit 367 and COM signal shaping circuit 365, the signals are output by TR-type signal output terminal 3603 to the beam control modules of each channel of the subsequent TR component.

[0125] Those skilled in the art will understand that the synchronous sampling circuit 361, T1 delay circuit 362, T2 delay circuit 363, T3 delay circuit 364, COM signal shaping circuit 365, T4 delay circuit 366, TR signal shaping circuit 367, and signal output driving circuit 368 described above can all be implemented by existing circuits, units, functional modules, or even computer programs with the same functions.

[0126] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0127] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A multi-channel TR component, the front end of which is connected to a main control chip (2), and internally integrates multiple parallel beam control chips (1); characterized in that: The multi-channel TR component also includes a wavecode communication module (3); The front end of the beam control code communication module (3) is connected to the main control chip (2), and its back end is connected to the multiple parallel beam control chips (1). The wave control code communication module (3) and the main control chip (2) use high-speed communication to receive wave control codes; The beam control code communication module (3) writes beam control codes to multiple beam control chips (1) connected in parallel in a parallel manner; The wave control code communication module (3) includes: The serial communication unit (31) is used to receive the channel control commands and beam control data sent by the main control chip (2) at high speed, and send the beam control code readback data of each channel to the main control chip (2). The instruction parsing data buffer unit (32) is used to receive and temporarily store the control instructions and beam control data of each channel output by the serial communication unit (31), and output the control instructions and beam control data to the data processing unit (33) in a first-in-first-out manner. The data processing unit (33) is used to classify and process the beam control data according to the control command; including sending the beam control code obtained from the beam control data processing to the output driving circuit (34); collecting the beam control code status data at the output terminal of the output driving circuit (34) in real time, and sending the beam control code status data to the serial communication unit (31). The output drive circuit (34) is used to amplify the beam control code signal to drive the subsequent beam control chips (1). PLL circuit (35) is used to generate an 800MHz clock signal for synchronizing and shaping the SW signal based on the LVDS communication clock signal. The signal synchronization shaping unit (36) is used to synchronously sample the SW signal according to the clock signal, and to shape the sampled SW signal according to the working requirements of the TR component, and output it to each beam control chip (1). It also includes the first to third LVDS interfaces (371, 372, 373); The first LVDS interface (371) is used to receive high-speed clock signals; The second LVDS interface (372) is used to receive high-speed data signals; The third LVDS interface (373) is used to send the wave control code readback data of each channel; The receiving data signal port (3102) of the serial communication unit (31) is connected to the wave control data output terminal (23) of the main control chip (2) through the second LVDS interface (372), and the sending data port (3103) of the serial communication unit (31) is connected to the readback data port (24) of the main control chip (2) through the third LVDS interface (373). The clock signal port (3101) of the serial communication unit (31) is connected to the input terminal of the PLL circuit (35), and is simultaneously connected to the clock signal port (22) of the main control chip (2) through the first LVDS interface (371).

2. The multi-channel TR component according to claim 1, characterized in that: The input end of the instruction parsing data buffer unit (32) is connected to the data output end (3104) of the serial communication unit (31), and its output end is connected to the data receiving end (3301) of the data processing unit (33). The input terminal (3401) of the output driving circuit (34) is connected to the output terminal (3303) of the data processing unit (33), its beam control code output terminal (3402) is connected to the beam control code input terminal of each beam control chip (1), and the beam control code status sampling terminal (3403) of the output driving circuit (34) is connected to the data acquisition input terminal (3304) of the data processing unit (33). The data processing unit (33) has its data acquisition output terminal (3302) connected to the serial communication unit (31)'s readback data port (3105); The clock input terminal (3601) of the signal synchronization shaping unit (36) is connected to the output terminal of the PLL circuit (35), the SW signal input terminal (3602) of the signal synchronization shaping unit (36) is connected to the SW signal transmission port (21) of the main control chip (2), and the TR-type signal output terminal (3603) of the signal synchronization shaping unit (36) is connected to the control terminal of each beam control chip (1).

3. The multi-channel TR component according to claim 2, characterized in that: The serial communication unit (31) includes a shift register (311), a data frame header parsing circuit (312), a data frame tail parsing circuit (313), a data receiving control circuit (314), a data verification circuit (315), a data buffer sending circuit (316), a data frame synthesis circuit (317), and a data frame sending circuit (318). The clock input terminal (3111) of the shift register (311) corresponds to the clock signal port (3101) and is used to connect to the first LVDS interface (371). Its receiving data input terminal (3112) corresponds to the receiving data signal port (3102) and is used to connect to the second LVDS interface (372). The receiving data output terminal (3113) of the shift register (311) is connected to the data input terminal of the data frame header parsing circuit (312), the second data input terminal (3132) of the data frame tail parsing circuit (313), and the third data input terminal (3143) of the data receiving control circuit (314), respectively. The output of the data frame header parsing circuit (312) is connected to the first data input terminal (3131) of the data frame tail parsing circuit (313) and the first data input terminal (3141) of the data receiving control circuit (314), respectively. The second data input terminal (3142) of the data receiving control circuit (314) is connected to the output terminal (3133) of the data frame end parsing circuit (313); The output terminal (3146) of the data receiving control circuit (314) is connected to the input terminal of the data buffer sending circuit (316); the output terminal of the data buffer sending circuit (316) corresponds to the data output terminal (3104) of the serial communication unit (31), and is used to connect to the input terminal of the instruction parsing data buffer unit (32). The data receiving control circuit (314) and the data verification circuit (315) are bidirectionally connected; The input terminal of the data frame synthesis circuit (317) corresponds to the readback data port (3105) of the serial communication unit (31), and is used to connect to the data acquisition output terminal (3302) of the data processing unit (33). The input terminal of the data frame sending circuit (318) is connected to the output terminal of the data frame synthesis circuit (317); its output terminal is used to connect to the third LVDS interface (373).

4. The multi-channel TR component according to claim 3, characterized in that: The data processing unit (33) includes a wave control code synthesis circuit (331), a wave control code parallel transmission circuit (332), a power control data buffer (333), an amplitude attenuation data buffer (334), a phase offset data buffer (335), a readback control circuit (336), a wave control code readback sampling circuit (337), a readback data transmission circuit (338), and a temperature detection circuit (339). The power control input terminal (3311) of the wave code synthesis circuit (331) is connected to the output terminal of the instruction parsing data buffer unit (32) through the power control data buffer (333); The amplitude attenuation value input terminal (3312) of the wave code synthesis circuit (331) is connected to the output terminal of the instruction parsing data buffer unit (32) through the amplitude attenuation data buffer (334); The phase offset input terminal (3313) of the wave code synthesis circuit (331) is connected to the output terminal of the instruction parsing data buffer unit (32) through the phase offset data buffer (335); The output terminal (3314) of the wave code synthesis circuit (331) is connected to the input terminal of the wave code parallel transmission circuit (332), and the output terminal of the wave code parallel transmission circuit (332) is used to connect to the input terminal (341) of the output driving circuit (34). The instruction terminal (3361) of the readback control circuit (336) is connected to the output terminal of the instruction parsing data buffer unit (32), its temperature input terminal (3362) is connected to the output terminal of the temperature detection circuit (339), its status data input terminal (3363) is connected to the output terminal of the wave control code readback sampling circuit (337), and its output terminal (3364) is connected to the input terminal of the readback data sending circuit (338). The input terminal of the wave control code readback sampling circuit (337) is used to connect to the wave control code status sampling terminal (3403) of the output driving circuit (34); The output of the readback data transmission circuit (338) is used to connect to the readback data port (3105) of the serial communication unit (31).

5. The multi-channel TR component according to claim 4, characterized in that: The signal synchronization shaping unit (36) includes a synchronization sampling circuit (361), a T1 delay circuit (362), a T2 delay circuit (363), a T3 delay circuit (364), a COM signal shaping circuit (365), a T4 delay circuit (366), a TR signal shaping circuit (367), and a signal output driving circuit (368). The clock sampling terminal (3611) of the synchronous sampling circuit (361) corresponds to the clock input terminal (3601), which is used to connect to the output terminal of the PLL circuit (35). Its SW signal sampling terminal (3612) corresponds to the SW signal input terminal (3602), which is used to connect to the SW signal sending port (21) of the main control chip (2). The output terminal of the synchronous sampling circuit (361) is connected to the input terminals of the T1 delay circuit (362) and the T4 delay circuit (366) respectively. The output terminal of the T1 delay circuit (362) is connected to the input terminal of the T2 delay circuit (363) and the first input terminal (3671) of the TR signal shaping circuit (367), respectively. The output terminal of the T2 delay circuit (363) is connected to the input terminal of the T3 delay circuit (364) and the second input terminal (3652) of the COM signal shaping circuit (365), respectively. The first input terminal (3651) of the COM signal shaping circuit (365) is connected to the output terminal of the T3 delay circuit (364), and its output terminal (3653) is connected to the first input terminal (3681) of the signal output driving circuit (368). The second input terminal (3672) of the TR signal shaping circuit (367) is connected to the output terminal of the T4 delay circuit (366), and its output terminal (3673) is connected to the second input terminal (3682) of the signal output driving circuit (368). The output terminal (3683) of the signal output driving circuit (368) corresponds to the TR-type signal output terminal (3603), which is used to connect to the control terminal of each beam control chip (1).

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