Array substrate, display device and display motherboard
By introducing a second conductive line in the array substrate and display motherboard to connect the test electrodes, the problem of misjudgment of dark lines caused by electrostatic discharge was solved, stable conduction of the signal path was achieved, the test accuracy and product yield were improved, and the production cost was reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING BOE DISPLAY TECH CO LTD
- Filing Date
- 2022-04-29
- Publication Date
- 2026-06-19
AI Technical Summary
The existing array substrate exhibits a phenomenon of misjudging dark lines during the cell signal illumination test, mainly due to damage to the conductive layer and obstruction of the signal path caused by electrostatic discharge.
A second conductive line is introduced into the array substrate and the display motherboard. The test electrode is connected through this line to form a test path, which replaces the metal wire and crosses the break line. This avoids static electricity generated by the friction between the cutting wheel and the metal wire, thereby reducing charge accumulation and static discharge.
This improved the accuracy and reliability of lamp testing, increased the product yield of display devices, and reduced production costs.
Smart Images
Figure CN117008382B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more specifically, to an array substrate, a display device, and a display motherboard. Background Technology
[0002] Liquid crystal displays (LCDs) have many advantages, such as being thin, energy-saving, and radiation-free, and are widely used in applications such as LCD TVs, mobile phones, personal digital assistants (PDAs), digital cameras, computer screens, and laptop screens.
[0003] The structure of an LCD panel typically consists of a color filter substrate (CF), a thin film transistor array substrate (TFT array substrate), and a liquid crystal layer (LC) disposed between the two substrates. Its working principle is to control the rotation of liquid crystal molecules in the liquid crystal layer by applying a driving voltage to the two glass substrates, thereby refracting the light from the backlight module to produce an image.
[0004] In the production of CF substrates and TFT array substrates, especially in the production of TFT array substrates, electrostatic discharge (ESD) is a very common and difficult-to-avoid phenomenon. ESD leads to reduced yield, increased cost, and decreased production capacity of LCD panels. The signal illumination inspection process is a crucial process in the LCD industry, aiming to screen out defective panels before panel bonding and signal terminal crimping, thus avoiding waste of module materials. Signal illumination includes array signal illumination testing (AT) and cell signal illumination testing (CT). AT is mainly performed after the array substrate production process is completed, and the panel is checked by applying power. CT is mainly performed after the panel is cut. The array substrate manufacturing process typically involves first creating a large-area master board, and then cutting the master board into many array substrates. After the master board is formed, AT testing is performed first, followed by CT testing after cutting. However, CT testing is prone to errors, resulting in low accuracy in good product detection.
[0005] In summary, the existing array substrate has a technical problem of misjudging dark lines during the cell signal illumination test. Summary of the Invention
[0006] This application addresses the shortcomings of existing methods by proposing an array substrate, a display device, and a display motherboard to solve the technical problem of misjudging dark lines during cell signal illumination testing of array substrates in the prior art.
[0007] In a first aspect, embodiments of this application provide an array substrate, comprising:
[0008] A first substrate includes a display area and a sub-peripheral region located on one side of the display area, the first sub-peripheral region including a bonding area;
[0009] The signal terminal is located in the bonding area and is connected to the data line in the corresponding display area;
[0010] A first test electrode is located in the first sub-peripheral region and connected to a signal terminal; and
[0011] The second conductive line is connected at one end to the first test electrode and extends to the edge of the array substrate at the other end.
[0012] In some embodiments of this application, the array substrate further includes a first signal line, a terminal lead, and a first conductive line. The first signal line is connected to the first test electrode and the first conductive line, respectively, and the terminal lead is connected to the first conductive line and the signal terminal, respectively.
[0013] In some embodiments of this application, at least one of the first conductive line and the second conductive line is made of a transparent conductive material.
[0014] In some embodiments of this application, the array substrate includes a first metal layer and a second metal layer located on the side of the first metal layer away from the first substrate, at least a portion of the first metal layer forms terminal leads, and at least a portion of the second metal layer forms first signal lines.
[0015] In some embodiments of this application, at least a portion of the first conductive wire is located on the side of the second metal layer away from the first metal layer, a first insulating layer is disposed between the first metal layer and the second metal layer, a second insulating layer is disposed between a portion of the first conductive wire and the second metal layer, a first bridging hole is provided in both the first insulating layer and the second insulating layer, and a portion of the first conductive wire is filled in the first bridging hole.
[0016] In some embodiments of this application, at least a portion of the first conductive wire is located on the side of the first metal layer away from the second metal layer, a first insulating layer is disposed between the first metal layer and the second metal layer, a second insulating layer is disposed between a portion of the first conductive wire and the first metal layer, a first bridging hole is provided in both the first insulating layer and the second insulating layer, and a portion of the first conductive wire is filled in the first bridging hole.
[0017] In some embodiments of this application, at least a portion of the first conductive wire is located between the second metal layer and the first metal layer, a first insulating layer is disposed between the first metal layer and a portion of the first conductive wire, a second insulating layer is disposed between a portion of the first conductive wire and the second metal layer, and a first bridging hole is formed in both the first insulating layer and the second insulating layer, with a portion of the first conductive wire filling the first bridging hole.
[0018] In some embodiments of this application, the first metal layer includes at least one of titanium, molybdenum, niobium, copper, and aluminum, and the second metal layer includes at least one of titanium, molybdenum, niobium, copper, and aluminum.
[0019] Secondly, embodiments of this application provide a display device, including: a color filter substrate disposed opposite to each other and an array substrate as provided in any embodiment of the first aspect.
[0020] In some embodiments of this application, the signal terminal is bonded to the chip terminal; or, the signal terminal is bonded to the flip-chip terminal.
[0021] Thirdly, embodiments of this application provide a display motherboard, comprising:
[0022] The second substrate includes at least two display areas, a peripheral region between the two display areas having a break line, a first sub-peripheral region between the break line and at least one of the two display areas, a second sub-peripheral region away from the break line from the first sub-peripheral region, and a bonding region in the first sub-peripheral region.
[0023] The signal terminal is located in the bonding area and is connected to the data line in the corresponding display area;
[0024] A first test electrode is located in the first sub-peripheral region and connected to a signal terminal; and
[0025] The second test electrode is located in the second sub-peripheral region and is connected to the first test electrode through a second conductive line. A portion of the second conductive line is located in the first sub-peripheral region and is connected to the first test electrode, while another portion of the second conductive line is located in the second sub-peripheral region and is connected to the second test electrode.
[0026] In some embodiments of this application, the display motherboard further includes a second signal line, which is connected to the second test electrode and the second conductive line, respectively.
[0027] In some embodiments of this application, the display motherboard includes a first metal layer and a second metal layer located on the side of the first metal layer away from the second substrate, at least a portion of the first metal layer forms terminal leads, and at least a portion of the second metal layer forms second signal lines.
[0028] In some embodiments of this application, at least a portion of the second conductive lines are located on the side of the second metal layer away from the second substrate, a third insulating layer is disposed between the portion of the second conductive lines and the second metal layer, a second bridging hole is formed in the third insulating layer, and a portion of the second conductive lines are filled in the second bridging hole.
[0029] The beneficial technical effects of the technical solution provided in this application include: by setting a second conductive line to connect the first test electrode and the second test electrode to form a test path, the second conductive line replaces the metal wire to cross the breaking line. Compared with the prior art, this avoids the static electricity generated by the friction between the cutting wheel and the metal wire during the breaking process, thereby reducing the charge accumulated on the metal wire and lowering the probability of electrostatic discharge from the metal wire. This ensures the conduction of the signal path, improves the accuracy and reliability of the lamp-lighting test, and thus improves the product yield of the display device and reduces production costs. Additional aspects and advantages of this application will be set forth in part in the description which follows, and will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0030] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:
[0031] Figure 1 This is a schematic diagram of the array substrate structure in one embodiment of this application;
[0032] Figure 2 for Figure 1 A schematic diagram of a cross-section of an array substrate along C-C';
[0033] Figure 3 for Figure 1 A schematic diagram of a cross-section along C-C' of another type of array substrate;
[0034] Figure 4 for Figure 1 An enlarged schematic diagram of the left connection point at Q on an array substrate;
[0035] Figure 5 for Figure 1 A schematic diagram of a cross-section of an array substrate along B-B';
[0036] Figure 6 for Figure 5 An enlarged schematic diagram of point P on an array substrate;
[0037] Figure 7 This is a schematic diagram showing the structure of the motherboard in one embodiment of this application.
[0038] In the picture:
[0039] 1-First substrate; 11-Break line;
[0040] 21-First test electrode; 22-First conductive line; 23-First signal line; 24-First insulating layer; 25-Second insulating layer;
[0041] 31-Second test electrode; 32-Second conductive line; 33-Second signal line; 34-Third insulating layer; 35-Fourth insulating layer;
[0042] 41 - Signal terminal; 42 - Terminal lead;
[0043] 5-Data line; 6-Second substrate; 7-Array substrate; 8-Color filter substrate; 9-Frame adhesive. Detailed Implementation
[0044] This application is described in detail below. Examples of embodiments of this application are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. Furthermore, detailed descriptions of known technologies that are unnecessary for the features of this application are omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0045] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.
[0046] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.
[0047] Research has found that during panel breaking, the cutting wheel accumulates charge on the metal wires under high-speed rotation. ESD can cause damage to the conductive layer, or even breakage of the conductive layer, preventing signals from being transmitted to the data lines, which manifests as dark lines in the display area.
[0048] In the existing array substrate, static electricity is easily generated during the panel splitting process, which can damage the conductive layer and cause a technical problem of misjudgment of dark lines during the signal lighting test of the box assembly.
[0049] This application provides an array substrate, a display device, and a display motherboard, aiming to solve the above-mentioned technical problems of the prior art. The technical solution of this application and how it solves the aforementioned technical problems are described in detail below with specific embodiments.
[0050] Firstly, embodiments of this application provide an array substrate. For example... Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of the array substrate 7 in one embodiment of this application. The array substrate 7 includes:
[0051] A first substrate 1 includes a display area and a sub-peripheral area located on one side of the display area, wherein the first sub-peripheral area includes a bonding area;
[0052] Signal terminal 41 is located in the binding area and connected to the data line 5 in the corresponding display area;
[0053] The first test electrode 21 is located in the first sub-peripheral region and connected to the signal terminal 41; and
[0054] The second conductive line 32 has one end connected to the first test electrode 21 and the other end extended to the edge of the array substrate 7. The second conductive line 32 is used to connect to the second test electrode 31 on the array motherboard before the array substrate 7 is broken.
[0055] In one specific embodiment, the second conductive line 32 is located in the common conductive layer, the portion of the common conductive layer located in the display area forms a common electrode, and the portion of the common conductive layer located in the first sub-peripheral area forms the second conductive line 32.
[0056] By setting a second conductive line 32 to connect the first test electrode 21 and the second test electrode 31 to form a test path, the second conductive line 32 replaces the metal wire and crosses the breaking line 11. Compared with the prior art, this avoids the static electricity generated by the friction between the cutting wheel and the metal wire during the breaking process, thereby reducing the charge accumulated on the metal wire and lowering the probability of static discharge from the metal wire.
[0057] In some embodiments of this application, at least a portion of the second conductive line 32 is located on the side of the first test electrode 21 away from the first substrate 1.
[0058] like Figure 2 As shown, Figure 2 for Figure 1 A schematic cross-sectional view of an array substrate along C-C' is shown. A first test electrode 21 and a first signal line 23 are disposed on the same layer on a first substrate 1. The main body of a second conductive line 32 is located on the side of the first test electrode 21 away from the first substrate 1. A third insulating layer 34 is disposed between the second conductive line 32 and the first test electrode 21. A second bridging hole is formed in the third insulating layer 34. The bridging portion of the second conductive line 32 is filled in the second bridging hole, and the second conductive line 32 is conductive to the first test electrode 21.
[0059] In the segmented manufacturing process, the second conductive wire 32 undergoes high-speed friction with the cutting wheel, potentially becoming a discharge source. The wire with weaker antistatic properties becomes the sensitive element. One factor affecting the intensity of electrostatic discharge is the distance between the discharge source and the sensitive element. Electrostatic discharge is a high-frequency interference, generating an electromagnetic field during discharge. When the discharge source and the sensitive element are close, there is a larger parasitic capacitance and a smaller coupling impedance, making the sensitive element more susceptible to interference and damage. In this embodiment, by placing the second conductive wire 32 on the side of the first test electrode 21 away from the first substrate 1, and in at least one embodiment, the sensitive element is located on the side of the first test electrode 21 closer to the first substrate 1, this embodiment increases the distance between the second conductive wire 32 and the sensitive element, reducing the probability of electrostatic discharge on the second conductive wire 32, decreasing the risk of damage to the sensitive element, and ensuring the continuity of the signal path.
[0060] like Figure 3 As shown, Figure 3 for Figure 1 A schematic diagram of a cross-section along C-C' of another type of array substrate. (See diagram below.) Figure 2 As shown, Figure 2 for Figure 1 A schematic cross-sectional view of an array substrate along C-C' is shown. A first test electrode 21 and a first signal line 23 are disposed on a first substrate 1 in the same layer. The main body of a second conductive line 32 is located on the side of the first test electrode 21 away from the first substrate 1. A third insulating layer 34 and a fourth insulating layer 35 are disposed between the second conductive line 32 and the first test electrode 21. Sub-holes are respectively formed in the third insulating layer 34 and the fourth insulating layer 35, and the two sub-holes are connected vertically to form a second bridging hole. The bridging portion of the second conductive line 32 fills the second bridging hole, and the second conductive line 32 is conductive to the first test electrode 21.
[0061] In some other embodiments of this application, the material in the first conductive wire 22 includes a transparent conductive material, and the material in the second conductive wire 32 includes a transparent conductive material.
[0062] In one embodiment, the transparent conductive material is indium tin oxide; in another embodiment, the transparent conductive material is indium zinc oxide.
[0063] Another factor affecting the intensity of electrostatic discharge includes the material of the discharge body. Different materials have different charge migration rates. In at least one embodiment, the material of the second conductive wire 32 includes indium tin oxide (ITO). ITO has a higher sheet resistance than the sheet resistance of metal wires in the prior art, and the charge migration rate in ITO is lower than that in metal wires. Therefore, the amount of charge exchanged between ITO and the cutting wheel is less than the amount of charge exchanged between the metal wire and the cutting wheel. This reduces the probability of electrostatic discharge on the second conductive wire 32, reduces the risk of damage to the sensitive element, and ensures the continuity of the signal path.
[0064] Based on the above embodiments, this application also discloses some embodiments, such as... Figure 4 As shown, Figure 4 for Figure 1 An enlarged schematic diagram of the left connection point at Q on an array substrate 7. The array substrate 7 also includes a first signal line 23, a terminal lead 42, and a first conductive line 22. The first signal line 23 is connected to the first test electrode 21 and the first conductive line 22, respectively. The terminal lead 42 is connected to the first conductive line 22 and the signal terminal 41, respectively.
[0065] After the separation process, the array substrate 7 retains at least one signal path for the cell assembly signal lighting test. This includes: a first test electrode 21 receiving the cell assembly test signal, which is then emitted from its output terminal and sequentially transmitted through a first signal line 23, a first conductive line 22, and a terminal lead 42 to a signal terminal 41. The signal terminal 41 transmits the signal to the data line 5 to activate the LEDs and identify defective panels.
[0066] It is understandable that, prior to the separation process, the display motherboard must simultaneously retain signal paths for both array signal illumination testing and cell-to-cell signal illumination testing. The signal path for cell-to-cell signal illumination testing is as described in the above embodiment and will not be repeated here. The signal path for array signal illumination testing includes: the second test electrode 31 receives the array test signal, which is then transmitted from the output terminal of the second test electrode 31 sequentially through the second signal line 33, the second conductive line 32, and the input terminal of the first test electrode 21 to the first test electrode 21. From the output terminal of the first test electrode 21, the signal is then transmitted sequentially through the first signal line 23, the first conductive line 22, and the terminal lead 42 to the signal terminal 41. The signal terminal 41 transmits the signal to the data line 5 to illuminate the LEDs and troubleshoot defective panels.
[0067] In some embodiments of this application, the array substrate 7 includes a first metal layer and a second metal layer located on the side of the first metal layer away from the first substrate 1, at least a portion of the first metal layer forms terminal leads 42, and at least a portion of the second metal layer forms first signal lines 23.
[0068] In this embodiment, the first signal line 23 and the terminal lead 42 are located on different layers to prevent the first signal line 23 and the terminal lead 42 from intersecting on the same layer, or to avoid extending the length of the first signal line 23 or the terminal lead 42, which would occupy more wiring space and waste more manufacturing costs. In one embodiment, the terminal lead 42 is located in a first metal layer close to the first substrate 1, and the first signal line 23 is located in a second metal layer away from the first substrate 1. In another embodiment, the terminal lead 42 is located in a second metal layer away from the first substrate 1, and the first signal line 23 is located in a first metal layer close to the first substrate 1.
[0069] In one embodiment of this application, such as Figure 5 and Figure 6 As shown, Figure 5 for Figure 1 A schematic diagram of a cross-section of an array substrate along B-B'. Figure 6 for Figure 5 An enlarged schematic diagram of an array substrate P. At least a portion of the first conductive lines 22 are located on the side of the second metal layer away from the first metal layer. A first insulating layer 24 is disposed between the first and second metal layers, and a second insulating layer 25 is disposed between a portion of the first conductive lines 22 and the second metal layer. First bridging holes are formed in both the first and second insulating layers, and a portion of the first conductive lines 22 fills the first bridging holes. The panel edge is where the break line 11 is located. The minimum distance between the break line 11 and the metal wire is D. If D is greater than 0, the metal wire closest to the panel edge still maintains a certain distance from the break line 11 to avoid the metal wire directly contacting the cutting wheel and accumulating static electricity.
[0070] In this embodiment, at least a portion of the first conductive line 22 is located on the side of the first metal layer and the second metal layer away from the first substrate 1, that is, the main body of the first conductive line 22 is located on the outermost side of the array substrate 7 relative to the first metal layer and the second metal layer. In a specific embodiment, the main body of the first conductive line 22, the first metal layer, and the second metal layer are parallel to each other. First bridging holes are formed between the main body of the first conductive line 22 and the first metal layer, and between the main body of the first conductive line 22 and the second metal layer. The bridging portion of the first conductive line 22 fills the at least two of the first bridging holes, thereby achieving electrical connection between the first conductive line 22 and the first metal layer and the second metal layer, respectively. This simultaneously achieves layer switching and conduction between the first metal layer and the second metal layer, forming a complete signal path. The above embodiments only describe the first conductive line 22 as including one main body. If the first conductive line 22 includes two or more main bodies, the two or more main bodies are located in different layers and are parallel to each other. More first bridging holes are opened between the different main bodies. The bridging portion of the first conductive line 22 fills the newly opened first bridging holes. The multiple main bodies work together to realize the electrical connection between the first conductive line 22 and the first metal layer and the second metal layer respectively.
[0071] It is worth mentioning that the main body of the first conductive line 22 and the main body of the second conductive line 32 can both be located in the common conductive layer, or one of them can be located in the common conductive layer and disposed in the same layer as the common electrode located in the display area.
[0072] In another embodiment of this application, at least a portion of the first conductive wire 22 is located on the side of the first metal layer away from the second metal layer, a first insulating layer 24 is disposed between the first metal layer and the second metal layer, a second insulating layer 25 is disposed between a portion of the first conductive wire 22 and the first metal layer, a first bridging hole is provided in both the first insulating layer 24 and the second insulating layer 25, and a portion of the first conductive wire 22 is filled in the first bridging hole.
[0073] In this embodiment, at least a portion of the first conductive line 22 is located on the side of the first metal layer and the second metal layer closer to the first substrate 1, that is, the main body of the first conductive line 22 is located at the innermost side of the array substrate 7 relative to the first metal layer and the second metal layer. In a specific embodiment, the main body of the first conductive line 22, the first metal layer, and the second metal layer are parallel to each other. First bridging holes are formed between the main body of the first conductive line 22 and the first metal layer, and between the main body of the first conductive line 22 and the second metal layer. The bridging portion of the first conductive line 22 fills the at least two of the first bridging holes, so that the first conductive line 22 is electrically connected to the first metal layer and the second metal layer respectively. Thus, the layer switching and conduction between the first metal layer and the second metal layer are realized simultaneously, forming a complete signal path. The above embodiments only describe the first conductive line 22 as including one main body. If the first conductive line 22 includes two or more main bodies, the two or more main bodies are located in different layers and are parallel to each other. More first bridging holes are opened between the different main bodies. The bridging portion of the first conductive line 22 fills the newly opened first bridging holes. The multiple main bodies work together to realize the electrical connection between the first conductive line 22 and the first metal layer and the second metal layer respectively.
[0074] In another embodiment of this application, at least a portion of the first conductive wire 22 is located between the second metal layer and the first metal layer. A first insulating layer 24 is disposed between the first metal layer and a portion of the first conductive wire 22, and a second insulating layer 25 is disposed between a portion of the first conductive wire 22 and the second metal layer. A first bridging hole is provided in both the first insulating layer 24 and the second insulating layer 25, and a portion of the first conductive wire 22 is filled in the first bridging hole.
[0075] In this embodiment, at least a portion of the first conductive line 22 is located between the first metal layer and the second metal layer, that is, the main body of the first conductive line 22 is located between the first metal layer and the second metal layer. In a specific embodiment, the main body of the first conductive line 22, the first metal layer, and the second metal layer are parallel to each other. First bridging holes are provided between the main body of the first conductive line 22 and the first metal layer, and between the main body of the first conductive line 22 and the second metal layer. The bridging portion of the first conductive line 22 fills at least two of the first bridging holes, thereby achieving electrical connection between the first conductive line 22 and the first metal layer and the second metal layer, respectively. This simultaneously achieves layer switching and conduction between the first metal layer and the second metal layer, forming a complete signal path. The above embodiments only describe the first conductive line 22 as including one main body. If the first conductive line 22 includes two or more main bodies, the two or more main bodies are located in different layers and are parallel to each other. More first bridging holes are opened between the different main bodies. The bridging portion of the first conductive line 22 fills the newly opened first bridging holes. The multiple main bodies work together to realize the electrical connection between the first conductive line 22 and the first metal layer and the second metal layer respectively.
[0076] In some embodiments of this application, the material in the first metal layer includes titanium, molybdenum, niobium, copper, or aluminum, and the material in the second metal layer includes titanium, molybdenum, niobium, copper, or aluminum.
[0077] The aforementioned materials possess excellent ductility and conductivity. The fabrication process for patterning the first and second metal layers to form various wires is simple and has low manufacturing costs. The various wires also offer fast signal transmission speeds.
[0078] Based on the same inventive concept, in a second aspect, this application provides a display device, which includes: a color filter substrate 8 and an array substrate 7 as described in the above embodiments, which are disposed opposite to each other, and the color filter substrate 8 and the array substrate 7 are connected by a frame adhesive 9.
[0079] In some embodiments of this application, signal terminal 41 is bonded to a chip-on-film (COF) terminal. COF is a die-on-film packaging technology that fixes integrated circuits onto a flexible circuit board, using a flexible add-on circuit board as a chip carrier to combine the chip with the flexible substrate circuitry. In addition to its panel connection function, COF can also support active and passive components, making products thinner and lighter.
[0080] In some other embodiments of this application, the signal terminal 41 is bonded to the chip terminal. The signal terminal is connected to the internal circuitry of the chip before packaging.
[0081] Based on the same inventive concept, in a third aspect, embodiments of this application also provide a display motherboard, such as... Figure 7 As shown, Figure 7 This is a schematic diagram of the structure of a display motherboard in one embodiment of this application. The display motherboard includes:
[0082] The second substrate 6 includes at least two display areas, a peripheral region between the two display areas having a break line 11, a first sub-peripheral region between the break line 11 and at least one of the two display areas, a second sub-peripheral region away from the break line 11, and a bonding area in the first sub-peripheral region.
[0083] Signal terminal 41 is located in the bonding area of the second substrate 6 and is connected to the data line 5 in the corresponding display area;
[0084] The first test electrode 21 is located in the first sub-peripheral region and is connected to the signal terminal 41 via terminal lead 42 and first conductive line 22; and
[0085] The second test electrode 31 is located in the second sub-peripheral region and is connected to the first test electrode 21 via a second conductive line 32. A portion of the second conductive line 32 is located in the first sub-peripheral region and connected to the first test electrode 21, while another portion of the second conductive line 32 is located in the second sub-peripheral region and connected to the second test electrode 31. The second conductive line 32 crosses the break line 11.
[0086] In this embodiment, the first test electrode 21 is located in the bonding area, the second test electrode 31 is located in the test area, and at least one break line 11 is located between the bonding area and the test area. After completing the array signal illumination test, the cutting wheel cuts the display motherboard along the break line 11 to form multiple array substrates 7. Since the subsequent cell-to-cell signal illumination test does not require the participation of the second test electrode 31, the break line 11 is usually intersected with the signal path of the array signal illumination test, without interfering with the signal path of the cell-to-cell signal illumination test. That is, the second conductive line 32 in the signal path of the array signal illumination test is intersected with at least one break line 11.
[0087] Before the separation process, the motherboard must simultaneously retain signal paths for both array signal illumination testing and cell signal illumination testing. The array signal illumination testing signal path includes: the second test electrode 31 receiving the array test signal, which is then transmitted from its output terminal to the first test electrode 21 via the second signal line 33, the second conductive line 32, and the input terminal of the first test electrode 21. From the output terminal of the first test electrode 21, the signal is transmitted sequentially via the first signal line 23, the first conductive line 22, and the terminal lead 42 to the signal terminal 41. The signal terminal 41 transmits the signal to the data line 5 to illuminate the LEDs and troubleshoot defective panels.
[0088] In some embodiments of this application, the display motherboard further includes a second signal line 33, which is connected to the second test electrode 31 and the second conductive line 32, respectively.
[0089] In some embodiments of this application, the display motherboard includes a first metal layer and a second metal layer located on the side of the first metal layer away from the second substrate 6. At least a portion of the first metal layer forms terminal leads 42, and at least a portion of the second metal layer forms second signal lines 33. The second signal lines 33 are disposed on the same layer as the first signal lines 23.
[0090] In this embodiment, the second signal line 33 and the terminal lead 42 are located on different layers to prevent the second signal line 33 and the terminal lead 42 from intersecting on the same layer, or to avoid intersecting by extending the length of the second signal line 33 or the terminal lead 42, which would occupy more wiring space and waste more manufacturing costs.
[0091] In one embodiment, the terminal lead 42 is located in a first metal layer close to the second substrate 6, and the second signal line 33 is located in a second metal layer away from the second substrate 6.
[0092] In another embodiment, the terminal lead 42 is located in a second metal layer away from the second substrate 6, and the second signal line 33 is located in a first metal layer close to the second substrate 6.
[0093] In another embodiment, the second signal line 33 is disposed on the same layer as the first signal line 23. During the fabrication of the metal layer, the first signal line 23 and the second signal line 33 can be formed simultaneously in a single patterning process, saving process and time costs.
[0094] In another embodiment, the second signal line 33 is disposed on a different layer than the first signal line 23. The positions of the film layers containing the second signal line 33 and the first signal line 23 are more flexible, which can adapt to more different types of display devices and has wider applicability.
[0095] In some embodiments of this application, at least a portion of the second conductive lines 32 are located on the side of the second metal layer away from the second substrate 6, and a third insulating layer 34 is disposed between the portion of the second conductive lines 32 and the second metal layer. A second bridging hole is formed in the third insulating layer 34, and a portion of the second conductive lines 32 are filled in the second bridging hole.
[0096] In this embodiment, at least a portion of the second conductive line 32 is located on the side of the second test electrode 31 and the second metal layer away from the second substrate 6, that is, the main body of the second conductive line 32 is located on the outermost side of the array substrate 7 relative to the second test electrode 31 and the second metal layer. In a specific embodiment, the main body of the first conductive line 22, the second test electrode 31, and the second metal layer are parallel to each other. First bridging holes are formed between the main body of the first conductive line 22 and the second test electrode 31, and between the main body of the first conductive line 22 and the second metal layer. The bridging portion of the first conductive line 22 fills at least two of the first bridging holes, thereby achieving electrical connection between the first conductive line 22 and the second test electrode 31 and the second metal layer, respectively. This simultaneously achieves layer switching and conduction between the second test electrode 31 and the second metal layer, forming a complete signal path. The above embodiments only describe the first conductive line 22 as including one main body. If the first conductive line 22 includes two or more main bodies, the two or more main bodies are located in different layers and are parallel to each other. More first bridging holes are opened between the different main bodies. The bridging portion of the first conductive line 22 fills the newly opened first bridging holes. The multiple main bodies work together to realize the electrical connection between the first conductive line 22 and the second test electrode 31 and the second metal layer, respectively.
[0097] By applying the embodiments of this application, at least the following beneficial effects can be achieved: by setting a second conductive line 32 to connect the first test electrode 21 and the second test electrode 31 to form a test path, the second conductive line 32 replaces the metal wire to cross the breaking line 11. Compared with the prior art, this avoids the static electricity generated by the friction between the cutting wheel and the metal wire during the breaking process, thereby reducing the charge accumulated on the metal wire and lowering the probability of static discharge from the metal wire. This ensures the conduction of the signal path, improves the accuracy and reliability of the lamp test, and thus improves the product yield of the display device and reduces production costs.
[0098] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0099] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0100] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0101] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0102] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.
Claims
1. An array substrate, characterized by, include: A first substrate includes a display area and a first sub-peripheral region located on one side of the display area, the first sub-peripheral region including a bonding area; The signal terminal is located in the bonding area and connected to the data line corresponding to the display area; The first test electrode is located in the peripheral region of the first sub-sub ... as well as The second conductive line has one end connected to the first test electrode and the other end extended to the edge of the array substrate; The array substrate further includes a first signal line, a terminal lead, and a first conductive line. The first signal line is connected to the first test electrode and the first conductive line, respectively, and the terminal lead is connected to the first conductive line and the signal terminal, respectively. The material in the second conductive wire includes a transparent conductive material. The first test electrode and the first signal line are disposed on the same layer on the first substrate. The main body of the second conductive line is located on the side of the first test electrode away from the first substrate. A third insulating layer is disposed between the second conductive line and the first test electrode. A second bridging hole is formed in the third insulating layer. The bridging portion of the second conductive line fills the second bridging hole, and the second conductive line is conductive to the first test electrode; or The first test electrode and the first signal line are disposed on the same layer on the first substrate. The main body of the second conductive line is located on the side of the first test electrode away from the first substrate. A third insulating layer and a fourth insulating layer are disposed between the second conductive line and the first test electrode. Sub-holes are respectively opened in the third insulating layer and the fourth insulating layer. The two sub-holes are connected vertically to form a second bridging hole. The bridging part of the second conductive line is filled in the second bridging hole. The second conductive line is conductive to the first test electrode.
2. The array substrate of claim 1, wherein, The material in the first conductive wire includes a transparent conductive material.
3. The array substrate of claim 1, wherein, The array substrate includes a first metal layer and a second metal layer located on the side of the first metal layer away from the first substrate. At least a portion of the first metal layer forms terminal leads, and at least a portion of the second metal layer forms first signal lines.
4. The array substrate of claim 3, wherein, At least a portion of the first conductive wire is located on the side of the second metal layer away from the first metal layer. A first insulating layer is provided between the first metal layer and the second metal layer. A second insulating layer is provided between a portion of the first conductive wire and the second metal layer. A first bridging hole is provided in both the first insulating layer and the second insulating layer. A portion of the first conductive wire is filled in the first bridging hole.
5. The array substrate of claim 3, wherein, At least a portion of the first conductive wire is located on the side of the first metal layer away from the second metal layer. A first insulating layer is disposed between the first metal layer and the second metal layer. A second insulating layer is disposed between a portion of the first conductive wire and the first metal layer. A first bridging hole is formed in both the first insulating layer and the second insulating layer. A portion of the first conductive wire is filled in the first bridging hole.
6. The array substrate of claim 3, wherein, At least a portion of the first conductive wire is located between the second metal layer and the first metal layer. A first insulating layer is disposed between the first metal layer and a portion of the first conductive wire, and a second insulating layer is disposed between a portion of the first conductive wire and the second metal layer. A first bridging hole is formed in both the first insulating layer and the second insulating layer, and a portion of the first conductive wire is filled in the first bridging hole.
7. The array substrate of claim 3, wherein, The first metal layer comprises at least one of titanium, molybdenum, niobium, copper, and aluminum, and the second metal layer comprises at least one of titanium, molybdenum, niobium, copper, and aluminum.
8. The array substrate of claim 1, wherein, At least a portion of the second conductive line is located on the side of the first test electrode away from the first substrate.
9. A display device comprising: It includes a color filter substrate disposed opposite to each other and an array substrate as described in any one of claims 1-8.
10. The display device according to claim 9, wherein The signal terminal is bonded to the chip terminal; or, the signal terminal is bonded to the flip-chip terminal.
11. A display motherboard, characterized by include: The second substrate includes at least two display areas, and a peripheral region located between the two display areas has a break line: a first sub-peripheral region is located between the break line and at least one of the two display areas, and a second sub-peripheral region is located away from the first sub-peripheral region of the break line, and the first sub-peripheral region has a bonding area. The signal terminal is located in the bonding area and connected to the data line corresponding to the display area; The first test electrode is located in the peripheral region of the first sub-sub ... as well as The second test electrode is located in the second sub-peripheral region and is connected to the first test electrode through a second conductive line. A portion of the second conductive line is located in the first sub-peripheral region and is connected to the first test electrode, and another portion of the second conductive line is located in the second sub-peripheral region and is connected to the second test electrode. The display motherboard further includes a first signal line, a terminal lead, and a first conductive line. The first signal line is connected to the first test electrode and the first conductive line, respectively, and the terminal lead is connected to the first conductive line and the signal terminal, respectively. The material in the second conductive wire includes a transparent conductive material. The first test electrode and the first signal line are disposed on the same layer on the second substrate. The main body of the second conductive line is located on the side of the first test electrode away from the second substrate. A third insulating layer is disposed between the second conductive line and the first test electrode. A second bridging hole is formed in the third insulating layer, and the bridging portion of the second conductive line fills the second bridging hole. The second conductive line is conductive to the first test electrode; or The first test electrode and the first signal line are disposed on the same layer on the second substrate. The main body of the second conductive line is located on the side of the first test electrode away from the second substrate. A third insulating layer and a fourth insulating layer are disposed between the second conductive line and the first test electrode. Sub-holes are respectively opened in the third insulating layer and the fourth insulating layer. The two sub-holes are connected vertically to form a second bridging hole. The bridging part of the second conductive line is filled in the second bridging hole. The second conductive line is conductive to the first test electrode.
12. The display motherboard according to claim 11, characterized in that, The display motherboard also includes a second signal line, which is connected to the second test electrode and the second conductive line respectively.
13. The display motherglass of claim 12, wherein, The display motherboard includes a first metal layer and a second metal layer located on the side of the first metal layer away from the second substrate. At least a portion of the first metal layer forms terminal leads, and at least a portion of the second metal layer forms second signal lines.
14. The display motherglass of claim 13, wherein, At least a portion of the second conductive line is located on the side of the second metal layer away from the second substrate, and a third insulating layer is disposed between a portion of the second conductive line and the second metal layer. A second bridging hole is formed in the third insulating layer, and a portion of the second conductive line fills the second bridging hole.