Tdc circuit, time interval measurement circuit and electronic device

Abstract

The application provides a TDC circuit, a time interval measurement circuit and an electronic device, comprising: a first ring delay chain, a second ring delay chain, a first timer, and a second timer; the first ring delay chain is configured to cyclically transmit the timing start signal; the second ring delay chain is configured to cyclically transmit the timing end signal; the first counter is configured to count the number of cycles of the cyclic transmission of the timing start signal during the cyclic transmission of the timing start signal, and obtain first count information; the second counter is configured to count the number of cycles of the cyclic transmission of the timing start signal during the cyclic transmission of the timing start signal, and obtain second count information; and a processing module is configured to obtain the first count information and the second count information, and determine current time interval information based on the first count information and the second count information.

Description

Technical Field

[0001] This invention relates to the field of time measurement, and more particularly to a TDC circuit, a time interval measurement circuit, and an electronic device. Background Technology

[0002] A time-to-digital converter (TDC) can be understood as any circuit capable of detecting the time interval between an input start signal and a received signal, which can be generated based on the rising and falling edges of a trigger pulse.

[0003] In existing related technologies, TDCs have strict requirements on the order of the input timing start and timing end signals, that is, the start signal must arrive before the end signal. However, when the start signal lags behind the end signal, the TDC will not work properly, which will cause the TDC to fail to output the correct measurement results in many cases.

[0004] To address this issue, a pre-processor circuit can be introduced before the TDC circuit. This pre-processor circuit can determine the order of the two input signals (start signal and end signal) before they are input into the TDC circuit. However, this pre-processor circuit not only increases the overall area and power consumption but also lengthens the time required to complete a measurement. Furthermore, this pre-processor circuit may introduce a certain amount of offset, which will affect the accuracy of the measurement. Summary of the Invention

[0005] This invention provides a TDC circuit, a time interval measurement circuit, and an electronic device to overcome the defects caused by introducing preceding circuits.

[0006] According to a first aspect of the present invention, a TDC circuit is provided, comprising: a first ring delay chain, a second ring delay chain, a first counter, and a second counter;

[0007] The input end of the first circular delay chain is used to receive the timing start signal, and the output end of the first circular delay chain is connected to the input end of the first circular delay chain; the first circular delay chain is used to: cyclically transmit the timing start signal in the first circular delay chain, and perform a delay of the timing start signal during the cyclic transmission process;

[0008] The input end of the second circular delay chain is used to receive the timing end signal, and the output end of the second circular delay chain is connected to the input end of the second circular delay chain; the second circular delay chain is used to: cyclically transmit the timing end signal in the second circular delay chain, and perform a delay on the timing end signal during the cyclic transmission process;

[0009] The signal transmission speed of the second ring delay chain to the timing end signal and the signal transmission speed of the first ring delay chain to the timing start signal can be configured to be different.

[0010] The first counter is used to count the number of cycles of the timing start signal during the cyclic transmission of the timing start signal, and obtain first counting information;

[0011] The second counter is used to count the number of cycles of the timing start signal during the cyclic transmission of the timing start signal, and to obtain second counting information;

[0012] Both the first counter and the second counter are connected to a processing module. The processing module is used to acquire the first counting information and the second counting information, and based on the first counting information and the second counting information, determine the current time interval information between the timing start signal connected to the first circular delay chain and the timing end signal connected to the second circular delay chain.

[0013] Optionally, the TDC circuit further includes N arbitrators, the first ring delay chain includes N first delay units, and the second ring delay chain includes N second delay units;

[0014] The N first delay units are connected in sequence, and the output of the last first delay unit is connected to the input of the first first delay unit; the N second delay units are connected in sequence, and the output of the last second delay unit is connected to the input of the first second delay unit.

[0015] Each arbitrator is connected to a corresponding first delay unit and a second delay unit, and the first delay unit and the second delay unit connected to the arbitrator are in the same order in the corresponding circular delay chain;

[0016] The arbitrator is used to determine phase comparison information, which characterizes the phase sequence relationship between the timing start signal transmitted by the first delay unit connected to the arbitrator and the timing end signal transmitted by the second delay unit connected to the arbitrator.

[0017] The processing module is also connected to the arbitrator; when the processing module acquires the first counting information and the second counting information, and determines the current time interval information between the timing start signal connected to the first ring delay chain and the timing end signal connected to the second ring delay chain based on the first counting information and the second counting information, it is specifically used for:

[0018] During the cyclic transmission of the timing start signal and the timing end signal, if a phase comparison information output by any arbitrator is detected to be reversed, the first count information and the second count information at the time of reversal are obtained, and the current time interval information is determined based on the first count information and the second count information at the time of reversal.

[0019] Optionally, when determining the time interval information based on the first count information at the time of reversal and the second count information at the time of reversal, the processing module is specifically used for:

[0020] The current time interval information OUTCODE satisfies the following formula:

[0021] OUTCODE=CNT1*MSB1-CNT2*MSB2+n*LSB;

[0022] in:

[0023] CNT1 represents the first count information during the reversal;

[0024] CNT2 represents the second counting information during inversion;

[0025] MSB1 characterizes the signal propagation period of the first ring delay chain;

[0026] MSB2 characterizes the signal propagation period of the second ring delay chain;

[0027] LSB represents the delay difference between the first and second delay units in the same order;

[0028] n represents the number of second delay units that the timing end signal has passed through in the current cycle of transmission up to the time of reversal.

[0029] Optionally, both the first delay unit and the second delay unit include a signal transmission module and a vernier delay control module;

[0030] The signal transmission module of any delay unit is connected between the signal transmission modules of the two adjacent delay units of any delay unit, and is used to perform the transmission of the corresponding signal; the corresponding signal is the timing start signal or the timing end signal; the two adjacent delay units include: the previous delay unit connected to the input terminal of any delay unit in the corresponding circular delay chain, and the next delay unit connected to the output terminal of any delay unit;

[0031] The vernier delay control module of any delay unit is connected to the signal transmission module of any delay unit and is used to control whether a delay difference is generated between the first ring delay chain and the second ring delay chain.

[0032] Optionally, the signal transmission module includes a cascaded first inverter and a second inverter, and the vernier delay control module includes a first transistor and a second transistor;

[0033] The input terminal of the first inverter in any delay unit is connected to the output terminal of the second inverter in the previous delay unit, the input terminal of the second inverter in any delay unit is connected to the output terminal of the first inverter in any delay unit, and the output terminal of the second inverter in any delay unit is connected to the input terminal of the first inverter in the next delay unit.

[0034] In any of the delay units, the input terminal of the second inverter is also connected to the control terminal of the first transistor, the first terminal of the first transistor is connected to the output terminal of the second inverter, the second terminal of the first transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is grounded.

[0035] The signals connected to the control terminals of the second transistors in the first delay unit and the second delay unit are used to determine whether the delay difference is generated.

[0036] The arbitrator is connected to the output of the first inverter;

[0037] When determining phase comparison information, the arbitrator is specifically used to: determine the phase comparison information by comparing the signals output by the first inverter of the first delay unit and the second delay unit.

[0038] Optionally, if the signal connected to the control terminal of the second transistor in any k-th first delay unit is at the same level as the signal connected to the control terminal of the second transistor in the k-th second delay unit, then: the delay of the k-th first delay unit is the same as that of the k-th second delay unit.

[0039] If the signal connected to the control terminal of the second transistor in any k-th first delay unit is at a different level than the signal connected to the control terminal of the second transistor in the k-th second delay unit, then the delay between the k-th first delay unit and the k-th second delay unit has a specified delay difference.

[0040] Optionally, both the first delay unit and the second delay unit further include a delay calibration module;

[0041] The delay calibration module includes multiple transistors connected in parallel. These multiple transistors are connected to one end of the power supply terminal of the first inverter. The multiple transistors are configured to be selectively turned on to control the delay implemented by the corresponding delay unit.

[0042] According to a second aspect of the present invention, a time interval measurement circuit is provided, comprising an M-level TDC circuit;

[0043] The P-level TDC circuit in the M-level TDC circuit is the TDC circuit involved in the first aspect and its optional schemes.

[0044] Where M and P are both positive integers, M≥1, M≥P≥1.

[0045] Optionally, the M-level TDC circuit is a two-level TDC circuit, including a first-level TDC circuit and a second-level TDC circuit; the P-level TDC circuit is the first-level TDC circuit.

[0046] The timing start signal is the start signal of TDC, and the timing end signal is the stop signal of TDC;

[0047] The second-stage TDC circuit is used to obtain the start. res Signals and Stop res Signal, and determine the start res Signal and the stop res The time interval information between signals is used to determine the final time interval information between the start signal and the stop signal based on this time interval information and the current time interval information. res Signals and Stop res The time interval of the signal is matched to the time interval between the start signal and the end signal output by the first-stage TDC circuit after the cyclic transmission stops.

[0048] According to a third aspect of the invention, an electronic device is provided, comprising the time interval measurement circuit described in the second aspect and its alternatives.

[0049] The TDC circuit, time interval measurement circuit, and electronic device provided by this invention count both the slower-moving and faster-moving circular delay chains. Furthermore, since both circular delay chains are delayed and counted, regardless of whether the timing start signal or timing end signal is received first, the transmission time of the corresponding circular delay chain after the signal reaches the TDC circuit can be reflected by the processing results of the timing unit, etc. Based on this, regardless of whether the timing start signal or timing end signal is received first, the current time interval information between the timing start signal and the timing end signal can be determined. Therefore, this invention eliminates the need for pre-processing circuits to determine the start and end signals, not only reducing the measurement time and improving measurement accuracy but also saving on-chip area and power consumption. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of the TDC circuit in one embodiment of the present invention;

[0052] Figure 2 This is a schematic diagram of the TDC circuit in another embodiment of the present invention;

[0053] Figure 3 This is a schematic diagram of the TDC circuit in another embodiment of the present invention;

[0054] Figure 4 This is a schematic diagram of the TDC circuit in another embodiment of the present invention;

[0055] Figure 5 This is a circuit diagram of a time interval measurement circuit according to an embodiment of the present invention.

[0056] Explanation of reference numerals in the attached figures:

[0057] 1-First counter;

[0058] 2-Second counter;

[0059] 3-First circular delay chain;

[0060] 30 - First Delay Unit;

[0061] 31-Delay calibration module;

[0062] 32 - Signal transmission module;

[0063] 33-Vernier Delay Control Module;

[0064] 4-First circular delay chain;

[0065] 40 - Second Delay Unit;

[0066] 41-Delay calibration module;

[0067] 42 - Signal transmission module;

[0068] 43-Vernier Delay Control Module;

[0069] 5-Processing module;

[0070] 6-Arbitrator;

[0071] 7-First-stage TDC circuit;

[0072] 8-Signal output circuit;

[0073] 9-Second-stage TDC circuit. Detailed Implementation

[0074] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0075] In the description of this invention, it should be understood that the terms "upper part", "lower part", "upper end", "lower end", "lower surface", "upper surface", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0076] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0077] In the description of this invention, "a plurality of" means multiple, such as two, three, four, etc., unless otherwise explicitly specified.

[0078] In the description of this invention, unless otherwise explicitly specified and limited, the term "connection" and other such terms should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection, an electrical connection, or a connection that allows communication between the components; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0079] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0080] Please refer to Figure 1The present invention provides a TDC circuit, including: a first ring delay chain 3, a second ring delay chain 4, a first counter 1, and a second counter 2.

[0081] The input terminal of the first circular delay chain 3 is used to receive the timing start signal, and the output terminal of the first circular delay chain 3 is connected to the input terminal of the first circular delay chain; the first circular delay chain 3 is used to: cyclically transmit the timing start signal in the first circular delay chain, and perform a delay of the timing start signal during the cyclic transmission process.

[0082] The input terminal of the second circular delay chain 4 is used to receive the timing end signal, and the output terminal of the second circular delay chain 4 is connected to the input terminal of the second circular delay chain 4; the second circular delay chain 4 is used to: cyclically transmit the timing end signal in the second circular delay chain, and perform a delay of the timing end signal during the cyclic transmission process;

[0083] The timing start signal can be understood as a signal indicating the start of the required measurement time interval. For example, it could be the start signal of a TDC (Time Digitizer). Other examples include... Figures 1 to 4 The circuit shown is used as a second-stage TDC circuit, and the timing start signal can also be a start signal input to the second-stage TDC circuit. res The start signal can be obtained from the corresponding circuit, for example, it can be emitted by a detection module when it detects the rising edge of the signal under test.

[0084] The timing end signal can be understood as a signal indicating the end of the required measurement time interval. For example, it could be the stop signal of a TDC (Time Digitizer). Other examples include... Figures 1 to 4 The circuit shown is used as a second-stage TDC circuit, and the timing start signal can also be a stop signal input to the second-stage TDC circuit. res The stop signal can be obtained from the corresponding circuit, for example, it can be emitted by a detection module when it detects the falling edge of the signal under test.

[0085] The second circular delay chain transmits the timing end signal faster than the first circular delay chain transmits the timing start signal faster. As a result, the timing end signal can catch up with and precede the timing start signal as it propagates.

[0086] The first counter 1 is used to count the number of cycles of the timing start signal during the cyclic transmission of the timing start signal to obtain first counting information. It can be seen that it will not count when the timing start signal has not been received. Therefore, it can ensure that the first counting information can accurately reflect the number of cycles after the timing start signal is sent to the first ring delay chain of the TDC circuit.

[0087] The second counter is used to count the number of cycles of the timing start signal during the cyclic transmission of the timing start signal, and obtain second counting information. It can be seen that it will not count before the timing end signal is received. Therefore, it can ensure that the second counting information can accurately reflect the number of cycles after the timing start signal is sent to the first ring delay chain of the TDC circuit.

[0088] Both the first counter 1 and the second counter 2 are connected to the processing module 5. The processing module can be any circuit module capable of data processing, such as an MCU, CPU, logic processing module, digital circuit, digital logic circuit, etc. In addition, if the time interval measurement circuit in which the TDC circuit is located contains multiple TDC circuits (e.g., two-level TDC circuits), the multiple TDC circuits can reuse and share the same processing module, or they can each use different processing modules.

[0089] The processing module 5 is used to acquire the first counting information and the second counting information, and determine the current time interval information based on the first counting information and the second counting information;

[0090] The current time interval information represents the interval between the timing start signal and the timing end signal. It can be understood as the interval between the time when the timing start signal and the timing end signal are generated or the time when they are sent, that is, the time interval between the timing start signal and the timing end signal before they are delayed (i.e. before the corresponding circular delay chain delay).

[0091] In a specific example, a TDC circuit comprising a first ring delay chain, a second ring delay chain, a first counter, and a second counter can serve as the first-stage TDC circuit of a time interval measurement circuit, thereby facilitating the coarse measurement of TDC over a wider range.

[0092] As can be seen, in this invention, while counting the slower-moving circular delay chain (i.e., the first circular delay chain), the faster-moving circular delay chain (i.e., the second circular delay chain) is also counted. Furthermore, since both circular delay chains are delayed and counted, regardless of whether the timing start signal or the timing end signal is received first, the transmission time of the signal in the corresponding circular delay chain after it reaches the TDC circuit can be reflected by the processing results of the timing unit, etc. (the time before arrival is not included).

[0093] Based on this, regardless of whether the timing start signal or timing end signal is received first, the current time interval information between the timing start signal and the timing end signal can be determined. Based on this, the present invention does not require the introduction of a pre-processor circuit for judging the start signal and the end signal, which not only reduces the time required for measurement and improves the measurement accuracy, but also saves on-chip area and power consumption.

[0094] Furthermore, this approach not only reduces the measurement time and improves measurement accuracy, but also saves on-chip area and power consumption. Moreover, since there is no need to deal with counting errors caused by phase, although this structure adds a counter on a fast delay line (i.e., the second circular delay chain), it saves two or more counters that would otherwise have to be added to eliminate errors, thus reducing the overall number of counters used in the circuit.

[0095] In one implementation method, please refer to Figure 2 The TDC circuit further includes N arbitrators 6, the first ring delay chain 3 includes N first delay units 30, and the second ring delay chain includes N second delay units 40; where N is an integer greater than or equal to 1.

[0096] The N first delay units 30 are connected in sequence, and the output terminal of the last first delay unit 30 is connected to the input terminal of the first first delay unit 30. Thus, a closed-loop ring delay chain can be formed. The timing start signal can be transmitted in the N first delay units 30 in sequence. After being transmitted to the last delay unit 30, it will be transmitted back to the first delay unit 30.

[0097] The N second delay units 40 are connected in sequence, and the output of the last second delay unit 40 is connected to the input of the first second delay unit 40, thus forming a closed-loop ring delay chain; the timing start signal can be transmitted in the N first delay units 30 in sequence, and after being transmitted to the last delay unit 30, it will be transmitted back to the first delay unit 30.

[0098] Each arbiter 6 is connected to a corresponding first delay unit 30 and a second delay unit 40, and the first delay unit 30 and the second delay unit 40 connected to the arbiter 6 are in the same order in the corresponding circular delay chain; the order refers to the arrangement order from the first delay unit to the last delay unit in a single cycle of the corresponding circular delay chain.

[0099] The arbitrator 6 is used to determine phase comparison information.

[0100] The phase comparison information characterizes the phase sequence relationship between the timing start signal transmitted by the first delay unit connected to the arbitrator and the timing end signal transmitted by the second delay unit connected to the arbitrator.

[0101] The phase sequence relationship includes two types: a first phase sequence relationship in which the phase of the timing start signal transmitted by the first delay unit leads the phase of the timing end signal transmitted by the second delay unit, and a second phase sequence relationship in which the phase of the timing start signal transmitted by the first delay unit lags behind the phase of the timing end signal transmitted by the second delay unit.

[0102] Generally, after both signals are received, the arbitrator can determine that the phase of the timing end signal transmitted by the second delay unit lags behind the phase of the timing end signal transmitted by the first delay unit. At this time, the arbitrator 6 outputs a level (e.g., high level) as a phase comparison information representing the first phase sequence. As the cycle continues, the timing end signal will catch up with the timing start signal. After catching up and surpassing, the corresponding arbitrator will reverse to output another level (e.g., low level) as a phase comparison information representing the second phase sequence. The processing module can obtain this phase comparison information.

[0103] As can be seen, the arbitrator can accurately determine the phase order of the propagating signals of the upper and lower delay chains, and change the output level when the phase order changes. Then, the control module (e.g., a digital circuit) analyzes the changes in the arbitrator's output level to ultimately calculate the TDC measurement result.

[0104] The processing module 50 is also connected to the arbitrator; when the processing module acquires the first counting information and the second counting information, and determines the current time interval information between the timing start signal connected to the first ring delay chain and the timing end signal connected to the second ring delay chain based on the first counting information and the second counting information, it is specifically used for:

[0105] During the cyclic transmission of the timing start signal and the timing end signal, if a phase comparison information output by any arbitrator is detected to be reversed, the first count information and the second count information at the time of reversal are obtained, and the current time interval information is determined based on the first count information and the second count information at the time of reversal.

[0106] Simultaneously, the two circular delay chains can be controlled to stop their cyclic transmission. In some examples, the two circular delay chains may not transmit signals externally. Alternatively, in other examples, the transmitted signals (such as timing start signal and timing end signal) can be output from the output end of the circular delay chain (i.e., the output end of the last delay unit). In some examples, while stopping the cyclic transmission, the delay changes of the two circular delay chains can also be controlled to have no delay difference (i.e., the delays are the same, for example, the processing module controls DCW and VDD to be the same).

[0107] In a further example, the current time interval information OUTCODE can satisfy the following formula:

[0108] OUTCODE=CNT1*MSB1-CNT2*MSB2+n*LSB;

[0109] in:

[0110] CNT1 represents the first count information during the reversal;

[0111] CNT2 represents the second counting information during inversion;

[0112] MSB1 characterizes the signal propagation period of the first ring delay chain;

[0113] MSB2 characterizes the signal propagation period of the second ring delay chain;

[0114] LSB represents the delay difference between the first and second delay units in the same order;

[0115] n represents the number of second delay units that the timing end signal has passed through in the current cycle of transmission up to the time of reversal.

[0116] Specifically, the current time interval information OUTCODE can be calculated using the above formula.

[0117] In other examples, in a coarser processing scheme, the current time interval information OUTCODE can be based solely on the result of CNT1*MSB1-CNT2*MSB2.

[0118] Various variations of the above formulas can also be used as an option for calculating the current time interval information.

[0119] In a specific example of integrating the above solutions, the processing procedure of the TDC circuit may include, for example:

[0120] S11. The first signal to arrive will propagate in the chain corresponding to its input terminal in one of the two delay chains. When the signal reaches the corresponding counter, the counter will count the signal propagation in that loop. For example, if the first signal to arrive is a timing start signal, the timing start signal input at the corresponding signal input terminal will propagate in the first loop delay chain and be counted by the first counter; conversely, if the first signal to arrive is a timing end signal, the timing end signal input at the corresponding signal input terminal will propagate in the second loop delay chain and be counted by the second counter.

[0121] S12. The delayed signal will propagate in another delay chain. When the signal is transmitted to the corresponding counter, the counter will count the signal transmission status of that loop. For example, if the delayed signal is a timing start signal, the timing start signal input to the corresponding signal input terminal will propagate in the first loop delay chain and be counted by the first counter; conversely, if the delayed signal is a timing end signal, the timing end signal input to the corresponding signal input terminal will propagate in the second loop delay chain and be counted by the second counter.

[0122] S13. The signals in the two delay chains continue to propagate without interfering with each other until the arbitrator output shows that the signal propagating in the fast delay chain FDL (i.e., the second ring delay chain) just leads the signal propagating in the slow delay chain SDL (i.e., the first ring delay chain). At this time, the LSB output (i.e. the signal output by the arbitrator) will show the position corresponding to when the FDL signal exceeds the SDL signal. Then, the signal propagation of the two loops will be terminated, and an enable signal will be transmitted to the processing module (e.g., digital logic circuit) to start calculating the final output result, i.e., the current time interval information OUTCOME.

[0123] S14: The processing module (e.g., digital logic circuit) receives the enable signal and, in conjunction with the output values ​​of CNT1, CNT2, and LSB, calculates the output result of the TDC circuit, i.e., the previous time interval information OUTCOME. For example, when the TDC circuit is used as the first-stage TDC circuit, the output result of the first-stage TDC circuit can be calculated at this time.

[0124] In one implementation method, please refer to Figure 3 and Figure 4Both the first delay unit 30 and the second delay unit 40 include a signal transmission module (e.g., the signal transmission module 32 in the first delay unit 30 and the signal transmission module 42 in the second delay unit 40) and a vernier delay control module (e.g., the vernier delay control module 33 in the first delay unit 30 and the vernier delay control module 43 in the second delay unit 40).

[0125] The signal transmission module of any delay unit is connected between the signal transmission modules of the two adjacent delay units to perform the transmission of the corresponding signal; the corresponding signal is the timing start signal or the timing end signal.

[0126] That is: the signal transmission module 32 of the first delay unit is connected between the signal transmission modules 32 of two adjacent first delay units, and is used to transmit the timing start signal, and a certain delay can be achieved during transmission; the signal transmission module 42 of the second delay unit is connected between the signal transmission modules 42 of two adjacent second delay units, and is used to transmit the timing end signal, and a certain delay can be achieved during transmission.

[0127] The two adjacent delay units include: the previous delay unit connected to the input terminal of any delay unit in the corresponding circular delay chain, and the next delay unit connected to the output terminal of any delay unit;

[0128] Specifically, if the first delay unit is any of the delay units, the previous delay unit is the last delay unit, and the next delay unit is the second delay unit. If the last delay unit is any of the delay units, the previous delay unit is the second-to-last delay unit, and the next delay unit is the first delay unit. If a delay unit that is neither the last nor the first is any of the delay units, the previous delay unit and the next delay unit are the preceding and following delay units in the signal transmission direction.

[0129] As can be seen, the signal transmission module is responsible for the propagation of input signals when the TDC is working.

[0130] For a specific example, please refer to Figure 4 The signal transmission module includes a cascaded first inverter and a second inverter.

[0131] The first inverter can be, for example, Figure 4 The first inverter formed by transistors M1 and M2 shown can also be, for example... Figure 4 The first inverter formed by transistors M4 and M5 shown; the second inverter therein can be, for example... Figure 4 The second inverter X1 shown can also be, for example, Figure 4The second inverter X2 shown;

[0132] The input terminal of the first inverter in any delay unit is connected to the output terminal of the second inverter in the previous delay unit, the input terminal of the second inverter in any delay unit is connected to the output terminal of the first inverter in any delay unit, and the output terminal of the second inverter in any delay unit is connected to the input terminal of the first inverter in the next delay unit.

[0133] In this circuit, the first terminal of transistor M1 (and transistor M4) is directly or indirectly connected to the power supply terminal, the second terminal of transistor M1 (and transistor M4) is connected to the first terminal of transistor M2 (and transistor M5), the second terminal of transistor M2 (and transistor M5) is directly or indirectly grounded, and the control terminal (e.g., the gate) of transistor M1 (and transistor M4) is directly or indirectly connected to the output terminal of the second inverter (e.g., the second inverter X1, the second inverter X2) of the previous delay unit.

[0134] The second inverter can be constructed in the same or similar way as the first inverter, or it can be different. The second inverter can also be implemented using a NOT gate.

[0135] Correspondingly, the arbitrator 6 is connected to the output terminal of the first inverter;

[0136] When determining phase comparison information, the arbitrator is specifically used to: determine the phase comparison information by comparing the signals output by the first inverter of the first delay unit and the second delay unit.

[0137] In addition, the signal transmission module may also include a ground control transistor (such as the ground control transistor M3 in the first delay unit 30 and the ground control transistor M6 in the second delay unit 40), which can be connected between the first inverter and ground to realize the ground control of the first inverter.

[0138] The vernier delay control module of any delay unit is connected to the signal transmission module of any delay unit. The connection method can vary based on the functional implementation of the vernier delay control module. The vernier delay control module of any delay unit is used to control whether a delay difference is generated between the first circular delay chain and the second circular delay chain.

[0139] When a delay difference is generated, different delays can be achieved between the two circular delay chains, thereby enabling the second circular delay chain to transmit the timing end signal faster than the first circular delay chain to transmit the timing start signal. When no delay difference is generated, and other modules are configured not to form a delay difference (e.g., after the delay calibration module calibrates the two delay chains), the two circular delay chains can be synchronized. This can be used in scenarios other than those for cyclically transmitting timing start and timing end signals, such as scenarios for circuit verification or outputting signals after the cyclic transmission ends.

[0140] In a specific example, the vernier delay control module includes a first transistor (e.g., the first transistor Q1 of the vernier delay control module 33 in the first delay unit 30, and the first transistor Q3 of the vernier delay control module 43 in the second delay unit 40) and a second transistor (e.g., the second transistor Q2 of the vernier delay control module 33 in the first delay unit 30, and the second transistor Q4 of the vernier delay control module 43 in the second delay unit 40).

[0141] In any of the delay units, the input terminal of the second inverter is also connected to the control terminal of the first transistor, the first terminal of the first transistor is connected to the output terminal of the second inverter, the second terminal of the first transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is grounded.

[0142] The signals connected to the control terminals of the second transistors in the first delay unit and the second delay unit are used to determine whether the delay difference is generated;

[0143] in:

[0144] If the signal connected to the control terminal of the second transistor in any k-th first delay unit is at the same level as the signal connected to the control terminal of the second transistor in the k-th second delay unit, then: the delay of the k-th first delay unit is the same as that of the k-th second delay unit; specifically, after calibration by the delay calibration module, the delay of the k-th first delay unit is the same as that of the k-th second delay unit.

[0145] If the signal connected to the control terminal of the second transistor in any k-th first delay unit is at a different level than the signal connected to the control terminal of the second transistor in any k-th second delay unit, then: the delay between the k-th first delay unit and the k-th second delay unit has a specified delay difference; specifically, after calibration by the delay calibration module, the delay of the k-th first delay unit and the k-th second delay unit are the same.

[0146] Furthermore, the signal input to the control terminal of the second transistor Q2 in each of the first delay units can be the same, i.e. Figure 4 The signals DCW1 to DCW8 are identical and can be described using DCW. The signals input to the control terminal of the second transistor Q4 in each second delay unit can be the same, for example... Figure 4 VDD is the same in both cases. When a delay difference occurs, DCW is different from VDD; when no delay difference occurs, DCW is the same as VDD.

[0147] As can be seen, the vernier delay control module receives control signals (such as DCW and VDD) from the processing module (e.g., digital circuit) to control the delay difference between the upper and lower delay chains. When the input levels of the upper and lower vernier delay control modules are the same, no vernier delay is introduced, and the delays of the upper and lower delay chains are the same. When the input levels of the upper and lower vernier delay control modules are different, a delay difference will be generated between the upper and lower delay chains. This delay difference is the resolution of the vernier TDC, and the vernier TDC can work normally under these conditions.

[0148] Specifically, if the TDC circuit is used as the first-stage TDC circuit, and the second-stage TDC circuit also uses a vernier delay control module, then: the delay difference in the first-stage TDC circuit is greater than the corresponding delay difference in the second-stage circuit. Therefore, the delay difference generated in the first-stage TDC circuit can be understood as a relatively large delay difference. The corresponding delay difference in the second-stage circuit is relatively small, less than the delay difference in the first-stage TDC circuit. Therefore, the resolution of the vernier TDC implemented by the first-stage TDC circuit is less than the resolution of the vernier TDC implemented by the second-stage TDC circuit, thus satisfying the requirements of coarse and fine TDC measurements.

[0149] In one implementation method, please refer to Figure 3 Both the first delay unit 30 and the second delay unit 40 further include a delay calibration module (e.g., delay calibration module 31 in the first delay unit 30 and delay calibration module 41 in the second delay unit 30).

[0150] Please refer to Figure 4 The delay calibration module includes multiple transistors connected in parallel. These multiple transistors are connected to one end of the power supply terminal of the first inverter (e.g., the first terminal of transistors M1 and M4 in the first inverter). The multiple transistors connected in parallel are configured to be selectively turned on to control the delay implemented by the corresponding delay unit.

[0151] As can be seen, the delay calibration module can be composed of several transistors of different sizes connected in parallel. The delay of the delay unit can be controlled by controlling the on and off states of the transistors. This module receives a calibration signal output from a control module (e.g., a digital circuit) and calibrates the delay of the delay unit so that, when DCW and VDD are the same, the delays of the upper and lower delay chains are equal.

[0152] This invention also provides a time interval measurement circuit, including an M-level TDC circuit;

[0153] The P-th stage TDC circuit in the M-stage TDC circuit is: Figures 1 to 4 The TDC circuit shown is given; where M and P are both positive integers, M≥1, M≥P≥1.

[0154] In one embodiment, the M-level TDC circuit is a two-level TDC circuit, including a first-level TDC circuit 7 and a second-level TDC circuit 9; the P-level TDC circuit is the first-level TDC circuit 7.

[0155] The timing start signal is the start signal of TDC, and the timing end signal is the stop signal of TDC;

[0156] The second-stage TDC circuit is used to obtain the start. res Signals and Stop res Signal, and determine the start res Signal and the stop res The time interval information between the signals is determined, and then, based on this time interval information and the current time interval information determined by the first-stage TDC circuit, the final time interval information between the start signal and the stop signal is determined. res Signals and Stop res The time interval of the signal is matched to the time interval of the two signals output by the first-stage TDC circuit after the cyclic transmission stops.

[0157] by Figure 5 For example, the signal output circuit 8 can be controlled by the processing module 5 (or the signal output circuit 8 can output directly without being controlled by the processing module 5) to start. res Signals and Stop res In terms of connection, the signal output circuit 8 can be connected to the output terminals of two ring delay chains, and then obtain the signals output by the output terminals of the two ring delay chains after the cyclic transmission stops.

[0158] In one example, the signal transmitting circuit 8 may only perform the function of signal transmission; in other examples, the signal transmitting circuit 8 may also perform functions such as amplification and adjustment of the time interval.

[0159] This invention also provides an electronic device, including the time interval measurement circuit described above.

[0160] In the description of this specification, the references to terms such as "an embodiment," "an example," "a specific implementation process," and "an example" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0161] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A TDC circuit, characterized in that, include: The system consists of a first circular delay chain, a second circular delay chain, a first counter, a second counter, and N arbitrators. The input end of the first circular delay chain is used to receive the timing start signal, and the output end of the first circular delay chain is connected to the input end of the first circular delay chain; the first circular delay chain is used to: cyclically transmit the timing start signal in the first circular delay chain, and perform a delay of the timing start signal during the cyclic transmission process; The input end of the second circular delay chain is used to receive the timing end signal, and the output end of the second circular delay chain is connected to the input end of the second circular delay chain; the second circular delay chain is used to: cyclically transmit the timing end signal in the second circular delay chain, and perform a delay on the timing end signal during the cyclic transmission process; Wherein, the second circular delay chain transmits the timing end signal faster than the first circular delay chain transmits the timing start signal faster. The first counter is used to count the number of cycles of the timing start signal during the cyclic transmission of the timing start signal, and obtain first counting information; The second counter is used to count the number of cycles of the timing start signal during the cyclic transmission of the timing start signal, and to obtain second counting information; Both the first counter and the second counter are connected to a processing module. The processing module is used to acquire the first counter information and the second counter information, and determine the current time interval information based on the first counter information and the second counter information. The current time interval information represents the interval between the timing start signal and the timing end signal. The first circular delay chain includes N first delay units, and the second circular delay chain includes N second delay units; where N is an integer greater than or equal to 1. The N first delay units are connected in sequence, and the output of the last first delay unit is connected to the input of the first first delay unit; the N second delay units are connected in sequence, and the output of the last second delay unit is connected to the input of the first second delay unit. Each arbitrator is connected to a corresponding first delay unit and a second delay unit, and the first delay unit and the second delay unit connected to the arbitrator are in the same order in the corresponding circular delay chain; The arbitrator is used to determine phase comparison information, which characterizes the phase sequence relationship between the timing start signal transmitted by the first delay unit connected to the arbitrator and the timing end signal transmitted by the second delay unit connected to the arbitrator. The processing module is also connected to the arbitrator; when the processing module acquires the first counting information and the second counting information, and determines the current time interval information between the timing start signal connected to the first ring delay chain and the timing end signal connected to the second ring delay chain based on the first counting information and the second counting information, it is specifically used for: During the cyclic transmission of the timing start signal and the timing end signal, if a phase comparison information output by any arbitrator is detected to be reversed, the first count information and the second count information at the time of reversal are obtained, and the current time interval information is determined based on the first count information and the second count information at the time of reversal.

2. The TDC circuit according to claim 1, characterized in that, When the processing module determines the time interval information based on the first count information and the second count information during the reversal, it is specifically used for: The current time interval information OUTCODE satisfies the following formula: OUTCODE=CNT1*MSB1-CNT2*MSB2+n*LSB; in: CNT1 represents the first count information during the reversal; CNT2 represents the second counting information during inversion; MSB1 characterizes the signal propagation period of the first ring delay chain; MSB2 characterizes the signal propagation period of the second ring delay chain; LSB represents the delay difference between the first and second delay units in the same order; n represents the number of second delay units that the timing end signal has passed through in the current cycle of transmission up to the time of reversal.

3. The TDC circuit according to claim 1, characterized in that, Both the first delay unit and the second delay unit include a signal transmission module and a vernier delay control module; The signal transmission module of any delay unit is connected between the signal transmission modules of the two adjacent delay units of any delay unit, and is used to perform the transmission of the corresponding signal; the corresponding signal is the timing start signal or the timing end signal; the two adjacent delay units include: the previous delay unit connected to the input terminal of any delay unit in the corresponding circular delay chain, and the next delay unit connected to the output terminal of any delay unit; The vernier delay control module of any delay unit is connected to the signal transmission module of any delay unit and is used to control whether a delay difference caused by the vernier occurs between the first circular delay chain and the second circular delay chain.

4. The TDC circuit according to claim 3, characterized in that, The signal transmission module includes a cascaded first inverter and a second inverter, and the vernier delay control module includes a first transistor and a second transistor; The input terminal of the first inverter in any delay unit is connected to the output terminal of the second inverter in the previous delay unit, the input terminal of the second inverter in any delay unit is connected to the output terminal of the first inverter in any delay unit, and the output terminal of the second inverter in any delay unit is connected to the input terminal of the first inverter in the next delay unit. In any of the delay units, the input terminal of the second inverter is also connected to the control terminal of the first transistor, the first terminal of the first transistor is connected to the output terminal of the second inverter, the second terminal of the first transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is grounded. The signals connected to the control terminals of the second transistors in the first delay unit and the second delay unit are used to determine whether the delay difference is generated. The arbitrator is connected to the output of the first inverter; When determining phase comparison information, the arbitrator is specifically used to: determine the phase comparison information by comparing the signals output by the first inverter of the first delay unit and the second delay unit.

5. The TDC circuit according to claim 4, characterized in that, If the signal connected to the control terminal of the second transistor in any k-th first delay unit is at the same level as the signal connected to the control terminal of the second transistor in the k-th second delay unit, then: the delay of the k-th first delay unit is the same as that of the k-th second delay unit. If the signal connected to the control terminal of the second transistor in any k-th first delay unit is at a different level than the signal connected to the control terminal of the second transistor in the k-th second delay unit, then the delay caused by the vernier between the k-th first delay unit and the k-th second delay unit has a specified delay difference.

6. The TDC circuit according to claim 4, characterized in that, Both the first delay unit and the second delay unit further include a delay calibration module; The delay calibration module includes multiple transistors connected in parallel. These multiple transistors are connected to one end of the power supply terminal of the first inverter. The multiple transistors are configured to be selectively turned on to control the delay implemented by the corresponding delay unit.

7. A time interval measurement circuit, characterized in that, Including M-level TDC circuits; The P-level TDC circuit in the M-level TDC circuit is the TDC circuit described in any one of claims 1 to 6; Where M and P are both positive integers, M≥1, M≥P≥1.

8. The time interval measuring circuit according to claim 7, characterized in that, The M-level TDC circuit is a two-level TDC circuit, including a first-level TDC circuit and a second-level TDC circuit; the P-level TDC circuit is the first-level TDC circuit. The timing start signal is the start signal of TDC, and the timing end signal is the stop signal of TDC; The second-stage TDC circuit is used to obtain the start. res Signals and Stop res Signal, and determine the start res Signal and the stop res The time interval information between signals is used to determine the final time interval information between the start signal and the stop signal based on this time interval information and the current time interval information. res Signals and Stop res The time interval of the signal is matched to the time interval between the start signal and the end signal output by the first-stage TDC circuit after the cyclic transmission stops.

9. An electronic device, characterized in that, Includes the time interval measurement circuit as described in claim 7 or 8.

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