A bowl-type segmented temperature compensation circuit for a bandgap reference source

Abstract

This invention discloses a bowl-shaped segmented temperature compensation circuit for a bandgap reference source. The bowl-shaped segmented temperature compensation circuit includes a high-temperature segment compensation current generation circuit, a low-temperature segment compensation current generation circuit, a first current subtractor, a second current subtractor, and a current adder. The output terminal of the high-temperature segment compensation current generation circuit is connected to the input terminal of the first current subtractor, and the output terminal of the low-temperature segment compensation current generation circuit is connected to the input terminal of the second current subtractor. The output terminals of both the first and second current subtractors are connected to the input terminal of the current adder. The output terminal of the current adder generates a compensation current. This invention can generate curvature compensation currents with different curvatures that do not affect each other in the low-temperature and high-temperature segments of the bandgap reference source circuit. The overall compensation presents a bowl shape, achieving high-order curvature compensation to improve the temperature characteristics of the reference source.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology and relates to a bowl-shaped segmented temperature compensation circuit for a bandgap reference source. Background Technology

[0002] The function of a bandgap voltage reference is to generate a DC voltage that is independent of power supply and manufacturing process and has a defined temperature characteristic. The temperature coefficient of its output voltage is an important indicator of the bandgap voltage reference's performance. In the structure of a bandgap voltage reference, the temperature characteristic of the voltage across a transistor is typically used to obtain a reference voltage with zero temperature coefficient. Under normal operating conditions, the base-emitter voltage VB of the transistor... BE Inversely proportional to absolute temperature, and at different collector current densities, the difference ΔV between the base and emitter voltages of two identical transistors... BE It is directly proportional to absolute temperature.

[0003] Superimposing the two types of voltages in a certain proportion yields a reference voltage that is insensitive to temperature changes. However, using V... BE With ΔV BE The approximate linear trend of V with temperature is not accurate. In fact, V BE With ΔV BE The functional relationship between temperature and temperature is high-order, and the reference voltage obtained by this method only has first-order temperature compensation. Therefore, under more demanding operating conditions, the temperature characteristics of the bandgap reference source output voltage often cannot meet the circuit design requirements.

[0004] To obtain a reference voltage with a lower temperature coefficient, higher-order temperature compensation is required for the output reference voltage of the reference source. Common temperature compensation methods, such as piecewise linear compensation, suffer from resistor mismatch and temperature coefficient issues that cause the compensated voltage to deviate from the ideal, and linear compensation cannot provide higher-order compensation for the reference output voltage. Single-segment exponential compensation, theoretically, can provide higher-order compensation for the reference output voltage, but it often cannot compensate for high, medium, and low temperature segments separately, leading to mutual interference between temperature segment compensations and making debugging difficult.

[0005] Based on the above considerations, it is essential to propose a high-order temperature compensation circuit that can accurately replicate the reference output voltage and segmentally compensate for the temperature characteristics of the reference source output voltage. Summary of the Invention

[0006] The purpose of this invention is to provide a bowl-shaped segmented temperature compensation circuit for a bandgap reference source. The technical solution adopted by this invention is:

[0007] A bowl-shaped segmented temperature compensation circuit for a bandgap reference source includes: a high-temperature segment compensation current generation circuit, a low-temperature segment compensation current generation circuit, a first current subtractor, a second current subtractor, and a current adder.

[0008] The output terminal of the high-temperature section compensation current generating circuit is connected to the input terminal of the first current subtractor, and the output terminal of the first current subtractor is connected to the first input terminal of the current adder.

[0009] The output terminal of the low-temperature compensation current generating circuit is connected to the input terminal of the second current subtractor, and the output terminal of the second current subtractor is connected to the second input terminal of the current adder.

[0010] The output of the current adder generates a compensation current.

[0011] In one embodiment of the present invention, the high-temperature range compensation current generating circuit includes a high-temperature range exponential current generating circuit and a high-temperature range exponential current compensation circuit, wherein the high-temperature range exponential current generating circuit is connected to the high-temperature range exponential current compensation circuit.

[0012] In one embodiment of the present invention, the high-temperature exponential current generating circuit includes a PMOS transistor M. P1 PMOS transistor M P2 PMOS transistor M P3 and PMOS transistor M P4 ;

[0013] The PMOS transistor M P1 With the PMOS transistor M P2 The source connection of the PMOS transistor M P1 The gate is connected to a temperature-insensitive voltage V. REF1 The PMOS transistor M P2 The gate is connected to a voltage V with a negative temperature coefficient. CTAT1 The PMOS transistor M P3 The source of the PMOS transistor M P1 The drain connection of the PMOS transistor M P3 The source of the PMOS transistor is grounded. P3 The gate and the PMOS transistor M P4 The gate is biased by a constant voltage V. B1 The PMOS transistor M P4 The source of the PMOS transistor M P2 The drain connection of the PMOS transistor M P4 The source output of the high-temperature exponential current generation circuit is the output current I. EXP1 .

[0014] In one embodiment of the present invention, the high-temperature exponential current compensation circuit includes a PMOS transistor M. P5 PMOS transistor M P6 First unity-gain buffer Buffer1, first current mirror M1, and second current mirror M2;

[0015] The input terminal of the first unity-gain buffer Buffer1 is connected to the PMOS transistor M. P3 The source is connected, and the output of the first unity-gain buffer Buffer1 is connected to the PMOS transistor M. P5 The source connection of the PMOS transistor M P5 The gate of the PMOS transistor M P2 The gate connection of the PMOS transistor M P5 The drain of the PMOS transistor M P6 The source connection of the PMOS transistor M P6 The gate of the PMOS transistor M P4 The gate connection of the PMOS transistor M P6 The drain of the first current mirror M1 is connected to the input terminal of the first current mirror M1, the output terminal of the first current mirror M1 is connected to the input terminal of the second current mirror M2, and the output terminal of the second current mirror M2 is connected to the input terminal of the first unity-gain buffer Buffer1.

[0016] In one embodiment of the present invention, the low-temperature segment compensation current generating circuit includes a low-temperature segment exponential current generating circuit and a low-temperature segment exponential current compensation circuit, wherein the low-temperature segment exponential current generating circuit is connected to the low-temperature segment exponential current compensation circuit.

[0017] In one embodiment of the present invention, the low-temperature exponential current generating circuit includes a PMOS transistor M. P7 PMOS transistor M P8 PMOS transistor M P9 and PMOS transistor M P10 ;

[0018] The PMOS transistor M P7 With the PMOS transistor M P8 The source connection of the PMOS transistor M P8 The gate is connected to a temperature-insensitive voltage V. REF2 The PMOS transistor M P7 The voltage V with a negative temperature coefficient at the gate CTAT2 The PMOS transistor M P9 The source of the PMOS transistor M P7 The drain connection of the PMOS transistor M P9The source of the PMOS transistor is grounded. P10 The source of the PMOS transistor M P8 The drain connection of the PMOS transistor M P9 and the PMOS transistor M P10 The gate is biased by a constant voltage V. B2 The PMOS transistor M P10 The source output of the low-temperature exponential current generation circuit is the output current I. EXP2 .

[0019] In one embodiment of the present invention, the low-temperature exponential current compensation circuit includes a PMOS transistor M. P11 PMOS transistor M P12 The second unity-gain buffer Buffer2, the third current mirror M3, and the fourth current mirror M4;

[0020] The input terminal of the second unity-gain buffer Buffer2 is connected to the PMOS transistor M. P8 The source is connected, and the output of the second unity-gain buffer Buffer2 is connected to the PMOS transistor M. P11 The source connection of the PMOS transistor M P11 The gate of the PMOS transistor M P8 The gate connection of the PMOS transistor M P11 The drain of the PMOS transistor M P12 The source connection of the PMOS transistor M P12 The gate of the PMOS transistor M P10 The gate connection of the PMOS transistor M P12 The drain of the device is connected to the input terminal of the third current mirror M3, the output terminal of the third current mirror M3 is connected to the input terminal of the fourth current mirror M4, and the output terminal of the fourth current mirror M4 is connected to the input terminal of the second unity-gain buffer Buffer2.

[0021] In one embodiment of the present invention, the first current subtraction circuit includes an NMOS transistor M. N1 NMOS transistor M N2 NMOS transistor M N3 NMOS transistor M N4 NMOS transistor M N5 NMOS transistor M N6 NMOS transistor M N7 NMOS transistor M N8 Resistors R1, R2, R3, and R4;

[0022] The NMOS transistor M N1 The drain of the NMOS transistor MN3 The gate connection of the NMOS transistor M N1 The gate of the NMOS transistor M N2 The gate is biased by a constant voltage V. B3 The NMOS transistor M N2 The source of the NMOS transistor M N3 The drain connection of the NMOS transistor M N3 The source of the NMOS transistor is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded. N2 The drain of the NMOS transistor M N5 The drain connection of the NMOS transistor M N2 The source of the NMOS transistor M N4 The drain connection of the NMOS transistor M N4 The gate of the NMOS transistor M N3 The gate connection of the NMOS transistor M N4 The source of the NMOS transistor is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded. N5 The drain of the NMOS transistor M N7 The gate connection of the NMOS transistor M N5 The gate of the NMOS transistor M N6 The gate is biased by a constant voltage V. B4 The NMOS transistor M N5 The source of the NMOS transistor M N7 The drain connection of the NMOS transistor M N7 The source of the NMOS transistor is connected to one end of resistor R3, and the other end of resistor R3 is grounded. N4 The gate of the NMOS transistor M N7 The gate connection of the NMOS transistor M N4 The source of the NMOS transistor is connected to one end of the resistor R4, and the other end of the resistor R4 is grounded. N6 The source of the NMOS transistor M N8 The drain connection of the NMOS transistor M N6 The drain output of the first current subtraction circuit is the output current I. CP1 .

[0023] In one embodiment of the present invention, the second current subtraction circuit has the same structure as the first current subtraction circuit, and the second current subtraction circuit outputs a current I. CP2 .

[0024] In one embodiment of the present invention, the current adding circuit includes a PMOS transistor M P13 PMOS transistor MP14 PMOS transistor M P15 PMOS transistor M P16 Resistors R5 and R6;

[0025] One end of resistor R5 is connected to VDD, and the other end of resistor R5 is connected to the PMOS transistor M. P13 The source of the transistor is connected, one end of resistor R6 is connected to VDD, and the other end of resistor R6 is connected to the PMOS transistor M. P14 The source connection of the PMOS transistor M P14 The drain of the PMOS transistor M P16 The source connection of the PMOS transistor M P13 The gate of the PMOS transistor M P14 The gate of the PMOS transistor M P16 The drain connection of the PMOS transistor M P13 The drain of the PMOS transistor M P15 The source connection of the PMOS transistor M P15 The gate of the PMOS transistor M P16 The gate is biased by a constant voltage V. B5 The PMOS transistor M P15 The drain output of the current adder circuit is the output current I. CP .

[0026] The beneficial effects of this invention are:

[0027] The bowl-shaped segmented temperature compensation circuit of the bandgap reference source of the present invention includes a high-temperature segment compensation current generation circuit, a low-temperature segment compensation current generation circuit, a first current subtractor, a second current subtractor, and a current adder. It can generate curvature compensation currents with different curvatures that do not affect each other in the low-temperature and high-temperature segments of the bandgap reference source circuit. The overall compensation presents a bowl shape, realizing high-order curvature compensation to improve the temperature characteristics of the reference source. Attached Figure Description

[0028] Figure 1 This is a structural block diagram of a bowl-shaped segmented temperature compensation circuit for a bandgap reference source provided in an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of a high-temperature range compensation current generation circuit provided in an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of a low-temperature compensation current generation circuit provided in an embodiment of the present invention;

[0031] Figure 4 A schematic diagram of the first current subtractor provided in an embodiment of the present invention;

[0032] Figure 5 A schematic diagram of a current adder provided in an embodiment of the present invention;

[0033] Figure 6 This is a simulation waveform diagram of the compensation current in an embodiment of the present invention;

[0034] Figure 7 This is a simulation waveform diagram of the output voltage of the reference source before and after compensation as a function of temperature, according to an embodiment of the present invention. Detailed Implementation

[0035] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0036] This invention provides a bowl-shaped segmented temperature compensation circuit for a bandgap reference source. The bowl-shaped segmented temperature compensation circuit includes: a high-temperature segment compensation current generation circuit, a low-temperature segment compensation current generation circuit, a first current subtractor, a second current subtractor, and a current adder. The output terminal of the high-temperature segment compensation current generation circuit is connected to the input terminal of the first current subtractor, and the output terminal of the first current subtractor is connected to the first input terminal of the current adder. The output terminal of the low-temperature segment compensation current generation circuit is connected to the input terminal of the second current subtractor, and the output terminal of the second current subtractor is connected to the second input terminal of the current adder. The output terminal of the current adder generates a compensation current.

[0037] See attached document Figure 1 The high-temperature exponential current generating circuit is used to generate a current I that increases exponentially with temperature. EXP1 , and temperature-insensitive current I REF3 After passing through the first current subtractor, the compensation current I is obtained to compensate the reference output in the high-temperature range. CP1 The low-temperature exponential current generating circuit is used to generate a current I that decreases exponentially with temperature. EXP2 , and temperature-insensitive current I REF4 After passing through the second current subtractor, the compensation current I is obtained to compensate the reference output in the high-temperature range. CP2 ;I CP1 with I CP2 The cup-shaped segmented temperature curvature compensation current I is obtained through a current adder. CP .

[0038] In one embodiment of the invention, the bowl-shaped segmented temperature compensation circuit of the bandgap reference source requires a matching output resistor. The input terminal of the reference output resistor is connected to the output terminal of a current adder, and the output terminal of the reference output resistor generates a compensation voltage. The bowl-shaped segmented temperature curvature compensation current I... CP Then, through voltage division by the reference output resistor, the bowl-shaped segmented temperature curvature compensation voltage V is obtained. CP .

[0039] The reference output resistor in this embodiment of the invention is composed of several resistors connected in series, with the number of resistors selected according to the actual circuit. In this embodiment, it is composed of four resistors with appropriate resistance values ​​connected in series. The purpose is to obtain three suitable nodes in the output branch to provide a suitable reference voltage for the temperature compensation circuit and to inject the current generated by the temperature compensation circuit.

[0040] See attached document Figure 2 The high-temperature range compensation current generation circuit includes a high-temperature range exponential current generation circuit and a high-temperature range exponential current compensation circuit, with the high-temperature range exponential current generation circuit and the high-temperature range exponential current compensation circuit connected together.

[0041] In one embodiment of the present invention, the high-temperature exponential current generating circuit includes PMOS transistors MP1, MP2, and M. P3 and PMOS transistor M P4 PMOS transistor M P1 With PMOS transistor M P2 The source of the PMOS transistor M1 is connected to a temperature-insensitive voltage V. REF1 PMOS transistor M P2 The gate is connected to a voltage V with a negative temperature coefficient. CTAT1 PMOS transistor M P3 The source and PMOS transistor M P1 The drain connection of the PMOS transistor M P3 The source is grounded, and the PMOS transistor M P3 and PMOS transistor M P4 The gate is biased by a constant voltage V. B1 PMOS transistor M P4 The source and PMOS transistor M P2 The drain connection of the PMOS transistor M P4 The source output high-temperature exponential current generation circuit generates the output current I. EXP1 .

[0042] The high-temperature exponential current compensation circuit includes a PMOS transistor M P5 PMOS transistor M P6 The system consists of a first unity-gain buffer (Buffer1), a first current mirror (M1), and a second current mirror (M2). The input of the first unity-gain buffer (Buffer1) is connected to the PMOS transistor M1. P3 The source is connected, and the output of the first unity-gain buffer Buffer1 is connected to the PMOS transistor M. P5 The source connection of the PMOS transistor M P5 The gate of the PMOS transistor M P2 The gate connection of the PMOS transistor M P5The drain of the PMOS transistor M P6 The source connection of the PMOS transistor M P6 The gate of the PMOS transistor M P4 The gate connection of the PMOS transistor M P6 The drain of the first current mirror M1 is connected to the input terminal of the first current mirror M1, the output terminal of the first current mirror M1 is connected to the input terminal of the second current mirror M2, and the output terminal of the second current mirror M2 is connected to the input terminal of the first unity-gain buffer Buffer1.

[0043] PMOS transistor M in this embodiment of the invention P2 PMOS transistor M P3 With PMOS transistor M P6 The design parameters remain consistent, and it operates in the subthreshold region; PMOS transistor M P4 PMOS transistor M P5 With PMOS transistor M P7 The design parameters remain consistent, and it operates in the saturation region; PMOS transistor M P1 The work is in the saturation zone.

[0044] See attached document Figure 3 The low-temperature range compensation current generation circuit includes a low-temperature range exponential current generation circuit and a low-temperature range exponential current compensation circuit, with the low-temperature range exponential current generation circuit and the low-temperature range exponential current compensation circuit connected together.

[0045] In one embodiment of the present invention, the low-temperature exponential current generating circuit includes a PMOS transistor M. P7 PMOS transistor M P8 PMOS transistor M P9 and PMOS transistor M P10 PMOS transistor M P7 With PMOS transistor M P8 The source connection of the PMOS transistor M P8 The gate is connected to a temperature-insensitive voltage V. REF2 PMOS transistor M P7 The voltage V with a negative temperature coefficient at the gate CTAT2 PMOS transistor M P9 and PMOS transistor M P10 The gate is biased by a constant voltage V. B2 PMOS transistor M P9 The source and PMOS transistor M P7 The drain connection of the PMOS transistor M P9 The source is grounded, and the PMOS transistor M P10 The source and PMOS transistor M P8 The drain connection of the PMOS transistor M P10 The source output low-temperature exponential current generation circuit generates the output current I.EXP2 .

[0046] The low-temperature exponential current compensation circuit includes a PMOS transistor M P11 PMOS transistor M P12 The system consists of a second unity-gain buffer (Buffer2), a third current mirror (M3), and a fourth current mirror (M4). The input of the second unity-gain buffer (Buffer2) is connected to the PMOS transistor M4. P8 The source is connected, and the output of the second unity-gain buffer Buffer2 is connected to the PMOS transistor M. P11 The source connection of the PMOS transistor M P11 The gate of the PMOS transistor M P8 The gate connection of the PMOS transistor M P11 The drain of the PMOS transistor M P12 The source connection of the PMOS transistor M P12 The gate of the PMOS transistor M P10 The gate connection of the PMOS transistor M P12 The drain of the first current mirror is connected to the input of the third current mirror M3, the output of the third current mirror M3 is connected to the input of the fourth current mirror M4, and the output of the fourth current mirror M4 is connected to the input of the second unity-gain buffer Buffer2.

[0047] PMOS transistor M in this embodiment of the invention P7 PMOS transistor M P8 NMOS transistor M P11 The design parameters remain consistent, and it operates in the subthreshold region; PMOS transistor M P9 PMOS transistor M P10 PMOS transistor M P12 The design parameters remain consistent, and the system operates in the saturation region.

[0048] See attached document Figure 4 The first current subtraction circuit includes an NMOS transistor M N1 NMOS transistor M N2 NMOS transistor M N3 NMOS transistor M N4 NMOS transistor M N5 NMOS transistor M N6 NMOS transistor M N7 NMOS transistor M N8 Resistors R1, R2, R3, and R4. NMOS transistor M. N1 The drain of the NMOS transistor M N3 Gate connection of NMOS transistor M N1 The gate of the NMOS transistor M N2 The gate is biased by a constant voltage V. B3 NMOS transistor MN2 The source and NMOS transistor M N3 The drain connection of the NMOS transistor M N3 The source of the NMOS transistor is connected to one end of resistor R1, and the other end of resistor R1 is grounded. N2 The drain of the NMOS transistor M N5 The drain connection of the NMOS transistor M N2 The source and NMOS transistor M N4 The drain connection of the NMOS transistor M N4 The gate of the NMOS transistor M N3 Gate connection of NMOS transistor M N4 The source of the NMOS transistor is connected to one end of resistor R2, and the other end of resistor R2 is grounded. N5 The drain of the NMOS transistor M N7 Gate connection of NMOS transistor M N5 The gate of the NMOS transistor M N6 The gate is biased by a constant voltage V. B4 NMOS transistor M N5 The source and NMOS transistor M N7 The drain connection of the NMOS transistor M N7 The source of the NMOS transistor is connected to one end of resistor R3, and the other end of resistor R3 is grounded. N6 The source and NMOS transistor M N8 The drain connection of the NMOS transistor M N4 The gate of the NMOS transistor M N7 Gate connection of NMOS transistor M N4 The source of the NMOS transistor is connected to one end of resistor R4, and the other end of resistor R4 is grounded. N6 The output current I of the drain output current subtraction circuit CP1 .

[0049] The current should be reduced when connecting the NMOS transistor M. N1 The drain of the NMOS transistor M is connected to the reduced current. N2 The drain of the NMOS transistor M; N1 The drain of the transistor pulls out the output current, and all PMOS transistors in the current subtraction circuit are biased in the saturation region.

[0050] The second current subtraction circuit of this embodiment has the same structure as the first current subtraction circuit, and the second current subtraction circuit outputs a current I. CP2 .

[0051] See attached document Figure 5 The current adding circuit includes a PMOS transistor M P13 PMOS transistor M P14 PMOS transistor M P15PMOS transistor M P16 Resistors R5 and R6. One end of resistor R5 is connected to VDD, and the other end of resistor R5 is connected to PMOS transistor M. P13 The source connection of the PMOS transistor M P13 The gate of the PMOS transistor M P14 The gate of the PMOS transistor M P16 The drain connection of the PMOS transistor M P13 The drain of the PMOS transistor M P15 The source connection of the PMOS transistor M P15 The gate of the PMOS transistor M P16 The gate is biased by a constant voltage V. B8 PMOS transistor M P15 The output current of the drain output current summing circuit is connected to VDD at one end of resistor R6 and the other end of resistor R6 is connected to the PMOS transistor M. P14 The source connection of the PMOS transistor M P14 The drain of the PMOS transistor M P16 The source connection.

[0052] In PMOS transistor M P16 The drain of the circuit injects the output current I from both the high-temperature exponential current generation circuit and the low-temperature exponential current generation circuit. CP1 and I CP2 The sum of the output current I CP From M P15 The drain of the transistor is pulled out; all PMOS transistors in the current-adding circuit are biased in the saturation region.

[0053] The bowl-shaped segmented temperature compensation circuit provided by this invention generates an exponentially form compensation current that accurately replicates the output current of the reference source at both ends of the operating temperature range, exhibiting excellent high-order temperature compensation performance. The temperature compensation currents for the high, medium, and low temperature ranges are separated and do not affect each other, making debugging convenient and easy to use. All bias currents and bias voltages are obtained from the bandgap reference source, eliminating the need for additional bias circuitry. This invention, in conjunction with a traditional current-mode bandgap reference source, achieves high-order segmented temperature compensation for the reference output.

[0054] In a current-mode reference source, a temperature-insensitive reference voltage V is obtained by dividing the reference output voltage. REF1 and V REF2 ; through V BE The voltage division yields a voltage V with a negative temperature coefficient. CTAT1 and V CTAT2 By using a current mirror to replicate the current in the reference output branch by multiples, a reference current I that meets the usage requirements and does not change with temperature is obtained. REF1～ I REF4 .

[0055] As attached Figure 2 As shown, V REF1 Connected to PMOS transistor M P1 The gate of V CTAT1 Connected to PMOS transistor M P2 With PMOS transistor M P5 The gate of I REF1 Injection node S1, i.e., PMOS transistor M P1 and PMOS transistor M P2 The source of the PMOS transistor. P7 PMOS transistor M P8 and PMOS transistor M P11 Operating in the subthreshold region with identical design parameters, and similar to a PMOS transistor operating in the saturation region. P9 PMOS transistor M P10 and PMOS transistor M P12 Forming a common-source, common-gate structure, therefore the PMOS transistor M P7 PMOS transistor M P8 and PMOS transistor M P11 The channel length modulation effect can be ignored.

[0056] PMOS transistor M P2 The current I2 flowing through it:

[0057]

[0058] PMOS transistor M P1 The current I1 flowing through it:

[0059]

[0060] In formulas (1) and (2), I2 represents the PMOS transistor M. P2 The current flowing through it, I1, is the PMOS transistor M. P1 The current flowing through it, μ p C represents the carrier mobility of the P-tube used. OX V is the capacitance per unit area of ​​the oxide layer. S1 V is the voltage at node S1. THP The threshold voltage of the P-type transistor used is given by η, which is a process-dependent coefficient. T =kT / q is the thermal voltage, k is the Boltzmann constant, T is the Kelvin (K) temperature, q is the elementary charge, W is the gate width of the MOSFET, and L is the gate length of the MOSFET.

[0061] The high-temperature range exponential current compensation circuit enables M P5The flowing current is a copy of I2, and an output current with a magnitude of I2 is injected into node S1. Applying Kirchhoff's Current Law (KCL) to node S1, we get:

[0062] I REF1 +I2 = I1 + I2 (3)

[0063] Furthermore, we have:

[0064]

[0065] V CTAT1 can be expressed as: V CTAT1 = V C1 - α CTAT (T - 300), where T is the Kelvin temperature, V C1 is the voltage of V CTAT1 at T = 300K, and α CATA is the rate of change of V CTAT1 with respect to temperature. Let m1 = (V REF1 - V C1 - 300α CTAT )q / ηk and n1 = α CTAT q / ηk, then I2 can be expressed as:

[0066]

[0067] where

[0068]

[0069] Equation (6) is obtained by performing a Taylor expansion at T = T0, and o((T - T0) ) is the Peano remainder. In the low temperature range, the range of T0 is 228K < T0 < 313K (-45 to 27°C); in the high temperature range, the range of T0 is 228K < T0 < 313K (-45 to 27°C). n ) is the Peano remainder. In the low temperature range, the range of T0 is 228K < T0 < 313K (-45 to 27°C); in the high temperature range, the range of T0 is 228K < T0 < 313K (-45 to 27°C).

[0070] By reasonably setting V REF1 and V CTAT1 , it can be ensured that m1 < 0. Therefore, the output current I EXP1 of the high temperature segment compensation current generation circuit is:

[0071]

[0072] The output current I EXP1 of the high temperature segment compensation current generation circuit increases exponentially with the increase in temperature.

[0073] I EXP1 serves as the subtracted current (I IN+ ), IREF3 As the current to be reduced (I) IN- ) was sent to the attached Figure 4 The first current subtractor shown has an output current of I. CP1 It is worth noting that I EXP1 Greater than I REF3 At that time, I CP1 =I EXP1 -I REF3 ;I EXP1 Less than I REF3 At that time, due to the NMOS transistor M N7 and NMOS transistor M N8 Entering the linear region, I CP1 =0.

[0074] As attached Figure 4 As shown, V CTAT2 Connected to PMOS transistor M P7 The gate of V REF2 Connected to PMOS transistor M P8 With PMOS transistor M P11 The gate of I REF2 Injection node S2, i.e., PMOS transistor M P1 and PMOS transistor M P2 The source of the PMOS transistor. P7 PMOS transistor M P8 and PMOS transistor M P11 Operating in the subthreshold region with identical design parameters, and similar to a PMOS transistor operating in the saturation region. P9 PMOS transistor M P10 and PMOS transistor M P12 They form a common-source, common-gate structure; therefore, the PMOS transistor M... P7 PMOS transistor M P8 and PMOS transistor M P11 The channel length modulation effect can be ignored.

[0075] PMOS transistor M P8 The current I8 flowing through it:

[0076]

[0077] PMOS transistor M P7 The current I7 flowing through it:

[0078]

[0079] In formulas (8) and (9), I8 is the PMOS transistor M P8 The current flowing through it, I7 is the PMOS transistor M P7 The current flowing through it, V S2Let be the voltage at node S2.

[0080] The low-temperature exponential compensation circuit enables the PMOS transistor M P11 The current flowing through is a copy of I8, and an output current of magnitude I8 is injected into node S2. Applying Kirchhoff's Current Law (KCL) to node S2, we obtain:

[0081] I REF2 +I8=I7+I8 (10)

[0082] Furthermore:

[0083]

[0084] V CTAT2 It can be represented as: V CTAT2 =V C2 -α CTAT (T-300), where T is the Kelvin temperature and V is the Kelvin temperature. C2 For V CTAT2 The voltage at T = 300K, α CATA It is V CTAT1 The rate of change with temperature. Let m2 = (VC1 + 300αCTAT - VREF1)q / ηk and n2 = α CTAT If q / ηk, then I8 can be expressed as:

[0085]

[0086] By properly setting V REF2 With V CTAT2 This ensures that m2 > 0. Therefore, the output current I of the low-temperature compensation current generation circuit is... EXP2 :

[0087]

[0088] The output current I of the low-temperature compensation current generation circuit EXP2 The index decreases as temperature rises.

[0089] I EXP2 As the reduced current (I) IN+ ), I REF4 As the current to be reduced (I) IN- The current is fed into the second current subtractor, whose output current is I. CP2 It is worth noting that I EXP2 Greater than I REF4 At that time, I CP2 =I EXP2 -I REF4 ;I EXP2 Less than I REF4 At that time, due to M N7and M N8 Entering the linear region, I CP2 =0.

[0090] Appendix Figure 5 This is a current adder circuit that adds I generated by the preceding circuit. CP1 with I CP2 Inject M P16 The drain of the MP15, through a proportional replication of the common-source cascode current mirror, generates the output current I of the drain output current adder. CP =I CP1 +I CP2 I CP Injecting a reference output resistor, the reference output voltage is generated through a bowl-shaped segmented temperature compensation voltage V by the voltage divider effect of the reference output resistor. CP This achieves temperature compensation for the output voltage of the reference source.

[0091] In embodiments of the present invention, a bowl-shaped segmented temperature compensation circuit of the bandgap reference source provided by the present invention is used to perform temperature compensation on a conventional current-mode bandgap reference (power supply voltage of 1.2V, reference output voltage of 600mV). The bowl-shaped segmented temperature compensation circuit provided in this embodiment of the present invention generates I... CP1 with I CP2 The simulation diagram is attached. Figure 6 Temperature compensation current I CP The curve shows the change in exponent with temperature within the usage range, with the exponent decreasing in the low temperature range, remaining at 0 in the middle temperature range, and increasing in the high temperature range, forming an overall bowl shape.

[0092] The bowl-shaped segmented temperature compensation circuit provided by this invention utilizes the transfer characteristics of PMOS transistors operating in the subthreshold region in the high and low temperature segment compensation current generation circuits. A compensation current is generated via a current adder, and then, through the voltage division effect of the reference output resistor, curvature compensation voltages with different curvatures that do not affect each other are generated. The overall compensation presents a bowl shape, accurately replicating the output current and output voltage of the reference source at the temperatures on both sides, forming a high-order temperature compensation while facilitating debugging and use. Furthermore, this circuit only contains resistors in the current adder and current subtractor, and these resistors are all used to mitigate the mismatch effect of the current mirror, aiming to make the current replication more accurate. Therefore, the resistor mismatch and temperature coefficient have almost no impact on the temperature characteristics of the output temperature compensation voltage.

[0093] The simulation diagram of the reference source output voltage changing with temperature before and after using the bowl-shaped segmented temperature compensation circuit provided in this embodiment of the invention is shown in the attached figure. Figure 7 V REF1 With V REF2These are the reference output voltages before and after temperature compensation. The calculated temperature coefficients of the reference output voltages before and after temperature compensation are 12.5 ppm / ℃ and 0.33 ppm / ℃, respectively. Therefore, the bandgap reference cup-shaped segmented temperature compensation circuit provided by this invention can effectively optimize the temperature characteristics of the reference output voltage.

[0094] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. All content that does not depart from the technical solution of the present invention should be included within the protection scope of the present invention.

Claims

1. A bowl-shaped segmented temperature compensation circuit for a bandgap reference source, characterized in that, include: High-temperature range compensation current generation circuit, low-temperature range compensation current generation circuit, first current subtractor, second current subtractor and current adder; The output terminal of the high-temperature section compensation current generating circuit is connected to the input terminal of the first current subtractor, and the output terminal of the first current subtractor is connected to the first input terminal of the current adder. The output terminal of the low-temperature compensation current generating circuit is connected to the input terminal of the second current subtractor, and the output terminal of the second current subtractor is connected to the second input terminal of the current adder. The output of the current adder generates a compensation current. The high-temperature range compensation current generating circuit includes a high-temperature range exponential current generating circuit and a high-temperature range exponential current compensation circuit, wherein the high-temperature range exponential current generating circuit is connected to the high-temperature range exponential current compensation circuit. The high-temperature exponential current generation circuit includes a PMOS transistor M. P1 PMOS transistor M P2 PMOS transistor M P3 and PMOS transistor M P4 ; The PMOS transistor M P1 With the PMOS transistor M P2 The source connection of the PMOS transistor M P1 The gate is connected to a temperature-insensitive voltage V. REF1 The PMOS transistor M P2 The gate is connected to a voltage V with a negative temperature coefficient. CTAT1 The PMOS transistor M P3 The source of the PMOS transistor M P1 The drain connection of the PMOS transistor M P3 The source of the PMOS transistor is grounded. P3 The gate and the PMOS transistor M P4 The gate is biased by a constant voltage V. B1 The PMOS transistor M P4 The source of the PMOS transistor M P2 The drain connection of the PMOS transistor M P4 The source output of the high-temperature exponential current generation circuit is the output current I. EXP1 .

2. The bowl-shaped segmented temperature compensation circuit for the bandgap reference source according to claim 1, characterized in that, The high-temperature exponential current compensation circuit includes a PMOS transistor M. P5 PMOS transistor M P6 First unity-gain buffer Buffer1, first current mirror M1, and second current mirror M2; The input terminal of the first unity-gain buffer Buffer1 is connected to the PMOS transistor M. P3 The source is connected, and the output of the first unity-gain buffer Buffer1 is connected to the PMOS transistor M. P5 The source connection of the PMOS transistor M P5 The gate of the PMOS transistor M P2 The gate connection of the PMOS transistor M P5 The drain of the PMOS transistor M P6 The source connection of the PMOS transistor M P6 The gate of the PMOS transistor M P4 The gate connection of the PMOS transistor M P6 The drain of the first current mirror M1 is connected to the input terminal of the first current mirror M1, the output terminal of the first current mirror M1 is connected to the input terminal of the second current mirror M2, and the output terminal of the second current mirror M2 is connected to the input terminal of the first unity-gain buffer Buffer1.

3. The bowl-shaped segmented temperature compensation circuit for the bandgap reference source according to claim 1, characterized in that, The low-temperature range compensation current generating circuit includes a low-temperature range exponential current generating circuit and a low-temperature range exponential current compensation circuit, wherein the low-temperature range exponential current generating circuit is connected to the low-temperature range exponential current compensation circuit.

4. The bowl-shaped segmented temperature compensation circuit for the bandgap reference source according to claim 3, characterized in that, The low-temperature exponential current generation circuit includes a PMOS transistor M. P7 PMOS transistor M P8 PMOS transistor M P9 and PMOS transistor M P10 ; The PMOS transistor M P7 With the PMOS transistor M P8 The source connection of the PMOS transistor M P8 The gate is connected to a temperature-insensitive voltage V. REF2 The PMOS transistor M P7 The voltage V with a negative temperature coefficient at the gate CTAT2 The PMOS transistor M P9 The source of the PMOS transistor M P7 The drain connection of the PMOS transistor M P9 The source of the PMOS transistor is grounded. P10 The source of the PMOS transistor M P8 The drain connection of the PMOS transistor M P9 and the PMOS transistor M P10 The gate is biased by a constant voltage V. B2 The PMOS transistor M P10 The source output of the low-temperature exponential current generation circuit is the output current I. EXP2 .

5. The bowl-shaped segmented temperature compensation circuit for the bandgap reference source according to claim 4, characterized in that, The low-temperature exponential current compensation circuit includes a PMOS transistor M. P11 PMOS transistor M P12 The second unity-gain buffer Buffer2, the third current mirror M3, and the fourth current mirror M4; The input terminal of the second unity-gain buffer Buffer2 is connected to the PMOS transistor M. P8 The source terminal is connected, and the output terminal of the second unity-gain buffer Buffer2 is connected to the PMOS transistor M. P11 The source connection of the PMOS transistor M P11 The gate of the PMOS transistor M P8 The gate connection of the PMOS transistor M P11 The drain of the PMOS transistor M P12 The source connection of the PMOS transistor M P12 The gate of the PMOS transistor M P10 The gate connection of the PMOS transistor M P12 The drain of the device is connected to the input terminal of the third current mirror M3, the output terminal of the third current mirror M3 is connected to the input terminal of the fourth current mirror M4, and the output terminal of the fourth current mirror M4 is connected to the input terminal of the second unity-gain buffer Buffer2.

6. The bowl-shaped segmented temperature compensation circuit for the bandgap reference source according to claim 1, characterized in that, The first current subtractor includes an NMOS transistor M N1 NMOS transistor M N2 NMOS transistor M N3 NMOS transistor M N4 NMOS transistor M N5 NMOS transistor M N6 NMOS transistor M N7 NMOS transistor M N8 Resistors R1, R2, R3, and R4; The NMOS transistor M N1 The drain of the NMOS transistor M N3 The gate connection of the NMOS transistor M N1 The gate of the NMOS transistor M N2 The gate is biased by a constant voltage V. B3 The NMOS transistor M N2 The source of the NMOS transistor M N3 The drain connection of the NMOS transistor M N3 The source of the NMOS transistor is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded. N2 The drain of the NMOS transistor M N5 The drain connection of the NMOS transistor M N2 The source of the NMOS transistor M N4 The drain connection of the NMOS transistor M N4 The gate of the NMOS transistor M N3 The gate connection of the NMOS transistor M N4 The source of the NMOS transistor is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded. N5 The drain of the NMOS transistor M N7 The gate connection of the NMOS transistor M N5 The gate of the NMOS transistor M N6 The gate is biased by a constant voltage V. B4 The NMOS transistor M N5 The source of the NMOS transistor M N7 The drain connection of the NMOS transistor M N7 The source of the NMOS transistor is connected to one end of resistor R3, and the other end of resistor R3 is grounded. N4 The gate of the NMOS transistor M N7 The gate connection of the NMOS transistor M N4 The source of the NMOS transistor is connected to one end of the resistor R4, and the other end of the resistor R4 is grounded. N6 The source of the NMOS transistor M N8 The drain connection of the NMOS transistor M N6 The drain output of the first current subtractor is the output current I. CP1 .

7. The bowl-shaped segmented temperature compensation circuit for the bandgap reference source according to claim 6, characterized in that, The second current subtractor has the same structure as the first current subtractor, and the second current subtractor outputs a current I. CP2 .

8. The bowl-shaped segmented temperature compensation circuit for the bandgap reference source according to claim 1, characterized in that, The current adder includes a PMOS transistor M P13 PMOS transistor M P14 PMOS transistor M P15 PMOS transistor M P16 Resistors R5 and R6; One end of resistor R5 is connected to VDD, and the other end of resistor R5 is connected to the PMOS transistor M. P13 The source of the transistor is connected, one end of resistor R6 is connected to VDD, and the other end of resistor R6 is connected to the PMOS transistor M. P14 The source connection of the PMOS transistor M P14 The drain of the PMOS transistor M P16 The source connection of the PMOS transistor M P13 The gate of the PMOS transistor M P14 The gate of the PMOS transistor M P16 The drain connection of the PMOS transistor M P13 The drain of the PMOS transistor M P15 The source connection of the PMOS transistor M P15 The gate of the PMOS transistor M P16 The gate is biased by a constant voltage V. B5 The PMOS transistor M P15 The drain output of the current adder is the output current I. CP .

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