Display panel, test method thereof and display device

Abstract

The application discloses a display panel, a testing method thereof and a display device. The display panel comprises a plurality of pixel units in a display area, a plurality of data lines and a plurality of first fan-out lines, a plurality of second fan-out lines, a plurality of testing circuit units and at least two testing signal lines in a non-display area, and the first fan-out line is electrically connected with the corresponding first data line. Each testing circuit unit comprises a plurality of first switches and a plurality of second switches, the first end of the plurality of first switches is electrically connected with the corresponding first fan-out line through the corresponding second fan-out line, the first end of the plurality of second switches is electrically connected with the corresponding second data line through the corresponding second fan-out line, the second end of the switches electrically connected with the pixel units in the same column is electrically connected to the same testing signal line, and the second end of the switches electrically connected with the pixel units in the adjacent two columns is electrically connected to different testing signal lines. When the display panel is abnormal, the bad detection of the display panel can be realized.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a display panel, a testing method thereof and a display device. BACKGROUND

[0002] After all film layers of the display panel are manufactured, a testing terminal can provide a detection signal for the display panel to realize detection of the display panel, so as to screen out defective display panels and avoid waste of subsequent processes caused by the defective display panels. SUMMARY

[0003] The present application provides a display panel, a testing method thereof and a display device to realize detection of defective display panels.

[0004] In a first aspect, embodiments of the present application provide a display panel, the display panel comprising a display area and a non-display area, and further comprising:

[0005] a plurality of pixel units arranged in an array, located in the display area;

[0006] a plurality of data lines located in the display area and electrically connected to corresponding columns of pixel units, the plurality of data lines extending along a column direction and arranged along a row direction, and the plurality of data lines comprising at least two first data lines and at least two second data lines;

[0007] a plurality of first fan-out lines located in the display area, each first fan-out line being electrically connected to a corresponding first data line;

[0008] a plurality of second fan-out lines, a plurality of testing circuit units and at least two testing signal lines located in the non-display area, each testing circuit unit comprising a plurality of first switches and a plurality of second switches, a first end of each first switch being electrically connected to a corresponding first fan-out line via a corresponding second fan-out line, a first end of each second switch being electrically connected to a corresponding second data line via a corresponding second fan-out line, a second end of each switch corresponding to a same column of pixel units being electrically connected to a same testing signal line, and a second end of each switch corresponding to adjacent columns of pixel units being electrically connected to different testing signal lines.

[0009] Optionally, the at least two testing signal lines comprise a first testing signal line and a second testing signal line,

[0010] a second end of each switch corresponding to an odd column of pixel units being electrically connected to the first testing signal line, and a second end of each switch corresponding to an even column of pixel units being electrically connected to the second testing signal line.

[0011] Optionally, the display panel further comprises a control signal line, a control end of each first switch and a control end of each second switch being electrically connected to the control signal line.

[0012] Optionally, the first switch comprises a first transistor, a first electrode of the first transistor serving as the first end of the first switch, a second electrode of the first transistor serving as the second end of the first switch, and a control electrode of the first transistor serving as the control end of the first switch.

[0013] Optionally, the second switch comprises a second transistor, a first electrode of the second transistor serving as the first end of the second switch, a second electrode of the second transistor serving as the second end of the second switch, and a control electrode of the second transistor serving as the control end of the second switch.

[0014] Optionally, the arrangement order of the plurality of second fan-out lines along the row direction is different from the arrangement order of the data lines to which the second fan-out lines are electrically connected.

[0015] Optionally, the first end of the first fan-out line to which the second fan-out line is electrically connected is closer to the middle second data line of the display area than the second end of the first fan-out line to which the first data line is electrically connected.

[0016] Optionally, the plurality of second fan-out lines are arranged along the row direction, and the outermost second fan-out line is electrically connected to the first end of the first switch.

[0017] Optionally, the first fan-out line comprises a first connection line and a second connection line, the second connection line being electrically connected to the corresponding first data line via the first connection line; the plurality of second connection lines extend along the column direction and are arranged along the row direction; N data lines are arranged between any two adjacent second connection lines; and N is an integer greater than or equal to 2.

[0018] Any pixel unit comprises M sub-pixels, or any pixel unit is electrically connected to M data lines, where M is an integer greater than or equal to 2; any test circuit unit comprises K*M first switches and N*K*M second switches, where K is an integer greater than or equal to 1.

[0019] Optionally, the plurality of pixel units are divided into at least two pixel repeating units, and any pixel repeating unit comprises K pixel units.

[0020] Optionally, the plurality of second fan-out lines comprise at least two third fan-out lines and at least two fourth fan-out lines; the third fan-out line is electrically connected to the first end of the first switch; and the fourth fan-out line is electrically connected to the first end of the second switch.

[0021] Optionally, the plurality of second fan-out lines are arranged along the row direction; the arrangement order of the third fan-out line is opposite to the arrangement order of the corresponding first data line, and the arrangement order of the fourth fan-out line is the same as the arrangement order of the corresponding second data line.

[0022] Optionally, N fourth fan-out lines are arranged between any two third fan-out lines; the N fourth fan-out lines arranged between any two third fan-out lines are electrically connected to the same column of pixel units; in the 2N fourth fan-out lines arranged between any three third fan-out lines, N fourth fan-out lines and another N fourth fan-out lines are electrically connected to different columns of pixel units.

[0023] Optionally, in each test circuit unit, the plurality of first switches and the plurality of second switches are arranged in a row direction; N second switches are arranged between any two first switches.

[0024] Optionally, in each test circuit unit, the second ends of the N second switches arranged between any two first switches are electrically connected to the same test signal line; in the 2N second switches arranged between any three first switches, the second ends of N second switches and the second ends of another N second switches are electrically connected to different test signal lines.

[0025] Optionally, the plurality of first switches in each test circuit unit are electrically connected to a column of pixel units or at least two adjacent columns of pixel units; the plurality of second switches in each test circuit unit are electrically connected to a plurality of adjacent columns of pixel units.

[0026] Optionally, M is equal to N.

[0027] Optionally, the display panel further comprises N+1 rows of pads located in the non-display area, each row of pads comprises a plurality of pads arranged in a row direction, a row of pads is electrically connected to the third fan-out line electrically connected to the first switch, and the arrangement order is opposite to that of the corresponding electrically connected data line; the remaining N rows of pads are electrically connected to the fourth fan-out line electrically connected to the second switch, and the arrangement order is the same as that of the corresponding electrically connected data line.

[0028] Optionally, N is 2, M is 2, and K is 2.

[0029] Optionally, the plurality of pixel units comprise at least two first pixel units and at least two second pixel units, the first pixel unit comprises a first color sub-pixel and a second color sub-pixel; the second pixel unit comprises a third color sub-pixel and a second color sub-pixel; in the same row of pixel units, the first pixel units and the second pixel units are arranged alternately in a row direction;

[0030] Optionally, in the same column of pixel units, the first pixel units and the second pixel units are arranged alternately in a column direction.

[0031] Optionally, in the two adjacent columns of sub-pixels, the first color sub-pixels and the third color sub-pixels in one column of sub-pixels are arranged alternately in a column direction; the other column of sub-pixels are all second color sub-pixels.

[0032] Optionally, the first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

[0033] Optionally, each test circuit unit includes 4 first switches and 8 second switches, and 2 data lines are arranged between two adjacent second connection lines; the 4 first switches in each test circuit unit are electrically connected to adjacent two columns of pixel units; and the 8 second switches in each test circuit unit are electrically connected to adjacent 4 columns of pixel units.

[0034] Of the 4 first switches in each test circuit unit, two first switches located on one side are electrically connected to the same column of pixel units, and the other two first switches located on the other side are electrically connected to the same column of pixel units.

[0035] Optionally, N is 3, M is 3, and K is 1.

[0036] Optionally, any pixel unit includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; each row of sub-pixels is arranged in a sequence of a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; and each column of sub-pixels is a sub-pixel of the same color.

[0037] Optionally, the first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

[0038] Optionally, each test circuit unit includes 3 first switches and 9 second switches, and 3 data lines are arranged between two adjacent second connection lines.

[0039] The 3 first switches in each test circuit unit are electrically connected to the same column of pixel units; and the 9 second switches in each test circuit unit are electrically connected to adjacent 3 columns of pixel units.

[0040] Optionally, the first connection lines extend in the row direction; of the first connection lines arranged in the column direction, the longer the first connection line, the closer the first data line electrically connected to the first connection line to the frame of the display panel, and the longer the second connection line electrically connected to the first connection line.

[0041] Optionally, at least part of the second fan-out lines are located in the same conductive layer.

[0042] Optionally, the second fan-out lines are arranged in the row direction, and adjacent two second fan-out lines are located in different conductive layers; of adjacent three second fan-out lines, two second fan-out lines located on the sides are located in the same conductive layer.

[0043] Optionally, the display region comprises a first display region, a second display region and a third display region arranged in sequence along a row direction, the first data line is located in the first display region and the third display region, and the second data line is located in the second display region.

[0044] In a second aspect, the embodiment of the present application further provides a display device, comprising a driving chip and the display panel of the first aspect, and the driving chip is electrically connected with the second fan-out line.

[0045] In a third aspect, the embodiment of the present application further provides a test method applied to the display panel of the first aspect, and the test method comprises:

[0046] In the first time period, the first switch and the second switch are controlled to be turned on, the second end of the switch corresponding to the odd-numbered column pixel unit is electrically connected with the test signal line to input the lighting voltage, and the second end of the switch corresponding to the even-numbered column pixel unit is electrically connected with the test signal line to input the extinguishing voltage.

[0047] And / or, in the second time period, the first switch and the second switch are controlled to be turned on, the second end of the switch corresponding to the odd-numbered column pixel unit is electrically connected with the test signal line to input the extinguishing voltage, and the second end of the switch corresponding to the even-numbered column pixel unit is electrically connected with the test signal line to input the lighting voltage.

[0048] The technical scheme of the embodiment of the present application, by setting the first end of the first switch in the test circuit unit to be electrically connected with the corresponding first data line through the corresponding second fan-out line and the first fan-out line, the first end of the second switch to be electrically connected with the corresponding second data line through the corresponding second fan-out line, the second end of the switch corresponding to the same column pixel unit to be electrically connected to the same test signal line, and the second end of the switch corresponding to the adjacent two column pixel units to be electrically connected to different test signal lines, can provide different test signals to different test signal lines when detecting the display panel, so that the test signals obtained by the adjacent two column pixel units are different, and when the display panel is normal, the detection picture of the pixel units spaced by at least one column lighting can be realized. When the display panel is abnormal, the display panel cannot realize the detection picture of the pixel units spaced by at least one column lighting, so that whether the display panel is abnormal can be judged according to the detection picture, and the bad detection of the display panel is realized. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 A partial structure schematic diagram of a display panel provided by the related art is shown;

[0050] Figure 2 A partial structure schematic diagram of a display panel provided by the embodiment of the present application is shown;

[0051] Figure 3 A partial enlarged structure schematic diagram of a display panel provided by the embodiment of the present application is shown;

[0052] Figure 4 A partial enlarged structural schematic view of another display panel provided by the embodiment of the present application is shown in FIG. 6;

[0053] Figure 5 A partial enlarged structural schematic view of another display panel provided by the embodiment of the present application is shown in FIG. 6;

[0054] Figure 6 A partial enlarged structural schematic view of another display panel provided by the embodiment of the present application is shown in FIG. 6;

[0055] Figure 7 A structural schematic view of a pad provided by the embodiment of the present application is shown in FIG. 6;

[0056] Figure 8 A partial enlarged structural schematic view of another display panel provided by the embodiment of the present application is shown in FIG. 6;

[0057] Figure 9 A partial enlarged structural schematic view of another display panel provided by the embodiment of the present application is shown in FIG. 6;

[0058] Figure 10 A partial enlarged structural schematic view of another display panel provided by the embodiment of the present application is shown in FIG. 6;

[0059] Figure 11 A partial enlarged structural schematic view of another display panel provided by the embodiment of the present application is shown in FIG. 6;

[0060] Figure 12 A partial cross-sectional structural schematic view of a display panel provided by the embodiment of the present application is shown in FIG. 6;

[0061] Figure 13 A structural schematic view of another display panel provided by the embodiment of the present application is shown in FIG. 6;

[0062] Figure 14 A structural schematic view of a display device provided by the embodiment of the present application is shown in FIG. 6;

[0063] Figure 15 A flowchart of a test method of a display panel provided by the embodiment of the present application is shown in FIG. 6. DETAILED DESCRIPTION

[0064] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended to serve only as an explanation of the present application and not as a limitation thereof. It should also be noted that, for the purpose of description, only the parts related to the present application are shown in the drawings rather than all the parts.

[0065] When a display panel adopts a fanout in active area (FIAA) structure in a display area for reducing the frame of the display panel, the fanout lines of the display panel have a disorder phenomenon, at this time, the display panel cannot be detected, and thus a defective display panel is easily generated, causing waste of subsequent processes.

[0066] Figure 1 A partial structure diagram of a display panel is provided in the related art. As shown in Figure 1 The display panel includes a display area 101 and a non-display area 102, the display area 101 is provided with a pixel A, a data line D and a connection line M1, one data line D is electrically connected with one column of pixels A, part of the data lines D are connected with the fanout lines M2 of the non-display area 102 through the connection lines M1, and part of the data lines D are directly connected with the fanout lines M2. That is, the display panel adopts the FIAA structure for reducing the frame of the display panel, at this time, the arrangement order of the fanout lines M2 of the non-display area 102 of the display panel is different from the arrangement order of the data lines D, which is equivalent to the disorder phenomenon of the fanout lines M2 of the non-display area 102. The non-display area 102 is further provided with a detection circuit 103, the detection circuit 103 includes a plurality of switches K, and each switch K is connected with one data line D through one fanout line M2. The display panel further includes a control line SW, a first detection line D_1 and a second detection line D_2. In the related art, two adjacent switches K are alternately connected with the first detection line D_1 and the second detection line D_2. In the detection process of the display panel, different voltages can be provided for the first detection line D_1 and the second detection line D_2. When the fanout lines M2 of the non-display area 102 have the disorder phenomenon, the detection picture of the isolated column lighting cannot be realized when the display panel is normal, which leads to the fact that whether the display panel is abnormal cannot be detected.

[0067] Exemplarily, when the fan-out lines M2 of the non-display area 102 exist the out-of-order phenomenon, along the row direction, the 1st switch K is connected with the 4th data line D through the 1st fan-out line M2, the 2nd switch K is connected with the 5th data line D through the 2nd fan-out line M2, the 3rd switch K is connected with the 6th data line D through the 3rd fan-out line M2, the 4th switch K is connected with the 3rd data line D through the 4th fan-out line M2, the 5th switch K is connected with the 7th data line D through the 5th fan-out line M2, the 6th switch K is connected with the 8th data line D through the 6th fan-out line M2, the 7th switch K is connected with the 2nd data line D through the 7th fan-out line M2, the 8th switch K is connected with the 9th data line D through the 8th fan-out line M2, the 9th switch K is connected with the 10th data line D through the 9th fan-out line M2, the 10th switch K is connected with the 1st data line D through the 10th fan-out line M2, the 11th switch K is connected with the 11th data line D through the 11th fan-out line M2, and the 12th switch K is connected with the 12th data line D through the 12th fan-out line M2. When the detection of the display panel is performed, the control line SW can be provided with a low level, for example, -7.5V, the first detection line D_1 can be provided with the lighting voltage, for example, 4V, and the second detection line D_2 can be provided with the extinguishing voltage, for example, 7.5V. At this time, the pixel corresponding to the data line D connected with the 1st switch K, the 2nd switch K, the 5th switch K, the 6th switch K, the 9th switch K and the 10th switch K is lit, that is, the pixel corresponding to the 4th, 5th, 7th, 8th, 10th and 1st data line D is lit; the pixel corresponding to the data line D connected with the 3rd switch K, the 4th switch K, the 7th switch K, the 8th switch K, the 11th switch K and the 12th switch K is extinguished, that is, the pixel corresponding to the 6th, 3rd, 2nd, 9th, 11th and 12th data line D is extinguished. When the display panel is normal, the detection picture of lighting two columns every two columns cannot be realized. Therefore, whether the display panel is abnormal cannot be judged according to the detection picture.

[0068] When the display panel adopts the FIAA structure for reducing the frame of the display panel, the arrangement order of the fan-out lines of the non-display area of the display panel is different from the arrangement order of the data lines, which is equivalent to the out-of-order phenomenon of the fan-out lines of the non-display area. At this time, when the detection circuit provided by the related technology is used for detection, when the display panel is normal, the display panel cannot realize the detection picture of lighting every column, and the bad detection of the display panel cannot be performed, so that the subsequent process is wasted due to the bad display panel.

[0069] In view of the above technical problems, the embodiment of the present application provides a display panel. Figure 2 A partial structure schematic diagram of a display panel provided by the embodiment of the present application is shown in the figure, Figure 3A local enlarged structure schematic view of a display panel is provided for an embodiment of the present application. As shown in Figure 2 and Figure 3 The display panel includes a display area AA and a non-display area NAA. The display panel further includes:

[0070] A plurality of pixel units 110 arranged in an array are located in the display area AA. Optionally, any pixel unit 110 includes at least two sub-pixels P.

[0071] A plurality of data lines DA are located in the display area AA and electrically connected to the pixel units 110 in corresponding columns. The plurality of data lines DA extend along a column direction Y and are arranged along a row direction X. The plurality of data lines DA include at least two first data lines DA1 (e.g., DA11-DA14) and at least two second data lines DA2 (e.g., DA21-DA28). The column direction Y can intersect the row direction X. Optionally, the column direction Y can be perpendicular to the row direction X.

[0072] A plurality of first fan-out lines F1 are located in the display area AA. The first fan-out lines F1 are electrically connected to the first data lines DA1.

[0073] A plurality of second fan-out lines F2, a plurality of test circuit units 120, and at least two test signal lines TES are located in the non-display area NAA. Each test circuit unit 120 includes a plurality of first switches 121 and a plurality of second switches 122. First ends of the plurality of first switches 121 are electrically connected to the first fan-out lines F1 via corresponding second fan-out lines F2. First ends of the plurality of second switches 122 are electrically connected to the second data lines DA2 via corresponding second fan-out lines F2. Second ends of the switches electrically connected to the pixel units 110 in the same column are electrically connected to the same test signal line TES. Second ends of the switches electrically connected to the pixel units 110 in adjacent columns are electrically connected to different test signal lines TES.

[0074] Specifically, in the same pixel unit 110, at least two sub-pixels can be located in different columns. Optionally, all the sub-pixels in the same pixel unit 110 are located in different columns and are adjacent in the same row. For example, when the pixel arrangement of the display panel is in the RGBG arrangement mode, the red sub-pixel and the blue sub-pixel are arranged in the same column and serve as the first column sub-pixel. The green sub-pixel is arranged in the same column and serves as the second column sub-pixel. The first column sub-pixel and the second column sub-pixel are arranged alternately. The arrangement order of the red sub-pixel and the blue sub-pixel in the two adjacent columns of the first column sub-pixel is different. At this time, the pixel unit 110 can include the sub-pixels in the adjacent columns in the same row, for example, can include the red sub-pixel and the green sub-pixel in the same row or the blue sub-pixel and the green sub-pixel in the same row, corresponding to the connection of the two data lines DA. When the pixel arrangement of the display panel is in the RGB arrangement mode, the red sub-pixel, the blue sub-pixel and the green sub-pixel are arranged in different columns respectively, and the columns of sub-pixels of different colors are arranged alternately. At this time, the pixel unit 110 can include three sub-pixels in the adjacent columns in the same row, which are the red sub-pixel, the blue sub-pixel and the green sub-pixel respectively, corresponding to the connection of the three data lines DA.

[0075] The display area AA is also provided with a first fan-out line F1 and is connected with the corresponding first data line DA1. The non-display area NAA is provided with a second fan-out line F2 and a test circuit unit 120. The first end of the first switch 121 in the test circuit unit 120 is connected with one end of the corresponding second fan-out line F2, and the other end of the corresponding second fan-out line F2 is connected with the corresponding first fan-out line F1, so that the first end of the first switch 121 can be connected with the corresponding first data line DA1 through the corresponding second fan-out line F2 and the first fan-out line F1, for providing a test signal for the sub-pixel connected with the first data line DA1. The first end of the second switch 122 in the test circuit unit 120 is connected with one end of the corresponding second fan-out line F2, and the other end of the corresponding second fan-out line F2 is connected with the corresponding second data line DA2, for providing a test signal for the sub-pixel connected with the second data line DA2. In order to reduce the size of the lower frame, when the first fan-out line F1 is arranged in the display area AA, one end of the first fan-out line F1 is electrically connected with the first data line DA1, and the other end is inserted between the second data lines DA2 and extends from the display area AA to the non-display area NAA. Therefore, the arrangement order of the second fan-out line F2 of the display panel is different from the arrangement order of the data line connected therewith, and the second fan-out line F2 has a disorder phenomenon. For example, continuing to refer to Figure 3 , the first data line DA1 and the second data line DA2 can be arranged in order along the row direction X. Figure 3A set of data lines DA corresponding to a test circuit unit 120 is exemplarily shown, wherein the first data line DA1 has four, which can be the first first data line DA11, the second first data line DA12, the third first data line DA13 and the fourth first data line DA14 in turn. It is also shown that the second data line DA2 has eight, which can be the first second data line DA21, the second second data line DA22, the third second data line DA23, the fourth second data line DA24, the fifth second data line DA25, the sixth second data line DA26, the seventh second data line DA27 and the eighth second data line DA28 in turn. Along the row direction X, the arrangement order of the first data line to the twelfth data line from left to right is the first first data line DA11, the second first data line DA12, the third first data line DA13, the fourth first data line DA14, the first second data line DA21, the second second data line DA22, the third second data line DA23, the fourth second data line DA24, the fifth second data line DA25, the sixth second data line DA26, the seventh second data line DA27 and the eighth second data line DA28 in turn. Four first fan-out lines F1 and twelve second fan-out lines F2 corresponding to a test circuit unit 120 are connected. Each first fan-out line F1 can be electrically connected to a first data line DA1 one by one, and each second fan-out line F2 can be electrically connected to a first fan-out line F1 or a second data line DA2. Exemplarily, four first fan-out lines F1 and twelve second fan-out lines F2 corresponding to a test circuit unit 120 are connected according to Figure 3In the direction from left to right, the first fan-out line F1 is arranged from the first first fan-out line F1 to the fourth first fan-out line F1, and the second fan-out line F2 is arranged from the first second fan-out line F2 to the twelfth second fan-out line F2. At this time, the first second fan-out line F2 can be electrically connected to the fourth first data line DA14 (the fifth data line on the left) through the first first fan-out line F1, which is equivalent to that the second fan-out line F2 located at the leftmost side is not electrically connected to the data line DA located at the leftmost side, that is, the arrangement order of the second fan-out line F2 is different from that of the data line DA electrically connected thereto, the second second fan-out line F2 and the third second fan-out line F2 are electrically connected to the first second data line DA21 (the fifth data line on the left) and the second second data line DA22 (the sixth data line on the left) respectively, the fourth second fan-out line F2 is electrically connected to the third first data line DA13 (the third data line on the left) through the second first fan-out line F1, the fifth second fan-out line F2 and the sixth second fan-out line F2 are electrically connected to the third second data line DA23 (the seventh data line on the left) and the fourth second data line DA24 (the eighth data line on the left) respectively, the seventh second fan-out line F2 is electrically connected to the second first data line DA12 (the second data line on the left) through the third first fan-out line F1, the eighth second fan-out line F2 and the ninth second fan-out line F2 are electrically connected to the fifth second data line DA25 (the ninth data line on the left) and the sixth second data line DA26 (the tenth data line on the left) respectively, the tenth second fan-out line F2 is electrically connected to the first first data line DA11 (the first data line on the left) through the fourth first fan-out line F1, and the eleventh second fan-out line F2 and the twelfth second fan-out line F2 are electrically connected to the seventh second data line DA27 (the eleventh data line on the left) and the eighth second data line DA28 (the twelfth data line on the left) respectively. At this time, according to the correspondence relationship between the arrangement order of the second fan-out line F2 and the data line from left to right, the first second fan-out line F2 to the twelfth second fan-out line F2 correspond to the fourth data line, the fifth data line, the sixth data line, the third data line, the seventh data line, the eighth data line, the second data line, the ninth data line, the tenth data line, the first data line, the eleventh data line and the twelfth data line respectively, that is, the arrangement order of the second fan-out line F2 is different from that of the data line electrically connected thereto, and the second fan-out line F2 has a disorder phenomenon. Figure 3

[0076] ​The number of the first switches 121 is equal to the number of the first data lines DA1, and the number of the second switches 122 is equal to the number of the second data lines DA2. When the pixel unit 110 includes at least two sub-pixels arranged in different columns, at least two switches corresponding to the same pixel unit 110 can be arranged. In the pixel units electrically connected to the same test circuit unit, all the sub-pixels in the same column of pixel units 110 can be electrically connected to the first switches, or all the sub-pixels in the same column of pixel units 110 can be electrically connected to the second switches. The first end of the first switch 121 is electrically connected to the corresponding first fan-out line F1 through the corresponding second fan-out line F2, and the first end of the second switch 122 is electrically connected to the corresponding second data line DA2 through the corresponding second fan-out line F2. When there is out-of-order in the second fan-out line F2, the switches electrically connected to the same column of pixel units 110 can include the first switch 121 and / or the second switch 122. At this time, the second end of the first switch 121 and / or the second switch 122 electrically connected to the same column of pixel units 110 can be electrically connected to the same test signal line TES, and the second end of the switches electrically connected to adjacent two columns of pixel units 110 can be electrically connected to different test signal lines TES. When detecting the display panel, different test signals can be provided to different test signal lines TES, so that the test signals obtained by adjacent two columns of pixel units 110 are different. When the display panel is normal, a detection picture in which the pixel units 110 in every x columns are lit up can be realized, for example, the detection picture is a white picture. When the display panel is abnormal, the display panel cannot realize the detection picture in which the pixel units 110 in every x columns are lit up, so that whether the display panel is abnormal can be judged according to the detection picture, and the bad detection of the display panel is realized. For example, the at least two second fan-out lines F2 electrically connected to the same column of pixel units 110 are arranged in different layers, and the at least two second fan-out lines F2 electrically connected to different columns of pixel units 110 are arranged in the same layer and there is no second fan-out line F2 in the same layer between them. When the second fan-out lines F2 in the same layer are short-circuited, the display panel cannot realize the detection picture in which the pixel units 110 in every x columns are lit up, for example, adjacent two columns of pixel units 110 are lit up at the same time, and the brightness of at least two columns of pixel units 110 is between the maximum brightness and off, so that the bad detection of the display panel is realized.

[0077] Optionally, the number of sub-pixels in each pixel unit in the same column of pixel units 110 is equal. Optionally, the number of sub-pixels in each pixel unit in different columns of pixel units 110 is equal or unequal. For example, referring to FIG. 1, the number of sub-pixels in each pixel unit in the same column of pixel units 110 is equal. Figure 3When the pixel unit 110 includes two sub-pixels P and different sub-pixels P are arranged in different columns, the display panel can include 4 first data lines DA1 and 8 second data lines DA2, and the connection relationship with the second fan-out line F2 is as shown in FIG. 7B. Figure 3The two sub-pixels P in the first column of pixel units 110 can correspond to the connection of the first first data line DA11 and the second first data line DA12, the two sub-pixels P in the second column of pixel units 110 can correspond to the connection of the third first data line DA13 and the fourth first data line DA14, the two sub-pixels P in the third column of pixel units 110 can correspond to the connection of the first second data line DA21 and the second second data line DA22, the two sub-pixels P in the fourth column of pixel units 110 can correspond to the connection of the third second data line DA23 and the fourth second data line DA24, the two sub-pixels P in the fifth column of pixel units 110 can correspond to the connection of the fifth second data line DA25 and the sixth second data line DA26, and the two sub-pixels P in the sixth column of pixel units 110 can correspond to the connection of the seventh second data line DA27 and the eighth second data line DA28. When the test signal line TES includes two, according to the corresponding relationship between the data line and the second fan-out line F2, it can be determined that the second end of the switch corresponding to the first column of pixel units 110, the third column of pixel units 110, the fifth column of pixel units 110 and the seventh column of pixel units 110 is electrically connected to one test signal line TES, and the second end of the switch corresponding to the second column of pixel units 110, the fourth column of pixel units 110, the sixth column of pixel units 110 and the eighth column of pixel units 110 is electrically connected to the other test signal line TES, so that the sub-pixels P in the adjacent column of pixel units 110 can obtain different test signals. When the display panel is normal, the detection picture of the pixel units 110 can be realized. For example, the detection picture can be that one column of pixel units 110 is lit up and the other column of pixel units 110 is not lit up, that is, it is extinguished. Alternatively, the light emitted by the multiple sub-pixels in each pixel unit that is lit up can be mixed into white light, and the detection picture can be a white picture. At the same time, the two second fan-out lines F2 corresponding to the same column of pixel units 110 can be arranged in different layers, two second fan-out lines F2 corresponding to the adjacent two columns of pixel units 110 can be arranged in the same layer, and the other two second fan-out lines F2 can be arranged in the same layer. For example, the two second fan-out lines F2 corresponding to the first column of pixel units 110 are arranged in two layers of conductive layers, the first second fan-out line F2 corresponding to the second column of pixel units 110 and the first second fan-out line F2 corresponding to the first column of pixel units 110 are arranged in the same layer of conductive layer, and the second second fan-out line F2 corresponding to the second column of pixel units 110 and the second second fan-out line F2 corresponding to the first column of pixel units 110 are arranged in the same layer of conductive layer. When the second fan-out lines F2 in the same layer are short-circuited, the display panel cannot realize the detection picture of the adjacent two columns of pixel units 110 lit up in the alternate columns, so that whether the display panel is abnormal can be judged according to the detection picture, and the short-circuit detection of the display panel is realized.

[0078] The technical scheme of the embodiment is characterized in that the first end of the first switch in the test circuit unit is electrically connected to the corresponding second fan-out line and the corresponding first fan-out line; the first end of the second switch is electrically connected to the corresponding second fan-out line and the corresponding second data line; the second ends of the switches corresponding to the same column of pixel units are electrically connected to the same test signal line; and the second ends of the switches corresponding to adjacent two columns of pixel units are electrically connected to different test signal lines. When the display panel is detected, different test signals can be provided to different test signal lines, so that the test signals obtained by adjacent two columns of pixel units are different. When the display panel is normal, a detection picture in which the pixel units are lit at intervals of at least one column can be realized. When the display panel is abnormal, the display panel cannot realize the detection picture in which the pixel units are lit at intervals of at least one column, so that whether the display panel is abnormal can be determined according to the detection picture, and the bad detection of the display panel is realized.

[0079] With reference to Figure 3 , the at least two test signal lines TES include a first test signal line TES1 and a second test signal line TES2, the second ends of the switches corresponding to the odd column of pixel units 110 are electrically connected to the first test signal line TES1, and the second ends of the switches corresponding to the even column of pixel units 110 are electrically connected to the second test signal line TES2.

[0080] When the display panel is detected, the first test signal line TES1 and the second test signal line TES2 can be used to input a lighting voltage and a darkening voltage respectively. When the display panel is normal, a detection picture in which adjacent two columns of pixel units 110 are lit at intervals of one column can be realized. When the display panel is abnormal, the display panel cannot realize the detection picture in which adjacent two columns of pixel units 110 are lit at intervals of one column, so that whether the display panel is abnormal can be determined according to the detection picture, and the bad detection of the display panel is realized.

[0081] Exemplarily, when the pixel unit 110 includes two sub-pixels P located in the same row and adjacent, and different sub-pixels P are arranged in different columns, the display panel can include two layers of conductive layers, and the second fan-out lines F2 can be alternately arranged in different layers in the two layers of conductive layers from left to right along the row direction X. At this time, the two second fan-out lines F2 corresponding to the pixel units 110 in the same column are arranged in different layers, and two of the four second fan-out lines corresponding to the pixel units 110 in adjacent two columns can be arranged in the same layer, and the other two second fan-out lines F2 can be arranged in the same layer. For example, the first second fan-out line F2 corresponding to the pixel unit 110 in an odd column and the first second fan-out line F2 corresponding to the pixel unit 110 in an even column are arranged in the same layer and are close to each other, for example, there is no other second fan-out line arranged in the same layer between them, and there is only one second fan-out line arranged in different layers between them. In the detection process of the display panel, the first test signal line TES1 can input the lighting voltage, and the second test signal line TES2 can input the extinguishing voltage. When the second fan-out lines F2 in the same layer are short-circuited, the pixel units 110 in the odd column and the even column input the lighting voltage or the extinguishing voltage, so that the display panel cannot realize the detection picture of the adjacent two columns of pixel units 110 in the column. Thus, whether the display panel is abnormal can be judged according to the detection picture, and the detection of the display panel is realized.

[0082] Figure 4 Another partial enlarged structure schematic view of a display panel provided by an embodiment of the present application is provided. As shown in Figure 3 The display panel further includes a control signal line CTRL, and the control end of the first switch 121 and the control end of the second switch 122 are electrically connected with the control signal line CTRL.

[0083] Specifically, the same control signal line CTRL can provide control signals for the first switch 121 and the second switch 122. When the display panel is not detected, the control signal provided by the control signal line CTRL can control the first switch 121 and the second switch 122 to be turned off. When the display panel is detected, the control signal provided by the control signal line CTRL can control the first switch 121 and the second switch 122 to be turned on, so that the test signals provided by the test signal lines TES connected with the second ends of the first switch 121 and the second switch 122 are respectively output to the pixel units 110 corresponding to the first switch 121 and the second switch 122, so as to realize the detection of the display panel.

[0084] Continuing to refer to Figure 4In an embodiment, the first switch 121 comprises a first transistor S1, a first electrode of the first transistor S1 is used as a first terminal of the first switch 121, a second electrode of the first transistor S1 is used as a second terminal of the first switch 121, and a control electrode of the first transistor S1 is used as a control terminal of the first switch 121; and / or, the second switch 122 comprises a second transistor S2, a first electrode of the second transistor S2 is used as a first terminal of the second switch 122, a second electrode of the second transistor S2 is used as a second terminal of the second switch 122, and a control electrode of the second transistor S2 is used as a control terminal of the second switch 122.

[0085] Specifically, Figure 4 It is exemplarily shown in FIG. 1 that the first switch 121 comprises the first transistor S1, and the second switch 122 comprises the second transistor S2. The channel types of the first transistor S1 and the second transistor S2 can be the same. It should be noted that, Figure 4 It is exemplarily shown that the first transistor S1 and the second transistor S2 are N-type transistors. In other embodiments, the first transistor S1 and the second transistor S2 can also be P-type transistors. In the detection process of the display panel, the timing of the control signal can be adaptively adjusted, which is not limited here.

[0086] Exemplarily, the first transistor S1 and the second transistor S2 can be P-type transistors. When the display panel is not detected, the control signal provided by the control signal line CTRL can be high, for example, 8.5V, at this time, the first transistor S1 and the second transistor S2 are in the off state. When the display panel is detected, the control signal provided by the control signal line CTRL can be low, for example, -7.5V, the first transistor S1 and the second transistor S2 are in the on state, the voltage provided by the first test signal line TES1 is the lighting voltage, for example, 4V, and the voltage provided by the second test signal line TES2 is the extinguishing voltage, for example, 7.5V. So that the pixel unit 110 corresponding to the transistor connected with the first test signal line TES1 is lit, and the pixel unit 110 corresponding to the transistor connected with the second test signal line TES2 is extinguished. When the display panel is normal, the detection picture of the pixel unit 110 can be realized. When the display panel is abnormal, the display panel cannot realize the detection picture of the pixel unit 110 in the adjacent two columns, so that whether the display panel is abnormal can be judged according to the detection picture, and the bad detection of the display panel can be realized.

[0087] On the basis of each of the above technical solutions, the arrangement order of the plurality of second fan-out lines F2 along the row direction X is different from the arrangement order of the data lines DA to which the second fan-out lines F2 correspond.

[0088] Specifically, the arrangement order of the data lines DA along the positive direction of the row direction X is the overall arrangement order of the first data line DA1 and the second data line DA2 along the row direction X. When the arrangement order of the plurality of second fan-out lines F2 along the positive direction of the row direction X is different from the arrangement order of the data lines DA to which the second fan-out lines F2 correspond to be electrically connected, the second fan-out lines F2 have a disorder phenomenon. When the display area AA has a rounded corner area on both sides of one end close to the test circuit unit 120, the second fan-out line F2 corresponding to the pixel unit 110 of the column of the rounded corner area can be moved to the middle area, and then connected to the data line DA corresponding to the pixel unit 110 through the first fan-out line F1, so that the second fan-out line F2 can be avoided to be arranged in the rounded corner area, and the width of the non-display area NAA can be reduced.

[0089] In other embodiments, optionally, the first end of the first fan-out line F1 electrically connected to the second fan-out line F2 is closer to the second data line DA2 in the middle of the display area AA than the second end of the first fan-out line F1 electrically connected to the first data line DA1.

[0090] In this way, compared with connecting all the data lines DA to the driving chip in the binding area through the fan-out lines in the non-display area NAA, the first data line DA1 at the edge of the display area AA is led out from the middle of the display area AA through the first fan-out line F1, which can reduce the occupied space of the fan-out lines in the non-display area NAA, and is beneficial to realize a narrow frame. For example, the first first data line DA11 is connected to the fourth first fan-out line F1, and the fourth first fan-out line F1 is connected to the tenth second fan-out line F2 in correspondence. The first end A of the fourth first fan-out line F1 electrically connected to the tenth second fan-out line F2 is closer to the second data line DA2 in the middle of the display area AA than the second end B of the fourth first fan-out line F1 electrically connected to the first first data line DA11, which can make the second fan-out line F2 corresponding to the first first data line DA11 closer to the middle area of the non-display area NAA, so that the width of the non-display area NAA can be reduced.

[0091] In other embodiments, optionally, a plurality of second fan-out lines F2 can also be arranged along the row direction X. Optionally, the outermost second fan-out line F2 is electrically connected to the first end of the first switch 121. Optionally, the outermost second fan-out line F2 is electrically connected to the first end of the second switch 122.

[0092] Figure 5 Another partial enlarged structure schematic diagram of a display panel is provided for the embodiments of the present application. As shown in Figure 5 The first fan-out line F1 includes the first connection line F11 and the second connection line F12 electrically connected, and the second connection line F12 is electrically connected to the corresponding first data line DA1 through the first connection line F11. The plurality of second connection lines F12 extend along the column direction Y and are arranged along the row direction X.

[0093] Optionally, among the plurality of second connection lines F12 electrically connected to the same test circuit unit 120, N data lines DA are arranged between any two adjacent second connection lines F12; wherein N is an integer greater than or equal to 2. That is, among the plurality of second connection lines F12 electrically connected to the same test circuit unit 120, every N data lines DA is inserted with one second connection line F12. Optionally, among the plurality of second connection lines F12 electrically connected to the same test circuit unit 120, the N data lines DA between any two adjacent second connection lines F12 are N second data lines DA2. The N second data lines DA2 arranged between any two adjacent second connection lines F12 are electrically connected to the same column of pixel units. Among the 2N second data lines DA2 arranged between any three adjacent second connection lines F12, N data lines DA and another N data lines DA are electrically connected to different columns of pixel units, for example, two adjacent columns of pixel units. The plurality of second connection lines F12 electrically connected to the same test circuit unit 120 are electrically connected to the same column of pixel units or at least two adjacent columns of pixel units.

[0094] Optionally, any pixel unit 110 includes M sub-pixels P, or any pixel unit 110 is electrically connected to M data lines DA, wherein M is an integer greater than or equal to 2; any test circuit unit 120 includes K*M first switches 121 and N*K*M second switches 122, K is an integer greater than or equal to 1.

[0095] Specifically, the extension direction of the first connection line F11 intersects with the extension direction of the second connection line F12, so that the first fan-out line F1 has a projection along the row direction X. For example, as shown in FIG. 1, the extension direction of the first connection line F11 is perpendicular to the extension direction of the second connection line F12, so that the first fan-out line F1 has a projection along the row direction X. Figure 5As shown, the first connecting line F11 can extend along the row direction X. Optionally, pixel unit 110 includes M sub-pixels P located in different columns. Optionally, the M sub-pixels P in pixel unit 110 are arranged along the row direction X and electrically connected to M data lines DA respectively. Alternatively, pixel unit 110 includes at least two sub-pixels P, and the at least two sub-pixels P are arranged in M ​​columns, in which case pixel unit 110 is electrically connected to M data lines DA. The second connecting line F12 corresponding to the same test circuit unit 120 can include K*M lines, which are respectively connected to the data lines DA corresponding to K pixel units 110. In this case, the data lines DA corresponding to K pixel units 110 can be the first data lines DA1. The second connecting line F12 is inserted between different second data lines DA2, so that N second data lines DA2 can be set between two adjacent second connecting lines F12. When the number of second connection lines F12 corresponding to the same test circuit unit 120 is K*M, K*M*(N+1) second fan-out lines F2 can be correspondingly set for the same test circuit unit 120, respectively used to provide test signals for the corresponding second connection line F12 and the data line DA between the corresponding second connection lines F12. Simultaneously, any test circuit unit 120 may include K*M first switches 121 and N*K*M second switches 122. The K*M first switches 121 are electrically connected to the first fan-out line F1 through the second fan-out line F2, thereby providing test signals for the first data line DA1 corresponding to the first fan-out line F1. The number and arrangement of the first switches 121 and second switches 122 in each test circuit unit 120 are the same or similar, equivalent to a test circuit repetition unit. Simultaneously, the N*K*M second switches 122 are electrically connected to the second data line DA2 through the second fan-out line F2, thereby providing test signals for the second data line DA2 corresponding to the second fan-out line F2. When the second terminal of the switch corresponding to the same column of pixel units 110 is electrically connected to the same test signal line TES, and the second terminals of the switches corresponding to adjacent columns of pixel units 110 are electrically connected to different test signal lines TES, different test signals can be provided to different test signal lines TES during the display panel detection process. This results in different test signals acquired by adjacent columns of pixel units 110. When the display panel is normal, a detection screen with pixel units 110 lit at intervals of x columns can be achieved. Where the display panel includes p test signal lines TES, x is an integer greater than or equal to 1 and less than or equal to p-1. When the display panel is abnormal, it cannot achieve the detection screen with pixel units 110 lit at intervals of x columns. Therefore, the detection screen can be used to determine whether the display panel is abnormal, thus achieving display panel detection.

[0096] Exemplarily, when M is 2, N is 2, and K is 2, each pixel unit 110 is electrically connected with 2 data lines DA, and 2 data lines DA are arranged between two adjacent second connection lines F12. The pixel repeating unit 10 includes 2 pixel units 110. At this time, the same test circuit unit 120 can be correspondingly provided with 1 first fan-out line F14, i.e., the number of second connection lines F12 is 4, and 12 second fan-out lines F2 are correspondingly provided. Meanwhile, the test circuit unit 120 can include 4 first switches 121 and 8 second switches 122, the 4 first switches 121 are respectively electrically connected with the first fan-out line F1 through a second fan-out line F2, so as to provide a test signal for the first data line DA1 corresponding to the first fan-out line F1. Meanwhile, the 8 second switches 122 are respectively electrically connected with the second data line DA2 through the second fan-out line F2, so as to provide a test signal for the second data line DA2 corresponding to the second fan-out line F2. When the test signal line TES includes two, the second ends of the switches corresponding to the pixel units 110 in the same column are electrically connected to the same test signal line TES; the second ends of the switches corresponding to the pixel units 110 in the adjacent two columns are electrically connected to different test signal lines TES. In the detection process of the display panel, different test signals can be provided for different test signal lines TES, so that the test signals obtained by the adjacent two columns of pixel units 110 are different. When the display panel is normal, the detection picture of the pixel units 110 in the column can be realized. When the display panel is abnormal, the display panel cannot realize the detection picture of the pixel units 110 in the column, so that whether the display panel is abnormal can be judged according to the detection picture, and the bad detection of the display panel can be realized.

[0097] With reference to Figure 5 , the plurality of pixel units 110 are divided into at least two pixel repeating units 10, and any pixel repeating unit 10 includes K pixel units 110. Optionally, when K is an integer greater than or equal to 2, any pixel repeating unit 10 can include K pixel units 110 arranged along the row direction X and adjacent to each other. The K pixel units 110 in the same row and adjacent to each other can be regarded as a pixel repeating unit 10.

[0098] Specifically, the pixel repeating unit 10 can be an integer multiple of the pixel units 110 included when the pixel arrangement is repeated, i.e., the pixel repeating unit 10 includes K pixel units 110, and K is an integer greater than or equal to 1. Exemplarily, when the pixel arrangement of the display panel is in the RGBG arrangement mode, along the row direction X, 2 pixel units 110 form a pixel repeating unit.

[0099] On the basis of the above technical solutions, with reference to Figure 5Optionally, the first connection lines F11 extend along the row direction X; and among the plurality of first connection lines F11 arranged along the column direction Y, the longer the first connection line F11, the closer the first data line DA1 to be electrically connected to the frame of the display panel, and the longer the second connection line F12 to be electrically connected.

[0100] Optionally, the display area of the display panel can be a rounded rectangle. The shorter the first data line DA1 closer to the frame of the display panel, the longer the first connection line F11 and the second connection line F12 connected, which is conducive to reducing the line impedance difference. In this way, the intersection of the first connection line F11 and the non-electrically connected second connection line F12 can be avoided, which is conducive to simplifying the arrangement of the first fan-out line F1.

[0101] With reference to Figure 5 The plurality of second fan-out lines F2 include at least two third fan-out lines F21 and at least two fourth fan-out lines F22; the third fan-out line F21 is electrically connected to the first end of the first switch 121; and the fourth fan-out line F22 is electrically connected to the first end of the second switch 122.

[0102] Specifically, the at least two third fan-out lines F21 can be electrically connected to the first data line DA1 through the first fan-out line F1 respectively, and at the same time, the third fan-out line F21 is electrically connected to the first end of the first switch 121, so that the first switch 121 provides a detection signal for the first data line DA1 through the third fan-out line F21 and the first fan-out line F1 when it is turned on. The at least two fourth fan-out lines F22 can be electrically connected to the second data line DA2 respectively, and at the same time, the fourth fan-out line F22 is electrically connected to the first end of the second switch 122, so that the second switch 122 provides a detection signal for the second data line DA2 through the fourth fan-out line F22 when it is turned on. When the display panel adopts the FIAA structure, along the row direction X, the arrangement order of the third fan-out line F21 is different from the arrangement order of the first data line DA1 to be electrically connected. In this case, the reverse sequence channel of the driving chip can be used to provide a driving signal for the third fan-out line F21. At the same time, the driving chip can also include a forward sequence channel, which can provide a driving signal for the fourth fan-out line F22.

[0103] With reference to Figure 5 The plurality of second fan-out lines F2 are arranged along the row direction X; and the arrangement order of the third fan-out line F21 is opposite to the arrangement order of the first data line DA1 to be electrically connected. In this way, the corresponding connection relationship between the third fan-out line F21 and the first data line DA1 is simplified

[0104] Optionally, the arrangement order of the fourth fan-out line F22 is the same as the arrangement order of the second data line DA2 to be electrically connected. In this way, the corresponding connection relationship between the fourth fan-out line F22 and the second data line DA2 is simplified.

[0105] On the basis of each of the technical solutions described above, in the plurality of second fan-out lines F2 electrically connected to the same test circuit unit 120, N fourth fan-out lines F22 are arranged between two adjacent third fan-out lines F21. That is, a third fan-out line F21 is inserted between every fourth fan-out line F22.

[0106] Optionally, in the plurality of second fan-out lines F2 electrically connected to the same test circuit unit 120, the N fourth fan-out lines F22 arranged between two adjacent third fan-out lines F21 are electrically connected to the same column of pixel units 110; of the 2N fourth fan-out lines F22 arranged between three adjacent third fan-out lines F21, N fourth fan-out lines F22 and another N fourth fan-out lines F22 are electrically connected to different columns of pixel units 110, for example, two adjacent columns of pixel units; and / or, in each test circuit unit 120, the plurality of first switches 121 and the plurality of second switches 122 are arranged along the row direction X; N second switches 122 are arranged between two adjacent first switches 121.

[0107] Specifically, the number of third fan-out lines F21 is equal to the number of second connection lines F12, and each third fan-out line F21 is electrically connected to a corresponding second connection line F12. When the second connection lines F12 corresponding to the same test circuit unit 120 include K*M, and each second connection line F12 is connected to a first data line DA1 corresponding to K pixel units 110, the third fan-out line F21 is electrically connected to the corresponding K pixel units 110. The fourth fan-out line F22 is electrically connected to the second data line DA2 and is electrically connected to the corresponding K*N pixel units 110. When N fourth fan-out lines F22 are arranged between two adjacent third fan-out lines F21, the repeating units of the third fan-out line F21 and the fourth fan-out line F22 have K*M*(N+1) second fan-out lines F2 in total.

[0108] When N data lines DA are arranged between two adjacent second connection lines F12, N fourth fan-out lines F22 can be arranged between two adjacent third fan-out lines F21, so that the third fan-out lines F21 can be connected with the corresponding second connection lines F12, and the N fourth fan-out lines F22 between the two adjacent third fan-out lines F21 are correspondingly electrically connected to the same column of pixel units 110, so that the N fourth fan-out lines F22 between the two adjacent third fan-out lines F21 can be correspondingly connected with the N data lines DA between the corresponding two adjacent second connection lines F12, and the wiring arrangement of the non-display area NAA can be simplified. Meanwhile, the N fourth fan-out lines F22 arranged between the two adjacent third fan-out lines F21 are correspondingly electrically connected to the same column of pixel units 110, and among the 2N fourth fan-out lines F22 arranged between three adjacent third fan-out lines F21, N fourth fan-out lines F22 and another N fourth fan-out lines F22 are correspondingly electrically connected to different columns of pixel units 110, so that K*M*(N+1) second fan-out lines F2 can be electrically connected with K pixel units 110 in the same pixel repeating unit 10, thereby the pixel units 110 in the plurality of pixel repeating units 10 can be electrically connected with the switch in the test circuit unit 120, for realizing the bad detection of the display panel.

[0109] Optionally, N is an integer multiple of M. N can be greater than or equal to M. Wherein, the larger N is, the more the number of second fan-out lines corresponding to one test circuit unit 120 is. As a circuit repeating unit, the more the number of second fan-out lines corresponding to the test circuit unit 120 is, the higher the labor cost and the lower the efficiency required for the sorting inspection of the third fan-out lines and the fourth fan-out lines. The larger N is, the number of first data lines will be reduced, which is not conducive to reducing the frame. The larger N is, the more conducive to improving the short circuit detection probability.

[0110] In addition, in other embodiments, a plurality of first switches 121 and a plurality of second switches 122 can be arranged in the row direction X in each test circuit unit 120; N second switches 122 are arranged between two adjacent first switches 121, so that the first switch 121 can be sequentially electrically connected with the corresponding third fan-out line F21, and the second switch 122 can be sequentially electrically connected with the corresponding fourth fan-out line F22, thereby the wiring design of the non-display area NAA can be further simplified.

[0111] On the basis of the above technical solutions, optionally, in each test circuit unit 120, the second ends of the N second switches 122 between two adjacent first switches 121 are electrically connected to the same test signal line TES; among the 2N second switches 122 between three adjacent first switches 121, the second ends of the N second switches 122 and the second ends of the other N second switches 122 are electrically connected to different test signal lines TES.

[0112] Specifically, when the second ends of the N second switches 122 located between two adjacent first switches 121 are electrically connected to the same test signal line TES, the second ends of the switches corresponding to the same column of pixel units 110 can be electrically connected to the same test signal line TES when the N second switches 122 located between two adjacent first switches 121 are electrically connected to the same column of pixel units 110. In the 2N second switches 122 between three adjacent first switches 121, the second ends of N second switches 122 and the second ends of another N second switches 122 are electrically connected to different test signal lines TES, which can be arranged in 2N fourth fan-out lines F22 between three adjacent third fan-out lines F21. When N fourth fan-out lines F22 and another N fourth fan-out lines F22 are electrically connected to different columns of pixel units 110, the second ends of the switches corresponding to two adjacent columns of pixel units 110 are electrically connected to different test signal lines TES, so that the detection of the display panel in the column direction Y can be realized.

[0113] On the basis of the above technical solutions, the plurality of first switches in each test circuit unit are electrically connected to one column of pixel units or at least two adjacent columns of pixel units; and the plurality of second switches in each test circuit unit are electrically connected to a plurality of adjacent columns of pixel units.

[0114] Specifically, the test circuit unit includes K*M first switches and N*K*M second switches. When K is 1, the test circuit unit can include M first switches and N*M second switches, and at this time, the M first switches can be electrically connected to one column of pixel units, and the N*M second switches can be electrically connected to N adjacent columns of pixel units. When K is greater than 1, the test circuit unit can include K*M first switches and K*N*M second switches, and at this time, the K*M first switches can be electrically connected to K adjacent columns of pixel units, and the K*N*M second switches can be electrically connected to K*N adjacent columns of pixel units. At the same time, N data lines are arranged between two adjacent second connection lines F12, so that the pixel units corresponding to the first switches 121 are arranged adjacent to each other, and the pixel units corresponding to the second switches are arranged adjacent to each other. At this time, the test circuit unit can be electrically connected to at least part of K*(N+1) adjacent columns of pixel units, and when the arrangement order of the second fan-out line and the corresponding data line is different, it is beneficial to simplify the line arrangement between the test circuit and the corresponding pixel units.

[0115] Optionally, M is equal to N.

[0116] Specifically, when the pixel unit is electrically connected with the M data lines, the second connection line corresponding to the same test circuit unit 120 can be provided with K*M lines, which are used to be electrically connected with the data lines corresponding to the K columns of pixel units. Meanwhile, M data lines can be arranged between the adjacent two second connection lines, so that the data lines between the adjacent two second connection lines can be electrically connected with the pixel units in the same column. When the arrangement order of the second fan-out line and the corresponding electrically connected data line is different, it is beneficial to simplify the wiring design of the data line and the corresponding electrically connected second fan-out line.

[0117] Figure 6 Another partial enlarged structure schematic diagram of the display panel is provided for the embodiment of the present application. As shown in the figure, Figure 6 The display panel further includes N+1 rows of pads 130 located in the non-display area NAA. Each row of pads 130 includes a plurality of pads 130 arranged along the row direction X. One row of pads 130 is electrically connected with the third fan-out line F21 electrically connected with the first switch 121, and the arrangement order of the pads 130 is opposite to that of the corresponding electrically connected data line DA. The remaining N rows of pads 130 are electrically connected with the fourth fan-out line F22 electrically connected with the second switch 122, and the arrangement order of the pads 130 is the same as that of the corresponding electrically connected data line DA.

[0118] Specifically, the pads 130 are arranged in the non-display area NAA, used to receive the externally input driving signal, and transmit the driving signal to the data line DA through the first fan-out line F1 and the second fan-out line F2, used to provide the driving signal for the pixel unit 110 electrically connected with the data line DA, and realize the driving of the display panel. The arrangement order of the pads 130 can be arranged according to the port order of the driving chip providing the driving signal. For example, when the arrangement order of the ports of the driving chip corresponding to one row of pads 130 is in normal order, the arrangement order of the pads 130 is in normal order, and the arrangement order of the pads 130 is the same as that of the corresponding electrically connected data line DA. When the arrangement order of the ports of the driving chip corresponding to one row of pads 130 is in reverse order, the arrangement order of the pads 130 is in reverse order, and the arrangement order of the pads 130 is opposite to that of the corresponding electrically connected data line DA. For example, along the row direction X, the order number of the odd ports of one row of normal order ports can be increased by 361-363-365-367…, and the order number of the even ports of the other row of normal order ports can be increased by 362-364-366-368…. At this time, the pads corresponding to the two rows of normal order ports are arranged in normal order. The order number of the reverse order ports is decreased by 360-359-358-357…, and at this time, the pads corresponding to the reverse order ports are arranged in reverse order, and the order number of the pads 130 can be consistent with the data number of the ports.

[0119] The arrangement order of the third fan-out line F21 is opposite to the arrangement order of the first data line DA1 corresponding to the electrical connection, and the third fan-out line F21 is electrically connected to the first end of the first switch 121. At this time, a row of pads 130 is electrically connected to the third fan-out line F21 electrically connected to the first switch 121, and is opposite to the arrangement order of the data line DA corresponding to the electrical connection, so that the row of pads 130 has the same arrangement order as the third fan-out line F21, which is beneficial to simplify the connection between the pads 130 and the third fan-out line F21, and can simplify the port arrangement of the driving chip for providing the driving signal. Similarly, the arrangement order of the fourth fan-out line F22 is the same as the arrangement order of the second data line DA2 corresponding to the electrical connection, and the fourth fan-out line F22 is electrically connected to the first end of the second switch 121. At this time, N rows of pads 130 are electrically connected to the fourth fan-out line F22 electrically connected to the second switch 122, and have the same arrangement order as the data line DA corresponding to the electrical connection, so that the N rows of pads 130 have the same arrangement order as the fourth fan-out line F22, which is beneficial to simplify the connection between the pads 130 and the fourth fan-out line F22, and can simplify the port arrangement of the driving chip for providing the driving signal.

[0120] Exemplarily, Figure 7 A structure schematic diagram of a pad is provided for an embodiment of the present application, Figure 8 A partial enlarged structure schematic diagram of another display panel is provided for an embodiment of the present application. As Figure 7 and Figure 8 shown, when N is 2, the adjacent two second connection lines F12 are spaced by 2 second data lines DA2. At this time, the display panel is provided with 3 rows of pads 130, one of which is a reverse sequence pad, and the other two are normal sequence pads. For example, as Figure 8 shown, the sequence numbers of the reverse sequence pads decrease by 360-359-358-357..., one of the normal sequence pads has odd-numbered ports which can increase by 361-363-365-367..., and the other normal sequence pad has even-numbered ports which can increase by 362-364-366-368.... Each row exemplarily shows 4 pads 130, the reverse sequence pads can be electrically connected to the third fan-out line F21 electrically connected to the first switch 121 in sequence, so that the sequence numbers of the reverse sequence pads are opposite to the arrangement order of the data line DA corresponding to the electrical connection, to match the port arrangement of the driving chip, so that the driving chip can provide driving signals to the data lines electrically connected to the third fan-out line F21. At the same time, the normal sequence pads can be electrically connected to the fourth fan-out line F22 electrically connected to the second switch 122 in sequence, so that the sequence numbers of the normal sequence pads are the same as the arrangement order of the data line DA corresponding to the electrical connection, to match the port arrangement of the driving chip, so that the driving chip can provide driving signals to the data lines electrically connected to the fourth fan-out line F22, to realize the display of the display panel.

[0121] Continue to refer to Figures 2 to 6 Based on the above technical solutions, when N is 2, M is 2, and K is 2, each pixel unit 110 is electrically connected to two data lines DA, and two data lines DA are set between two adjacent second connection lines F12. The pixel repeating unit 10 includes two adjacent pixel units 110 in the same row. The test circuit unit 120 may include four first switches 121 and eight second switches 122. At the same time, four first fan-out lines F1 and twelve second fan-out lines F2 may be set correspondingly with the same test circuit unit 120. The six columns of pixel units 10 electrically connected to the twelve second fan-out lines F2 are arranged at least partially adjacent to each other. The two columns of pixel units 10 electrically connected to the four first fan-out lines F1 are arranged adjacent to each other. The four third fan-out lines of the twelve second fan-out lines F2 are arranged adjacent to each other. The eight third fan-out lines are arranged adjacent to each other. When the second terminal of the switch corresponding to the same column of pixel units 110 is electrically connected to the same test signal line TES, and the second terminals of the switches corresponding to adjacent columns of pixel units 110 are electrically connected to different test signal lines TES, different test signals can be provided to different test signal lines TES during the display panel detection process. This results in different test signals acquired by adjacent columns of pixel units 110. When the display panel is normal, a detection screen with pixel units 110 lit at intervals of x columns can be achieved. Where the display panel includes p test signal lines TES, x is an integer greater than or equal to 1 and less than or equal to p-1. When the display panel malfunctions, the display panel cannot achieve the detection screen with pixel units 110 lit at intervals of x columns. Therefore, the display panel malfunction can be determined based on the detection screen, thus achieving defect detection of the display panel.

[0122] Exemplarily, the adjacent second fan-out lines F2 can be arranged alternately in different layers, such that two second fan-out lines F2 corresponding to the same column of pixel units 110 are arranged in different layers, two second fan-out lines F2 corresponding to two adjacent columns of pixel units 110 are arranged in the same layer, and the other two second fan-out lines F2 are arranged in the same layer. For example, the display panel includes a first conductive layer and a second conductive layer. The 3 pixel repeat units 10 corresponding to the test circuit unit 120 are arranged in the same row, and are arranged adjacently or partially not adjacently, and 1 pixel repeat unit 10 corresponding to 4 first switches 121 is located on one side of the display area AA relative to 2 pixel repeat units 10 corresponding to 8 second switches 122. The arrangement order of the second fan-out lines F2 corresponding to the first data lines DA1 is opposite, and the arrangement order of the second fan-out lines F2 corresponding to the second data lines DA2 is the same. In the same test circuit unit 120, 1 pixel repeat unit 10 corresponding to 4 first switches 121 and 2 pixel repeat units 10 corresponding to 8 second switches 122 are arranged in the same row and adjacently or not adjacently, and 2 pixel repeat units 10 corresponding to 8 second switches 122 are arranged in the same row and adjacently. Exemplarily, 1 test circuit unit 120 can correspond to 12 second fan-out lines F2 arranged in the positive direction along the row direction X, which are located in the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, and the second conductive layer, respectively. The second fan-out lines F2 corresponding to the same column of pixel units 110 are arranged in different layers. The second fan-out lines F2 corresponding to the adjacent columns of pixel units 110 are at least partially arranged in the same layer, and there is no second fan-out line in the same layer between them, which can be detected when short circuit occurs. The second fan-out lines F2 corresponding to the odd-numbered columns of pixel units 110 and the second fan-out lines F2 corresponding to the even-numbered columns of pixel units 110 are at least partially arranged in the same layer, and there is no second fan-out line in the same layer between them, which can be detected when short circuit occurs. When the second ends of the switches corresponding to the same column of pixel units 110 are electrically connected to one test signal line TES, and the second ends of the switches corresponding to two adjacent columns of pixel units 110 are electrically connected to another test signal line TES, different test signals can be provided for different test signal lines TES in the detection process of the display panel, so that the test signals obtained by the adjacent two columns of pixel units 110 are different, and the detection picture of the column-by-column lighting can be realized when the display panel is normal. When the second fan-out lines F2 in the same layer are short-circuited, the adjacent two columns or the two columns not adjacent to each other of pixel units 110 can be lit at the same time, and the brightness is between the maximum brightness and the extinguishing, and the detection picture of the column-by-column lighting of the display panel cannot be realized, thereby realizing the bad detection of the display panel.

[0123] Optionally, the plurality of pixel units 110 includes at least two first pixel units 110A and at least two second pixel units 110B, the first pixel unit 110A includes one first color sub-pixel P1 and one second color sub-pixel P2; the second pixel unit 110B includes one third color sub-pixel P3 and one second color sub-pixel P2; in the same row of pixel units 110, the first pixel unit 110A and the second pixel unit 110B are arranged alternately along the row direction X. The first pixel unit 110A includes one first color sub-pixel P1 and one second color sub-pixel P2 located in different columns; the second pixel unit 110B includes one third color sub-pixel P3 and one second color sub-pixel P2 located in different columns.

[0124] With reference to the foregoing description Figures 2 to 6 , the pixel units 110 can be divided into first pixel units 110A and second pixel units 110B according to the colors of the included sub-pixels, the first pixel unit 110A can include one first color sub-pixel P1 and one second color sub-pixel P2 arranged along the row direction X, so that the first pixel unit 110A has two columns of sub-pixels P, corresponding to the connection of 2 data lines DA. The second pixel unit 110B can include one third color sub-pixel P3 and one second color sub-pixel P2 arranged along the row direction X, so that the second pixel unit 110B also has two columns of sub-pixels P, corresponding to the connection of 2 data lines DA. In the same row of pixel units 110, the first pixel unit 110A and the second pixel unit 110B are arranged alternately along the row direction X, so that along the row direction X, the two first pixel units 110A and the second pixel units 110B in the same row and adjacent to each other are the smallest repeating units of pixel arrangement. In addition, the pixel units 110 in the adjacent two columns include the first pixel units 110A and the second pixel units 110B, that is, the pixel units 110 in the adjacent two columns simultaneously include the first color sub-pixel P1, the second color sub-pixel P2 and the third color sub-pixel P3, which is beneficial to ensure the uniformity of the mixed light of the display panel.

[0125] Optionally, in the same column of pixel units 110, the first pixel unit 110A and the second pixel unit 110B are arranged alternately along the column direction Y.

[0126] With reference to the foregoing description Figures 2 to 6In the same column of pixel units 110, the first pixel unit 110A and the second pixel unit 110B are arranged alternately along the column direction Y, so that two first pixel units 110A and two second pixel units 110B in the same row and adjacent to each other are the minimum repeating units of pixel arrangement along the column direction Y. In addition, the pixel units 110 in the adjacent two rows include the first pixel unit 110A and the second pixel unit 110B, that is, the pixel units 110 in the adjacent two rows simultaneously include the first color sub-pixel P1, the second color sub-pixel P2 and the third color sub-pixel P3, which is also conducive to ensuring the uniformity of the mixed light of the display panel.

[0127] Optionally, Figure 9 Another partial enlarged structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 6. As shown in FIG. 6, in the adjacent two columns of sub-pixels P, the first color sub-pixels P1 and the third color sub-pixels P3 in one column of sub-pixels P are arranged alternately along the column direction Y; and the other column of sub-pixels 110 all are the second color sub-pixels P2. Figure 9

[0128] Specifically, the first pixel unit 110A and the second pixel unit 110B both include the second color sub-pixel P2, and when the first pixel unit 110A and the second pixel unit 110B are arranged alternately along the column direction Y in the same column of pixel units 110, the second color sub-pixels P2 in the first pixel unit 110A and the second pixel unit 110B can be arranged in the same column, the first color sub-pixel P1 and the third color sub-pixel P3 are arranged in the same column, and the first color sub-pixel P1 and the third color sub-pixel P3 are arranged alternately along the column direction Y, which is conducive to ensuring the uniformity of the mixed light of the display panel.

[0129] For example, the first color sub-pixel P1 is a red sub-pixel, the second color sub-pixel P2 is a green sub-pixel, and the third color sub-pixel P3 is a blue sub-pixel; at this time, the pixel arrangement of the display panel is RGBG arrangement. That is, the red sub-pixels and the blue sub-pixels are arranged in the same column, and the green sub-pixels are arranged in the same column. In the adjacent two columns of sub-pixels, in one column of sub-pixels, the red sub-pixels and the blue sub-pixels are arranged alternately, and in the other column of sub-pixels, all are green sub-pixels. In the same row of sub-pixels, the red sub-pixels, the green sub-pixels, the blue sub-pixels and the green sub-pixels are arranged in sequence.

[0130] Optionally, each test circuit unit 120 includes 4 first switches 121 and 8 second switches 122, and 2 data lines DA are arranged between the adjacent two second connection lines F12; the 4 first switches 121 in each test circuit unit 120 are electrically connected to the adjacent two columns of pixel units 110; and the 8 second switches 122 in each test circuit unit 120 are electrically connected to the adjacent 4 columns of pixel units 110.

[0131] ​Specifically, when N is 2, M is 2, and K is 2, the pixel repeating unit 10 includes 2 pixel units 110, and the pixel repeating unit 10 is electrically connected to 4 data lines DA at this time. At this time, the test circuit unit 120 can be provided to include 4 first switches 121 and 8 second switches 122, and 4 first fan-out lines F1 and 12 second fan-out lines F2 are correspondingly provided. The first fan-out line F1 includes a first connection line F11 and a second connection line F12. The 4 first switches 121 are respectively electrically connected to the 4 first data lines DA1 corresponding to one pixel repeating unit 10 through the second connection line F12, and among the 8 second switches 122, adjacent two second switches 122 are respectively electrically connected to the 2 data lines DA between adjacent two second connection lines F12, and the 8 second switches 122 are electrically connected to the 8 first data lines DA1 corresponding to the 2 pixel repeating units 10 located in the same row and adjacent to each other, so that the test circuit unit 120 can be electrically connected to the 3 pixel repeating units 10 located in the same row through the first fan-out line F1 and the second fan-out line F2. The corresponding connection relationship between the 3 pixel repeating units 10 located in the same row and the test circuit unit 120 can be used as the minimum repeating unit of the corresponding connection relationship between the test circuit unit 120 and the pixel unit 110, and when the display panel includes a plurality of rows and a plurality of columns of pixel units 110, the corresponding connection relationship between all the test circuit units 120 and the pixel units 110 in the display panel can be realized according to the minimum repeating unit of the corresponding connection relationship between the test circuit unit 120 and the pixel unit 110.

[0132] Optionally, among the 4 first switches 121 in each test circuit unit 120, two first switches 121 adjacent to each other on one side are electrically connected to the same column of pixel units 110, and the other two first switches 121 adjacent to each other on the other side are electrically connected to the same column of pixel units 110. This can reduce the probability of spatial overlap between the lines between the first switch 121 and the pixel unit 110 electrically connected thereto, and is beneficial to simplify the wiring design.

[0133] Figure 10 Another partial structure schematic diagram of a display panel provided by an embodiment of the present application. Figure 11 Another partial enlarged structure schematic diagram of a display panel provided by an embodiment of the present application. Figure 10 and Figure 11As shown, N is 3, M is 3, and K is 1. Each pixel unit 110 is electrically connected to three data lines DA, and three data lines DA are arranged between two adjacent second connection lines F12. The pixel repetition unit 10 includes one pixel unit 110. The test circuit unit 120 may include three first switches 121 and nine second switches 122. The display panel includes three first fan-out lines F1 and twelve second fan-out lines F2. The three first switches 121 are each electrically connected to a first fan-out line F1 via a second fan-out line F2, thereby providing a test signal for the first data line DA1 corresponding to the first fan-out line F1. Simultaneously, the nine second switches 122 are each electrically connected to a second data line DA2 between the second fan-out line F2 and the second connection line F12, thereby providing a test signal for the second data line DA2 corresponding to the second fan-out line F2. When there are two test signal lines (TES), the second terminals of the switches electrically connected to the same column of pixel units 110 are electrically connected to the same test signal line (TES); the second terminals of the switches electrically connected to adjacent columns of pixel units 110 are electrically connected to different test signal lines (TES). During the display panel testing process, by providing different test signals to different test signal lines (TES), the test signals acquired by adjacent columns of pixel units 110 are different. When the display panel is normal, a test screen with every other column of pixel units 110 lit can be achieved. When the display panel is abnormal, the display panel cannot achieve the test screen with every other column of pixel units 110 lit, thus allowing the determination of whether the display panel is abnormal based on the test screen, achieving defect detection of the display panel.

[0134] Exemplarily, the adjacent second fan-out lines F2 can be arranged alternately in different layers. For example, the display panel includes a first conductive layer and a second conductive layer, 3 first switches 121 corresponding to 1 pixel repeating unit 10 electrically connected are located on one side (for example, the first display area) of the display area AA relative to 9 second switches 122 corresponding to 3 pixel repeating units 10 electrically connected, the arrangement order of the second fan-out lines F2 corresponding to the first data lines DA1 is opposite, and the arrangement order of the second fan-out lines F2 corresponding to the second data lines DA2 is the same. For example, 12 second fan-out lines F2 corresponding to the same test circuit unit and arranged in the positive direction of the row direction X are located on the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, and the second conductive layer, respectively. The second fan-out lines F2 corresponding to the adjacent column pixel units 110 are at least partially arranged in the same layer and are free of second fan-out lines in the same layer therebetween, and when short circuit occurs, they can be detected. For example, the second fan-out lines F2 corresponding to the odd column pixel units 110 are at least partially arranged in the same layer as the second fan-out lines F2 corresponding to the even column pixel units 110 and are free of second fan-out lines in the same layer therebetween, and when short circuit occurs, they can be detected. When the second ends of the switches corresponding to the same column pixel unit 110 are electrically connected to one test signal line TES, and the second ends of the switches corresponding to the adjacent two column pixel units 110 are electrically connected to another test signal line TES, different test signals can be provided for different test signal lines TES in the detection process of the display panel, so that the test signals obtained by the adjacent two column pixel units 110 are different, and when the display panel is normal, a detection picture of column-by-column lighting can be realized. When the second fan-out lines F2 in the same layer are short-circuited, the adjacent two column pixel units 110 can be lit at the same time, and the brightness is between the maximum brightness and off, and the detection picture of column-by-column lighting of the display panel cannot be realized, thereby realizing the bad detection of the display panel.

[0135] Alternatively, the display panel can also be provided to include the first conductive layer, the second conductive layer and the third conductive layer, the test circuit unit 120 corresponding to the 4 pixel repeating units 10 electrically connected can be arranged adjacently or partially adjacently, and the 3 first switches 121 corresponding to the 1 pixel repeating unit 10 electrically connected are located on one side (for example, the first display area) of the 9 second switches 122 corresponding to the 3 pixel repeating units 10 electrically connected in the display area AA, the arrangement order of the second fan-out line F2 corresponding to the first data line DA1 is opposite, and the arrangement order of the second fan-out line F2 corresponding to the second data line DA2 is the same. At this time, the 12 second fan-out lines F2 arranged in the positive direction of the row direction X are respectively located in the first conductive layer, the second conductive layer, the third conductive layer, the first conductive layer, the second conductive layer, the third conductive layer, the first conductive layer, the second conductive layer, the third conductive layer, the first conductive layer, the second conductive layer and the third conductive layer. The second fan-out lines F2 corresponding to the second fan-out lines F2 electrically connected by the adjacent column pixel units 110 are at least partially arranged in the same layer, and there is no second fan-out line in the same layer therebetween, and when a short circuit occurs, it can be detected. For example, the second fan-out lines F2 corresponding to the second fan-out lines F2 electrically connected by the odd column pixel units 110 are at least partially arranged in the same layer as the second fan-out lines F2 corresponding to the second fan-out lines F2 electrically connected by the even column pixel units 110, and there is no second fan-out line in the same layer therebetween, and when a short circuit occurs, it can be detected. When the second ends of the switches corresponding to the same column pixel units 110 are electrically connected to one test signal line TES; the second ends of the switches corresponding to the adjacent two column pixel units 110 are electrically connected to another test signal line TES, during the detection process of the display panel, different test signals can be provided to different test signal lines TES, so that the test signals obtained by the adjacent two column pixel units 110 are different, and when the display panel is normal, the detection picture of the column-by-column lighting can be realized. When the second fan-out lines F2 in the same layer are short-circuited, the adjacent two column pixel units 110 can be lit at the same time, and the brightness is between the maximum brightness and extinguishing, and the detection picture of the column-by-column lighting of the display panel cannot be realized, thereby realizing the bad detection of the display panel.

[0136] In addition, the display panel can be provided with 4 rows of pads 130 in the non-display area NAA, each row of pads 130 includes a plurality of pads 130 arranged in the row direction X, and one row of pads 130 is electrically connected with the third fan-out line F21 electrically connected with the first switch 121, and the arrangement order of the data line DA corresponding thereto is opposite; the remaining 3 rows of pads 130 are electrically connected with the fourth fan-out line F22 electrically connected with the second switch 122, and the arrangement order of the data line DA corresponding thereto is the same. Continue to refer to Figure 11For example, the sequence numbers of the reverse sequence pads are sequentially decreased from 180-179-178, the sequence numbers of the pads in one row of the normal sequence pads can be sequentially increased from 181-184-187, the sequence numbers of the pads in another row of the normal sequence pads can be sequentially increased from 182-185-188, and the sequence numbers of the pads in another row of the normal sequence pads can be sequentially increased from 183-186-189. In Figure 11 each row of pads 130 is exemplarily shown as three. The reverse sequence pads can be electrically connected to the third fan-out line F21 electrically connected to the first switch 121 in sequence, so that the sequence numbers of the reverse sequence pads are opposite to the arrangement sequence of the corresponding electrically connected data lines DA, to match the port arrangement of the driving chip, so that the driving chip can provide driving signals to the data lines electrically connected to the third fan-out line F21. Meanwhile, the normal sequence pads can be electrically connected to the fourth fan-out line F22 electrically connected to the second switch 122 in sequence, so that the sequence numbers of the normal sequence pads are the same as the arrangement sequence of the corresponding electrically connected data lines DA, to match the port arrangement of the driving chip, so that the driving chip can provide driving signals to the data lines electrically connected to the fourth fan-out line F22, to realize the display of the display panel.

[0137] Optionally, any pixel unit 110 includes a first color sub-pixel P1, a second color sub-pixel P2, and a third color sub-pixel P3; each row of sub-pixels P is arranged in a sequence of the first color sub-pixel P1, the second color sub-pixel P2, and the third color sub-pixel P3; and each column of sub-pixels P is the same color sub-pixel. Optionally, any pixel unit 110 includes a first color sub-pixel P1, a second color sub-pixel P2, and a third color sub-pixel P3 in different columns.

[0138] Specifically, continuing to refer to Figure 10 the pixel unit 110 includes a first color sub-pixel P1, a second color sub-pixel P2, and a third color sub-pixel P3 arranged along the row direction X, so that the pixel unit 110 has three columns of sub-pixels P, corresponding to three data lines DA. Optionally, each pixel unit 110 includes a first color sub-pixel P1, a second color sub-pixel P2, and a third color sub-pixel P3, which is conducive to ensuring the uniformity of the mixed light of the display panel. Each row of sub-pixels P is arranged in a sequence of the first color sub-pixel P1, the second color sub-pixel P2, and the third color sub-pixel P3, so that along the row direction X, one pixel unit 110 is the smallest repeating unit of pixel arrangement.

[0139] For example, the first color sub-pixel P1 is a red sub-pixel, the second color sub-pixel P2 is a green sub-pixel, and the third color sub-pixel P3 is a blue sub-pixel; at this time, the pixel arrangement of the display panel is RGB. That is, each row of sub-pixels P is arranged cyclically in the order of red sub-pixels, blue sub-pixels, and green sub-pixels, and the red sub-pixels, blue sub-pixels, and green sub-pixels are set in the same column.

[0140] Optionally, each test circuit unit 120 includes 3 first switches 121 and 9 second switches 122, and 3 data lines DA are provided between two adjacent second connection lines F12; the 3 first switches 121 in each test circuit unit 120 are electrically connected to the pixel unit 110 in the same column; the 9 second switches 122 in each test circuit unit 120 are electrically connected to the three adjacent pixel units 110.

[0141] Specifically, when N is 3, M is 3, and K is 1, the pixel repeating unit 10 includes one pixel unit 110, and the pixel repeating unit 10 is electrically connected to three data lines DA. The test circuit unit 120 can then be configured to include three first switches 121 and nine second switches 122, corresponding to three first fan-out lines F1 and twelve second fan-out lines F2. The first fan-out line F1 includes a first connecting line F11 and a second connecting line F12. The three first switches 121 are electrically connected to the three first data lines DA1 corresponding to one pixel repeating unit 10 via the second connecting lines F12. Of the nine second switches 122, three adjacent second switches 122 are electrically connected to the three data lines DA between two adjacent second connecting lines F12, thus allowing the test circuit unit 120 to be electrically connected to four pixel repeating units 10 via the first fan-out lines F1 and the second fan-out lines F2. Furthermore, the corresponding connection relationship between the four pixel repeating units 10 and the test circuit unit 120 can be used as the smallest repeating unit of the corresponding connection relationship between the test circuit unit 120 and the pixel unit 110. When the display panel includes multiple rows and columns of pixel units 110, the corresponding connection between all the test circuit units 120 and the pixel units 110 in the display panel can be realized according to the smallest repeating unit of the corresponding connection relationship between the test circuit unit 120 and the pixel unit 110.

[0142] Based on the above technical solutions, see Figure 12 At least part of the second fan-out line F2 is located in the same conductive layer. Figure 12 Can be along Figure 9 A schematic diagram of the cross-sectional structure along the C1C2 direction. Figure 12 Can be along Figure 11 A schematic diagram of the cross-sectional structure along the D1D2 direction.

[0143] Specifically, at least part of the second fan-out lines are located in the same conductive layer and electrically connected to different column pixel units, and there is no second fan-out line in the same layer between them. When the second ends of the switches corresponding to the pixel units in the same column are electrically connected to one test signal line, and the second ends of the switches corresponding to the pixel units in the adjacent column are electrically connected to another test signal line, if a short circuit occurs between the second fan-out lines located in the same conductive layer when the display panel is being tested, the display panel cannot realize the detection picture of the adjacent column pixel units being lit in the column, so that whether the display panel is abnormal can be determined according to the detection picture, and the bad detection of the display panel is realized.

[0144] Optionally, referring to Figure 11 , a plurality of second fan-out lines F2 are arranged along the row direction, and adjacent two second fan-out lines F2 are located in different conductive layers (for example, the first conductive layer 301 and the second conductive layer 302 located on the substrate 300, which can be metal layers); of the adjacent three second fan-out lines F2, the two second fan-out lines F2 located on the two sides are located in the same conductive layer. An insulating layer can be arranged between the adjacent conductive layers.

[0145] Specifically, the number of second fan-out lines is relatively large, and by arranging adjacent at least part of the second fan-out lines in different conductive layers, the spacing between the second fan-out lines can be ensured, and the arrangement of the second fan-out lines is simplified. At the same time, the adjacent two second fan-out lines are located in different conductive layers; of the adjacent three second fan-out lines, the two second fan-out lines located on the two sides are located in the same conductive layer, and can be arranged along the row direction, the second fan-out lines are alternately arranged in different conductive layers, and the spacing between the second fan-out lines can be further ensured. On the basis of each of the above technical solutions, part or all of the second fan-out lines corresponding to the pixel units in the same column can be arranged in different layers, and at least part of the second fan-out lines corresponding to the pixel units in the adjacent column can be arranged in the same layer.

[0146] On the basis of each of the above technical solutions, Figure 13 another structure diagram of a display panel is provided. As shown in Figure 13 , the display area AA includes a first display area AA1, a second display area AA2 and a third display area AA3 arranged in sequence along the row direction X, the first data line DA1 is located in the first display area AA1 and the third display area AA3, and the second data line DA2 is located in the second display area AA2.

[0147] Specifically, along the row direction X, the first display area AA1 and the third display area AA3 are located on the two sides of the display area AA, and the second display area AA2 is located in the middle part of the display area AA. The first display area AA1 and the third display area AA3 can be located on the two sides of the second display area AA2 along the row direction X. Optionally, the second connection lines F12 are all located in the second display area AA2. The second connection line F12 with a longer length can be closer to the data line at the middle position of the second display area AA2.

[0148] Optionally, the number of the first data lines DA1 corresponding to the first display area AA1 can be equal to the number of the first data lines DA1 corresponding to the third display area AA3. For example, when the first display area AA1 corresponds to 360 first data lines DA1, the third display area AA3 also corresponds to 360 first data lines DA1, and the display area AA includes 2560 data lines DA, the second display area AA2 corresponds to 1840 second data lines DA2, and the first data line DA1 corresponding to the third display area AA3 is the 2201th data line DA. For example, the data lines DA are numbered in the direction from the first display area AA1 to the second display area AA2, the sequential numbers of the data lines DA of the first display area AA1 are 1 to 360, the sequential numbers of the data lines DA of the second display area AA2 are 361 to 2200, and the sequential numbers of the data lines DA of the third display area AA3 are 2201 to 2560. The first data lines DA1 corresponding to the first display area AA1 and the first data lines DA1 corresponding to the third display area AA3 can be symmetrically arranged, with the symmetry axis parallel to the column direction. The first data lines DA1 corresponding to the first display area AA1 and the first data lines DA1 corresponding to the third display area AA3 can be symmetrically arranged, with the symmetry axis parallel to the column direction. The first data lines DA1 corresponding to the first display area AA1 and the first data lines DA1 corresponding to the third display area AA3 can be symmetrically arranged, with the symmetry axis parallel to the column direction. Optionally, the display panel can further include a third switch 140, a first end of the third switch 140 can be electrically connected to the second data line DA2 through the corresponding second fan-out line F2. A second end of the third switch 140 can be electrically connected to the corresponding test signal line. The test circuit unit 120 can be located on the two sides of the third switch 140 in the direction X. The control end of the third switch 140 can be electrically connected to the control signal line CTRL. The same column of pixel units electrically connected to the third switch 140 are electrically connected to the same test signal line. Adjacent two columns of pixel units electrically connected to the third switch 140 are electrically connected to different test signal lines through the third switch 140. For example, the odd-numbered column of pixel units 110 electrically connected to the third switch 140 are electrically connected to the first test signal line TES1 through the third switch 140; the even-numbered column of pixel units 110 electrically connected to the third switch 140 are electrically connected to the second test signal line TES2 through the third switch 140. When detecting the display panel, the first test signal line TES1 and the second test signal line TES2 can be used to input the lighting voltage and the extinguishing voltage, respectively, and when the display panel is normal, the detection picture of the adjacent two columns of pixel units 110 with column-by-column lighting can be realized.When the display panel is abnormal, the display panel cannot realize the detection picture of the adjacent two column pixel units 110 column-by-column lighting, so that whether the display panel is abnormal can be judged according to the detection picture, and the bad detection of the display panel is realized. Optionally, the third switch 140 includes a third transistor, the first electrode of the third transistor is used as the first end of the third switch 140, the second electrode of the third transistor is used as the second end of the third switch 140, and the control electrode of the third transistor is used as the control end of the third switch 140.

[0149] The embodiment of the present application also provides a display device. Figure 14 A structural schematic diagram of a display device provided by the embodiment of the present application is shown in FIG. 1. Figure 14 As shown in the figure, the display device 00 includes a driving chip 20 and the display panel 21 provided by any embodiment of the present application, and the driving chip 20 is electrically connected with the second fan-out line.

[0150] Specifically, the driving chip 20 is electrically connected with the second fan-out line, and can provide driving signals for the display panel through the second fan-out line. Exemplarily, the display panel can also include a pad located in the binding area, and the driving chip 20 can be connected with the second fan-out line through the binding connection with the pad. Since the display device 00 includes the display panel provided by any embodiment of the present application, the display device 00 has the same beneficial effects as the display panel provided by any embodiment of the present application, which will not be described here. The display device 00 can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, etc.

[0151] The embodiment of the present application also provides a test method of a display panel, which is applied to the display panel provided by any embodiment of the present application. Figure 15 A flowchart of the test method of the display panel provided by the embodiment of the present application is shown in FIG. 2. Figure 15 As shown in the figure, the test method includes step S101 and / or step S102.

[0152] S101, in a first time period, the first switch and the second switch are controlled to be turned on, the odd-numbered column pixel units are connected to the test signal line through the second end of the corresponding electrically connected switch, and the even-numbered column pixel units are connected to the test signal line through the second end of the corresponding electrically connected switch.

[0153] When the display panel is normal, when the first switch and the second switch are turned on, the lighting voltage is transmitted to the odd-numbered column pixel units through the first switch and / or the second switch, so that the odd-numbered column pixel units can be lit. When the display panel is normal, the extinguishing voltage is transmitted to the even-numbered column pixel units through the first switch and / or the second switch, so that the even-numbered column pixel units can be extinguished. When the display panel is normal, the odd-numbered column pixel units are lit, and the even-numbered column pixel units are extinguished. When the display panel is abnormal, at least one of the odd-numbered column pixel units is extinguished, and / or at least one of the even-numbered column pixel units is lit, and / or the brightness of at least two column pixel units is between the brightness of the normally lit pixel units and the extinguished state. Thus, whether the display panel is abnormal can be determined according to the light-emitting states of the odd-numbered column pixel units and the even-numbered column pixel units, and the bad detection of the display panel is realized. Optionally, the display panel can further include a third switch 140, and in the first time period, the first switch, the second switch and the third switch are controlled to be turned on.

[0154] In the second time period, the first switch and the second switch are controlled to be turned on, the test signal line electrically connected to the second end of the switch corresponding to the odd-numbered column pixel units is connected to the extinguishing voltage, and the test signal line electrically connected to the second end of the switch corresponding to the even-numbered column pixel units is connected to the lighting voltage.

[0155] When the display panel is normal, when the first switch and the second switch are turned on, the lighting voltage is transmitted to the odd-numbered column pixel units through the first switch and / or the second switch, so that the odd-numbered column pixel units can be lit. When the display panel is normal, the lighting voltage is transmitted to the even-numbered column pixel units through the first switch and / or the second switch, so that the even-numbered column pixel units can be lit. When the display panel is normal, the odd-numbered column pixel units are lit, and the even-numbered column pixel units are extinguished. When the display panel is abnormal, at least one of the odd-numbered column pixel units is lit, and / or at least one of the even-numbered column pixel units is extinguished, and / or the brightness of at least two column pixel units is between the brightness of the normally lit pixel units and the extinguished state. Thus, whether the display panel is abnormal can be determined according to the light-emitting states of the odd-numbered column pixel units and the even-numbered column pixel units, and the bad detection of the display panel is realized. Optionally, the display panel can further include a third switch 140, and in the second time period, the first switch, the second switch and the third switch are controlled to be turned on.

[0156] It should be noted that the order of the first time period and the second time period is not limited. Optionally, the first time period is before the second time period, or the first time period is after the second time period.

[0157] The technical scheme of the embodiment of the present application controls the first switch and the second switch to be turned on in the first time period, and the test signal line connected to the second end of the switch corresponding to the odd-numbered column pixel unit is connected to the lighting voltage, and the test signal line connected to the second end of the switch corresponding to the even-numbered column pixel unit is connected to the extinguishing voltage. And / or, the first switch and the second switch are controlled to be turned on in the second time period, the test signal line connected to the second end of the switch corresponding to the odd-numbered column pixel unit is connected to the extinguishing voltage, and the test signal line connected to the second end of the switch corresponding to the even-numbered column pixel unit is connected to the lighting voltage, so that the test signals obtained by the adjacent two column pixel units are different, and when the display panel is normal, the detection picture of the pixel unit column-by-column lighting can be realized. When the display panel is abnormal, the display panel cannot realize the detection picture of the pixel unit column-by-column lighting, so that whether the display panel is abnormal can be judged according to the detection picture, and the bad detection of the display panel is realized.

[0158] It should be noted that the above only describes the preferred embodiments of the present application and the applied technical principles. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the protection scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and more other equivalent embodiments can be included without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area, and the display panel further includes: Multiple pixel units arranged in an array are located in the display area; Multiple data lines are located in the display area and electrically connected to the pixel units of the corresponding columns; the multiple data lines extend along the column direction and are arranged along the row direction; the multiple data lines include at least two first data lines and at least two second data lines. Multiple first fan-out lines are located in the display area, and the first fan-out lines are electrically connected to the corresponding first data lines. Multiple second fan-out lines, multiple test circuit units, and at least two test signal lines are located in the non-display area. Each test circuit unit includes multiple first switches and multiple second switches. The first terminals of the multiple first switches are electrically connected to the corresponding first fan-out lines via the corresponding second fan-out lines. The first terminals of the multiple second switches are electrically connected to the corresponding second data lines via the corresponding second fan-out lines. The second terminals of the switches correspondingly connected to the pixel units in the same column are electrically connected to the same test signal line. The second terminals of the switches correspondingly connected to the pixel units in two adjacent columns are electrically connected to different test signal lines. The plurality of second fan outgoing lines include at least two third fan outgoing lines and at least two fourth fan outgoing lines; the third fan outgoing lines are electrically connected to the first terminal of the first switch; the fourth fan outgoing lines are electrically connected to the first terminal of the second switch; The multiple second fan-out lines are arranged along the row direction; the arrangement order of the third fan-out lines is the opposite of the arrangement order of the first data lines corresponding to the electrical connection, and the arrangement order of the fourth fan-out lines is the same as the arrangement order of the second data lines corresponding to the electrical connection; The display panel further includes N+1 rows of pads located in the non-display area. Each row of pads includes multiple pads arranged along the row direction. One row of pads is electrically connected to the third fan-out line of the first switch, and the arrangement order of the corresponding electrically connected data lines is reversed. The remaining N rows of pads are electrically connected to the fourth fan-out line of the second switch, and the arrangement order of the corresponding electrically connected data lines is the same. Wherein, N is an integer greater than or equal to 2.

2. The display panel according to claim 1, characterized in that, At least two test signal lines are included: a first test signal line and a second test signal line. The second end of the switch corresponding to the odd-numbered pixel units is electrically connected to the first test signal line, and the second end of the switch corresponding to the even-numbered pixel units is electrically connected to the second test signal line.

3. The display panel according to claim 1, characterized in that, The display panel further includes a control signal line, wherein the control terminals of the first switch and the second switch are electrically connected to the control signal line.

4. The display panel according to claim 3, characterized in that, The first switch includes a first transistor, the first electrode of the first transistor serves as the first terminal of the first switch, the second electrode of the first transistor serves as the second terminal of the first switch, and the control electrode of the first transistor serves as the control terminal of the first switch.

5. The display panel according to claim 3, characterized in that, The second switch includes a second transistor, the first electrode of the second transistor serves as the first terminal of the second switch, the second electrode of the second transistor serves as the second terminal of the second switch, and the control electrode of the second transistor serves as the control terminal of the second switch.

6. The display panel according to claim 1, characterized in that, The arrangement order of the plurality of second fan-out lines along the row direction is different from the arrangement order of the data lines electrically connected to the second fan-out lines.

7. The display panel according to claim 6, characterized in that, The first end of the first fan-out line that is electrically connected to the second fan-out line is closer to the second data line located in the middle of the display area than the second end of the first fan-out line that is electrically connected to the first data line.

8. The display panel according to claim 6, characterized in that, The multiple second fan-outgoing lines are arranged along the row direction, and the outermost second fan-outgoing line is electrically connected to the first terminal of the first switch.

9. The display panel according to claim 1, characterized in that, The first fan-out line includes a first connecting line and a second connecting line that are electrically connected. The second connecting line is electrically connected to the corresponding first data line via the first connecting line. Multiple second connecting lines extend along the column direction and are arranged along the row direction. N data lines are arranged between two adjacent second connecting lines. Any of the pixel units includes M sub-pixels, or any of the pixel units is electrically connected to M data lines, where M is an integer greater than or equal to 2; any of the test circuit units includes K*M first switches and N*K*M second switches, where K is an integer greater than or equal to 1.

10. The display panel according to claim 9, characterized in that, The plurality of pixel units are divided into at least two pixel repeating units, and any pixel repeating unit includes K pixel units.

11. The display panel according to claim 9, characterized in that, N fourth fan-out lines are arranged between two adjacent third fan-out lines; the N fourth fan-out lines arranged between two adjacent third fan-out lines are electrically connected to the same column of pixel units; among the 2N fourth fan-out lines arranged between three adjacent third fan-out lines, N fourth fan-out lines and the other N fourth fan-out lines are electrically connected to the pixel units in different columns.

12. The display panel according to claim 9, characterized in that, In each of the test circuit units, a plurality of first switches and a plurality of second switches are arranged along the row direction; N second switches are arranged between two adjacent first switches.

13. The display panel according to claim 12, characterized in that, In each of the test circuit units, the second ends of N second switches located between two adjacent first switches are electrically connected to the same test signal line; among the 2N second switches between three adjacent first switches, the second ends of N second switches are electrically connected to different test signal lines from the second ends of the other N second switches.

14. The display panel according to claim 9, characterized in that, The plurality of first switches in each of the test circuit units are electrically connected to one column of the pixel units or at least two adjacent columns of the pixel units; the plurality of second switches in each of the test circuit units are electrically connected to multiple adjacent columns of the pixel units.

15. The display panel according to claim 14, characterized in that, M equals N.

16. The display panel according to claim 9, characterized in that, N is 2, M is 2, K is 2.

17. The display panel according to claim 16, characterized in that, The plurality of pixel units include at least two first pixel units and at least two second pixel units. The first pixel unit includes a first color sub-pixel and a second color sub-pixel. The second pixel unit includes a third color sub-pixel and a second color sub-pixel. In the same row of pixel units, the first pixel units and the second pixel units are arranged alternately along the row direction.

18. The display panel according to claim 17, characterized in that, In the same column of pixel units, the first pixel unit and the second pixel unit are arranged alternately along the column direction.

19. The display panel according to claim 18, characterized in that, In two adjacent columns of sub-pixels, the first color sub-pixels and the third color sub-pixels in one column are arranged alternately along the column direction; the other column of sub-pixels consists entirely of the second color sub-pixels.

20. The display panel according to claim 19, characterized in that, The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

21. The display panel according to claim 16, characterized in that, Each of the test circuit units includes 4 first switches and 8 second switches, and 2 data lines are arranged between two adjacent second connection lines; the 4 first switches in each of the test circuit units are electrically connected to two adjacent columns of pixel units; the 8 second switches in each of the test circuit units are electrically connected to four adjacent columns of pixel units. In each of the four first switches in the test circuit unit, two first switches located on one side are electrically connected to the same column of pixel units, and the other two first switches located on the other side are electrically connected to the same column of pixel units.

22. The display panel according to claim 9, characterized in that, N is 3, M is 3, and K is 1.

23. The display panel according to claim 22, characterized in that, Each pixel unit includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; the sub-pixels in each row are arranged cyclically in the order of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel; and the sub-pixels in each column are sub-pixels of the same color.

24. The display panel according to claim 23, characterized in that, The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

25. The display panel according to claim 24, characterized in that, Each of the test circuit units includes 3 first switches and 9 second switches, and 3 data lines are provided between two adjacent second connection lines; The three first switches in each test circuit unit are electrically connected to the pixel units in the same column; the nine second switches in each test circuit unit are electrically connected to the pixel units in three adjacent columns.

26. The display panel according to claim 9, characterized in that, The first connecting line extends along the row direction; among the multiple first connecting lines arranged along the column direction, the longer the first connecting line, the closer the corresponding first data line to the edge of the display panel is, and the longer the corresponding second connecting line is.

27. The display panel according to claim 1, characterized in that, At least a portion of the second fan-out line is located in the same conductive layer.

28. The display panel according to claim 27, characterized in that, Multiple second fan-out lines are arranged along the row direction, and two adjacent second fan-out lines are located in different conductive layers; among three adjacent second fan-out lines, the two second fan-out lines located on both sides are located in the same conductive layer.

29. The display panel according to claim 1, characterized in that, The display area includes a first display area, a second display area, and a third display area arranged sequentially along the row direction. The first data line is located in the first display area and the third display area, and the second data line is located in the second display area.

30. A display panel, characterized in that, The display panel includes a display area and a non-display area, and the display panel further includes: Multiple pixel units arranged in an array are located in the display area; Multiple data lines are located in the display area and electrically connected to the pixel units of the corresponding columns; the multiple data lines extend along the column direction and are arranged along the row direction; the multiple data lines include at least two first data lines and at least two second data lines. Multiple first fan-out lines are located in the display area, and the first fan-out lines are electrically connected to the corresponding first data lines. Multiple second fan-out lines, multiple test circuit units, and at least two test signal lines are located in the non-display area. Each test circuit unit includes multiple first switches and multiple second switches. The first terminals of the multiple first switches are electrically connected to the corresponding first fan-out lines via the corresponding second fan-out lines. The first terminals of the multiple second switches are electrically connected to the corresponding second data lines via the corresponding second fan-out lines. The second terminals of the switches correspondingly connected to the pixel units in the same column are electrically connected to the same test signal line. The second terminals of the switches correspondingly connected to the pixel units in two adjacent columns are electrically connected to different test signal lines. The plurality of second fan outgoing lines include at least two third fan outgoing lines and at least two fourth fan outgoing lines; the third fan outgoing lines are electrically connected to the first terminal of the first switch; the fourth fan outgoing lines are electrically connected to the first terminal of the second switch; The multiple second fan-out lines are arranged along the row direction; the arrangement order of the third fan-out lines is the opposite of the arrangement order of the first data lines corresponding to the electrical connection, and the arrangement order of the fourth fan-out lines is the same as the arrangement order of the second data lines corresponding to the electrical connection; The display panel also includes reverse-order pads and forward-order pads; The reverse-order pads are electrically connected to the third fan-out line of the first switch, and the sequential numbering of the reverse-order pads is the opposite of the arrangement order of the corresponding electrically connected data lines; the forward-order pads are electrically connected to the fourth fan-out line of the second switch, and the sequential numbering of the forward-order pads is the same as the arrangement order of the corresponding electrically connected data lines.

31. The display panel according to claim 30, characterized in that, At least two test signal lines are included: a first test signal line and a second test signal line. The second end of the switch corresponding to the odd-numbered pixel units is electrically connected to the first test signal line, and the second end of the switch corresponding to the even-numbered pixel units is electrically connected to the second test signal line.

32. The display panel according to claim 30, characterized in that, The display panel further includes a control signal line, wherein the control terminals of the first switch and the second switch are electrically connected to the control signal line.

33. The display panel according to claim 32, characterized in that, The first switch includes a first transistor, the first electrode of the first transistor serves as the first terminal of the first switch, the second electrode of the first transistor serves as the second terminal of the first switch, and the control electrode of the first transistor serves as the control terminal of the first switch.

34. The display panel according to claim 32, characterized in that, The second switch includes a second transistor, the first electrode of the second transistor serves as the first terminal of the second switch, the second electrode of the second transistor serves as the second terminal of the second switch, and the control electrode of the second transistor serves as the control terminal of the second switch.

35. The display panel according to claim 30, characterized in that, The arrangement order of the plurality of second fan-out lines along the row direction is different from the arrangement order of the data lines electrically connected to the second fan-out lines.

36. The display panel according to claim 35, characterized in that, The first end of the first fan-out line that is electrically connected to the second fan-out line is closer to the second data line located in the middle of the display area than the second end of the first fan-out line that is electrically connected to the first data line.

37. The display panel according to claim 35, characterized in that, The multiple second fan-outgoing lines are arranged along the row direction, and the outermost second fan-outgoing line is electrically connected to the first terminal of the first switch.

38. The display panel according to claim 30, characterized in that, The first fan-out line includes a first connecting line and a second connecting line that are electrically connected. The second connecting line is electrically connected to the corresponding first data line via the first connecting line. Multiple second connecting lines extend along the column direction and are arranged along the row direction. N data lines are arranged between two adjacent second connecting lines. Wherein, N is an integer greater than or equal to 2. Any of the pixel units includes M sub-pixels, or any of the pixel units is electrically connected to M data lines, where M is an integer greater than or equal to 2; any of the test circuit units includes K*M first switches and N*K*M second switches, where K is an integer greater than or equal to 1.

39. The display panel according to claim 38, characterized in that, The plurality of pixel units are divided into at least two pixel repeating units, and any pixel repeating unit includes K pixel units.

40. The display panel according to claim 38, characterized in that, N fourth fan-out lines are arranged between two adjacent third fan-out lines; the N fourth fan-out lines arranged between two adjacent third fan-out lines are electrically connected to the same column of pixel units; among the 2N fourth fan-out lines arranged between three adjacent third fan-out lines, N fourth fan-out lines and the other N fourth fan-out lines are electrically connected to the pixel units in different columns.

41. The display panel according to claim 38, characterized in that, In each of the test circuit units, a plurality of first switches and a plurality of second switches are arranged along the row direction; N second switches are arranged between two adjacent first switches.

42. The display panel according to claim 41, characterized in that, In each of the test circuit units, the second ends of N second switches located between two adjacent first switches are electrically connected to the same test signal line; among the 2N second switches between three adjacent first switches, the second ends of N second switches are electrically connected to different test signal lines from the second ends of the other N second switches.

43. The display panel according to claim 38, characterized in that, The plurality of first switches in each of the test circuit units are electrically connected to one column of the pixel units or at least two adjacent columns of the pixel units; the plurality of second switches in each of the test circuit units are electrically connected to multiple adjacent columns of the pixel units.

44. The display panel according to claim 43, characterized in that, M equals N.

45. The display panel according to claim 38, characterized in that, N is 2, M is 2, K is 2.

46. ​​The display panel according to claim 45, characterized in that, The plurality of pixel units include at least two first pixel units and at least two second pixel units. The first pixel unit includes a first color sub-pixel and a second color sub-pixel. The second pixel unit includes a third color sub-pixel and a second color sub-pixel. In the same row of pixel units, the first pixel units and the second pixel units are arranged alternately along the row direction.

47. The display panel according to claim 46, characterized in that, In the same column of pixel units, the first pixel unit and the second pixel unit are arranged alternately along the column direction.

48. The display panel according to claim 47, characterized in that, In two adjacent columns of sub-pixels, the first color sub-pixels and the third color sub-pixels in one column are arranged alternately along the column direction; the other column of sub-pixels consists entirely of the second color sub-pixels.

49. The display panel according to claim 48, characterized in that, The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

50. The display panel according to claim 45, characterized in that, Each of the test circuit units includes 4 first switches and 8 second switches, and 2 data lines are arranged between two adjacent second connection lines; the 4 first switches in each of the test circuit units are electrically connected to two adjacent columns of pixel units; the 8 second switches in each of the test circuit units are electrically connected to four adjacent columns of pixel units. In each of the four first switches in the test circuit unit, two first switches located on one side are electrically connected to the same column of pixel units, and the other two first switches located on the other side are electrically connected to the same column of pixel units.

51. The display panel according to claim 38, characterized in that, N is 3, M is 3, and K is 1.

52. The display panel according to claim 51, characterized in that, Each pixel unit includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; the sub-pixels in each row are arranged cyclically in the order of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel; and the sub-pixels in each column are sub-pixels of the same color.

53. The display panel according to claim 52, characterized in that, The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

54. The display panel according to claim 53, characterized in that, Each of the test circuit units includes 3 first switches and 9 second switches, and 3 data lines are provided between two adjacent second connection lines; The three first switches in each test circuit unit are electrically connected to the pixel units in the same column; the nine second switches in each test circuit unit are electrically connected to the pixel units in three adjacent columns.

55. The display panel according to claim 38, characterized in that, The first connecting line extends along the row direction; among the multiple first connecting lines arranged along the column direction, the longer the first connecting line, the closer the corresponding first data line to the edge of the display panel is, and the longer the corresponding second connecting line is.

56. The display panel according to claim 30, characterized in that, At least a portion of the second fan-out line is located in the same conductive layer.

57. The display panel according to claim 56, characterized in that, Multiple second fan-out lines are arranged along the row direction, and two adjacent second fan-out lines are located in different conductive layers; among three adjacent second fan-out lines, the two second fan-out lines located on both sides are located in the same conductive layer.

58. The display panel according to claim 30, characterized in that, The display area includes a first display area, a second display area, and a third display area arranged sequentially along the row direction. The first data line is located in the first display area and the third display area, and the second data line is located in the second display area.

59. A display device, characterized in that, It includes a driver chip and a display panel as described in any one of claims 1-58, wherein the driver chip is electrically connected to the second fan-out line.

60. A testing method for a display panel according to any one of claims 1-58, characterized in that, The testing method includes: During the first time period, the first switch and the second switch are controlled to be turned on. The test signal line connected to the second terminal of the switch corresponding to the odd-numbered pixel unit is connected to the lighting voltage, and the test signal line connected to the second terminal of the switch corresponding to the even-numbered pixel unit is connected to the extinguishing voltage. And / or, During the second time period, the first switch and the second switch are turned on. The test signal line connected to the second terminal of the switch corresponding to the odd-numbered pixel units is connected to the extinguishing voltage, and the test signal line connected to the second terminal of the switch corresponding to the even-numbered pixel units is connected to the lighting voltage.

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