Pixel circuit, driving method thereof and display panel

Abstract

Embodiments of the present application disclose a pixel circuit, a driving method thereof and a display panel. The pixel circuit comprises an initialization module, a driving module and a light-emitting module. The initialization module comprises a switching unit, a first coupling unit and a voltage writing unit. The voltage writing unit is configured to write a first level signal to a first end and a second end of the first coupling unit in a first initialization stage, and write a second level signal to the second end of the first coupling unit in a second initialization stage, so as to couple the second level signal to the switching unit through the first coupling unit. The switching unit is configured to be turned on in the second initialization stage, so as to write the second level signal to a control end of the driving module. The technical scheme of the embodiments of the present application helps to eliminate the leakage path between the signal inputted from the control end of the driving module to the initialization module, thereby improving the stability of the control end voltage of the driving module and improving the display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a pixel circuit, its driving method, and a display panel. Background Technology

[0002] With the continuous development of display technology, people have increasingly higher requirements for the display effect of display panels. At present, the pixel circuits in display panels generally suffer from leakage, which causes problems such as colored dots, screen flickering, or black and bright spots when the display panel is in normal display, affecting the display effect. Summary of the Invention

[0003] This invention provides a pixel circuit, its driving method, and a display panel, which helps to eliminate leakage paths between the control terminal of the driving module and the signal connected to the initialization module, thereby improving the stability of the control terminal voltage of the driving module and enhancing the display effect.

[0004] In a first aspect, embodiments of the present invention provide a pixel circuit, including: an initialization module, a driving module, and a light-emitting module; the initialization module includes a switching unit, a first coupling unit, and a voltage writing unit;

[0005] The switching unit is connected between the control terminal of the driving module and the first terminal of the first coupling unit; the voltage writing unit is connected to the first and second terminals of the first coupling unit, and is used to write a first level signal to the first and second terminals of the first coupling unit in the first initialization phase, and to write a second level signal to the second terminal of the first coupling unit in the second initialization phase, so as to couple the second level signal to the switching unit through the first coupling unit; the switching unit is used to be turned on in the second initialization phase to write the second level signal to the control terminal of the driving module;

[0006] The driving module is connected to the light-emitting module and is used to control the light-emitting module to emit light according to the voltage and data voltage at its own control terminal during the light-emitting stage.

[0007] Optionally, the voltage writing unit includes a first voltage writing subunit and a second voltage writing subunit;

[0008] The first end of the first voltage writing subunit is connected to the first level signal, and the second end of the first voltage writing subunit is connected to the first end of the first coupling unit. The first voltage writing subunit is used to write the first level signal to the first end of the first coupling unit during the first initialization phase.

[0009] The second voltage writing subunit is connected to the second end of the first coupling unit. The second voltage writing subunit is connected to the first level signal and the second level signal. The second voltage writing subunit is used to write the first level signal to the second end of the first coupling unit in the first initialization phase and to write the second level signal to the second end of the first coupling unit in the second initialization phase.

[0010] Optionally, the switching unit includes a first transistor, the first voltage writing subunit includes a second transistor, the second voltage writing subunit includes a third transistor and a fourth transistor, and the first coupling unit includes a first capacitor;

[0011] The gate of the first transistor is connected to the first scan signal, the first terminal of the first transistor is connected to the control terminal of the driving module, and the second terminal of the first transistor is connected to the first terminal of the first capacitor.

[0012] The gate of the second transistor is connected to the second scan signal, the first terminal of the second transistor is connected to the first level signal, and the second terminal of the second transistor is connected to the first terminal of the first capacitor;

[0013] The gate of the third transistor is connected to the first scan signal, the first terminal of the third transistor is connected to the second level signal, and the second terminal of the third transistor is connected to the second terminal of the first capacitor;

[0014] The gate of the fourth transistor is connected to the second scan signal, the first terminal of the fourth transistor is connected to the first level signal, and the second terminal of the fourth transistor is connected to the second terminal of the first capacitor.

[0015] Optionally, the driving module includes a first data writing unit, a first storage unit, and a first driving unit;

[0016] The first data writing unit is used to write the data voltage to the control terminal of the first driving unit during the voltage writing stage;

[0017] The first storage unit is connected to the control terminal of the first driving unit and is used to store the voltage of the control terminal of the first driving unit;

[0018] The first driving unit and the light-emitting module are connected between the first power supply terminal and the second power supply terminal, and are used to control the light-emitting module to emit light according to the voltage of its own control terminal during the light-emitting stage;

[0019] Wherein, the control terminal of the first drive unit is connected to the switch unit as the control terminal of the drive module;

[0020] Preferably, the first data writing unit includes a fifth transistor, the first driving unit includes a first driving transistor, the first storage unit includes a second capacitor, and the light-emitting module includes a light-emitting device; the gate of the fifth transistor is connected to a third scan signal, the first terminal of the fifth transistor is connected to the data voltage, and the second terminal of the fifth transistor is connected to the first driving transistor; the first driving transistor and the light-emitting device are connected between the first power supply terminal and the second power supply terminal, and the gate of the first driving transistor is connected to the switching unit; the first terminal of the second capacitor is connected to a fixed voltage signal, and the second terminal of the second capacitor is connected to the gate of the first driving transistor;

[0021] Preferably, the driving module further includes a first compensation unit, which is connected between the control terminal and the second terminal of the first driving unit and is used to compensate the threshold voltage of the first driving unit.

[0022] Preferably, the first compensation unit includes a sixth transistor, the gate of which is connected to the third scan signal, and the sixth transistor is connected between the gate and the second electrode of the first driving transistor.

[0023] Optionally, the drive module includes an analog drive submodule and a digital drive submodule, and the data voltage includes a first data voltage and a second data voltage;

[0024] The analog driving submodule and the light-emitting module are connected between the first power supply terminal and the second power supply terminal, and are used to generate a driving current according to the voltage of its own control terminal and the first data voltage during the light-emitting stage, so as to drive the light-emitting module to emit light.

[0025] The digital driving submodule is connected between the third power supply terminal and the analog driving submodule. It is used to provide the signal from the third power supply terminal to the analog driving submodule according to the voltage of its own control terminal, the second data voltage and the control voltage during the light emission stage, so as to control the time when the analog driving submodule drives the light emission module to emit light.

[0026] Wherein, the control terminal of the analog drive submodule is connected to the switch unit as the control terminal of the drive module, and / or, the control terminal of the digital drive submodule is connected to the switch unit as the control terminal of the drive module.

[0027] Optionally, the digital drive submodule includes a second coupling unit and a second drive unit;

[0028] The second coupling unit is used to couple the second data voltage and the control voltage to the control terminal of the second driving unit; the second driving unit is connected between the third power supply terminal and the analog driving submodule, and is used to provide the signal of the third power supply terminal to the analog driving submodule according to the voltage of its own control terminal during the light emission stage;

[0029] Wherein, when the control terminal of the digital drive submodule is connected to the switch unit as the control terminal of the drive module, the control terminal of the second drive unit is connected to the switch unit as the control terminal of the digital drive submodule;

[0030] Preferably, the second coupling unit includes a third capacitor, and the second driving unit includes a second driving transistor; the first terminal of the third capacitor is connected to the second data voltage and the control voltage, and the second terminal of the third capacitor is connected to the gate of the second driving transistor; the second driving transistor is connected between the third power supply terminal and the analog driving submodule, and the gate of the second driving transistor serves as the control terminal of the second driving unit;

[0031] Preferably, the digital drive submodule further includes a second compensation unit, which is connected between the control terminal and the second terminal of the second drive unit and is used to compensate the threshold voltage of the second drive unit.

[0032] Preferably, the second compensation unit includes a seventh transistor, the gate of which is connected to a fourth scan signal, and the seventh transistor is connected between the gate and the second electrode of the second driving transistor;

[0033] Preferably, the second coupling unit is connected to the data voltage line, and the second data voltage and the control voltage share the data voltage line;

[0034] Preferably, the digital drive submodule further includes a voltage control unit, which is connected between the third power supply terminal and the first terminal of the second drive unit, and is used to control the voltage of the third power supply terminal to be written to the first terminal of the second drive unit;

[0035] Preferably, the voltage control unit includes a fourteenth transistor and a fifteenth transistor; the gate of the fourteenth transistor is connected to the fourth scan signal, the first terminal of the fourteenth transistor is connected to the third power supply terminal, and the second terminal of the fourteenth transistor is connected to the first terminal of the second driving transistor; the gate of the fifteenth transistor is connected to the first light emission control signal, the first terminal of the fifteenth transistor is connected to the third power supply terminal, and the second terminal of the fifteenth transistor is connected to the first terminal of the second driving transistor.

[0036] Optionally, the analog drive submodule includes a second data writing unit, a second storage unit, and a current control unit;

[0037] The second data writing unit is used to write the first data voltage to the control terminal of the current control unit during the voltage writing stage;

[0038] The second storage unit is connected to the control terminal of the current control unit and is used to store the voltage of the control terminal of the current control unit;

[0039] The current control unit and the light-emitting module are connected between the first power supply terminal and the second power supply terminal. The current control unit is used to generate a driving current according to the voltage of its own control terminal during the light-emitting stage, so as to drive the light-emitting module to emit light.

[0040] The analog drive submodule is connected to the digital drive submodule through the current control unit, so that the digital drive submodule can control the current control unit to drive the light-emitting module to emit light for a certain period of time.

[0041] Wherein, when the control terminal of the analog drive submodule is connected to the switch unit as the control terminal of the drive module, the control terminal of the current control unit is connected to the switch unit as the control terminal of the analog drive submodule;

[0042] Preferably, the current control unit includes a driving subunit connected between the first power supply terminal and the first terminal of the light-emitting module. The driving subunit generates a driving current based on the voltage of its control terminal during the light-emitting phase to drive the light-emitting module to emit light. The control terminal of the driving subunit is connected to the digital driving submodule, and the control terminal of the driving subunit serves as the control terminal of the current control unit. Alternatively, the current control unit includes a driving subunit and a light-emitting control subunit connected between the first power supply terminal and the first terminal of the light-emitting module. The light-emitting control subunit controls the connection or disconnection between the first power supply terminal and the light-emitting module. The control terminal of the light-emitting control subunit or the control terminal of the driving subunit is connected to the digital driving submodule, and the control terminal of the driving subunit serves as the control terminal of the current control unit.

[0043] Preferably, the second data writing unit includes an eighth transistor, the driving subunit includes a third driving transistor, the second storage unit includes a fourth capacitor, and the light-emitting module includes a light-emitting device; the gate of the eighth transistor is connected to a fifth scan signal, the first terminal of the eighth transistor is connected to the first data voltage, and the second terminal of the eighth transistor is connected to the third driving transistor; the third driving transistor and the light-emitting device are connected between the first power supply terminal and the second power supply terminal, and the gate of the third driving transistor serves as the control terminal of the driving subunit; the first terminal of the fourth capacitor is connected to a fixed voltage signal, and the second terminal of the fourth capacitor is connected to the gate of the third driving transistor;

[0044] Preferably, the light-emitting control subunit includes a ninth transistor, which is connected between the first power supply terminal and the first electrode of the light-emitting device;

[0045] Preferably, the analog drive submodule further includes a third compensation unit, which is connected between the control terminal and the second terminal of the drive submodule and is used to compensate the threshold voltage of the drive submodule.

[0046] Preferably, the third compensation unit includes a tenth transistor, which is connected between the gate and the second electrode of the third driving transistor, and the gate of the tenth transistor is connected to the fifth scan signal.

[0047] Secondly, embodiments of the present invention also provide a driving method for a pixel circuit, the pixel circuit comprising: an initialization module, a driving module, and a light-emitting module; the initialization module comprising a switching unit, a first coupling unit, and a voltage writing unit; the switching unit being connected between a control terminal of the driving module and a first terminal of the first coupling unit; the voltage writing unit being connected between a first terminal and a second terminal of the first coupling unit; and the driving module being connected to the light-emitting module.

[0048] The driving method for the pixel circuit includes:

[0049] The voltage writing unit writes a first level signal to the first and second terminals of the first coupling unit during the first initialization phase, and writes a second level signal to the second terminal of the first coupling unit during the second initialization phase, so as to couple the second level signal to the switching unit through the first coupling unit;

[0050] The switching unit is turned on during the second initialization phase to write the second level signal into the control terminal of the drive module;

[0051] During the light-emitting phase, the driving module controls the light-emitting module to emit light based on the voltage and data voltage at its control terminal.

[0052] Optionally, the voltage writing unit includes a first voltage writing subunit and a second voltage writing subunit; a first terminal of the first voltage writing subunit is connected to the first level signal, a second terminal of the first voltage writing subunit is connected to the first terminal of the first coupling unit, and the second voltage writing subunit is connected to the second terminal of the first coupling unit, and the second voltage writing subunit is connected to both the first level signal and the second level signal;

[0053] The voltage writing unit writes a first-level signal to the first and second terminals of the first coupling unit during the first initialization phase, and writes a second-level signal to the second terminal of the first coupling unit during the second initialization phase, so as to couple the second-level signal to the second terminal of the switching unit through the first coupling unit, including:

[0054] The first voltage writing subunit writes the first level signal to the first terminal of the first coupling unit during the first initialization phase.

[0055] The second voltage writing subunit writes the first level signal to the second end of the first coupling unit during the first initialization phase, and writes the second level signal to the second end of the first coupling unit during the second initialization phase.

[0056] Thirdly, embodiments of the present invention also provide a display panel, including the pixel circuit described in the first aspect.

[0057] The pixel circuit, driving method, and display panel provided in this invention, through a voltage writing unit, write a first-level signal to the first and second ends of a first coupling unit during a first initialization phase, and writes a second-level signal to the second end of the first coupling unit during a second initialization phase. This couples the second-level signal to the second end of a switching unit via the first coupling unit, and then writes the second-level signal to the control terminal of the driving module via the switching unit. This achieves voltage initialization of the control terminal of the driving module, helping to ensure sufficient data voltage is written to the control terminal. The initialization voltage of the control terminal of the driving module can be generated by the first coupling unit, which helps to block the leakage path between the control terminal of the driving module and the first and second-level signals. The switching unit helps to block the first-level signal from being written to the control terminal of the driving module, preventing the first-level signal from affecting the voltage of the control terminal. Furthermore, during the light-emitting phase, there is leakage between the second end of the switching unit and the first-level signal connected to the voltage writing unit, making the voltage difference across the switching unit small or zero, thus further preventing any impact on the voltage of the control terminal of the driving module. The technical solution of this invention helps to eliminate the leakage path between the control terminal of the drive module and the signal connected to the initialization module, thereby improving the stability of the control terminal voltage of the drive module, alleviating problems such as color dots, screen flickering or black screen bright spots caused by leakage, and improving the display effect.

[0058] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 This is a schematic diagram of a pixel circuit in related technologies;

[0061] Figure 2 This is a schematic diagram of another pixel circuit structure in related technologies;

[0062] Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0063] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0064] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0065] Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0066] Figure 7 This is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present invention;

[0067] Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0068] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0069] Figure 10 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0070] Figure 11 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0071] Figure 12 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0072] Figure 13 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0073] Figure 14 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0074] Figure 15 This is a schematic flowchart of a pixel circuit driving method provided in an embodiment of the present invention. Detailed Implementation

[0075] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0076] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0077] As described in the background section, pixel circuits in existing display panels commonly suffer from leakage, leading to issues such as colored dots, flickering, or black / bright spots during normal display, thus affecting the display quality. The inventors' research has revealed the specific causes of these problems as follows:

[0078] The pixel circuit in related technologies includes a driving transistor and an initialization transistor. Before writing data to the driving transistor, an initialization voltage needs to be written to the gate of the driving transistor through the initialization transistor to initialize the gate voltage of the driving transistor, and then the threshold voltage of the driving transistor is compensated. Because there is a large voltage difference between the gate voltage of the driving transistor after data writing and the initialization voltage, the voltage difference across the initialization transistor is large, resulting in severe leakage current in the gate voltage of the driving transistor during the light-emitting stage.

[0079] Figure 1 This is a schematic diagram of a pixel circuit in related technologies, showing only a portion of its structure. For example, see [link to related documentation]. Figure 1The pixel circuit includes a driving transistor M1, an initialization transistor M2, a data writing module 01, a compensation module 02, and a storage module 03. The first terminal of the driving transistor M1 is connected to a power supply voltage V1. During the initialization phase, the initialization voltage Vinit is written to the gate of the driving transistor M1 through the initialization transistor M2, making the voltage of the N node Vinit. During the data writing phase, the data voltage Vdata is written to the gate of the driving transistor M1 through the data writing module 01, the driving transistor M1, and the compensation module 02, while compensating for the threshold voltage Vth of the driving transistor M1. When the driving transistor M1 is a P-type transistor, to ensure that the driving transistor M1 is turned on, Vinit - Vdata < Vth must be satisfied, so Vinit < Data_min + Vth ≈ -1.5V, where Data_min is the minimum value of the data voltage Vdata. The maximum voltage of the N node can reach Data_max + Vth ≈ 4.5V, so the maximum voltage difference between the two terminals of the initialization transistor M2 is about 6V.

[0080] Figure 2 This is a schematic diagram of another pixel circuit in related technologies, showing only a portion of its structure. For example, see [link to related documentation]. Figure 2 The pixel circuit includes a driving transistor M1, an initialization transistor M2, a compensation module 02, and a coupling module 04. During initialization, the initialization transistor M2 writes an initialization voltage Vinit to the gate of the driving transistor M1, making the voltage of node N Vinit. During data writing, the coupling module 04 couples the gate voltage of the driving transistor M1 according to the change in the data voltage Vdata to achieve data writing. The maximum voltage jump value of node N is Data_range = Data_max - Data_min, and the voltage of node N after data writing is Vinit + Data_range, where Data_max is the maximum value of the data voltage Vdata. To compensate the threshold voltage Vth of the driving transistor M1 through the compensation module 02, the driving transistor M1 needs to be turned on. When the driving transistor M1 is a P-type transistor, the voltage of node N must satisfy Vinit + Data_range - V1 < Vth for the driving transistor M1 to turn on, that is, the initialization voltage must satisfy Vinit ≤ V1 + Vth - (Data_max - Data_min) ≈ -4V. The maximum voltage of node N can reach V1+Vth+Data_max-Data_min≈9.5V, so the maximum voltage difference between the two terminals of transistor M2 is about 13.5V.

[0081] Therefore, it can be seen that the voltage difference across the terminals of the initialization transistor M2 is relatively large in both of the above schemes, reaching up to approximately 13.5V. During the light-emitting stage, the light-emitting device needs to be controlled by driving transistor M1 according to the voltage at node N. Figure 1 and Figure 2 (Not shown in the image) When the voltage difference across the initialization transistor M2 is large, the voltage at node N will leak through the initialization transistor M2, thereby affecting the light-emitting time of the light-emitting device or the driving current, causing problems such as colored dots, screen flickering or black screen bright spots to appear on the display panel during normal display, thus degrading the display effect.

[0082] To address the above problems, embodiments of the present invention provide a pixel circuit. Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. See also... Figure 3 The pixel circuit includes an initialization module 10, a driving module 20, and a light-emitting module 30. The initialization module 10 includes a switching unit 110, a first coupling unit 120, and a voltage writing unit 130.

[0083] In this configuration, the first end of the switching unit 110 is connected to the control terminal G of the driving module 20, and the second end of the switching unit 110 is connected to the first end of the first coupling unit 120. The voltage writing unit 130 is connected to both the first and second ends of the first coupling unit 120, and is used to write a first-level signal VGH to both ends of the first coupling unit 120 during a first initialization phase, and to write a second-level signal VGL to the second end of the first coupling unit 120 during a second initialization phase, thereby coupling the second-level signal VGL to the second end of the switching unit 110 through the first coupling unit 120. The switching unit 110 is turned on during the second initialization phase to write the second-level signal VGL to the control terminal G of the driving module 20.

[0084] The driver module 20 is connected to the light-emitting module 30 and is used to control the light-emitting module 30 to emit light according to the voltage of its own control terminal G and the data voltage Data during the light-emitting stage.

[0085] Specifically, one of the first level signal VGH and the second level signal VGL is a relatively high level signal, and the other is a relatively low level signal. The second level signal VGL is a level signal capable of initializing the voltage of the control terminal G of the driving module 20. For example, the driving module 20 may include a driving transistor, and the gate of the driving transistor can serve as the control terminal of the driving module 20. The second level signal VGL can initialize the gate voltage of the driving transistor. When the driving transistor is a P-type transistor, the second level signal VGL is a low level signal; when the driving transistor is an N-type transistor, the first level signal VGH is a high level signal.

[0086] For example, the operation phases of the pixel circuit include at least a first initialization phase, a second initialization phase, a voltage writing phase, and a light emission phase.

[0087] In the first initialization phase, the control voltage writing unit 130 writes a first level signal VGH to the first and second ends of the first coupling unit 120 to initialize the voltage across the first coupling unit 120, so that the voltage across the first coupling unit 120 is VGH and the voltage difference across the first coupling unit 120 is 0V.

[0088] In the second initialization phase, the control voltage writing unit 130 writes a second-level signal VGL to the second terminal of the first coupling unit 120, causing the voltage at the second terminal of the first coupling unit 120 to jump from VGH to VGL. Since the first coupling unit 120 has a coupling function, it can couple the voltage at its first terminal according to the voltage change at its second terminal, keeping the voltage difference across the first coupling unit 120 constant. Therefore, the first coupling unit 120 can couple the voltage at its first terminal to VGL. Simultaneously, the control switch unit 110 is turned on, so that the second-level signal VGL is written to the control terminal G of the drive module 20 through the switch unit 110, and the voltage at the control terminal G of the drive module 20 is initialized through the second-level signal VGL.

[0089] During the voltage writing stage, the data voltage Data of the driving module 20 can be written to the control terminal G of the driving module 20, so that the driving module 20 can control the light-emitting module 30 to emit light at the corresponding brightness according to the data voltage Data during the light-emitting stage.

[0090] When the voltage initialization signal for the control terminal G of the driving module 20, i.e., the second level signal VGL, is a low level signal, the first level signal VGH is a high level signal. The data voltage Data is typically higher than the voltage value of the second level signal VGL, resulting in the voltage value of the control terminal G of the driving module 20 during the light-emitting stage being higher than the voltage value of the second level signal VGL and close to the voltage value of the first level signal VGH. In this embodiment, a first coupling unit 120 is provided between the control terminal G of the driving module 20 and the first level signal VGH and the second level signal VGL connected to the voltage writing unit 130. This first coupling unit 120 helps to block the leakage path between the control terminal G of the driving module 20 and the first level signal VGH and the second level signal VGL. A switching unit 110 is provided between the control terminal G of the driving module 20 and the first level signal VGH connected to the voltage writing unit 130. This switching unit 110 helps to block the writing of the first level signal VGH to the control terminal G of the driving module 20, preventing the first level signal VGH from affecting the voltage of the control terminal G of the driving module 20. Furthermore, after the second initialization phase, the voltage at the second terminal of the switching unit 110 is VGL, which is relatively low. During the light-emitting phase, the first level signal VGH can leak current to the second terminal of the switching unit 110 through the voltage writing unit 130, causing the voltage at the second terminal of the switching unit 110 to rise. Meanwhile, the voltage at the control terminal G of the driving module 20 is also relatively high, resulting in a small or zero voltage difference across the switching unit 110. Therefore, this further avoids affecting the voltage at the control terminal G of the driving module 20. In summary, this solution helps eliminate the leakage path between the control terminal G of the driving module 20 and the signal connected to the initialization module 10, thereby improving the stability of the control terminal voltage of the driving module 20 and enhancing the display effect.

[0091] Similarly, when the initial voltage level signal for the control terminal G of the driving module 20, i.e., the second level signal VGL, is a high level signal, the first level signal VGH is a low level signal (VGL and VGH are only used to distinguish between the first level signal and the second level signal, not to indicate the high or low signal level). The data voltage Data is usually lower than the voltage value of the second level signal VGL, so that the voltage value of the control terminal G of the driving module 20 during the light emission stage is lower than the voltage value of the second level signal VGL and close to the voltage value of the first level signal VGH. In this embodiment, the first coupling unit 120 also helps to block the leakage path between the control terminal G of the driving module 20 and the first level signal VGH and the second level signal VGL, and the switching unit 110 also helps to block the first level signal VGH from being written to the control terminal G of the driving module 20, thus preventing the first level signal VGH from affecting the voltage of the control terminal G of the driving module 20. Furthermore, after the second initialization phase, the voltage at the second terminal of the switching unit 110 is VGL, which is relatively high. During the light-emitting phase, the second terminal of the switching unit 110 can leak current to the first level signal VGH through the voltage writing unit 130, causing the voltage at the second terminal of the switching unit 110 to decrease. Simultaneously, the voltage at the control terminal G of the driving module 20 is also low, resulting in a small or zero voltage difference across the switching unit 110. This further avoids affecting the voltage at the control terminal G of the driving module 20. This solution also helps eliminate the leakage path between the control terminal G of the driving module 20 and the signal connected to the initialization module 10, thereby improving the stability of the control terminal voltage of the driving module 20 and enhancing the display effect.

[0092] In summary, the technical solution of this invention, through a voltage writing unit writing a first-level signal to the first and second ends of the first coupling unit in the first initialization phase, and writing a second-level signal to the second end of the first coupling unit in the second initialization phase, couples the second-level signal to the second end of the switching unit via the first coupling unit, and then writes the second-level signal to the control end of the driving module via the switching unit. This achieves voltage initialization of the control end of the driving module, helping to ensure that the data voltage is fully written to the control end of the driving module. The initialization voltage of the control end of the driving module can be generated by coupling through the first coupling unit, which helps to block the leakage path between the control end of the driving module and the first and second-level signals. The switching unit helps to block the first-level signal from being written to the control end of the driving module, preventing the first-level signal from affecting the voltage of the control end of the driving module. Furthermore, during the light-emitting phase, there is leakage between the second end of the switching unit and the first-level signal connected to the voltage writing unit, making the voltage difference across the switching unit small or zero, thus further preventing any impact on the voltage of the control end of the driving module. The technical solution of this invention helps to eliminate the leakage path between the control terminal of the drive module and the signal connected to the initialization module, thereby improving the stability of the control terminal voltage of the drive module, alleviating problems such as color dots, screen flickering or black screen bright spots caused by leakage, and improving the display effect.

[0093] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. See also... Figure 4 Based on the above embodiments, optionally, the voltage writing unit 130 includes a first voltage writing subunit 131 and a second voltage writing subunit 132.

[0094] The first voltage writing subunit 131 is connected to a first level signal VGH at its first end, and the second end of the first voltage writing subunit 131 is connected to the first end of the first coupling unit 120. The first voltage writing subunit 131 is used to write the first level signal VGH to the first end of the first coupling unit 120 during the first initialization phase.

[0095] The second voltage writing subunit 132 is connected to the second end of the first coupling unit 120. The second voltage writing subunit 132 is connected to the first level signal VGH and the second level signal VGL. The second voltage writing subunit 132 is used to write the first level signal VGH to the second end of the first coupling unit 120 in the first initialization phase and to write the second level signal VGL to the second end of the first coupling unit 120 in the second initialization phase.

[0096] In this embodiment, the first voltage writing subunit 131 can provide a first-level signal VGH to the first terminal of the first coupling unit 120 during the first initialization phase to initialize the voltage at the first terminal of the first coupling unit 120. The second voltage writing subunit 132 can provide a switching voltage to the second terminal of the first coupling unit 120 during the first and second initialization phases to couple and generate the initialization voltage of the control terminal G of the driving module 20, i.e., the second-level signal VGL, through the first coupling unit 120. The second-level signal VGL generated by the first coupling unit 120 is then transmitted to the control terminal G of the driving module 20 through the switching unit 110 to initialize the voltage at the control terminal G of the driving module 20. Since the second-level signal VGL is the initialization voltage, the voltage value of the first-level signal VGH is not limited. Furthermore, after the second initialization phase, the voltage at the second terminal of the switching unit 110 is the voltage of the second level signal VGL. During the light emission phase, the first level signal VGH can leak current to the second terminal of the switching unit 110 through the first voltage writing subunit 131, making the voltage at the second terminal of the switching unit 110 close to the voltage of the control terminal G of the driving module 20. This makes the voltage difference between the two terminals of the switching unit 110 small or zero, thus further avoiding affecting the voltage of the control terminal G of the driving module 20.

[0097] See also Figure 4 Based on the above embodiments, optionally, the switching unit 110 includes a first transistor T1, the first voltage writing subunit 131 includes a second transistor T2, the second voltage writing subunit 132 includes a third transistor T3 and a fourth transistor T4, and the first coupling unit 120 includes a first capacitor C1. The gate of the first transistor T1 is connected to a first scan signal S1, the first terminal of the first transistor T1 is connected to the control terminal G of the driving module 20, and the second terminal of the first transistor T1 is connected to the first terminal of the first capacitor C1. The gate of the second transistor T2 is connected to a second scan signal S2, the first terminal of the second transistor T2 is connected to a first level signal VGH, and the second terminal of the second transistor T2 is connected to the first terminal of the first capacitor C1. The gate of the third transistor T3 is connected to the first scan signal S1, the first terminal of the third transistor T3 is connected to a second level signal VGL, and the second terminal of the third transistor T3 is connected to the second terminal of the first capacitor C1. The gate of the fourth transistor T4 is connected to the second scan signal S2, the first terminal of the fourth transistor T4 is connected to the first level signal VGH, and the second terminal of the fourth transistor T4 is connected to the second terminal of the first capacitor C1.

[0098] The initialization module provided in this embodiment of the invention is applicable to various pixel circuit structures, and several of them are described below as examples. Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. See also... Figure 5In one embodiment, the driving module may include a first data writing unit 210, a first storage unit 211, and a first driving unit 212. The first data writing unit 210 writes a data voltage (Data) to the control terminal G1 of the first driving unit 212 during the voltage writing phase. The first storage unit 211 is connected to the control terminal G1 of the first driving unit 212 and stores the voltage of the control terminal G1. The first driving unit 212 and the light-emitting module 30 are connected between a first power supply terminal and a second power supply terminal, and the first driving unit 212 controls the light-emitting module 30 to emit light according to the voltage of its own control terminal G1 during the light-emitting phase. The first power supply terminal is connected to a first power supply voltage (VDD), and the second power supply terminal is connected to a second power supply voltage (VSS). The control terminal G1 of the first driving unit 212 is connected to the switching unit 110 as the control terminal of the driving module.

[0099] For example, the first terminal of the first data writing unit 210 is connected to the data voltage Data, and the second terminal of the first data writing unit 210 can be connected to the control terminal G1 of the first driving unit 212. One end of the first storage unit 211 is connected to the control terminal G1 of the first driving unit 212, and the other end can be connected to any fixed voltage. Figure 5 This illustrates the case where the fixed voltage connected to the first storage cell 211 is the first power supply voltage VDD.

[0100] In this embodiment, by setting the control terminal G1 of the first driving unit 212 as the control terminal of the driving module and connecting it to the switching unit 110, the initialization module 10 can write the second level signal VGL to the control terminal G1 of the first driving unit 212 after the first and second initialization stages are completed, thereby initializing the voltage of the control terminal G1 of the first driving unit 212. In this way, during the voltage writing stage, the data voltage Data can be more fully written to the control terminal G1 of the first driving unit 212, enabling the first driving unit 212 to control the light-emitting module 30 to emit light according to the voltage of its control terminal G1 during the light-emitting stage. By applying the initialization module 10 to this pixel circuit, leakage paths between the control terminal G1 of the first driving unit 212 and the signal connected to the initialization module 10 are eliminated, thereby improving the stability of the control terminal voltage of the first driving unit 212 and enhancing the display effect.

[0101] Furthermore, when the data voltage Data is an analog data voltage signal, the first driving unit 212 can generate a driving current according to the voltage of its control terminal G1 during the light-emitting stage, thereby driving the light-emitting module 30 to emit light at a corresponding brightness, thus achieving analog driving. When the data voltage Data is a digital data voltage signal, the first driving unit 212 can control the light-emitting time of the light-emitting module 30 according to the voltage of its control terminal G1 during the light-emitting stage, thus achieving digital driving. Therefore, the technical solution of this embodiment of the invention is applicable to both analog pixel circuits and digital pixel circuits.

[0102] See also Figure 5 Based on the above embodiments, optionally, the first data writing unit 210 includes a fifth transistor T5, the first driving unit 212 includes a first driving transistor DT1, the first storage unit 211 includes a second capacitor C2, and the light-emitting module 30 includes a light-emitting device D1. The gate of the fifth transistor T5 is connected to a third scan signal S3, the first terminal of the fifth transistor T5 is connected to a data voltage Data, and the second terminal of the fifth transistor T5 is connected to the first driving transistor DT1. The first driving transistor DT1 and the light-emitting device D1 are connected between a first power supply terminal and a second power supply terminal, and the gate of the first driving transistor DT1 is connected to the switching unit 110. The first terminal of the second capacitor C2 is connected to a fixed voltage signal, and the second terminal of the second capacitor C2 is connected to the gate of the first driving transistor DT1.

[0103] For example, the second terminal of the fifth transistor T5 can be connected to the gate of the first driving transistor DT1, and the fixed voltage signal connected to the second capacitor C2 can be any fixed voltage signal, such as the first power supply voltage VDD. After the first initialization stage and the second initialization stage are completed, the second level signal VGL is written to the gate of the first driving transistor DT1 through the initialization module 10 to initialize the gate voltage of the first driving transistor DT1. In the voltage writing stage, the fifth transistor T5 is controlled to turn on in response to the third scan signal S3, so as to write the data voltage Data to the gate of the first driving transistor DT1 through the fifth transistor T5, and store the data voltage Data through the second capacitor C2. In the light emission stage, the first driving transistor DT1 can control the light-emitting device D1 to emit light according to the data voltage Data stored in the second capacitor C2.

[0104] Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. See also... Figure 6The driving module may further include a first compensation unit 213, which is connected between the control terminal G1 and the second terminal of the first driving unit 212, and is used to compensate the threshold voltage of the first driving unit 212. For example, when the driving module includes the first compensation unit 213, the first terminal of the first data writing unit 210 can be connected to the data voltage Data, and the second terminal of the first data writing unit 210 can be connected to the first terminal of the first driving unit 212. In this embodiment, after the first initialization stage and the second initialization stage are completed, the initialization module 10 writes the second level signal VGL to the control terminal G1 of the first driving unit 212 to initialize the voltage of the control terminal G1 of the first driving unit 212, and simultaneously controls the first driving unit 212 to conduct through the second level signal VGL. During the voltage writing stage, the first data writing unit 210 and the first compensation unit 213 are turned on so that the data voltage Data is written to the control terminal of the first driving unit 212 in sequence through the first data writing unit 210, the first driving unit 212 and the first compensation unit 213. At the same time, the threshold voltage compensation of the first driving unit 212 is realized through the first compensation unit 213.

[0105] See also Figure 6 Optionally, the driving module further includes a first initialization unit 214, a first light-emitting control unit 215, and a second light-emitting control unit 216. The first initialization unit 214 has an initialization signal Vref connected to its first terminal, and its second terminal connected to the first terminal of the light-emitting module 30. The first initialization unit 214 is used to write the initialization signal Vref to the first terminal of the light-emitting module 30 to initialize the voltage at the first terminal of the light-emitting module 30. The first terminal of the first light-emitting control unit 215 has a first power supply voltage VDD connected to its first terminal, and its second terminal connected to the first terminal of the first driving unit 212. The first light-emitting control unit 215 is used to write the first power supply voltage VDD to the first terminal of the first driving unit 212 in response to a light-emitting control signal EM. The control terminal of the second light-emitting control unit 216 has a light-emitting control signal EM connected to its control terminal. The first terminal of the second light-emitting control unit 216 is connected to the second terminal of the first driving unit 212, and its second terminal is connected to the first terminal of the light-emitting module 30. The second light-emitting control unit 216 is used to connect or disconnect the first driving unit 212 and the light-emitting module 30.

[0106] It should be noted that, Figure 6The illustration only shows the case where the driving module includes a first light-emitting control unit 215 and a second light-emitting control unit 216. In other embodiments, the driving module may include only one of the first light-emitting control unit 215 and the second light-emitting control unit 216, or the driving module may not include the first light-emitting control unit 215 and the second light-emitting control unit 216.

[0107] See also Figure 6 Optionally, the second terminal of the fifth transistor T5 is connected to the first terminal of the first driving transistor DT1. The first compensation unit 213 includes a sixth transistor T6, the gate of which is connected to a third scan signal S3, and the sixth transistor T6 is connected between the gate and the second terminal of the first driving transistor DT1. The first initialization unit 214 includes an eleventh transistor T11, the gate of which is connected to the first scan signal S1, the first terminal of which is connected to an initialization signal Vref, and the first terminal of which is connected to the first terminal of the light-emitting device D1. The first light-emitting control unit 215 includes a twelfth transistor T12, the gate of which is connected to a light-emitting control signal EM, the first terminal of which is connected to a first power supply voltage VDD, and the second terminal of which is connected to the first terminal of the first driving transistor DT1. The second light-emitting control unit 216 includes a thirteenth transistor T13, the first terminal of which is connected to the light-emitting control signal EM, and the thirteenth transistor T13 is connected between the second terminal of the first driving transistor DT1 and the first terminal of the light-emitting device D1. The second terminal of the light-emitting device D1 is connected to the second power supply voltage VSS.

[0108] Figure 7 This is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present invention. Figure 7 The driving timing shown can be applied to drivers. Figure 6 The pixel circuitry operates within this. The following section combines... Figure 6 and Figure 7 Taking a pixel circuit where all transistors are P-type transistors, the first level signal VGH is a high-level signal, and the second level signal VGL is a low-level signal as an example, for... Figure 6 The working principle of the pixel circuit in the image is explained.

[0109] For example, the operation phases of the pixel circuit include a first initialization phase t01, a second initialization phase t02, a voltage writing phase t03, and an emission phase t04.

[0110] In the first initialization phase t01, the second scan signal S2 is a low-level signal, while the first scan signal S1, the third scan signal S3, and the light emission control signal EM are high-level signals. The second transistor T2 and the fourth transistor T4 are turned on, and the remaining transistors are turned off. The first-level signal VGH is written to the two terminals of the first capacitor C1 through the second transistor T2 and the fourth transistor T4 and held thereafter, so that the voltage across the first capacitor C1 is initialized by the first-level signal VGH, making both voltages of the first capacitor C1 VGH, and the voltage difference between the two terminals of the first capacitor C1 0V.

[0111] During the second initialization phase t02, the first scan signal S1 is a low-level signal, while the second scan signal S2, the third scan signal S3, and the light-emitting control signal EM are high-level signals. The first transistor T1, the third transistor T3, and the eleventh transistor T11 are turned on, while the fifth transistor T5, the sixth transistor T6, the twelfth transistor T12, and the thirteenth transistor T13 are turned off. The initialization signal Vref is written to the first terminal of the light-emitting device D1 through the eleventh transistor T11 to initialize the voltage at the first terminal of the light-emitting device D1. The second-level signal VGL is written to the second terminal of the first capacitor C1 through the third transistor T3, causing the voltage at the second terminal of the first capacitor C1 to jump from VGH to VGL. Since the first capacitor C1 has a coupling effect, the voltage difference between the two terminals of the first capacitor C1 remains constant. Therefore, the first capacitor C1 can couple the voltage of its first terminal according to the voltage change of its second terminal, causing the voltage at the first terminal of the first capacitor C1 to jump from VGH to VGL. The second-level signal VGL at the first terminal of the first capacitor C1 can be written to the gate of the first driving transistor DT1 through the first transistor T1, initializing the gate of the first driving transistor DT1 and turning on the first driving transistor DT1.

[0112] During the voltage writing stage t03, the third scan signal S3 is a low-level signal, while the first scan signal S1, the second scan signal S2, and the light emission control signal EM are high-level signals. The fifth transistor T5, the sixth transistor T6, and the first driving transistor DT1 are turned on, while the other transistors are turned off. The data voltage Data is sequentially written to the gate of the first driving transistor DT1 through the fifth transistor T5, the first driving transistor DT1, and the sixth transistor T6. The data voltage Data written to the gate of the first driving transistor DT1 is stored through the second capacitor C2, simultaneously achieving threshold voltage compensation for the first driving transistor DT1.

[0113] During the light-emitting stage t04, the light-emitting control signal EM is a low-level signal, while the first scan signal S1, the second scan signal S2, and the third scan signal S3 are high-level signals. The twelfth transistor T12, the thirteenth transistor T13, and the first driving transistor DT1 are turned on, while the other transistors are turned off. The first power supply voltage VDD is written to the first terminal of the light-emitting device D1 through the twelfth transistor T12, the first driving transistor DT1, and the thirteenth transistor T13. The second power supply voltage VSS is written to the second terminal of the light-emitting device D1. The first driving transistor DT1 generates a driving current according to the data voltage Data, driving the light-emitting device D1 to emit light at a corresponding brightness.

[0114] Compared to the above solutions, the technical solution of this embodiment of the invention includes a first capacitor C1 in the initialization module. This allows the initialization voltage of the gate of the first driving transistor DT1 to be generated by coupling with the first capacitor C1. This helps decouple the gate of the first driving transistor DT1 from the first level signal VGH and the second level signal VGL connected to the initialization module. Furthermore, the first capacitor C1 blocks the leakage path between the gate of the first driving transistor DT1 and the first level signal VGH and the second level signal VGL connected to the initialization module. The first transistor T1 in the initialization module is positioned between the gate of the first driving transistor DT1 and the second transistor T2. This protects the gate of the first driving transistor DT1 and helps prevent a high-level signal connected to the second transistor T2 from being written into the gate of the first driving transistor DT1, thus avoiding damage to the first driving transistor DT1. After the second initialization phase t02, the voltage at the second terminal of the second transistor T2 is low and floating. The first level signal VGH leaks through the second transistor T2 to its second terminal, making the voltage at the second terminal of the second transistor T2 and the second terminal of the first transistor T1 close to VGH. Meanwhile, the gate voltage of the first driving transistor DT1 is high after data writing, resulting in both terminals of the first transistor T1 being at high voltage. The voltage difference between the two terminals of the first transistor T1 is close to or equal to 0V, which helps eliminate the leakage path from the gate of the first driving transistor DT1 to the initialization module, thereby alleviating problems such as screen flickering or black / bright spots caused by leakage and improving display quality. Furthermore, the initialization voltage in existing pixel circuits is generally negative, while in this solution, the first level signal VGH connected to the initialization module can be positive, and the initialization voltage at the gate of the first driving transistor DT1 is ultimately generated by coupling with the first capacitor C1, making the magnitude of the first level signal VGH unrestricted and flexibly set.

[0115] It should be noted that the above embodiments are only illustrative examples assuming that all transistors in the pixel circuit are P-type transistors, the first level signal VGH is a high-level signal, and the second level signal VGL is a low-level signal. In other embodiments, the transistors in the pixel circuit can also be N-type transistors. When the first driving transistor DT1 is an N-type transistor, the signal that initializes the gate voltage of the first driving transistor DT1 is a high-level signal. Accordingly, the first level signal VGH can be set to a low-level signal, and the second level signal VGL to a high-level signal. This scheme can also achieve the beneficial effects described in the above embodiments. The specific principle can be understood by referring to the above embodiments, and will not be repeated here.

[0116] Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. See also... Figure 8 In another embodiment, the driving module may include a digital driving submodule 220 and an analog driving submodule 230. The data voltages connected to the driving module include a first data voltage Data1 and a second data voltage Data2. The analog driving submodule 230 and the light-emitting module 30 are connected between the first power supply terminal and the second power supply terminal. During the light-emitting phase, the analog driving submodule 230 generates a driving current based on the voltage of its own control terminal and the first data voltage Data1 to drive the light-emitting module 30 to emit light. The digital driving submodule 220 is connected between the third power supply terminal and the analog driving submodule 230. During the light-emitting phase, the digital driving submodule 220 provides a signal from the third power supply terminal to the analog driving submodule 230 based on the voltage of its own control terminal G2, the second data voltage Data2, and the control voltage Sweep to control the duration for which the analog driving submodule 230 drives the light-emitting module 30 to emit light. The control terminal G2 of the digital driving submodule 220 can be connected to the switching unit 110 as the control terminal of the driving module.

[0117] Specifically, the pixel circuit can be an analog pulse width modulation (PWM) pixel circuit, that is, a pixel circuit that combines analog driving and digital driving. The first power supply terminal is connected to the first power supply voltage VDD, the second power supply terminal is connected to the second power supply voltage VSS, and the third power supply terminal is connected to the third power supply voltage VDDW. The first power supply voltage VDD and the third power supply voltage VDDW are positive voltages, and the first power supply voltage VDD and the third power supply voltage VDDW can be the same or different. The second power supply voltage VSS is negative voltage or 0V.

[0118] The digital drive submodule 220 can be connected to a data voltage line. The second data voltage Data2 and the control voltage Sweep can share the same data voltage line so that the second data voltage Data2 and the control voltage Sweep can be transmitted to the digital drive submodule 220 in time intervals through the data voltage line.

[0119] The operation of this pixel circuit includes at least a first initialization stage, a second initialization stage, a voltage writing stage, and a light emission stage. For example, by setting the control terminal G2 of the digital driving submodule 220 as the control terminal of the driving module and connecting it to the switching unit 110, after the first and second initialization stages are completed, the initialization module 10 can write the second level signal VGL to the control terminal G2 of the digital driving submodule 220 to initialize the voltage of the control terminal G2. During the voltage writing stage, the first data voltage Data1 can be written to the control terminal of the analog driving submodule 230, and the data voltage line can transmit the second data voltage Data2 to the digital driving submodule 220. During the light emission stage, the analog driving submodule 230 can generate a driving current based on the first data voltage Data1 when a path is formed between the first power supply terminal and the second power supply terminal, thereby driving the light emission module 30 to emit light. The data voltage line can transmit the control voltage Sweep to the digital drive submodule 220. The digital drive submodule 220 can provide the third power supply voltage VDDW to the analog drive submodule 230 according to the second data voltage Data2 and the control voltage Sweep, so as to control the time when the analog drive submodule 230 generates the drive current through the third power supply voltage VDDW, thereby controlling the light emission time of the light-emitting module 30.

[0120] When the initial voltage level signal for the control terminal G2 of the digital driving submodule 220, i.e., the second level signal VGL, is a low level signal, the first level signal VGH is a high level signal. During the light-emitting phase, the voltage value of the control terminal G2 of the digital driving submodule 220 is higher than the voltage value of the second level signal VGL and close to the voltage value of the first level signal VGH. This embodiment's technical solution helps to block the leakage path between the control terminal G2 of the digital driving submodule 220 and the first level signal VGH and the second level signal VGL connected to the voltage writing unit 130 through the first coupling unit 120, and to prevent the first level signal VGH from being written to the control terminal G2 of the digital driving submodule 220 through the switching unit 110, thus avoiding the first level signal VGH affecting the voltage of the control terminal G2 of the digital driving submodule 220. Furthermore, during the light-emitting stage, the first level signal VGH can leak to the second terminal of the switching unit 110 through the voltage writing unit 130, making the voltage difference across the switching unit 110 small or zero. This further avoids affecting the voltage of the control terminal G2 of the digital driving submodule 220. This solution helps to eliminate the leakage path between the control terminal G2 of the digital driving submodule 220 and the signal connected to the initialization module 10, thereby improving the stability of the control terminal voltage of the digital driving submodule 220 and avoiding affecting the light-emitting time of the light-emitting module 30.

[0121] Similarly, when the initial voltage level signal for the control terminal G2 of the digital driving submodule 220, i.e., the second level signal VGL, is a high level signal, the first level signal VGH is a low level signal. During the light-emitting stage, the voltage value of the control terminal G2 of the digital driving submodule 220 is lower than the voltage value of the second level signal VGL and close to the voltage value of the first level signal VGH. This scheme can also achieve the beneficial effects described in the above embodiments. The specific principle can be understood by referring to the above embodiments, and will not be repeated here.

[0122] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. See also... Figure 9 In this embodiment, the digital driving submodule 220 may include a second coupling unit 221 and a second driving unit 222. The second coupling unit 221 is used to couple the second data voltage and the control voltage to the control terminal G3 of the second driving unit 222. The second driving unit 222 is connected between the third power supply terminal and the analog driving submodule 230, and is used to provide the signal from the third power supply terminal to the analog driving submodule 230 according to the voltage of its own control terminal G3 during the light emission stage.

[0123] In this configuration, when the control terminal of the digital driving submodule is connected to the switching unit 110 as the control terminal of the driving module, the control terminal G3 of the second driving unit 222 is also connected to the switching unit 110 as the control terminal of the digital driving submodule. The advantage of this configuration is that, after the initialization module 10 completes the first and second initialization phases, it writes the second level signal VGL to the control terminal G3 of the second driving unit 222 to initialize the voltage of the control terminal G3. This ensures that, during the voltage writing phase, the second data voltage is more fully written to the control terminal G3 of the second driving unit 222. By applying the initialization module 10 to this pixel circuit, it helps eliminate leakage paths between the control terminal G3 of the second driving unit 222 and the signal connected to the initialization module 10, thereby improving the stability of the control terminal voltage of the second driving unit 222 and preventing any impact on the light emission time of the light-emitting module 30.

[0124] See also Figure 9 Optionally, the second coupling unit 221 is connected to the data voltage line D0, and the second data voltage and the control voltage share the data voltage line D0, so that the second data voltage and the control voltage are transmitted to the second coupling unit 221 in a time-division manner through the data voltage line D0. This helps to reduce the number of signal lines connected to the pixel circuit. In other embodiments, the second coupling unit 221 may also be configured to connect to the signal transmission line of the second data voltage and the signal transmission line of the control voltage respectively.

[0125] Figure 10This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. See also... Figure 10 Based on the above embodiments, optionally, the second coupling unit 221 includes a third capacitor C3, and the second driving unit 222 includes a second driving transistor DT2. The first terminal of the third capacitor C3 is connected to the second data voltage Data2 and the control voltage Sweep, and the second terminal of the third capacitor C3 is connected to the gate of the second driving transistor DT2. The second driving transistor DT2 is connected between the third power supply terminal and the analog driving submodule 230, and the gate of the second driving transistor DT2 serves as the control terminal G3 of the second driving unit 222.

[0126] Specifically, the third capacitor C3 can be connected to the data voltage line to transmit the second data voltage Data2 and the control voltage Sweep to the third capacitor C3 in a time-division manner. During the voltage writing phase, the data voltage line can transmit the second data voltage Data2 to the third capacitor C3, thereby coupling the second data voltage Data2 to the gate of the second driving transistor DT2 through the third capacitor C3. During the light emission phase, the data voltage line can transmit the control voltage Sweep to the third capacitor C3, thereby coupling the control voltage Sweep to the second driving transistor DT2 through the third capacitor C3. During the light emission phase, the gate voltage of the second driving transistor DT2 is related to both the second data voltage Data2 and the control voltage Sweep. The second driving transistor DT2 can provide the third power supply voltage VDDW to the analog driving submodule 230 according to its own gate voltage, thereby controlling the time when the analog driving submodule 230 generates the driving current through the third power supply voltage VDDW, thus controlling the light emission time of the light emission module 30.

[0127] See also Figure 10 The digital drive submodule may further include a second compensation unit 223 and a voltage control unit 224. The second compensation unit 223 is connected between the control terminal G3 and the second terminal of the second drive unit 222, and is used to compensate the threshold voltage of the second drive unit 222. The voltage control unit 224 is connected between the third power supply terminal and the first terminal of the second drive unit 222, and is used to control the third power supply voltage VDDW to be written to the first terminal of the second drive unit 222. In this embodiment, after the first initialization stage and the second initialization stage are completed, the initialization module 10 writes the second level signal VGL to the control terminal G3 of the second drive unit 222 to initialize the voltage of the control terminal G3 of the second drive unit 222. At the same time, the second level signal VGL controls the second drive unit 222 to be turned on, and controls the voltage control unit 224 to be turned on, so that the third power supply terminal, the voltage control unit 224, the second drive unit 222, the second compensation unit 223 and the control terminal G3 of the first drive unit 212 form a path, thereby realizing the threshold voltage compensation of the second drive unit 222.

[0128] It should be noted that, Figure 10 The illustration only shows the case where the digital drive submodule includes the voltage control unit 224. In other embodiments, the voltage control unit 224 may not be provided in the digital drive submodule.

[0129] See also Figure 10 Optionally, the second compensation unit 223 includes a seventh transistor T7, the gate of which is connected to a fourth scan signal S4, and the seventh transistor T7 is connected between the gate and the second terminal of the second driving transistor DT2. The voltage control unit 224 includes a fourteenth transistor T14 and a fifteenth transistor T15. The gate of the fourteenth transistor T14 is connected to the fourth scan signal S4, the first terminal of the fourteenth transistor T14 is connected to a third power supply voltage VDDW, and the second terminal of the fourteenth transistor T14 is connected to the first terminal of the second driving transistor DT2. The gate of the fifteenth transistor T15 is connected to a first light emission control signal EM1, the first terminal of the fifteenth transistor T15 is connected to the third power supply voltage VDDW, and the second terminal of the fifteenth transistor T15 is connected to the first terminal of the second driving transistor DT2.

[0130] Figure 11 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. See also... Figure 11 In this embodiment, the control terminal of the analog driving submodule 230 is set as the control terminal G of the driving module and connected to the switching unit 110. The specific structure of the analog driving submodule 230 can include various methods. In one embodiment, the analog driving submodule 230 includes a second data writing unit 231, a second storage unit 232, and a current control unit 233. The second data writing unit 231 is used to write the first data voltage Data1 to the control terminal G4 of the current control unit 233 during the voltage writing stage. The second storage unit 232 is connected to the control terminal G4 of the current control unit 233 and is used to store the voltage of the control terminal G4 of the current control unit 233. The current control unit 233 and the light-emitting module 30 are connected between the first power supply terminal and the second power supply terminal. The current control unit 233 is used to generate a driving current according to the voltage of its own control terminal G4 during the light-emitting stage to drive the light-emitting module 30 to emit light. The analog driving submodule 230 is connected to the digital driving submodule 220 through the current control unit 233, so that the digital driving submodule 220 can control the duration for which the current control unit 233 drives the light-emitting module 30 to emit light.

[0131] Among them, the control terminal G4 of the current control unit 233 is connected to the switch unit 110 as the control terminal of the analog drive submodule 230.

[0132] For example, the first terminal of the second data writing unit 231 is connected to the first data voltage Data1, and the second terminal of the second data writing unit 231 can be connected to the control terminal G4 of the current control unit 233. One end of the second storage unit 232 is connected to the control terminal G4 of the current control unit 233, and the other end can be connected to any fixed voltage. Figure 11 This illustrates the case where the fixed voltage connected to the second storage unit 232 is the first power supply voltage VDD.

[0133] In this embodiment, by setting the control terminal G4 of the current control unit 233 as the control terminal of the analog drive submodule 230 and connecting it to the switch unit 110, the initialization module 10 can write the second level signal VGL to the control terminal G4 of the current control unit 233 after the first and second initialization stages are completed, thereby initializing the voltage of the control terminal G4 of the current control unit 233. In this way, during the voltage writing stage, the first data voltage Data1 can be more fully written to the control terminal G4 of the current control unit 233, enabling the current control unit 233 to control the light-emitting module 30 to emit light according to the voltage of its control terminal G4 during the light-emitting stage. By applying the initialization module 10 to this pixel circuit, leakage paths between the control terminal G4 of the current control unit 233 and the signal connected to the initialization module 10 are eliminated, thereby improving the stability of the control terminal voltage of the current control unit 233 and enhancing the display effect.

[0134] See also Figure 11 The current control unit 233 may include a drive subunit 2331, which is connected between the first power supply terminal and the first terminal of the light-emitting module 30. The drive subunit 2331 generates a drive current based on the voltage of its control terminal during the light-emitting phase to drive the light-emitting module 30 to emit light. The control terminal of the drive subunit 2331 is connected to a digital drive submodule 220. During the light-emitting phase, the digital drive submodule 220 provides a third power supply voltage VDDW to the control terminal of the drive subunit 2331 based on the voltage of its control terminal, the second data voltage Data2, and the control voltage Sweep. This allows the third power supply voltage VDDW to control the time at which the drive subunit 2331 generates the drive current based on the voltage of its control terminal, thereby controlling the light-emitting time of the light-emitting module 30.

[0135] The control terminal of the driving subunit 2331 can serve as the control terminal G4 of the current control unit 233. After the initialization module 10 completes the first and second initialization phases, it writes the second level signal VGL to the control terminal of the driving subunit 2331 to initialize the voltage of the control terminal. This not only ensures that the first data voltage Data1 is written more fully to the control terminal of the driving subunit 2331, but also helps to eliminate leakage paths between the control terminal of the driving subunit 2331 and the signal connected to the initialization module 10, thereby improving the stability of the voltage at the control terminal of the driving subunit 2331 and enhancing the display effect.

[0136] See also Figure 11 The second data writing unit 231 includes an eighth transistor T8, the driving subunit 2331 includes a third driving transistor DT3, the second storage unit 232 includes a fourth capacitor C4, and the light-emitting module 30 includes a light-emitting device D1. The gate of the eighth transistor T8 is connected to a fifth scan signal S5, the first terminal of the eighth transistor T8 is connected to a first data voltage Data1, and the second terminal of the eighth transistor T8 is connected to the third driving transistor DT3. The third driving transistor DT3 and the light-emitting device D1 are connected between a first power supply terminal and a second power supply terminal. The gate of the third driving transistor DT3 serves as the control terminal of the driving subunit 2331 and is connected to the switching unit 110. The first terminal of the fourth capacitor C4 is connected to a fixed voltage signal, and the second terminal of the fourth capacitor C4 is connected to the gate of the third driving transistor DT3.

[0137] In this circuit, the second terminal of the eighth transistor T8 can be directly connected to the gate of the third driving transistor DT3. The fixed voltage signal connected to the fourth capacitor C4 can be any fixed voltage signal, such as the first power supply voltage VDD. After the first and second initialization stages are completed, the second level signal VGL is written to the gate of the third driving transistor DT3 through the initialization module 10 to initialize the gate voltage of the third driving transistor DT3. During the voltage writing stage, the eighth transistor T8 is turned on in response to the fifth scan signal S5 to write the first data voltage Data1 to the gate of the third driving transistor DT3 through the eighth transistor T8, and the first data voltage Data1 is stored through the fourth capacitor C4. During the light emission stage, the third driving transistor DT3 can control the light-emitting device D1 to emit light according to the first data voltage Data1 stored in the fourth capacitor C4. The digital driving submodule 220 can provide the third power supply voltage VDDW to the gate of the third driving transistor DT3 according to the voltage of its own control terminal, the second data voltage Data2, and the control voltage Sweep, thereby controlling the time for the third driving transistor DT3 to generate the driving current according to its own gate voltage through the third power supply voltage VDDW, and thus controlling the light emission time of the light-emitting device D1.

[0138] Figure 12 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. See also... Figure 12 The current control unit 233 may further include a driving subunit 2331 and a light-emitting control subunit (referred to as the first light-emitting control subunit 2332 for ease of description), which are connected between the first power supply terminal and the first terminal of the light-emitting module 30. The first light-emitting control subunit 2332 is used to control the connection or disconnection between the first power supply terminal and the light-emitting module 30. The control terminal of the driving subunit 2331 serves as the control terminal G4 of the current control unit 233. Figure 12 The illustration shows the case where the control terminal of the first light-emitting control subunit 2332 is connected to the digital driving submodule 220. In other embodiments, the control terminal of the driving subunit 2331 may also be connected to the digital driving submodule 220.

[0139] By connecting the control terminal of the first light-emitting control subunit 2332 to the digital driving submodule 220, the digital driving submodule 220 can provide the third power supply voltage VDDW to the control terminal of the first light-emitting control subunit 2332 according to the voltage of its own control terminal, the second data voltage Data2, and the control voltage Sweep during the light-emitting stage. This allows the third power supply voltage VDDW to control the conduction time of the first light-emitting control subunit 2332, thereby controlling the light-emitting time of the light-emitting module 30.

[0140] See also Figure 12 The analog drive submodule may further include a third compensation unit 234, which is connected between the control terminal and the second terminal of the drive submodule 2331, and is used to compensate the threshold voltage of the drive submodule 2331. For example, when the analog drive submodule includes the third compensation unit 234, the first terminal of the second data writing unit 231 can be connected to the first data voltage Data1, and the second terminal of the second data writing unit 231 can be connected to the control terminal of the drive submodule 2331. In this embodiment, after the first initialization stage and the second initialization stage are completed, the initialization module 10 writes the second level signal VGL to the control terminal of the drive submodule 2331 to initialize the voltage of the control terminal of the drive submodule 2331, and simultaneously controls the drive submodule 2331 to conduct through the second level signal VGL. During the voltage writing stage, the second data writing unit 231 and the third compensation unit 234 are turned on so that the first data voltage Data1 is written to the control terminal of the driving subunit 2331 in sequence through the second data writing unit 231, the driving subunit 2331 and the third compensation unit 234. At the same time, the threshold voltage compensation of the driving subunit 2331 is realized through the third compensation unit 234.

[0141] See also Figure 12 Optionally, the analog driving submodule further includes a second light-emitting control subunit 2333, a second initialization unit 235, and a third storage unit 236. The second light-emitting control subunit 2333 is connected between the second terminal of the driving subunit 2331 and the first terminal of the light-emitting module 30, used to connect or disconnect the driving subunit 2331 and the light-emitting module 30. The first terminal of the second initialization unit 235 is connected to a first initialization voltage Vref1, and the second terminal of the second initialization unit 235 is connected to the control terminal of the first light-emitting control subunit 2332, used to initialize the voltage of the control terminal of the first light-emitting control subunit 2332. The third storage unit 236 is connected to the control terminal of the first light-emitting control subunit 2332, used to store the voltage of the control terminal of the first light-emitting control subunit 2332. For example, the first terminal of the third storage unit 236 is connected to the control terminal of the first light-emitting control subunit 2332, and the second terminal is connected to a fixed voltage signal, which can be any fixed voltage signal, such as the first power supply voltage VDD.

[0142] See also Figure 12 Optionally, the second terminal of the eighth transistor T8 is connected to the first terminal of the third driving transistor DT3. The first light-emitting control subunit 2332 includes a ninth transistor T9, which is connected between the first power supply terminal and the first terminal of the light-emitting device D1. The gate of the ninth transistor T9 is connected to the digital driving submodule 220. The third compensation unit 234 includes a tenth transistor T10, which is connected between the gate and the second terminal of the third driving transistor DT3. The gate of the tenth transistor T10 is connected to the fifth scan signal S5. The second light-emitting control subunit 2333 includes a sixteenth transistor T16, whose gate is connected to the second light-emitting control signal EM2. The first terminal of the sixteenth transistor T16 is connected to the second terminal of the third driving transistor DT3, and the second terminal of the sixteenth transistor T16 is connected to the first terminal of the light-emitting device D1. The second initialization unit 235 includes a seventeenth transistor T17, whose gate is connected to the sixth scan signal S6. The first terminal of the seventeenth transistor T17 is connected to the first initialization voltage Vref1, and the second terminal of the seventeenth transistor T17 is connected to the gate of the ninth transistor T9. The third storage cell 236 includes a fifth capacitor C5. The first terminal of the fifth capacitor C5 is connected to the gate of the ninth transistor T9. The first terminal of the fifth capacitor C5 is connected to a fixed voltage signal, which can be any fixed voltage signal, such as the first power supply voltage VDD.

[0143] Figure 13 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 13This illustrates the case where the gate of the second driving transistor DT2 serves as the control terminal of the digital driving submodule, and the initialization module 10 is connected to the gate of the second driving transistor DT2. See also... Figure 13 Optionally, the pixel circuit may further include a third initialization unit 237. The first terminal of the third initialization unit 237 is connected to a second initialization signal Vref2, and the second terminal of the third initialization unit 237 is connected to the control terminal of the driving subunit 2331 for initializing the control terminal voltage of the driving subunit 2331. The third initialization unit 237 may include an eighteenth transistor T18. The gate of the eighteenth transistor T18 is connected to a second scan signal S2, the first terminal of the eighteenth transistor T18 is connected to the second initialization signal Vref2, and the second terminal of the eighteenth transistor T18 is connected to the gate of a third driving transistor DT3.

[0144] Figure 14 This is a schematic diagram of the driving timing of another pixel circuit provided in an embodiment of the present invention. Figure 14 The driving timing shown can be applied to drivers. Figure 13 The pixel circuitry operates within this. The following section combines... Figure 13 and Figure 14 Taking a pixel circuit where all transistors are P-type transistors, the first level signal VGH is a high-level signal, and the second level signal VGL is a low-level signal as an example, for... Figure 13 The working principle of the pixel circuit in this embodiment will be explained. In this embodiment, the fifth scan signal S5 and the first scan signal S1 can be the same signal.

[0145] For example, the operation stages of the pixel circuit include a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, a sixth stage t6, a seventh stage t7, and an eighth stage t8.

[0146] Phase 1 (t1): Phase 1 (t1) is the first initialization phase. The second scan signal S2 is a low-level signal, and the remaining signals are high-level signals. The second transistor T2, the fourth transistor T4, and the eighteenth transistor T18 are turned on, and the remaining transistors are turned off. The first-level signal VGH is written to the two terminals of the first capacitor C1 through the second transistor T2 and the fourth transistor T4 and held, so as to initialize the voltage across the two terminals of the first capacitor C1, making both voltages of the first capacitor C1 VGH and the voltage difference between the two terminals of the first capacitor C1 0V. The second initialization signal Vref2 is written to the gate of the third driving transistor DT3 through the eighteenth transistor T18, initializing the gate voltage of the third driving transistor DT3 and turning on the third driving transistor DT3.

[0147] Phase 2 (t2): Phase 2 is the second initialization phase and also the voltage writing phase. The first scan signal S1 and the fifth scan signal S5 are low-level signals, the signal on the data voltage line D0 is low-level, and the remaining signals are high-level. The first transistor T1, the third transistor T3, the eighth transistor T8, the tenth transistor T10, and the third driving transistor DT3 are turned on, while the remaining transistors are turned off. The second-level signal VGL is written to the second terminal of the first capacitor C1 through the third transistor T3, causing the voltage at the second terminal of the first capacitor C1 to jump from VGH to VGL. Because the first capacitor C1 has a coupling effect, the voltage difference between its two terminals remains constant. Therefore, the first capacitor C1 can couple its own first-terminal voltage according to the voltage change at its second terminal, causing the voltage at its first terminal to jump from VGH to VGL. Furthermore, the second-level signal VGL at the first terminal of the first capacitor C1 can be written to the gate of the second driving transistor DT2 through the first transistor T1, initializing the gate voltage of the second driving transistor DT2 and turning it on. The first data voltage Data1 is written to the gate of the third driving transistor DT3 through the eighth transistor T8, the third driving transistor DT3, and the tenth transistor T10, and is stored through the fourth capacitor C4. At the same time, the threshold voltage compensation of the third driving transistor DT3 is realized.

[0148] The third stage, t3, is the threshold voltage compensation stage and voltage writing stage for the second driving transistor DT2. The fourth scan signal S4 is low, while the remaining signals are high. The data voltage line D0 transmits the high-level second data voltage Data2, which is connected to the first terminal of the third capacitor C3. The seventh transistor T7, the second driving transistor DT2, and the fourteenth transistor T14 are turned on, while the remaining transistors are turned off. The third power supply voltage VDDW is written to the gate of the second driving transistor DT2 through the fourteenth transistor T14, the second driving transistor DT2, and the seventh transistor T7, achieving threshold voltage compensation for DT2. Simultaneously, the first terminal of the third capacitor C3 writes the data voltage Data2, realizing data writing to the sub-pixel of this row.

[0149] In the fourth stage t4: the remaining sub-pixels proceed step by step through the first stage t1, the second stage t2, and the third stage t3 to complete the data writing for all pixel rows.

[0150] In the fifth stage (t5), after all pixel rows of data have been written, the data voltage line D0 transmits the high level of the control voltage Sweep (Sweep_H), and the voltage connected to the first terminal of the third capacitor C3 uniformly jumps to the high level of the control voltage Sweep (Sweep_H). In this embodiment, the high level of the control voltage Sweep (Sweep_H) can be set to be greater than or equal to the maximum value of the second data voltage Data2. The gate voltage Vg of the second driving transistor DT2 is VDDW + Vth1 + Sweep_H - Data2, where Vth1 is the threshold voltage of the second driving transistor DT2. The second driving transistor DT is in the off state.

[0151] Stage 6 (t6): The sixth scan signal S6 is a low-level signal, and the other signals are high-level signals. The seventeenth transistor T17 is turned on, and the other transistors are turned off. The first initialization signal Vref1 is written to the gate of the ninth transistor T9 through the seventeenth transistor T17, turning on the ninth transistor T9, and maintaining the gate voltage of the ninth transistor T9 through the fifth capacitor C5.

[0152] Stage 7 (t7): Stage 7 is the light-emitting stage. The first light-emitting control signal EM1 and the second light-emitting control signal EM2 are low-level signals. The control voltage Sweep transmitted through the data voltage line D0 gradually changes from high level Sweep_H to low level Sweep_L, while the remaining signals are high-level signals. The fifteenth transistor T15, the ninth transistor T9, the third driving transistor DT3, and the sixteenth transistor T16 are turned on, while the remaining transistors are turned off. The third driving transistor DT3 generates a driving current based on the first data voltage Data1, driving the light-emitting device D1 to emit light. When the control voltage Sweep decreases to a level where the gate voltage of the second driving transistor DT2 satisfies Vg - VDDW = Vth1 (i.e., the control voltage Sweep decreases to the second data voltage Data2), the second driving transistor DT2 turns on. The third power supply voltage VDDW is written to the gate of the ninth transistor T9 through the fifteenth transistor T15 and the second driving transistor DT2, controlling the ninth transistor T9 to turn off. Therefore, the first power supply terminal is disconnected from the third driving transistor DT3, the driving current is zero, and the light-emitting device D1 stops emitting light, thus achieving control over the light-emitting time.

[0153] The technical solution of this invention includes a first capacitor C1 in the initialization module. This capacitor C1 couples the initialization voltage of the gate of the second driving transistor DT2, helping to decouple the gate of DT2 from the first-level signal VGH and the second-level signal VGL input to the initialization module. The first capacitor C1 also blocks the leakage path between the gate of DT2 and the first-level signals VGH and VGL input to the initialization module. A first transistor T1 in the initialization module is positioned between the gate of DT2 and the second transistor T2, protecting the gate of DT2 and preventing high-level signals input to T2 from being written into its gate and damaging it. After the second initialization phase t02, the voltage at the second terminal of the second transistor T2 is low and floating. The first level signal VGH leaks through the second transistor T2 to its second terminal, making the voltage at the second terminal of the second transistor T2 and the second terminal of the first transistor T1 close to VGH. Meanwhile, the gate voltage of the second driving transistor DT2 is high after data writing, resulting in high voltage at both terminals of the first transistor T1. The voltage difference between the two terminals of the first transistor T1 is close to or equal to 0V, which helps eliminate the leakage path from the gate of the second driving transistor DT2 to the initialization module. This improves the stability of the gate voltage of the second driving transistor DT2, reducing the impact of leakage on the light emission time and alleviating problems such as color dots, flickering, or bright spots in black screens, thus improving the display effect. Furthermore, the initialization voltage in existing pixel circuits is generally negative, while in this solution, the first level signal VGH connected to the initialization module can be positive, and the initialization voltage of the gate of the second driving transistor DT2 is ultimately generated by coupling with the first capacitor C1. This allows the magnitude of the first level signal VGH to be unrestricted and flexibly set.

[0154] It should be noted that the above embodiments are only illustrative examples assuming that all transistors in the pixel circuit are P-type transistors, the first level signal VGH is a high-level signal, and the second level signal VGL is a low-level signal. In other embodiments, the transistors in the pixel circuit can also be N-type transistors. When the second driving transistor DT2 is an N-type transistor, the signal that initializes the gate voltage of the second driving transistor DT2 is a high-level signal. Accordingly, the first level signal VGH can be set to a low-level signal, and the second level signal VGL to a high-level signal. This scheme can also achieve the beneficial effects described in the above embodiments. The specific principle can be understood by referring to the above embodiments, and will not be repeated here.

[0155] Figure 13This illustration only shows the case where the gate of the second driving transistor DT2 serves as the control terminal of the digital driving submodule, and the initialization module 10 is connected to the gate of the second driving transistor DT2. In other embodiments, the gate of the third driving transistor DT3 can serve as the control terminal of the analog driving submodule, and the initialization module 10 can also be connected to the gate of the third driving transistor DT3 to initialize the gate voltage of the third driving transistor DT3. Alternatively, the pixel circuit may include two initialization modules 10: one initialization module 10 connected to the gate of the second driving transistor DT2 to initialize its gate voltage, and the other initialization module 10 connected to the gate of the third driving transistor DT3 to initialize its gate voltage. Both schemes can achieve the beneficial effects described in the above embodiments. The specific principles can be understood by referring to the above embodiments, and will not be repeated here.

[0156] This invention also provides a display panel, which can be an organic light-emitting diode (OLED) display panel, an active-matrix organic light-emitting diode (OLED) display panel, or a micron-scale light-emitting diode (Micro-LED or Mini LED) display panel, etc. The display panel provided in this invention includes the pixel circuit provided in any embodiment of this invention, and therefore has the corresponding structure and beneficial effects of the pixel circuit, which will not be described in detail here.

[0157] This invention also provides a method for driving a pixel circuit. Figure 15 This is a schematic flowchart illustrating a pixel circuit driving method according to an embodiment of the present invention. The pixel circuit driving method provided by this embodiment is applicable to driving the pixel circuits in any of the above embodiments. See also... Figure 15 The driving method for this pixel circuit specifically includes the following steps:

[0158] S110. A first-level signal is written to the first and second ends of the first coupling unit through the voltage writing unit in the first initialization phase, and a second-level signal is written to the second end of the first coupling unit in the second initialization phase, so as to couple the second-level signal to the switching unit through the first coupling unit.

[0159] S120: The switching unit is turned on during the second initialization phase to write the second level signal into the control terminal of the drive module.

[0160] S130: During the light-emitting stage, the driver module controls the light-emitting module to emit light based on the voltage and data voltage at its own control terminal.

[0161] The technical solution of this invention involves a voltage writing unit writing a first-level signal to the first and second ends of a first coupling unit during a first initialization phase, and writing a second-level signal to the second end of the first coupling unit during a second initialization phase. This couples the second-level signal to the second end of a switching unit via the first coupling unit, and then writes the second-level signal to the control terminal of the driving module via the switching unit. This achieves voltage initialization of the driving module's control terminal, helping to ensure sufficient data voltage is written to the driving module's control terminal. The initialization voltage of the driving module's control terminal can be generated by the first coupling unit, which helps to block the leakage path between the driving module's control terminal and the first and second-level signals. The switching unit helps to block the first-level signal from being written to the driving module's control terminal, preventing the first-level signal from affecting the voltage of the driving module's control terminal. Furthermore, during the light-emitting phase, there is leakage between the second end of the switching unit and the first-level signal connected to the voltage writing unit, resulting in a small or zero voltage difference across the switching unit, thus further preventing any impact on the voltage of the driving module's control terminal. The technical solution of this invention helps to eliminate the leakage path between the control terminal of the drive module and the signal connected to the initialization module, thereby improving the stability of the control terminal voltage of the drive module, alleviating problems such as color dots, screen flickering or black screen bright spots caused by leakage, and improving the display effect.

[0162] Based on the above embodiments, step S110 may optionally include:

[0163] The first voltage writing subunit writes a first level signal to the first terminal of the first coupling unit during the first initialization phase;

[0164] The second voltage writing subunit writes a first level signal to the second end of the first coupling unit during the first initialization phase, and writes a second level signal to the second end of the first coupling unit during the second initialization phase.

[0165] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pixel circuit, characterized in that, include: The system comprises an initialization module, a driving module, and a light-emitting module; the initialization module includes a switching unit, a first coupling unit, and a voltage writing unit. The switching unit is connected between the control terminal of the driving module and the first terminal of the first coupling unit; the voltage writing unit is connected to the first terminal and the second terminal of the first coupling unit, and is used to write a first level signal to the first terminal and the second terminal of the first coupling unit in the first initialization phase, and to write a second level signal to the second terminal of the first coupling unit in the second initialization phase, so as to couple the second level signal to the switching unit through the first coupling unit. The switching unit is used to turn on during the second initialization phase so as to write the second level signal into the control terminal of the drive module; The driving module is connected to the light-emitting module and is used to control the light-emitting module to emit light according to the voltage and data voltage at its own control terminal during the light-emitting stage.

2. The pixel circuit according to claim 1, characterized in that, The voltage writing unit includes a first voltage writing subunit and a second voltage writing subunit; The first end of the first voltage writing subunit is connected to the first level signal, and the second end of the first voltage writing subunit is connected to the first end of the first coupling unit. The first voltage writing subunit is used to write the first level signal to the first end of the first coupling unit during the first initialization phase. The second voltage writing subunit is connected to the second end of the first coupling unit. The second voltage writing subunit is connected to the first level signal and the second level signal. The second voltage writing subunit is used to write the first level signal to the second end of the first coupling unit in the first initialization phase and to write the second level signal to the second end of the first coupling unit in the second initialization phase.

3. The pixel circuit according to claim 2, characterized in that, The switching unit includes a first transistor, the first voltage writing subunit includes a second transistor, the second voltage writing subunit includes a third transistor and a fourth transistor, and the first coupling unit includes a first capacitor; The gate of the first transistor is connected to the first scan signal, the first terminal of the first transistor is connected to the control terminal of the driving module, and the second terminal of the first transistor is connected to the first terminal of the first capacitor. The gate of the second transistor is connected to the second scan signal, the first terminal of the second transistor is connected to the first level signal, and the second terminal of the second transistor is connected to the first terminal of the first capacitor; The gate of the third transistor is connected to the first scan signal, the first terminal of the third transistor is connected to the second level signal, and the second terminal of the third transistor is connected to the second terminal of the first capacitor; The gate of the fourth transistor is connected to the second scan signal, the first terminal of the fourth transistor is connected to the first level signal, and the second terminal of the fourth transistor is connected to the second terminal of the first capacitor.

4. The pixel circuit according to claim 1, characterized in that, The driving module includes a first data writing unit, a first storage unit, and a first driving unit; The first data writing unit is used to write the data voltage to the control terminal of the first driving unit during the voltage writing stage; The first storage unit is connected to the control terminal of the first driving unit and is used to store the voltage of the control terminal of the first driving unit; The first driving unit and the light-emitting module are connected between the first power supply terminal and the second power supply terminal, and are used to control the light-emitting module to emit light according to the voltage of its own control terminal during the light-emitting stage; The control terminal of the first drive unit is connected to the switch unit as the control terminal of the drive module.

5. The pixel circuit according to claim 4, characterized in that, The first data writing unit includes a fifth transistor, the first driving unit includes a first driving transistor, the first storage unit includes a second capacitor, and the light-emitting module includes a light-emitting device; the gate of the fifth transistor is connected to a third scan signal, the first terminal of the fifth transistor is connected to the data voltage, and the second terminal of the fifth transistor is connected to the first driving transistor; The first driving transistor and the light-emitting device are connected between the first power supply terminal and the second power supply terminal, and the gate of the first driving transistor is connected to the switching unit; The first terminal of the second capacitor is connected to a fixed voltage signal, and the second terminal of the second capacitor is connected to the gate of the first driving transistor.

6. The pixel circuit according to claim 5, characterized in that, The driving module further includes a first compensation unit, which is connected between the control terminal and the second terminal of the first driving unit and is used to compensate the threshold voltage of the first driving unit.

7. The pixel circuit according to claim 6, characterized in that, The first compensation unit includes a sixth transistor, the gate of which is connected to the third scan signal, and the sixth transistor is connected between the gate and the second electrode of the first driving transistor.

8. The pixel circuit according to claim 1, characterized in that, The drive module includes an analog drive submodule and a digital drive submodule, and the data voltage includes a first data voltage and a second data voltage. The analog driving submodule and the light-emitting module are connected between the first power supply terminal and the second power supply terminal, and are used to generate a driving current according to the voltage of its own control terminal and the first data voltage during the light-emitting stage, so as to drive the light-emitting module to emit light. The digital driving submodule is connected between the third power supply terminal and the analog driving submodule. It is used to provide the signal from the third power supply terminal to the analog driving submodule according to the voltage of its own control terminal, the second data voltage and the control voltage during the light emission stage, so as to control the time when the analog driving submodule drives the light emission module to emit light. Wherein, the control terminal of the analog drive submodule is connected to the switch unit as the control terminal of the drive module, and / or, the control terminal of the digital drive submodule is connected to the switch unit as the control terminal of the drive module.

9. The pixel circuit according to claim 8, characterized in that, The digital drive submodule includes a second coupling unit and a second drive unit; The second coupling unit is used to couple the second data voltage and the control voltage to the control terminal of the second drive unit; The second driving unit is connected between the third power supply terminal and the analog driving submodule, and is used to provide the signal from the third power supply terminal to the analog driving submodule according to the voltage of its own control terminal during the light emission stage; In the case where the control terminal of the digital drive submodule is connected to the switch unit as the control terminal of the drive module, the control terminal of the second drive unit is connected to the switch unit as the control terminal of the digital drive submodule.

10. The pixel circuit according to claim 9, characterized in that, The second coupling unit includes a third capacitor, and the second driving unit includes a second driving transistor; the first terminal of the third capacitor is connected to the second data voltage and the control voltage, and the second terminal of the third capacitor is connected to the gate of the second driving transistor; The second driving transistor is connected between the third power supply terminal and the analog driving submodule, and the gate of the second driving transistor serves as the control terminal of the second driving unit.

11. The pixel circuit according to claim 10, characterized in that, The digital drive submodule further includes a second compensation unit, which is connected between the control terminal and the second terminal of the second drive unit and is used to compensate the threshold voltage of the second drive unit.

12. The pixel circuit according to claim 11, characterized in that, The second compensation unit includes a seventh transistor, the gate of which is connected to a fourth scan signal, and the seventh transistor is connected between the gate and the second electrode of the second driving transistor.

13. The pixel circuit according to claim 12, characterized in that, The second coupling unit is connected to the data voltage line, and the second data voltage and the control voltage share the data voltage line.

14. The pixel circuit according to claim 12, characterized in that, The digital drive submodule further includes a voltage control unit, which is connected between the third power supply terminal and the first terminal of the second drive unit, and is used to control the voltage of the third power supply terminal to be written to the first terminal of the second drive unit.

15. The pixel circuit according to claim 14, characterized in that, The voltage control unit includes a fourteenth transistor and a fifteenth transistor; the gate of the fourteenth transistor is connected to the fourth scan signal, the first terminal of the fourteenth transistor is connected to the third power supply terminal, and the second terminal of the fourteenth transistor is connected to the first terminal of the second driving transistor; the gate of the fifteenth transistor is connected to the first light emission control signal, the first terminal of the fifteenth transistor is connected to the third power supply terminal, and the second terminal of the fifteenth transistor is connected to the first terminal of the second driving transistor.

16. The pixel circuit according to claim 8, characterized in that, The analog drive submodule includes a second data writing unit, a second storage unit, and a current control unit; The second data writing unit is used to write the first data voltage to the control terminal of the current control unit during the voltage writing stage; The second storage unit is connected to the control terminal of the current control unit and is used to store the voltage of the control terminal of the current control unit; The current control unit and the light-emitting module are connected between the first power supply terminal and the second power supply terminal. The current control unit is used to generate a driving current according to the voltage of its own control terminal during the light-emitting stage, so as to drive the light-emitting module to emit light. The analog drive submodule is connected to the digital drive submodule through the current control unit, so that the digital drive submodule can control the current control unit to drive the light-emitting module to emit light for a certain period of time. In the case where the control terminal of the analog drive submodule is connected to the switch unit as the control terminal of the drive module, the control terminal of the current control unit is connected to the switch unit as the control terminal of the analog drive submodule.

17. The pixel circuit according to claim 16, characterized in that, The current control unit includes a driving subunit connected between the first power supply terminal and the first terminal of the light-emitting module. The driving subunit generates a driving current based on the voltage of its control terminal during the light-emitting phase to drive the light-emitting module to emit light. The control terminal of the driving subunit is connected to the digital driving submodule, and the control terminal of the driving subunit serves as the control terminal of the current control unit. Alternatively, the current control unit includes a driving subunit and a light-emitting control subunit connected between the first power supply terminal and the first terminal of the light-emitting module. The light-emitting control subunit controls the connection or disconnection between the first power supply terminal and the light-emitting module. The control terminal of the light-emitting control subunit or the control terminal of the driving subunit is connected to the digital driving submodule, and the control terminal of the driving subunit serves as the control terminal of the current control unit.

18. The pixel circuit according to claim 16, characterized in that, The second data writing unit includes an eighth transistor, the driving subunit includes a third driving transistor, the second storage unit includes a fourth capacitor, and the light-emitting module includes a light-emitting device; the gate of the eighth transistor is connected to a fifth scan signal, the first terminal of the eighth transistor is connected to the first data voltage, and the second terminal of the eighth transistor is connected to the third driving transistor; The third driving transistor and the light-emitting device are connected between the first power supply terminal and the second power supply terminal, and the gate of the third driving transistor serves as the control terminal of the driving sub-unit. The first terminal of the fourth capacitor is connected to a fixed voltage signal, and the second terminal of the fourth capacitor is connected to the gate of the third driving transistor.

19. The pixel circuit according to claim 17, characterized in that, The light-emitting control subunit includes a ninth transistor, which is connected between the first power supply terminal and the first electrode of the light-emitting device.

20. The pixel circuit according to claim 18, characterized in that, The analog drive submodule also includes a third compensation unit, which is connected between the control terminal and the second terminal of the drive submodule and is used to compensate the threshold voltage of the drive submodule.

21. The pixel circuit according to claim 20, characterized in that, The third compensation unit includes a tenth transistor, which is connected between the gate and the second electrode of the third driving transistor, and the gate of the tenth transistor is connected to the fifth scan signal.

22. A driving method for a pixel circuit, characterized in that, The pixel circuit includes: an initialization module, a driving module, and a light-emitting module; the initialization module includes a switching unit, a first coupling unit, and a voltage writing unit; the switching unit is connected between the control terminal of the driving module and the first terminal of the first coupling unit; the voltage writing unit is connected between the first terminal and the second terminal of the first coupling unit; the driving module is connected to the light-emitting module. The driving method for the pixel circuit includes: The voltage writing unit writes a first level signal to the first and second terminals of the first coupling unit during the first initialization phase, and writes a second level signal to the second terminal of the first coupling unit during the second initialization phase, so as to couple the second level signal to the switching unit through the first coupling unit; The switching unit is turned on during the second initialization phase to write the second level signal into the control terminal of the drive module; During the light-emitting phase, the driving module controls the light-emitting module to emit light based on the voltage and data voltage at its control terminal.

23. The driving method for the pixel circuit according to claim 22, characterized in that, The voltage writing unit includes a first voltage writing subunit and a second voltage writing subunit; a first end of the first voltage writing subunit is connected to the first level signal, a second end of the first voltage writing subunit is connected to the first end of the first coupling unit, the second voltage writing subunit is connected to the second end of the first coupling unit, and the second voltage writing subunit is connected to both the first level signal and the second level signal; The voltage writing unit writes a first-level signal to the first and second terminals of the first coupling unit during the first initialization phase, and writes a second-level signal to the second terminal of the first coupling unit during the second initialization phase, so as to couple the second-level signal to the second terminal of the switching unit through the first coupling unit, including: The first voltage writing subunit writes the first level signal to the first terminal of the first coupling unit during the first initialization phase. The second voltage writing subunit writes the first level signal to the second end of the first coupling unit during the first initialization phase, and writes the second level signal to the second end of the first coupling unit during the second initialization phase.

24. A display panel, characterized in that, Includes the pixel circuit described in any one of claims 1-21.

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