Method of forming a semiconductor structure
By forming high aspect ratio trenches and epitaxial layers on the substrate, combined with self-aligned etching, the performance degradation caused by the short channel effect is solved, and the performance and material uniformity of the semiconductor structure are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2022-04-29
- Publication Date
- 2026-06-26
AI Technical Summary
In the prior art, as device feature size shrinks, the short-channel effect leads to a decline in semiconductor structure performance, especially for transistors with silicon-germanium material channels, which have many problems.
By forming a first edge trench and a middle trench on the substrate, filling the edge layer with different materials, and forming an epitaxial layer through an epitaxial process, combined with self-aligned etching, production costs are reduced, process efficiency is improved, fillet span is reduced, and the uniformity of fin materials is ensured.
It effectively reduces the non-uniformity of doped materials in the fins, improves the performance of semiconductor structures, especially the hole mobility in the channel region of NMOS and PMOS transistors, and improves device performance.
Smart Images
Figure CN117012720B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology
[0002] With the development of semiconductor technology, the feature size of devices in integrated circuits is becoming smaller and smaller. However, as the feature size of devices becomes smaller, the length of the channel region between the source and drain also becomes shorter. When the length of the channel region decreases to a certain value, a short-channel effect occurs. Since the existence of the short-channel effect affects the performance of the device, it also hinders the further reduction of the feature size of devices in integrated circuits.
[0003] In order to overcome the short-channel effect and promote the development of semiconductor technology, the channel material has been replaced with germanium silicon (SiGe) material. Since germanium silicon material has a high hole mobility, which is usually 6 to 25 times that of silicon (Si) material, the performance of the device can be greatly improved by using germanium silicon material as the channel material.
[0004] However, existing silicon-germanium channel transistors still have many problems. Summary of the Invention
[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure, which can effectively improve the performance of the final semiconductor structure.
[0006] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region adjacent to each other, the second region including a first edge region and a middle region, and the first edge region being adjacent to the first region; forming a first edge trench in the first edge region, the first edge trench having a first aspect ratio; filling the first edge trench with a first edge layer, the material of the first edge layer being different from the material of the substrate; forming a middle trench in the middle region, the middle trench exposing the sidewalls of the first edge layer; removing the first edge layer to form an epitaxial trench, the epitaxial trench including the first edge trench and the middle trench, the epitaxial trench having a second aspect ratio, the first aspect ratio being greater than the second aspect ratio; forming an epitaxial layer in the epitaxial trench, the material of the epitaxial layer being different from the material of the substrate; and performing a patterning process on the first region of the substrate and the epitaxial layer, such that the first region of the substrate forms a plurality of mutually discrete first fins, and the epitaxial layer forms a plurality of mutually discrete second fins.
[0007] Optionally, the substrate further includes: a third region, wherein the second region is located between the first region and the third region; the second region further includes: a second edge region, wherein the middle region is located between the first edge region and the second edge region, and the second edge region is adjacent to the third region.
[0008] Optionally, the process of forming the first edge groove further includes: forming a second edge groove in the second edge region, the second edge groove having a third aspect ratio, the first aspect ratio and the third aspect ratio being equal.
[0009] Optionally, the process of forming the first edge layer further includes: filling the second edge trench with a second edge layer, wherein the material of the first edge layer is the same as the material of the second edge layer.
[0010] Optionally, the intermediate trench also exposes the sidewalls of the second edge layer.
[0011] Optionally, the process of removing the first edge layer may also include: removing the second edge layer; the epitaxial trench may further include the second edge trench.
[0012] Optionally, the second aspect ratio ranges from 0.05 to 0.40.
[0013] Optionally, the first aspect ratio is in the range of 1.5 to 6.0.
[0014] Optionally, the material of the first edge layer includes silicon oxide.
[0015] Optionally, the method of forming a first edge trench in the first edge region includes: forming a mask layer on the substrate; forming a first photoresist layer on the mask layer, the first photoresist layer exposing the top surface of the mask layer located on the second region; forming a first sacrificial layer on the sidewall of the first photoresist layer, the first sacrificial layer covering the top surface of the mask layer located on the first edge region, and the material of the first sacrificial layer being different from the materials of the first photoresist layer and the mask layer; forming a second photoresist layer, the second photoresist layer covering the top surface of the mask layer located on the intermediate region; removing the first sacrificial layer; and using the first photoresist layer and the second photoresist layer as a mask, etching the mask layer and the first edge region to form the first edge trench.
[0016] Optionally, the material of the first sacrificial layer includes silicon oxide; the material of the mask layer includes silicon nitride.
[0017] Optionally, the method of forming a first sacrificial layer on the sidewall of the first photoresist layer includes: forming a sacrificial material layer on the top surface of the mask layer located on the second region, the sidewall of the first photoresist layer, and the top surface of the first photoresist layer; and etching back the sacrificial material layer until the top surface of the first photoresist layer and the mask layer is exposed to form the first sacrificial layer.
[0018] Optionally, the process for forming the sacrificial material layer includes: atomic layer deposition process.
[0019] Optionally, the epitaxial layer is formed in the epitaxial trench using an epitaxial growth process.
[0020] Optionally, the substrate is made of silicon; the epitaxial layer is made of silicon-germanium.
[0021] Optionally, the first fin is used to form an NMOS transistor; the second fin is used to form a PMOS transistor.
[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0023] In the method for forming the technical solution of the present invention, since the first depth-to-width ratio of the first edge trench is high, the radius of the fillet at the bottom of the first edge trench is relatively small. The subsequently formed epitaxial trench includes the first edge trench and the intermediate trench, and the fillet at the bottom of the epitaxial trench is the same as the fillet at the bottom of the first edge trench, thereby making the fillet at the bottom of the epitaxial trench relatively small. This ensures that after the patterning process, the amount of material doped with the epitaxial layer in some of the first fins is reduced, and also reduces the problem of insufficient material in some of the second fins, thus affecting the performance of the final semiconductor structure.
[0024] Furthermore, the first edge layer and the substrate are made of different materials, which reduces the etching damage to the first edge layer during the subsequent etching process to remove part of the second region.
[0025] Further, the method for forming a first edge trench within the first edge region includes: forming a mask layer on the substrate; forming a first photoresist layer on the mask layer, the first photoresist layer exposing the top surface of the mask layer located on the second region; forming a first sacrificial layer on the sidewall of the first photoresist layer, the first sacrificial layer covering the top surface of the mask layer located on the first edge region, and the material of the first sacrificial layer being different from the materials of the first photoresist layer and the mask layer; forming a second photoresist layer, the second photoresist layer covering the top surface of the mask layer located on the intermediate region; removing the first sacrificial layer; and using the first photoresist layer and the second photoresist layer as a mask, etching the mask layer and the first edge region to form the first edge trench. Since the material of the first sacrificial layer is different from the materials of the first photoresist layer and the mask layer, a self-aligned process can be used to remove the first sacrificial layer, avoiding the need for a photomask process, thereby reducing production costs and improving process efficiency. Attached Figure Description
[0026] Figures 1 to 2 This is a schematic diagram of the steps involved in forming a semiconductor structure.
[0027] Figures 3 to 12 This is a schematic diagram of the steps in a semiconductor structure formation method according to an embodiment of the present invention. Detailed Implementation
[0028] As described in the background section, existing silicon-germanium channel transistors still have many problems. These will be explained in detail below with reference to the accompanying drawings.
[0029] Figures 1 to 2 This is a schematic diagram of the steps involved in forming a semiconductor structure.
[0030] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 including a first region I and a second region II that are adjacent to each other; a mask layer 101 is formed on the substrate 100, the mask layer 101 exposing the top surface of the second region II; the second region II is etched using the mask layer 101 as a mask to form a trench (not shown) in the second region II; an epitaxial layer 102 is formed in the trench using an epitaxial growth process, the material of the epitaxial layer 102 being different from the material of the substrate 100.
[0031] Please refer to Figure 2 The first region I of the substrate 100 and the epitaxial layer 102 are patterned, such that the first region I of the substrate 100 forms a plurality of first fins 103 and the epitaxial layer 102 forms a plurality of second fins 104.
[0032] In this embodiment, the substrate 100 is made of silicon, and the epitaxial layer 102 is made of silicon-germanium. Therefore, the first fin 103 is made of silicon, and the second fin 104 is made of silicon-germanium. Subsequently, the first fin 103 is used as the channel region of the formed NMOS transistor, and the second fin 104 is used as the channel region of the formed PMOS transistor. The silicon-germanium channel region can effectively improve the hole mobility, thereby improving the performance of the finally formed semiconductor structure.
[0033] In this embodiment, due to the small depth-to-width ratio of the trench, the problem of lateral etching along the direction perpendicular to the trench sidewall is more prominent during the etching process to form the trench. This results in a large-span rounded corner structure at the bottom of the formed trench. There is a preset spacing d1 between adjacent first fins 103 and second fins 104. When the span d2 of the rounded corner structure is greater than the preset spacing d1, after the patterning process, some first fins 103 are doped with silicon-germanium material, while some second fins 104 have less silicon-germanium material, thus affecting the performance of the final semiconductor structure.
[0034] Based on this, the present invention provides a method for forming a semiconductor structure. Because the first edge trench has a high depth-to-width ratio, the fillet radius at the bottom of the first edge trench is relatively small. The subsequently formed epitaxial trench includes the first edge trench and the intermediate trench, and the fillet radius at the bottom of the epitaxial trench is the same as that at the bottom of the first edge trench, thus making the fillet radius at the bottom of the epitaxial trench relatively small. This ensures that after the patterning process, the amount of material doped with the epitaxial layer in the first fin is reduced, and also reduces the problem of insufficient silicon-germanium material in the second fin, thereby affecting the performance of the final semiconductor structure.
[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0036] Figures 3 to 12 This is a schematic diagram of the steps in a semiconductor structure formation method according to an embodiment of the present invention.
[0037] Please refer to Figure 3 A substrate 200 is provided, the substrate including a first region I and a second region II that are adjacent to each other, the second region II including a first edge region A1 and a middle region B1, and the first edge region A1 is adjacent to the first region I.
[0038] In this embodiment, the substrate 200 further includes: a third region III, and the second region II is located between the first region I and the third region III; the second region II further includes: a second edge region A2, and the middle region B1 is located between the first edge region A1 and the second edge region A2, and the second edge region A2 is adjacent to the third region III.
[0039] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.
[0040] After providing the substrate 200, the method further includes: forming a first edge trench in the first edge region A1; and forming a second edge trench in the second edge region A2 during the formation of the first edge trench. Please refer to [reference needed for details]. Figures 4 to 7 .
[0041] Please refer to Figure 4 A mask layer 201 is formed on the substrate 200; a first photoresist layer 202 is formed on the mask layer 201, the first photoresist layer 202 exposing the top surface of the mask layer 201 located in the second region II.
[0042] In this embodiment, the first photoresist layer 202 specifically covers the mask layer 201 located on the first region I and the third region III.
[0043] In this embodiment, the mask layer 201 is made of silicon nitride.
[0044] In this embodiment, the first photoresist layer 202 has a sandwich structure, specifically including: a first amorphous carbon layer, a first dielectric anti-reflection layer located on the first amorphous carbon layer, and a first photoresist (not shown) located on the first dielectric anti-reflection layer.
[0045] In this embodiment, the first dielectric anti-reflection layer is made of silicon oxycarbonate. In other embodiments, the first dielectric anti-reflection layer may also be made of silicon oxynitride.
[0046] Please refer to Figure 5 A first sacrificial layer 203 is formed on the sidewall of the first photoresist layer 202. The first sacrificial layer 203 covers the top surface of the mask layer 201 located on the first edge region A1, and the material of the first sacrificial layer 203 is different from the materials of the first photoresist layer 202 and the mask layer 201.
[0047] In this embodiment, the process of forming the first sacrificial layer 203 further includes: forming a second sacrificial layer 204 on the sidewall of the first photoresist layer 202, the second sacrificial layer 204 covering the top surface of the mask layer 201 located on the second edge region A2, and the material of the second sacrificial layer 204 being different from the materials of the first photoresist layer 202 and the mask layer 201.
[0048] In this embodiment, the first sacrificial layer 203 is made of silicon oxide; the second sacrificial layer 204 is made of silicon oxide.
[0049] In this embodiment, the method of forming a first sacrificial layer 203 and a second sacrificial layer 204 on the sidewall of the first photoresist layer 202 includes: forming a sacrificial material layer (not shown) on the top surface of the mask layer 201 located on the second region II, the sidewall of the first photoresist layer 202, and the top surface; etching back the sacrificial material layer until the top surface of the first photoresist layer 202 and the mask layer 201 is exposed, thereby forming the first sacrificial layer 203 and the second sacrificial layer 204.
[0050] In this embodiment, the sacrificial material layer is formed using atomic layer deposition.
[0051] Please refer to Figure 6 A second photoresist layer 205 is formed, which covers the top surface of the mask layer 201 located on the intermediate region B1.
[0052] In this embodiment, the method for forming the second photoresist layer 205 includes: forming a photoresist material layer (not shown) on the top surface of the mask layer 201 located on the intermediate region B1, and on the top surfaces of the first sacrificial layer 203, the second sacrificial layer 204, and the first photoresist layer 202; and performing planarization on the photoresist material layer until the top surfaces of the first sacrificial layer 203 and the second sacrificial layer 204 are exposed, thereby forming the second photoresist layer 205.
[0053] In this embodiment, the process of planarizing the photoresist material layer is a heat treatment process.
[0054] In this embodiment, the second photoresist layer 205 also has a sandwich structure, specifically including: a second amorphous carbon layer, a second dielectric anti-reflection layer located on the second amorphous carbon layer, and a second photoresist (not shown) located on the second dielectric anti-reflection layer.
[0055] In this embodiment, the material of the second dielectric anti-reflection layer is silicon oxycarbonate. In other embodiments, the material of the second dielectric anti-reflection layer may also be silicon oxynitride.
[0056] Please refer to Figure 7 Remove the first sacrificial layer 203, and use the first photoresist layer 202 and the second photoresist layer 205 as a mask to etch the mask layer 201 and the first edge region A1 to form the first edge trench 206.
[0057] In this embodiment, the process of removing the first sacrificial layer 203 further includes: removing the second sacrificial layer 204; the process of forming the first edge trench 206 further includes: using the first photoresist layer 202 and the second photoresist layer 205 as a mask, etching the mask layer 201 and the second edge region A2 to form the second edge trench 207.
[0058] In this embodiment, since the material of the first sacrificial layer 203 is different from the materials of the first photoresist layer 202 and the mask layer 201, and the material of the second sacrificial layer 204 is different from the materials of the first photoresist layer 202 and the mask layer 201, a self-aligned process can be used to remove the first sacrificial layer 203 and the second sacrificial layer 204, avoiding the need for a photomask process to remove them. This reduces production costs and improves process efficiency.
[0059] In this embodiment, the first edge groove 206 has a first aspect ratio, the second edge groove 207 has a third aspect ratio, and the first aspect ratio and the third aspect ratio are equal.
[0060] In this embodiment, the first aspect ratio ranges from 1.5 to 6.0; the third aspect ratio ranges from 1.5 to 6.0.
[0061] Please refer to Figure 8 A first edge layer 208 is filled in the first edge trench 206, and the material of the first edge layer 208 is different from the material of the substrate 200.
[0062] In this embodiment, the process of forming the first edge layer 208 further includes filling the second edge trench 207 with a second edge layer 209, wherein the material of the first edge layer 208 is the same as the material of the second edge layer 209.
[0063] In this embodiment, the first edge layer 208 is made of silicon oxide; the second edge layer 209 is also made of silicon oxide. By using different materials for the first edge layer 208 and the substrate 200, and for the second edge layer 209 and the substrate 200, etching damage to the first edge layer 208 and the second edge layer 209 is reduced during the subsequent etching process to remove portions of the second region II.
[0064] In this embodiment, the method for forming the first edge layer 208 and the second edge layer 209 includes: forming an edge material layer (not shown) in the first edge trench 206 and the second edge trench 207, on the first photoresist layer 202 and the second photoresist layer 205; and planarizing the edge material layer until the top surfaces of the first photoresist layer 202 and the second photoresist layer 205 are exposed, thereby forming the first edge layer 208 and the second edge layer 209.
[0065] In this embodiment, since the top of the first photoresist layer 202 is the first photoresist and the top of the second photoresist layer 205 is the second photoresist, and the materials of the first and second photoresists are relatively soft, chemical mechanical polishing is not suitable for the planarization process. Therefore, the planarization process uses an etch-back process, with etching stopping at the first and second photoresists. By modulating the etching gas to a suitable selectivity ratio, it can be ensured that only the edge material layer is etched without damaging the first and second photoresists. Due to steric hindrance, the edge material layer located on the first and second photoresists will be removed. However, because the etching gas has difficulty penetrating the first edge trench 206 and the second edge trench 207, which have a high aspect ratio, the edge material layer within the first edge trench 206 and the second edge trench 207 will be retained.
[0066] In other embodiments, the first photoresist and the first dielectric anti-reflection layer of the first photoresist layer can be removed to expose the first amorphous carbon layer with a harder texture, and the second photoresist and the second dielectric anti-reflection layer of the second photoresist layer can be removed to expose the second amorphous carbon layer with a harder texture. In this case, the planarization of the edge material layer can be performed by chemical mechanical polishing.
[0067] It should be noted that, in this embodiment, the first edge layer 208 extends onto the first edge groove 206; the second edge layer 209 extends onto the second edge groove 207.
[0068] Please refer to Figure 9An intermediate groove 210 is formed in the intermediate region B1, and the intermediate groove 210 exposes the sidewall of the first edge layer 208.
[0069] It should be noted that, in this embodiment, before forming the intermediate trench 210, the method further includes: removing the second photoresist layer 205, the first edge layer 208 and the second edge layer 209 located between the first photoresist layer 201 and the second photoresist layer 205, and the mask layer 201 located on the intermediate region B1; after forming the intermediate trench 210, removing the first photoresist layer 202.
[0070] In this embodiment, the intermediate trench 210 also exposes the sidewalls of the second edge layer 209.
[0071] Please refer to Figure 10 After the intermediate trench 210 is formed, the first edge layer 208 is removed to form an epitaxial trench 211. The epitaxial trench 211 includes the first edge trench 206 and the intermediate trench 210. The epitaxial trench 211 has a second aspect ratio, and the first aspect ratio is greater than the second aspect ratio.
[0072] In this embodiment, the process of removing the first edge layer 208 also includes removing the second edge layer 209; the epitaxial trench 211 also includes the second edge trench 207.
[0073] In this embodiment, the second aspect ratio ranges from 0.05 to 0.40.
[0074] Please refer to Figure 11 An epitaxial layer 212 is formed in the epitaxial trench 211, and the material of the epitaxial layer 212 is different from the material of the substrate 200.
[0075] In this embodiment, the epitaxial layer 212 is formed in the epitaxial trench 211 using an epitaxial growth process.
[0076] In this embodiment, the epitaxial layer 212 is made of silicon-germanium.
[0077] It should be noted that, in this embodiment, the epitaxial layer 212 extends onto the epitaxial trench 211.
[0078] Please refer to Figure 12 The first region I of the substrate 200 and the epitaxial layer 212 are patterned, such that the first region I of the substrate 200 forms a plurality of mutually discrete first fins 213, and the epitaxial layer 212 forms a plurality of mutually discrete second fins 214.
[0079] In this embodiment, because the first edge trench 206 has a high depth-to-width ratio, the fillet radius at the bottom of the first edge trench 206 is relatively small. The subsequently formed epitaxial trench 211 includes the first edge trench 206 and the intermediate trench 210, and the fillet radius at the bottom of the epitaxial trench 211 is the same as that at the bottom of the first edge trench 206, resulting in a smaller fillet radius at the bottom of the epitaxial trench 211. This ensures that after the patterning process, the amount of material doped with the epitaxial layer 212 in some of the first fins 213 is reduced, and also reduces the problem of insufficient material in some of the epitaxial layers in some of the second fins 214, thereby affecting the performance of the final semiconductor structure.
[0080] It should be noted that, in this embodiment, before performing the patterning process, the mask layer 201 is removed; the epitaxial layer 212 is planarized until the top surface of the substrate 200 is exposed.
[0081] In this embodiment, during the formation of the first fin 213 and the second fin 214, the process further includes: performing a patterning process on the third region III of the substrate 200, so that the third region III of the substrate 200 forms a plurality of mutually discrete third fins 215.
[0082] In this embodiment, the first fin 213 is used to form an NMOS transistor; the second fin 214 is used to form a PMOS transistor. Since the material of the second fin 214 is silicon-germanium, by using the second fin 214 as the channel region of the formed PMOS transistor, the hole mobility can be effectively improved, thereby improving the performance of the final semiconductor structure.
[0083] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region and a second region adjacent to each other, the second region including a first edge region and a middle region, and the first edge region being adjacent to the first region; A first edge groove is formed in the first edge region, and the first edge groove has a first aspect ratio. A first edge layer is filled within the first edge trench, the material of the first edge layer being different from the material of the substrate; An intermediate trench is formed within the intermediate region, the intermediate trench exposing the sidewall of the first edge layer; The first edge layer is removed to form an epitaxial trench, the epitaxial trench including the first edge trench and the intermediate trench, the epitaxial trench having a second aspect ratio, the first aspect ratio being greater than the second aspect ratio; An epitaxial layer is formed within the epitaxial trench, and the material of the epitaxial layer is different from the material of the substrate. The first region of the substrate and the epitaxial layer are patterned to form a plurality of mutually discrete first fins in the first region of the substrate and a plurality of mutually discrete second fins in the epitaxial layer.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate further includes: a third region, wherein the second region is located between the first region and the third region; the second region further includes: a second edge region, wherein the middle region is located between the first edge region and the second edge region, and the second edge region is adjacent to the third region.
3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process of forming the first edge groove also includes: forming a second edge groove in the second edge region, the second edge groove having a third aspect ratio, the first aspect ratio and the third aspect ratio being equal.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The process of forming the first edge layer also includes: filling the second edge trench with a second edge layer, wherein the material of the first edge layer is the same as the material of the second edge layer.
5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The intermediate trench also exposes the sidewalls of the second edge layer.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The process of removing the first edge layer also includes: removing the second edge layer; the epitaxial trench further includes the second edge trench.
7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The second aspect ratio ranges from 0.05 to 0.
40.
8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first aspect ratio ranges from 1.5 to 6.
0.
9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first edge layer includes silicon oxide.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, A method for forming a first edge trench within a first edge region includes: forming a mask layer on a substrate; forming a first photoresist layer on the mask layer, the first photoresist layer exposing a top surface of the mask layer located on a second region; forming a first sacrificial layer on a sidewall of the first photoresist layer, the first sacrificial layer covering the top surface of the mask layer located on the first edge region, and the material of the first sacrificial layer being different from the materials of the first photoresist layer and the mask layer; forming a second photoresist layer covering the top surface of the mask layer located on an intermediate region; removing the first sacrificial layer; and using the first photoresist layer and the second photoresist layer as masks, etching the mask layer and the first edge region to form the first edge trench.
11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The material of the first sacrificial layer includes silicon oxide; the material of the mask layer includes silicon nitride.
12. The method for forming a semiconductor structure as described in claim 10, characterized in that, A method for forming a first sacrificial layer on the sidewall of the first photoresist layer includes: forming a sacrificial material layer on the top surface of the mask layer located on the second region, the sidewall of the first photoresist layer, and the top surface of the first photoresist layer; and etching back the sacrificial material layer until the top surface of the first photoresist layer and the mask layer is exposed to form the first sacrificial layer.
13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process for forming the sacrificial material layer includes atomic layer deposition.
14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The epitaxial layer is formed in the epitaxial trench using an epitaxial growth process.
15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate is made of silicon; the epitaxial layer is made of silicon-germanium.
16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first fin is used to form an NMOS transistor; the second fin is used to form a PMOS transistor.