Encoder and method of operation thereof, control apparatus and readable storage medium

Abstract

The application provides an encoder, a running method thereof, a control device and a readable storage medium. The encoder comprises a microcontroller, the microcontroller has a wake-up port, a first communication port, a second communication port and a third communication port, the wake-up port is used for receiving a wake-up signal, the first communication port is used for receiving a first power supply signal, the second communication port is used for receiving a first detection signal, and the third communication port is used for receiving a second detection signal; a combination circuit is used for generating the wake-up signal according to the first power supply signal and the first detection signal, the combination circuit comprises a first input end used for receiving the first power supply signal, a second input end used for receiving the first detection signal, a third input end used for receiving the first detection signal, and an output end connected with the wake-up port of the microcontroller and used for sending the wake-up signal to the microcontroller. The power supply signal and the detection signal are integrated into the wake-up signal, so that the microcontroller only needs one wake-up port.

Description

Technical Field

[0001] This invention relates to the field of encoder technology, and more specifically, to an encoder, its operating method, control device, and readable storage medium. Background Technology

[0002] In existing technologies, to ensure multi-turn operation, the encoder requires the microcontroller to enter sleep mode after power failure. Then, the microcontroller needs to be woken up to count after the multi-turn signal is triggered, and it also needs to be woken up again upon power-on. Therefore, the selection of the microcontroller is highly restrictive. For microcontrollers that can be triggered by both rising and falling edges, two wake-up ports are required; for microcontrollers triggered by only a single edge, three wake-up ports are required. Microcontrollers with these resources are generally large in size and expensive, which is detrimental to the overall cost control of the encoder. Summary of the Invention

[0003] The present invention aims to solve or improve at least one of the above-mentioned technical problems.

[0004] Therefore, the first objective of the present invention is to provide an encoder.

[0005] A second objective of this invention is to provide a method for operating an encoder.

[0006] A third objective of this invention is to provide a control device for an encoder.

[0007] The fourth objective of this invention is to provide a control device for an encoder.

[0008] The fifth objective of this invention is to provide a readable storage medium.

[0009] To achieve the first objective of this invention, the technical solution of this invention provides an encoder, comprising: a microcontroller having a wake-up port, a first communication port, a second communication port, and a third communication port, wherein the wake-up port is used to receive a wake-up signal, the first communication port is used to receive a first power signal, the second communication port is used to receive a first detection signal, and the third communication port is used to receive a second detection signal; and a combination circuit for generating a wake-up signal based on the first power signal and the first detection signal, the combination circuit comprising: a first input terminal for receiving the first power signal; a second input terminal for receiving the first detection signal; a third input terminal for receiving the first detection signal; and an output terminal connected to the wake-up port of the microcontroller for sending a wake-up signal to the microcontroller; in response to the wake-up port being triggered by the wake-up signal, the microcontroller performs a target operation based on the signal reception status of the first communication port, the second communication port, and the third communication port.

[0010] The encoder provided by this invention includes a microcontroller and a combinational circuit. The microcontroller has a wake-up port, a first communication port, a second communication port, and a third communication port. The wake-up port can receive a wake-up signal; when the wake-up port is triggered, the microcontroller is awakened. The first communication port can receive a first power signal. The second communication port can receive a first detection signal. The third communication port can receive a second detection signal. The combinational circuit has a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal receives the first power signal, and the second and third input terminals both receive the first detection signal. The first power signal and the first detection signal are combined into a wake-up signal in the combinational circuit and sent to the wake-up port of the microcontroller through the output terminal of the combinational circuit. When the wake-up port of the microcontroller is triggered by the wake-up signal, the microcontroller obtains the current signal reception status of the first, second, and third communication ports and performs a target operation based on the current signal reception status of the first, second, and third communication ports. The first and second detection signals can be the same motor signal, but their phases are different.

[0011] This invention utilizes a combinational circuit to combine a power signal and a motor signal, which can wake up a microcontroller, into a single wake-up signal, which is then sent to the microcontroller's wake-up port. This allows the wake-up port to be triggered by the wake-up signal when the power is on, thereby waking up the microcontroller. Similarly, the wake-up signal can be triggered when a motor signal is detected, waking up the microcontroller as well. This eliminates the need for a single wake-up port for the microcontroller. Simultaneously, the microcontroller's first, second, and third communication ports acquire the first power signal, the first detection signal, and the second detection signal, respectively. Once awakened by the wake-up signal, the microcontroller can determine whether it is currently powered on or has detected a motor signal based on the signal reception status of these ports, thus executing the operations initiated by power-on or motor signal detection, satisfying all encoder operating conditions. The encoder provided by this invention allows the use of a microcontroller with only one wake-up port, thereby reducing the overall cost of the encoder.

[0012] In addition, the technical solution provided by this invention may also have the following additional technical features:

[0013] In some technical solutions, optionally, the combinational circuit includes: a first logic gate circuit having a first input terminal, a second input terminal, and an output terminal, the output terminal of the first logic gate circuit being connected to the wake-up port of the microcontroller; a first conversion circuit for converting a first power supply signal into a second power supply signal; the output terminal of the first conversion circuit being connected to the first input terminal of the first logic gate circuit; a second conversion circuit for converting a first detection signal into a third detection signal; the output terminal of the second conversion circuit being connected to the second input terminal of the first logic gate circuit; wherein, the first logic gate circuit is capable of generating a wake-up signal based on the second power supply signal and the third detection signal.

[0014] In this technical solution, the combinational circuit may include a first logic gate circuit, a first conversion circuit, and a second conversion circuit. The first logic gate circuit includes a first input terminal, a second input terminal, and an output terminal. The output terminal of the first logic gate circuit serves as the output terminal of the combinational circuit and is connected to the wake-up port of the microcontroller to transmit the wake-up signal to the microcontroller. The first conversion circuit includes an input terminal and an output terminal. The input terminal of the first conversion circuit can serve as the first input terminal of the combinational circuit, receiving a first power signal. The first power signal is a steady-state signal, meaning it only changes when the power supply is switched on or off. Therefore, the first power signal needs to be input into the first conversion circuit, which converts the steady-state first power signal into a metastable second power signal. Since the output terminal of the first conversion circuit is connected to the first input terminal of the first logic gate circuit, the second power signal can enter the first logic gate circuit. The second conversion circuit includes an input terminal and an output terminal. The second conversion circuit can have two input terminals, serving as the second and third input terminals of the combinational circuit, respectively, receiving a first detection signal. Since the first detection signal can be a motor signal, which is a square wave signal, it needs to be converted. Two first detection signals are input to a second conversion circuit. The second conversion circuit converts the two square wave signals into a rising edge signal, i.e., converts the first detection signal into a third detection signal. Since the output of the second conversion circuit is connected to the second input of the first logic gate circuit, the third detection signal can enter the first logic gate circuit through the second input. The first logic gate circuit can generate a trigger signal based on the second power supply signal and the third detection signal, and send it to the wake-up port of the microcontroller to wake up the microcontroller. Specifically, the first logic gate circuit can be an OR gate circuit, thus enabling the combinational circuit to uniformly convert the steady-state power supply signal and the square wave motor signal into rising edge signals with different pulse widths, i.e., wake-up signals. This allows the microcontroller to be woken up by a single wake-up signal when the power is turned on and / or when the motor signal is triggered.

[0015] In some technical solutions, optionally, the first conversion circuit includes: a first resistor; a first capacitor, one end of the first capacitor being connected to the first resistor, and the other end of the first capacitor being connected to the first input terminal of the first logic gate circuit.

[0016] In this technical solution, the first conversion circuit includes a first resistor and a first capacitor. Through the series connection of the first resistor and the first capacitor, a steady-state first power supply signal is converted into a metastable second power supply signal. Specifically, one end of the first resistor serves as the input terminal of the first conversion circuit, receiving the first power supply signal. The other end of the first resistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the first input terminal of a first logic gate circuit, used to input the converted second power supply signal into the first logic gate circuit. The time parameter in the second power supply signal is determined by the parameters of the first resistor and the first capacitor.

[0017] In some technical solutions, optionally, the second conversion circuit includes: a second logic gate circuit having a first input terminal, a second input terminal, and an output terminal; the first input terminal of the second logic gate circuit is used to receive a first detection signal, and the output terminal of the second logic gate circuit is connected to the second input terminal of the first logic gate circuit; a delay circuit for converting the first detection signal into a fourth detection signal, and the output terminal of the delay circuit is connected to the second input terminal of the second logic gate circuit; wherein, the second logic gate circuit is capable of generating a third detection signal based on the first detection signal and the fourth detection signal.

[0018] In this technical solution, the second conversion circuit includes a second logic gate circuit and a delay circuit. The input terminal of the delay circuit serves as the third input terminal of the combinational circuit, receiving the first detection signal and delaying it to change its phase, thus forming a fourth detection signal. The second logic gate circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second logic gate circuit serves as the second input terminal of the combinational circuit, receiving the first detection signal. The second input terminal of the second logic gate circuit is connected to the output terminal of the delay circuit, receiving the fourth detection signal. The second logic gate circuit can generate a third detection signal based on the first and fourth detection signals. Specifically, the second logic gate circuit can be an XOR gate circuit. By combining the delay circuit and the XOR gate circuit, the square wave signal is transformed into a rising edge signal.

[0019] In some technical solutions, the delay circuit may optionally include: a second resistor, the first end of which receives a first detection signal, and the second end of which is connected to the second input terminal of a second logic gate circuit; and a second capacitor, one end of which is connected to the second end of the second resistor, and the other end of which is grounded.

[0020] In this technical solution, the delay circuit includes a second resistor and a second capacitor. The first end of the second resistor serves as the input terminal of the delay circuit, receiving the first detection signal. The second end of the second resistor is connected to the second input terminal of the second logic gate circuit and one end of the second capacitor, while the other end of the second capacitor is grounded. The delay circuit composed of the second resistor and the second capacitor can delay the first detection signal, thereby generating a fourth detection signal with a phase difference from the first detection signal.

[0021] In some technical solutions, the combined circuit may optionally include: a diode, the negative terminal of which is connected to the output terminal of the first conversion circuit, and the positive terminal of which is grounded; and a third resistor, one end of which is connected to the output terminal of the first conversion circuit, and the other end of which is grounded.

[0022] In this technical solution, the combined circuit also includes a diode and a third resistor. The cathode of the diode is connected to the output terminal of the first conversion circuit, and the anode is grounded, providing directional protection for the second power signal output by the first conversion circuit. One end of the third resistor is connected to the output terminal of the first conversion circuit, and the other end is grounded. The third resistor provides a discharge path for the current in the first capacitor in the first conversion circuit, thereby improving the power detection response. Specifically, the diode can be replaced with other protection devices, and the third resistor can be replaced with a discharge circuit.

[0023] In some technical solutions, the encoder may optionally further include: a power detection circuit, the output of which is connected to a first communication port of the microcontroller and a first input of the combinational circuit, for sending a first power signal to the microcontroller and the combinational circuit; a first detection circuit, the output of which is connected to a second communication port of the microcontroller, a second input of the combinational circuit, and a third input of the combinational circuit, for sending a first detection signal to the microcontroller and the combinational circuit; and a second detection circuit, the output of which is connected to a third communication port of the microcontroller, for sending a second detection signal to the microcontroller.

[0024] In this technical solution, the encoder also includes a power detection circuit, a first detection circuit, and a second detection circuit. The power detection circuit detects whether the power supply is on or off and generates a first power signal. The output of the power detection circuit is connected to the first communication port of the microcontroller and the first input of the combination circuit, enabling the power detection circuit to send the first power signal to the microcontroller and the combination circuit. The first detection circuit detects the rotation of the motor and generates a first detection signal. The output of the first detection circuit is connected to the second communication port of the microcontroller, the second input of the combination circuit, and the third input of the combination circuit, enabling the first detection circuit to send the first detection signal to the microcontroller and the combination circuit. The second detection circuit detects the rotation of the motor and generates a second detection signal. The output of the second detection circuit is connected to the third communication port of the microcontroller, enabling the second detection circuit to send the second detection signal to the microcontroller. The first and second detection signals pertain to the same motor and have a 90-degree phase difference, ensuring that the encoder can count when the motor is rotating forward and backward.

[0025] To achieve the second objective of this invention, the technical solution of this invention provides an encoder operation method for the encoder in any of the above-described technical solutions. The operation method includes: in response to a wake-up signal triggering a wake-up port, acquiring the signal reception states of a first communication port, a second communication port, and a third communication port; and performing a target operation based on the signal reception states of the first communication port, the second communication port, and the third communication port.

[0026] This invention provides an encoder operation method for encoders used in any of the above-described technical solutions. When the microcontroller's trigger port is activated by a wake-up signal, the microcontroller is awakened. However, since the wake-up signal is a combination of a first power signal and a first detection signal, there can be multiple reasons for the microcontroller to be awakened, such as power-triggered or motor-triggered. To determine the specific cause, the microcontroller needs to acquire the signal reception status of the first communication port, the second communication port, and the third communication port, i.e., the current status of the first power signal, the first detection signal, and the second detection signal. The first power signal indicates the power supply status, and the first and second detection signals indicate the motor status. Therefore, the microcontroller can determine the specific reason for its wake-up based on the signal reception status of the first, second, and third communication ports, and then execute the target operation corresponding to that reason. This invention enables a microcontroller with only one wake-up port to perform encoder operations.

[0027] In some technical solutions, optionally, the step of performing the target operation based on the signal reception status of the first communication port, the second communication port, and the third communication port includes: determining whether to perform the first operation based on the signal reception status of the first communication port being in a triggered state, and entering the running mode; and performing the first operation based on the signal reception status of the first communication port being in a non-triggered state, and entering the sleep mode.

[0028] In this technical solution, when the signal reception state of the first communication port is in the triggered state, i.e., the current state of the first power signal is high, it indicates that the microcontroller is woken up due to power-on, and therefore the microcontroller enters the operating mode. However, when power-on and motor triggering occur simultaneously, the microcontroller will also be woken up. Therefore, the microcontroller also needs to obtain the signal reception states of the second and third communication ports and determine whether there is still motor triggering based on the states of the second and third communication ports, thereby determining whether to execute the first operation. When the signal reception state of the first communication port is in the non-triggered state, i.e., the current state of the first power signal is low, it indicates that the current power supply is down. In this case, the reason for the microcontroller being woken up can only be motor triggering. Therefore, the microcontroller needs to execute the first operation and then enter sleep mode.

[0029] In some technical solutions, optionally, the step of determining whether to perform the first operation based on the signal reception status of the second communication port and the third communication port includes: obtaining a first relationship between the signal reception status of the second communication port and the third communication port and the previous signal reception status; not performing the first operation if the signal reception status of the second communication port and the third communication port is the same as the previous signal reception status; and performing the first operation if the signal reception status of the second communication port and the third communication port is different from the previous signal reception status.

[0030] In this technical solution, the step of determining whether to execute the first operation based on the signal reception states of the second and third communication ports includes: obtaining a first relationship between the signal reception states of the second and third communication ports and their signal reception states when the microcontroller was previously woken up, wherein the first relationship is that the signal reception states of the second and third communication ports are the same as or different from their signal reception states when the microcontroller was previously woken up. It is understood that the first detection signal and the second detection signal have two consecutive different states, namely high level and low level. Furthermore, since the first detection signal and the second detection signal are 90 degrees out of phase, when the microcontroller is woken up by a motor, the signal reception states of the second and third communication ports will have four consecutive different states. Therefore, when the signal reception states of the second and third communication ports are the same as their signal reception states when the microcontroller was previously woken up, it indicates that the microcontroller was not woken up by a motor, and therefore the microcontroller does not execute the first operation. When the signal reception states of the second and third communication ports are different from those when the microcontroller was woken up the previous time, it indicates that the microcontroller was woken up by the motor, and therefore the microcontroller performs the first operation.

[0031] In some technical solutions, optionally, the first operation includes: obtaining a second relationship between the signal reception status of the second communication port and the third communication port and the historical signal reception status; recording the number of cycles based on the fact that the signal reception status of the second communication port and the third communication port is the same as the historical signal reception status; and recording the signal reception status of the first communication port, the second communication port, and the third communication port based on the fact that the signal reception status of the second communication port and the third communication port is different from the historical signal reception status.

[0032] In this technical solution, the first operation includes: acquiring a second relationship between the signal reception states of the second and third communication ports and historical signal reception states. The historical signal reception states are the first recorded signal reception states of the second and third communication ports by the microcontroller, and the second relationship is whether the signal reception states of the second and third communication ports are the same as or different from the first recorded signal reception states. It can be understood that for every one revolution of the motor, the signal reception states of the second and third communication ports will exhibit four consecutive different states. Therefore, when the signal reception states of the second and third communication ports are the same as the first recorded signal reception states, it indicates that the motor has completed one revolution, and the microcontroller records the revolution count. When the signal reception states of the second and third communication ports are different from the first recorded signal reception states, it indicates that the motor has not yet completed one revolution, and the microcontroller does not record the revolution count, but only records the current signal reception states of the first, second, and third communication ports.

[0033] In some technical solutions, optionally, the step of recording the number of cycles based on the fact that the signal reception states of the second and third communication ports are the same as the historical signal reception states includes: obtaining a third relationship between the changes in the signal reception states of the second and third communication ports and the preset changes in the signal reception states; incrementing the number of cycles by one based on the fact that the changes in the signal reception states of the second and third communication ports are the same as the preset changes in the signal reception states; and decrementing the number of cycles by one based on the fact that the changes in the signal reception states of the second and third communication ports are different from the preset changes in the signal reception states.

[0034] In this technical solution, the microcontroller's counting steps are as follows: It acquires a third relationship between the signal reception status changes of the second and third communication ports and a preset signal reception status change. The signal reception status change of the second and third communication ports refers to the change from the previous signal reception status to the current signal reception status. The preset signal reception status change can be the change in the signal reception status of the second and third communication ports when the motor is rotating forward. When the signal reception status changes of the second and third communication ports are the same as the preset signal reception status change, it indicates that the motor is rotating forward, so the microcontroller increments the revolution count by one. When the signal reception status changes of the second and third communication ports are different from the preset signal reception status change, it indicates that the motor is rotating in reverse, so the microcontroller decrements the revolution count by one.

[0035] To achieve the third objective of this invention, the technical solution of this invention provides a control device for an encoder, used in any of the above-described technical solutions. The control device includes: a first acquisition module, configured to acquire the signal reception status of a first communication port, a second communication port, and a third communication port in response to a wake-up signal; and a first execution module, configured to execute a target operation based on the signal reception status of the first communication port, the second communication port, and the third communication port.

[0036] This invention provides a control device for an encoder, used in any of the aforementioned technical solutions. It includes a first acquisition module and a first execution module. When the microcontroller's trigger port is activated by a wake-up signal, the microcontroller is awakened. However, since the wake-up signal is a combination of a power signal and a motor signal, there can be multiple reasons for the microcontroller to be awakened, such as power-triggered or motor-triggered. To determine the specific cause, the first acquisition module needs to acquire the signal reception status of the first communication port, the second communication port, and the third communication port, i.e., the current status of the first power signal, the first detection signal, and the second detection signal. The first power signal indicates the power supply status, and the first and second detection signals indicate the motor status. Therefore, the microcontroller can determine the specific reason for its awakening based on the signal reception status of the first, second, and third communication ports, and then the first execution module performs the target operation corresponding to that reason.

[0037] To achieve the fourth objective of this invention, the technical solution of this invention provides a control device for an encoder, comprising: a memory and a processor, wherein the memory stores a program or instructions, and the processor executes the program or instructions; wherein, when the processor executes the program or instructions, it implements the steps of the encoder operation method as described in any technical solution of this invention.

[0038] The encoder control device provided by this technical solution implements the steps of the encoder operation method of any technical solution of the present invention, and therefore has all the beneficial effects of the encoder operation method of any technical solution of the present invention, which will not be repeated here.

[0039] To achieve the fifth objective of this invention, the technical solution of this invention provides a readable storage medium that stores a program or instructions, which, when executed, implement the steps of the encoder operation method of any of the above technical solutions.

[0040] The readable storage medium provided by this technical solution implements the steps of the encoder operation method of any technical solution of the present invention, and therefore has all the beneficial effects of the encoder operation method of any technical solution of the present invention, which will not be repeated here.

[0041] Additional aspects and advantages of the invention will become apparent in the following description or may be learned by practice of the invention. Attached Figure Description

[0042] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0043] Figure 1 This is a schematic diagram of the structure of an encoder according to an embodiment of the present invention;

[0044] Figure 2 This is a schematic diagram of a combinational circuit according to an embodiment of the present invention;

[0045] Figure 3 This is one of the flowcharts illustrating an encoder operation method according to an embodiment of the present invention;

[0046] Figure 4 This is a second schematic flowchart of an encoder operation method according to an embodiment of the present invention;

[0047] Figure 5 This is a third flowchart illustrating an encoder operation method according to an embodiment of the present invention;

[0048] Figure 6 This is a fourth flowchart illustrating an encoder operation method according to an embodiment of the present invention;

[0049] Figure 7 This is a fifth flowchart illustrating an encoder operation method according to an embodiment of the present invention.

[0050] Figure 8 This is a sixth flowchart illustrating an encoder operation method according to an embodiment of the present invention;

[0051] Figure 9 A timing diagram of signals received by a microcontroller according to an embodiment of the present invention;

[0052] Figure 10 This is one of the structural block diagrams of an encoder control device according to an embodiment of the present invention;

[0053] Figure 11 This is a second structural block diagram of an encoder control device according to an embodiment of the present invention.

[0054] in, Figure 1 and Figure 2 The correspondence between the reference numerals and component names in the attached drawings is as follows:

[0055] 10 Encoder, 102 Microcontroller, 1022 Wake-up Port, IO1 First Communication Port, IO2 Second Communication Port, IO3 Third Communication Port, 104 Combinational Circuit, DI1 First Input Terminal of Combinational Circuit, DI2 Second Input Terminal of Combinational Circuit, DI3 Third Input Terminal of Combinational Circuit, DO1 Output Terminal of Combinational Circuit, 1042 First Logic Gate Circuit, CH1 First Input Terminal of First Logic Gate Circuit, CH2 Second Input Terminal of First Logic Gate Circuit, OUT1 Output Terminal of First Logic Gate Circuit, 1044 First Conversion Circuit, R1 First Resistor, C1 First Capacitor, 1046 Second Conversion Circuit, 1048 Second Logic Gate Circuit, CH3 First Input Terminal of Second Logic Gate Circuit, CH4 Second Input Terminal of Second Logic Gate Circuit, OUT2 Output Terminal of Second Logic Gate Circuit, 1050 Delay Circuit, R2 Second Resistor, C2 Second Capacitor, D1 Diode, R3 Third Resistor, 106 Power Supply Detection Circuit, 108 First Detection Circuit, 110 Second Detection Circuit. Detailed Implementation

[0056] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0057] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0058] The following reference Figures 1 to 11 This invention describes encoders, their operation methods, control devices, and readable storage media according to some embodiments of the present invention.

[0059] like Figure 1 and Figure 2As shown, the technical solution of the present invention provides an encoder 10, including: a microcontroller 102, the microcontroller 102 having a wake-up port 1022, a first communication port IO1, a second communication port IO2, and a third communication port IO3, the wake-up port 1022 being used to receive a wake-up signal, the first communication port IO1 being used to receive a first power signal, the second communication port IO2 being used to receive a first detection signal, and the third communication port IO3 being used to receive a second detection signal; a combination circuit 104 being used to generate a wake-up signal based on the first power signal and the first detection signal, the combination circuit 104 including: a first input terminal DI1 being used to receive the first power signal; a second input terminal DI2 being used to receive the first detection signal; a third input terminal DI3 being used to receive the first detection signal; and an output terminal DO1 being connected to the wake-up port 1022 of the microcontroller 102 and used to send a wake-up signal to the microcontroller 102; in response to the wake-up port 1022 being triggered by the wake-up signal, the microcontroller 102 performs a target operation based on the signal reception status of the first communication port IO1, the second communication port IO2, and the third communication port IO3.

[0060] The encoder 10 provided by this invention includes a microcontroller 102 and a combinational circuit 104. The microcontroller 102 has a wake-up port 1022, a first communication port IO1, a second communication port IO2, and a third communication port IO3. The wake-up port 1022 can receive a wake-up signal and be triggered by the wake-up signal, thereby waking up the microcontroller 102. The first communication port IO1 can receive a first power signal. The second communication port IO2 can receive a first detection signal. The third communication port IO3 can receive a second detection signal. The combinational circuit 104 has a first input terminal DI1, a second input terminal DI2, a third input terminal DI3, and an output terminal DO1. The first input terminal DI1 of the combinational circuit 104 can receive the first power signal, and the second input terminal DI2 and the third input terminal DI3 of the combinational circuit 104 both receive the first detection signal. The first power signal and the first detection signal are combined into a wake-up signal in the combinational circuit 104 and sent to the wake-up port 1022 of the microcontroller 102 through the output terminal DO1 of the combinational circuit 104. When the wake-up port 1022 of the microcontroller 102 is triggered by a wake-up signal, the microcontroller 102 acquires the signal reception status of its first communication port IO1, second communication port IO2, and third communication port IO3, and executes the target operation based on these statuses. The first detection signal and the second detection signal can be the same motor signal, but their phases are different.

[0061] This invention utilizes a combination circuit 104 to combine a power signal and a motor signal that can wake up the microcontroller 102 into a single wake-up signal, which is then sent to the wake-up port 1022 of the microcontroller 102. This allows the wake-up port 1022 to be triggered by the wake-up signal when the power is on, thereby waking up the microcontroller 102. Similarly, the wake-up port 1022 can be triggered by the wake-up signal when a motor signal is detected, thus requiring only one wake-up port 1022 for the microcontroller 102. Simultaneously, the first communication port IO1, the second communication port IO2, and the third communication port IO3 of the microcontroller 102 acquire the first power signal, the first detection signal, and the second detection signal, respectively. When the microcontroller 102 is woken up by the wake-up signal, it can determine whether the current state is power-on or a motor signal has been detected based on the signal reception status of the first communication port IO1, the second communication port IO2, and the third communication port IO3, and then execute the operation performed after power-on or after motor signal detection, thereby satisfying all operating conditions of the encoder 10. The encoder 10 provided by the present invention can use a microcontroller 102 with only one wake-up port 1022, thereby saving the overall cost of the encoder 10.

[0062] In some embodiments, optionally, the combinational circuit 104 includes: a first logic gate circuit 1042, the first logic gate circuit 1042 having a first input terminal CH1, a second input terminal CH2, and an output terminal OUT1, the output terminal OUT1 being connected to the wake-up port 1022 of the microcontroller 102; a first conversion circuit 1044 for converting a first power signal into a second power signal; the output terminal of the first conversion circuit 1044 being connected to the first input terminal CH1 of the first logic gate circuit 1042; a second conversion circuit 1046 for converting a first detection signal into a third detection signal; the output terminal of the second conversion circuit 1046 being connected to the second input terminal CH2 of the first logic gate circuit 1042; wherein, the first logic gate circuit 1042 is capable of generating a wake-up signal based on the second power signal and the third detection signal.

[0063] In this embodiment, the combinational circuit 104 may include a first logic gate circuit 1042, a first conversion circuit 1044, and a second conversion circuit 1046. The first logic gate circuit 1042 includes a first input terminal CH1, a second input terminal CH2, and an output terminal OUT1. The output terminal OUT1 serves as the output terminal DO1 of the combinational circuit and is connected to the wake-up port 1022 of the microcontroller 102 to transmit a wake-up signal to the microcontroller 102. The first conversion circuit 1044 includes an input terminal and an output terminal. The input terminal of the first conversion circuit 1044 can serve as the first input terminal DI1 of the combinational circuit, receiving a first power signal. The first power signal is a steady-state signal, meaning it only changes when the power supply is powered on or off. Therefore, by inputting the first power signal into the first conversion circuit 1044, the first conversion circuit 1044 can convert the steady-state first power signal into a metastable second power signal. Since the output of the first conversion circuit 1044 is connected to the first input CH1 of the first logic gate circuit, the second power supply signal can enter the first logic gate circuit 1042. The second conversion circuit 1046 includes input and output terminals. The second conversion circuit 1046 can have two input terminals, serving as the second input DI2 and the third input DI3 of the combinational circuit, respectively, to receive the first detection signal. Since the first detection signal can be a motor signal, it is a square wave signal. Therefore, it needs to be converted. By inputting the two first detection signals into the second conversion circuit 1046, the second conversion circuit 1046 can convert the two square wave signals into rising edge signals, that is, convert the first detection signal into the third detection signal. Since the output of the second conversion circuit 1046 is connected to the second input CH2 of the first logic gate circuit, the third detection signal can enter the first logic gate circuit 1042 through the second input CH2. The first logic gate circuit 1042 can generate a trigger signal based on the second power signal and the third detection signal, and send it to the wake-up port 1022 of the microcontroller 102 to wake up the microcontroller 102. Specifically, the first logic gate circuit 1042 can be an OR gate circuit, thereby enabling the combinational circuit 104 to uniformly convert the steady-state power signal and the square wave motor signal into rising edge signals with different pulse widths, i.e., wake-up signals. This allows the microcontroller 102 to be woken up by a single wake-up signal when the power is turned on and / or the motor signal is triggered.

[0064] In some embodiments, the first conversion circuit 1044 may optionally include: a first resistor R1; a first capacitor C1, one end of the first capacitor C1 being connected to the first resistor R1, and the other end of the first capacitor C1 being connected to the first input terminal CH1 of the first logic gate circuit 1042.

[0065] In this embodiment, the first conversion circuit 1044 includes a first resistor R1 and a first capacitor C1. Through the series connection of the first resistor R1 and the first capacitor C1, a steady-state first power supply signal is converted into a metastable second power supply signal. Specifically, one end of the first resistor R1 can serve as the input terminal of the first conversion circuit 1044, i.e., receiving the first power supply signal. The other end of the first resistor R1 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the first input terminal CH1 of the first logic gate circuit, used to input the converted second power supply signal into the first logic gate circuit 1042. The time parameter in the second power supply signal is determined by the parameters of the first resistor R1 and the first capacitor C1.

[0066] In some embodiments, optionally, the second conversion circuit 1046 includes: a second logic gate circuit 1048, the second logic gate circuit 1048 having a first input terminal CH3, a second input terminal CH4, and an output terminal OUT2, the first input terminal CH3 being used to receive a first detection signal, and the output terminal OUT2 being connected to the second input terminal CH2 of the first logic gate circuit; a delay circuit 1050, used to convert the first detection signal into a fourth detection signal, the output terminal of the delay circuit 1050 being connected to the second input terminal CH4 of the second logic gate circuit; wherein, the second logic gate circuit 1048 is capable of generating a third detection signal based on the first detection signal and the fourth detection signal.

[0067] In this embodiment, the second conversion circuit 1046 includes a second logic gate circuit 1048 and a delay circuit 1050. The input terminal of the delay circuit 1050 serves as the third input terminal DI3 of the combinational circuit, receiving the first detection signal and delaying it to change its phase, thus forming a fourth detection signal. The second logic gate circuit 1048 includes a first input terminal CH3, a second input terminal CH4, and an output terminal OUT2. The first input terminal CH3 serves as the second input terminal DI2 of the combinational circuit, receiving the first detection signal. The second input terminal CH4 is connected to the output terminal of the delay circuit 1050, receiving the fourth detection signal. The second logic gate circuit 1048 generates a third detection signal based on the first and fourth detection signals. Specifically, the second logic gate circuit 1048 can be an XOR gate circuit. By combining the delay circuit 1050 with the XOR gate circuit, the square wave signal is transformed into a rising edge signal.

[0068] In some embodiments, the delay circuit 1050 may optionally include: a second resistor R2, the first end of which receives a first detection signal, and the second end of which is connected to the second input terminal CH4 of the second logic gate circuit 1048; and a second capacitor C2, one end of which is connected to the second end of the second resistor R2, and the other end of which is grounded.

[0069] In this embodiment, the delay circuit 1050 includes a second resistor R2 and a second capacitor C2. The first terminal of the second resistor R2 serves as the input terminal of the delay circuit 1050, receiving the first detection signal. The second terminal of the second resistor R2 is connected to the second input terminal CH4 of the second logic gate circuit and one terminal of the second capacitor C2, while the other terminal of the second capacitor C2 is grounded. The delay circuit 1050, composed of the second resistor R2 and the second capacitor C2, can delay the first detection signal, thereby generating a fourth detection signal with a phase difference from the first detection signal.

[0070] In some embodiments, the combination circuit 104 may optionally include: a diode D1, the negative terminal of which is connected to the output terminal of the first conversion circuit 1044, and the positive terminal of which is grounded; and a third resistor R3, one end of which is connected to the output terminal of the first conversion circuit 1044, and the other end of which is grounded.

[0071] In this embodiment, the combined circuit 104 further includes a diode D1 and a third resistor R3. The cathode of diode D1 is connected to the output terminal of the first conversion circuit 1044, and the anode is grounded, providing directional protection for the second power signal output by the first conversion circuit 1044. One end of the third resistor R3 is connected to the output terminal of the first conversion circuit 1044, and the other end is grounded. The third resistor R3 can provide a discharge path for the current in the first capacitor C1 in the first conversion circuit 1044, thereby improving the response of the power detection. Specifically, diode D1 can be replaced with other protection devices, and the third resistor R3 can be replaced with a discharge circuit.

[0072] In some embodiments, the encoder 10 may optionally include: a power detection circuit 106, the output of which is connected to the first communication port IO1 of the microcontroller 102 and the first input terminal DI1 of the combination circuit 104, respectively, for sending a first power signal to the microcontroller 102 and the combination circuit 104; a first detection circuit 108, the output of which is connected to the second communication port IO2 of the microcontroller 102, the second input terminal DI2 of the combination circuit 104 and the third input terminal DI3 of the combination circuit 104, respectively, for sending a first detection signal to the microcontroller 102 and the combination circuit 104; and a second detection circuit 110, the output of which is connected to the third communication port IO3 of the microcontroller 102, for sending the second detection signal to the microcontroller 102.

[0073] In this embodiment, the encoder 10 further includes a power detection circuit 106, a first detection circuit 108, and a second detection circuit 110. The power detection circuit 106 can detect whether the power supply is on or off and generate a first power signal. The output terminal of the power detection circuit 106 is connected to the first communication port IO1 of the microcontroller 102 and the first input terminal DI1 of the combination circuit, thereby enabling the power detection circuit 106 to send the first power signal to the microcontroller 102 and the combination circuit 104. The first detection circuit 108 can detect the rotation of the motor and generate a first detection signal. The output terminal of the first detection circuit 108 is connected to the second communication port IO2 of the microcontroller 102, the second input terminal DI2 of the combination circuit, and the third input terminal DI3 of the combination circuit, thereby enabling the first detection circuit 108 to send the first detection signal to the microcontroller 102 and the combination circuit 104. The second detection circuit 110 can detect the rotation of the motor and generate a second detection signal. The output terminal of the second detection circuit 110 is connected to the third communication port IO3 of the microcontroller 102, so that the second detection circuit 110 can send the second detection signal to the microcontroller 102. The first and second detection signals are from the same motor, and there is a 90-degree phase difference between them, ensuring that the encoder 10 can count when the motor is rotating forward and backward.

[0074] In some embodiments, optionally, the first logic gate 1042 can be an OR gate, and the second logic gate 1048 can be an XOR gate. The microcontroller 102 is set to rise-edge triggering, causing it to enter the running mode from the sleep mode. Table 1 is the logic truth table of the combinational circuit 104. In Table 1, L represents a low-level state, and H represents a high-level state. As can be seen from Table 1, when the first input terminal DI1 of the combinational circuit 104 receives a power-down signal, the second input terminal DI2 of the combinational circuit 104 receives a hold signal, the first input terminal CH3 of the second logic gate in the combinational circuit 104 receives a low-level signal, and the second input terminal CH4 of the second logic gate in the combinational circuit 104 receives a low-level signal, then the first input terminal CH1 of the first logic gate in the combinational circuit 104 receives a low-level signal, and the second input terminal CH2 of the first logic gate in the combinational circuit 104 receives a low-level signal. Therefore, the final output terminal DO1 of the combinational circuit 104 outputs a low-level signal, i.e., not... The microcontroller 102 is triggered. When the first input terminal DI1 of the combinational circuit receives a power-down signal, the second input terminal DI2 of the combinational circuit receives a falling edge signal, the first input terminal CH3 of the second logic gate circuit in the combinational circuit 104 receives a low-level signal, and the second input terminal CH4 of the second logic gate circuit receives a high-level signal, then the first input terminal CH1 of the first logic gate circuit in the combinational circuit 104 receives a low-level signal, and the second input terminal CH2 of the first logic gate circuit receives a high-level signal. Therefore, the rising edge signal output by the final output terminal DO1 of the combinational circuit, i.e., the signal received by the microcontroller... Triggered by 102; when the first input terminal DI1 of the combinational circuit receives a rising edge signal, the second input terminal DI2 of the combinational circuit receives a rising edge signal, the first input terminal CH3 of the second logic gate circuit in combinational circuit 104 receives a high-level signal, and the second input terminal CH4 of the second logic gate circuit receives a low-level signal, then the first input terminal CH1 of the first logic gate circuit in combinational circuit 104 receives a high-level signal, and the second input terminal CH2 of the first logic gate circuit receives a high-level signal. Therefore, the rising edge signal output by the final output terminal DO1 of the combinational circuit, i.e., the signal triggered by the microcontroller 102, is... Triggering occurs when the first input terminal DI1 of the combinational circuit receives a rising edge signal, the second input terminal DI2 of the combinational circuit receives a hold signal, the first input terminal CH3 of the second logic gate circuit in the combinational circuit 104 receives a high-level signal, and the second input terminal CH4 of the second logic gate circuit in the combinational circuit 104 receives a high-level signal. Then, the first input terminal CH1 of the first logic gate circuit in the combinational circuit 104 receives a high-level signal, and the second input terminal CH2 of the first logic gate circuit receives a low-level signal. Finally, the rising edge signal output by the output terminal DO1 of the combinational circuit triggers the microcontroller 102.Therefore, the present invention utilizes the combination circuit 104 to enable the microcontroller 102 to be triggered regardless of whether the power signal, the motor signal, or both the power signal and the motor signal are rising edges. This allows the microcontroller 102, which has a wake-up port 1022, to also perform the function of the encoder 10.

[0075] Table 1

[0076]

[0077] like Figure 3 As shown, the technical solution of the present invention provides an encoder operation method for the encoder 10 in any of the above embodiments. The operation method includes:

[0078] Step 302: In response to the wake-up signal of the wake-up port, obtain the signal reception status of the first communication port, the second communication port and the third communication port;

[0079] Step 304: Execute the target operation based on the signal reception status of the first communication port, the second communication port, and the third communication port.

[0080] This invention provides an encoder operation method for the encoder 10 in any of the above embodiments. When the trigger port of the microcontroller 102 is triggered by a wake-up signal, the microcontroller 102 is woken up. However, since the wake-up signal is a combination of a first power signal and a first detection signal, there can be multiple reasons for the microcontroller 102 to be woken up, such as power triggering or motor triggering. To determine the specific cause, the microcontroller 102 needs to acquire the signal reception status of the first communication port IO1, the second communication port IO2, and the third communication port IO3, i.e., the current status of the first power signal, the first detection signal, and the second detection signal. The first power signal indicates the power supply status, and the first and second detection signals indicate the motor status. Therefore, the microcontroller 102 can determine the specific reason for being woken up based on the signal reception status of the first communication port IO1, the second communication port IO2, and the third communication port IO3, and then execute the target operation corresponding to that reason. This invention enables a microcontroller 102 with a wake-up port 1022 to also perform the operation of the encoder 10.

[0081] like Figure 4 As shown, the steps for performing the target operation based on the signal reception status of the first communication port, the second communication port, and the third communication port include:

[0082] Step 402: Based on the signal reception status of the first communication port being in a triggered state, determine whether to execute the first operation according to the signal reception status of the second and third communication ports, and enter the running mode;

[0083] Step 404: Based on the fact that the signal reception status of the first communication port is in an untriggered state, perform the first operation and enter sleep mode.

[0084] In this embodiment, when the signal reception state of the first communication port IO1 is in the triggered state, that is, when the current state of the first power signal is high, it indicates that the microcontroller 102 is woken up due to power-on, and therefore the microcontroller 102 enters the running mode. However, when power-on and motor triggering occur simultaneously, the microcontroller 102 will also be woken up. Therefore, the microcontroller 102 also needs to obtain the signal reception states of the second communication port IO2 and the third communication port IO3, and determine whether there is still motor triggering based on the states of the second communication port IO2 and the third communication port IO3, thereby determining whether to execute the first operation. When the signal reception state of the first communication port IO1 is in the non-triggered state, that is, when the current state of the first power signal is low, it indicates that the current power supply is in a power-off state. In this case, the reason for the microcontroller 102 being woken up can only be due to motor triggering. Therefore, the microcontroller 102 needs to execute the first operation and then enter the sleep mode.

[0085] like Figure 5 As shown, the steps for determining whether to perform the first operation based on the signal reception status of the second and third communication ports include:

[0086] Step 502: Obtain the first relationship between the signal reception status of the second and third communication ports and the previous signal reception status;

[0087] Step 504: Since the signal reception status of the second and third communication ports is the same as the previous signal reception status, the first operation is not performed;

[0088] Step 506: Since the signal reception status of the second and third communication ports is different from the previous signal reception status, perform the first operation.

[0089] In this embodiment, a first relationship is obtained between the signal reception states of the second communication port IO2 and the third communication port IO3 and the signal reception states of the second communication port IO2 and the third communication port IO3 when the microcontroller 102 was previously woken up. The first relationship is that the signal reception states of the second communication port IO2 and the third communication port IO3 are the same as or different from the signal reception states of the second communication port IO2 and the third communication port IO3 when the microcontroller 102 is woken up previously. It is understood that the first detection signal and the second detection signal have two consecutive different states, namely high level and low level. Furthermore, since the first detection signal and the second detection signal are 90 degrees out of phase, when the microcontroller 102 is woken up by a motor, the signal reception states of the second communication port IO2 and the third communication port IO3 will have four consecutive different states. Therefore, when the signal reception states of the second communication port IO2 and the third communication port IO3 are the same as the signal reception states of the second communication port IO2 and the third communication port IO3 when the microcontroller 102 was previously woken up, it indicates that the microcontroller 102 was not woken up by a motor, and therefore the microcontroller 102 does not perform the first operation. When the signal reception states of the second communication port IO2 and the third communication port IO3 are different from those when the microcontroller 102 was woken up the previous time, it indicates that the microcontroller 102 was woken up by the motor, and therefore the microcontroller 102 performs the first operation.

[0090] like Figure 6 As shown, the first operation includes:

[0091] Step 602: Obtain the second relationship between the signal reception status of the second communication port and the third communication port and the historical signal reception status;

[0092] Step 604: Based on the fact that the signal reception status of the second and third communication ports is the same as the historical signal reception status, record the number of cycles;

[0093] Step 606: Based on the fact that the signal reception status of the second and third communication ports is different from the historical signal reception status, record the signal reception status of the first, second, and third communication ports.

[0094] In this embodiment, the first operation includes: obtaining a second relationship between the signal reception status of the second communication port IO2 and the third communication port IO3 and the historical signal reception status, wherein the historical signal reception status is the first signal reception status of the second communication port IO2 and the third communication port IO3 recorded by the microcontroller 102, and the second relationship is whether the signal reception status of the second communication port IO2 and the third communication port IO3 is the same as or different from the first signal reception status of the second communication port IO2 and the third communication port IO3. Understandably, for every one revolution of the motor, the signal reception states of the second communication port IO2 and the third communication port IO3 will exhibit four consecutive different states. Therefore, when the signal reception states of the second and third communication ports IO2 and IO3 are the same as the first signal reception states of the second and third communication ports IO2 and IO3, it indicates that the motor has completed one revolution, and the microcontroller 102 records the number of revolutions. When the signal reception states of the second and third communication ports IO2 and IO3 are different from the first signal reception states of the second and third communication ports IO2 and IO3, it indicates that the motor has not yet completed one revolution, and the microcontroller 102 does not record the number of revolutions, but only records the current signal reception states of the first, second, and third communication ports IO1 and IO2.

[0095] like Figure 7 As shown, the steps for recording the number of cycles based on the fact that the signal reception status of the second and third communication ports is the same as the historical signal reception status include:

[0096] Step 702: Obtain the third relationship between the signal reception status changes of the second and third communication ports and the preset signal reception status changes;

[0097] Step 704: Based on the fact that the signal reception status changes of the second and third communication ports are the same as the preset signal reception status changes, increment the number of cycles by one;

[0098] Step 706: Since the signal reception status changes of the second and third communication ports are different from the preset signal reception status changes, the number of cycles is reduced by one.

[0099] In this embodiment, the counting step of the microcontroller 102 is as follows: It acquires a third relationship between the signal reception state changes of the second communication port IO2 and the third communication port IO3 and a preset signal reception state change. The signal reception state change of the second communication port IO2 and the third communication port IO3 refers to the change from the previous signal reception state of the second communication port IO2 and the third communication port IO3 to the current signal reception state of the second communication port IO2 and the third communication port IO3. The preset signal reception state change can be the change in the signal reception state of the second communication port IO2 and the third communication port IO3 when the motor is rotating forward. When the signal reception state change of the second communication port IO2 and the third communication port IO3 is the same as the preset signal reception state change, it indicates that the motor is rotating forward, so the microcontroller 102 increments the revolution count by one when recording the revolution count. When the signal reception state change of the second communication port IO2 and the third communication port IO3 is different from the preset signal reception state change, it indicates that the motor is rotating in reverse, so the microcontroller 102 decrements the revolution count by one when recording the revolution count.

[0100] like Figure 8 As shown, the operation method includes:

[0101] Step 802: Hibernation mode is running;

[0102] Step 804: Wake-up port trigger;

[0103] Step 806: Exit hibernation mode;

[0104] Step 808: Read the status of IO1, IO2, and IO3;

[0105] Step 810: Determine if IO1 is at a high level; if the result is Y, proceed to step 812; if the result is N, proceed to step 828.

[0106] Step 812: Compare the previous states of IO2 and IO3;

[0107] Step 814: Determine if multiple laps are triggered simultaneously; if the result is Y, proceed to step 816; if the result is N, proceed to step 826.

[0108] Step 816: Compare whether it is one lap; if the result is Y, proceed to step 818; if the result is N, proceed to step 824.

[0109] Step 818: Compare whether it is rotating in the correct direction; if the result is Y, proceed to step 820; if the result is N, proceed to step 822.

[0110] Step 820: Increment the lap count by one;

[0111] Step 822: Decrease the number of laps by one;

[0112] Step 824: Save the data;

[0113] Step 826: Enter normal operating mode;

[0114] Step 828: Compare whether it is one lap; if the result is Y, proceed to step 830; if the result is N, proceed to step 836.

[0115] Step 830: Compare whether the rotation is clockwise; if the result is Y, proceed to step 832; if the result is N, proceed to step 834.

[0116] Step 832: Increment the lap count by one;

[0117] Step 834: Decrease the number of laps by one;

[0118] Step 836: Save the data;

[0119] Step 838: Enter hibernation mode.

[0120] In this embodiment, the microcontroller 102 is running in sleep mode. When the wake-up port 1022 of the microcontroller 102 is triggered, the microcontroller 102 exits sleep mode and reads the signal reception status of the first communication port IO1, the second communication port IO2, and the third communication port IO3 of the microcontroller 102. First, it is determined whether the triggering of the wake-up port 1022 of the microcontroller 102 is caused by power-on, that is, whether the first communication port IO1 is currently in a high-level state.

[0121] When the first communication port IO1 is in a high-level state, it indicates that the wake-up port 1022 of the microcontroller 102 is triggered by power-on. Then, the signal reception states of the second communication port IO2 and the third communication port IO3 are compared with the signal reception states of the second communication port IO2 and the third communication port IO3 when the microcontroller 102 was woken up previously, thereby determining whether the motor signal has also triggered the microcontroller 102 at this time.

[0122] Specifically, such as Figure 9As shown, the signal reception states of the second communication port IO2 and the third communication port IO3 can have four consecutive different states: 11, 10, 00, and 01, where the second communication port IO2 is triggered (i.e., the first detection signal is high) and the third communication port IO3 is triggered (i.e., the second detection signal is high); 21, 10, 00, and 01, where the second communication port IO2 is triggered (i.e., the first detection signal is high) and the third communication port IO3 is not triggered (i.e., the second detection signal is low); 22, 10, 00, and 01, where the second communication port IO2 is triggered (i.e., the first detection signal is high) and the third communication port IO3 is not triggered (i.e., the second detection signal is low); and 22, 10, 00, and 01, where the second communication port IO2 is not triggered (i.e., the first detection signal is low) and the third communication port IO3 is triggered (i.e., the second detection signal is high). In simpler terms, if 1 represents trigger and 0 represents not trigger, the signal reception states of the second communication port IO2 and the third communication port IO3 could be: 11, 10, 00, and 01, and these four states would appear consecutively.

[0123] When the signal reception states of the second communication port IO2 and the third communication port IO3 are the same as when the microcontroller 102 was previously woken up (e.g., the current signal reception states of the second communication port IO2 and the third communication port IO3 are 01, and the previous signal reception states of the microcontroller 102 were also 01), it indicates that the motor has not reached the trigger condition, and therefore the microcontroller 102 does not record the number of revolutions and directly enters the running mode. However, when the signal reception states of the second communication port IO2 and the third communication port IO3 are different from those when the microcontroller 102 was previously woken up (e.g., the current signal reception states of the second communication port IO2 and the third communication port IO3 are 00, and the previous signal reception states of the microcontroller 102 were 10), it indicates that the motor has also triggered the microcontroller 102, and therefore the microcontroller 102 needs to record the number of revolutions before entering the running mode.

[0124] When the microcontroller 102 needs to record the number of revolutions, it first needs to determine whether the motor has rotated one revolution. Figure 9As shown, during one revolution of the motor, the signal reception states of the second communication port IO2 and the third communication port IO3 change from 11 to 10, then to 00, and finally to 01. Therefore, we can determine whether the motor has completed one revolution by comparing the signal reception states of the second and third communication ports IO2 and IO3 with their initial signal reception states. When the signal reception status of the second communication port IO2 and the third communication port IO3 is different from the first signal reception status of the second communication port IO2 and the third communication port IO3, for example, when the current signal reception status of the second communication port IO2 and the third communication port IO3 is 00, while the first signal reception status of the second communication port IO2 and the third communication port IO3 is 11, it means that the motor has not rotated one revolution. At this time, the microcontroller 102 needs to record the current signal reception status of the second communication port IO2 and the third communication port IO3, and then enter the running mode. When the signal reception status of the second communication port IO2 and the third communication port IO3 is the same as the first signal reception status of the second communication port IO2 and the third communication port IO3, for example, when the current signal reception status of the second communication port IO2 and the third communication port IO3 is 11, while the first signal reception status of the second communication port IO2 and the third communication port IO3 is also 11, it means that the motor has rotated one revolution. At this time, the microcontroller 102 needs to record the number of revolutions and enter the running mode.

[0125] Because the method of recording the number of revolutions is different when the motor is rotating forward and when it is rotating in reverse, it is also necessary to determine whether the motor is rotating forward. Specifically, for example... Figure 9It can be seen that the four signal reception states of the second communication port IO2 and the third communication port IO3 change cyclically in the order of 11 to 10, then to 00, and finally to 01. Therefore, this cyclical change in the order of 11 to 10, then to 00, and finally to 01 can be preset as the signal reception state changes of the second communication port IO2 and the third communication port IO3 when the motor is rotating forward. Therefore, whether the motor is rotating forward can be determined by whether the signal reception state changes of the second communication port IO2 and the third communication port IO3 are the same as the preset signal reception state changes. When the signal reception status changes of the second communication port IO2 and the third communication port IO3 are the same as the preset signal reception status changes, for example, if the current signal reception status of the second communication port IO2 and the third communication port IO3 is 00, and the previous signal reception status was 10, it means that the signal reception status changes of the second communication port IO2 and the third communication port IO3 from 10 to 00, while the preset signal reception status changes from 11 to 10, then to 00, and finally to 01. This indicates that the two changes are the same, therefore the motor rotates forward, and the microcontroller 102 increments the revolution count by one before entering the operating mode. When the signal reception status changes of the second communication port IO2 and the third communication port IO3 are different from the preset signal reception status changes, for example, the current signal reception status of the second communication port IO2 and the third communication port IO3 is 10, and the previous signal reception status of the second communication port IO2 and the third communication port IO3 was 00, it means that the signal reception status changes of the second communication port IO2 and the third communication port IO3 from 00 to 10, while the preset signal reception status changes from 11 to 10, then to 00, and finally to 01. This indicates that the two changes are different, so the motor is in reverse at this time, and the microcontroller 102 decrements the number of revolutions by one and then enters the operating mode.

[0126] When the signal reception status of the first communication port IO1 is not triggered, it indicates that the wake-up of the microcontroller 102 is triggered by the motor. Therefore, it can directly determine whether the motor has rotated one revolution. If the motor has not rotated one revolution, the current signal reception status of the second communication port IO2 and the third communication port IO3 is recorded, and then the microcontroller enters sleep mode. If the motor has rotated one revolution, it is determined whether the motor is rotating forward. If the motor is rotating forward, the microcontroller 102 increments the revolution count by one when recording the revolution count, and then enters sleep mode. If the motor is rotating in reverse, the microcontroller 102 decrements the revolution count by one when recording the revolution count, and then enters sleep mode. The encoder operation method provided by this invention enables the microcontroller 102 with a wake-up port 1022 to also perform the work of the encoder 10.

[0127] like Figure 10As shown, the technical solution of the present invention provides a control device for an encoder, used in any of the above embodiments of the encoder. The encoder control device 100 includes:

[0128] The first acquisition module 1002 is used to acquire the signal reception status of the first communication port, the second communication port and the third communication port in response to the wake-up signal of the wake-up port.

[0129] The first execution module 1004 is used to execute the target operation based on the signal reception status of the first communication port, the second communication port and the third communication port.

[0130] This invention provides a controller device 100 for an encoder 10 in any of the above-described technical solutions. The controller device 10 includes a first acquisition module 1002 and a first execution module 1004. When the trigger port of the microcontroller 102 is triggered by a wake-up signal, the microcontroller 102 is woken up. However, since the wake-up signal is a combination of a first power signal and a first detection signal, there can be multiple reasons for the microcontroller 102 to be woken up, such as power triggering or motor triggering. To determine the specific cause, the first acquisition module 1002 needs to acquire the signal reception status of the first communication port IO1, the second communication port IO2, and the third communication port IO3, i.e., the current status of the first power signal, the first detection signal, and the second detection signal. The first power signal indicates the power supply status, and the first and second detection signals indicate the motor status. Therefore, the microcontroller 102 can determine the specific reason for being woken up based on the signal reception status of the first communication port IO1, the second communication port IO2, and the third communication port IO3, and then the first execution module 1004 executes the target operation corresponding to that reason.

[0131] In some embodiments, optionally, the first execution module 1004 is specifically configured to: determine whether to execute the first operation based on the signal reception status of the first communication port being in a triggered state, and enter the running mode based on the signal reception status of the second and third communication ports; and execute the first operation based on the signal reception status of the first communication port being in a non-triggered state, and enter the sleep mode.

[0132] In this embodiment, when the signal reception state of the first communication port IO1 is in the triggered state, that is, when the current state of the first power signal is high, it indicates that the microcontroller 102 is woken up due to power-on, and therefore the first execution module 1004 enters the running mode. However, when power-on and motor triggering occur simultaneously, the microcontroller 102 will also be woken up. Therefore, the first execution module 1004 also needs to obtain the signal reception states of the second communication port IO2 and the third communication port IO3, and determine whether there is still motor triggering based on the states of the second communication port IO2 and the third communication port IO3, thereby determining whether the first execution module 1004 should perform the first operation. When the signal reception state of the first communication port IO1 is in the non-triggered state, that is, when the current state of the first power signal is low, it indicates that the current power supply is in a power-off state. In this case, the reason for the microcontroller 102 being woken up can only be due to motor triggering. Therefore, the first execution module 1004 performs the first operation and then enters the sleep mode.

[0133] In some embodiments, optionally, the first execution module 1004 includes:

[0134] The second acquisition module is used to acquire the first relationship between the signal reception status of the second communication port and the third communication port and the previous signal reception status.

[0135] The second execution module is configured to not perform the first operation if the signal reception status of the second and third communication ports is the same as the previous signal reception status; and to perform the first operation if the signal reception status of the second and third communication ports is different from the previous signal reception status.

[0136] In this embodiment, the first execution module 1004 includes a second acquisition module and a second execution module. The second acquisition module acquires a first relationship between the signal reception states of the second communication port IO2 and the third communication port IO3 and the signal reception states of the second communication port IO2 and the third communication port IO3 when the microcontroller 102 was previously woken up. The first relationship is that the signal reception states of the second communication port IO2 and the third communication port IO3 are the same as or different from the signal reception states of the second communication port IO2 and the third communication port IO3 when the microcontroller 102 was previously woken up. When the signal reception states of the second communication port IO2 and the third communication port IO3 are the same as the signal reception states of the second communication port IO2 and the third communication port IO3 when the microcontroller 102 was previously woken up, it indicates that the wake-up of the microcontroller 102 was not triggered by the motor, therefore the second execution module does not perform the first operation. When the signal reception states of the second communication port IO2 and the third communication port IO3 are different from those when the microcontroller 102 was woken up the previous time, it indicates that the microcontroller 102 was woken up by the motor, and therefore the second execution module performs the first operation.

[0137] In some embodiments, the second execution module includes:

[0138] The third acquisition module is used to acquire the second relationship between the signal reception status of the second communication port and the third communication port and the historical signal reception status;

[0139] The third execution module is used to record the number of cycles when the signal reception status of the second and third communication ports is the same as the historical signal reception status; and to record the signal reception status of the first, second, and third communication ports when the signal reception status of the second and third communication ports is different from the historical signal reception status.

[0140] In this embodiment, the second execution module includes a third acquisition module and a third execution module. The third acquisition module acquires a second relationship between the signal reception states of the second communication port IO2 and the third communication port IO3 and the historical signal reception states. The historical signal reception states are the first signal reception states of the second communication port IO2 and the third communication port IO3 recorded by the microcontroller 102. The second relationship is whether the signal reception states of the second communication port IO2 and the third communication port IO3 are the same as or different from the first signal reception states. When the signal reception states of the second communication port IO2 and the third communication port IO3 are the same as the first signal reception states, it indicates that the motor has completed one revolution, and therefore the third execution module records the number of revolutions. When the signal reception states of the second communication port IO2 and the third communication port IO3 are different from the first signal reception states, it indicates that the motor has not yet completed one revolution, and therefore the third execution module does not record the number of revolutions, but only records the current signal reception states of the first communication port IO1, the second communication port IO2, and the third communication port IO3.

[0141] In some embodiments, optionally, the third execution module includes:

[0142] Fourth acquisition module: Acquires the third relationship between the signal reception status changes of the second and third communication ports and the preset signal reception status changes;

[0143] The fourth execution module is used to increment the number of cycles by one based on the fact that the changes in the signal reception status of the second and third communication ports are the same as the preset changes in the signal reception status.

[0144] The fifth execution module is used to decrement the number of cycles by one when the changes in the signal reception status of the second and third communication ports are different from the preset changes in the signal reception status.

[0145] In this embodiment, the third execution module includes a fourth acquisition module, a fourth execution module, and a fifth execution module. The fourth acquisition module acquires a third relationship between the signal reception state changes of the second communication port IO2 and the third communication port IO3 and a preset signal reception state change. The signal reception state change of the second communication port IO2 and the third communication port IO3 refers to the change from the previous signal reception state of the second communication port IO2 and the third communication port IO3 to the current signal reception state. The preset signal reception state change can be the change in the signal reception state of the second communication port IO2 and the third communication port IO3 when the motor is rotating forward. When the signal reception state change of the second communication port IO2 and the third communication port IO3 is the same as the preset signal reception state change, it indicates that the motor is rotating forward, so the fourth execution module increments the revolution count by one. When the signal reception state change of the second communication port IO2 and the third communication port IO3 is different from the preset signal reception state change, it indicates that the motor is rotating in reverse, so the fifth execution module decrements the revolution count by one.

[0146] like Figure 11 As shown, the present invention provides an encoder control device 1100, including: a memory 1102 and a processor 1104. The memory 1102 stores programs or instructions, and the processor 1104 executes the programs or instructions. When executing the programs or instructions, the processor 1104 implements the steps of the encoder operation method as described in any embodiment of the present invention.

[0147] The encoder control device 1100 provided by this technical solution implements the steps of the encoder operation method as described in any embodiment of the present invention, and therefore has all the beneficial effects of the encoder operation method as described in any embodiment of the present invention, which will not be repeated here.

[0148] The present invention provides a readable storage medium storing a program or instructions, which, when executed, implement the steps of the encoder operation method of any of the above embodiments.

[0149] The readable storage medium provided by this technical solution implements the steps of the encoder operation method as described in any embodiment of the present invention, and therefore has all the beneficial effects of the encoder operation method as described in any embodiment of the present invention, which will not be repeated here.

[0150] In this invention, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise explicitly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0151] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "front," "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0152] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0153] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An encoder, characterized in that, The encoder includes: The microcontroller has a wake-up port, a first communication port, a second communication port and a third communication port. The wake-up port is used to receive a wake-up signal, the first communication port is used to receive a first power signal, the second communication port is used to receive a first detection signal, and the third communication port is used to receive a second detection signal. A combination circuit is configured to generate the wake-up signal based on the first power supply signal and the first detection signal, the combination circuit comprising: The first input terminal is used to receive the first power signal; The second input terminal is used to receive the first detection signal; The third input terminal is used to receive the first detection signal; The output terminal is connected to the wake-up port of the microcontroller and is used to send the wake-up signal to the microcontroller. In response to the wake-up port being triggered by the wake-up signal, the microcontroller performs the target operation based on the signal reception status of the first communication port, the second communication port, and the third communication port.

2. The encoder according to claim 1, characterized in that, The combined circuit includes: A first logic gate circuit has a first input terminal, a second input terminal, and an output terminal. The output terminal of the first logic gate circuit is connected to the wake-up port of the microcontroller. A first conversion circuit is used to convert the first power signal into a second power signal; the output terminal of the first conversion circuit is connected to the first input terminal of the first logic gate circuit. The second conversion circuit is used to convert the first detection signal into a third detection signal; the output terminal of the second conversion circuit is connected to the second input terminal of the first logic gate circuit. The first logic gate circuit can generate the wake-up signal based on the second power supply signal and the third detection signal.

3. The encoder according to claim 2, characterized in that, The first conversion circuit includes: First resistor; A first capacitor, one end of which is connected to the first resistor, and the other end of which is connected to the first input terminal of the first logic gate circuit.

4. The encoder according to claim 2, characterized in that, The second conversion circuit includes: The second logic gate circuit has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second logic gate circuit is used to receive the first detection signal, and the output terminal of the second logic gate circuit is connected to the second input terminal of the first logic gate circuit. A delay circuit is used to convert the first detection signal into a fourth detection signal, and the output terminal of the delay circuit is connected to the second input terminal of the second logic gate circuit. The second logic gate circuit is capable of generating the third detection signal based on the first detection signal and the fourth detection signal.

5. The encoder according to claim 4, characterized in that, The delay circuit includes: The second resistor has a first end that receives the first detection signal and a second end that is connected to the second input terminal of the second logic gate circuit. The second capacitor has one end connected to the second end of the second resistor, and the other end grounded.

6. The encoder according to claim 2, characterized in that, The combined circuit further includes: A diode, wherein the negative terminal of the diode is connected to the output terminal of the first conversion circuit, and the positive terminal of the diode is grounded; The third resistor has one end connected to the output terminal of the first conversion circuit and the other end grounded.

7. The encoder according to any one of claims 1 to 6, characterized in that, The encoder also includes: A power detection circuit, the output of which is connected to the first communication port of the microcontroller and the first input of the combined circuit, respectively, for sending the first power signal to the microcontroller and the combined circuit; A first detection circuit, the output of which is connected to the second communication port of the microcontroller, the second input of the combination circuit, and the third input of the combination circuit, respectively, for sending the first detection signal to the microcontroller and the combination circuit; The second detection circuit has its output connected to the third communication port of the microcontroller and is used to send the second detection signal to the microcontroller.

8. A method for operating an encoder, used with any one of claims 1 to 7, characterized in that, The operating method includes: In response to the wake-up port being triggered by the wake-up signal, the signal reception status of the first communication port, the second communication port, and the third communication port is obtained; The target operation is executed based on the signal reception status of the first communication port, the second communication port, and the third communication port.

9. The encoder operation method according to claim 8, characterized in that, The step of performing the target operation based on the signal reception status of the first communication port, the second communication port, and the third communication port includes: Based on the signal reception status of the first communication port being in a triggered state, the system determines whether to execute the first operation and enters the running mode according to the signal reception status of the second and third communication ports. Based on the fact that the signal reception status of the first communication port is in an untriggered state, the first operation is executed, and the system enters sleep mode.

10. The encoder operation method according to claim 9, characterized in that, The step of determining whether to perform the first operation based on the signal reception status of the second communication port and the third communication port includes: Obtain the first relationship between the signal reception status of the second communication port and the third communication port and the previous signal reception status; Since the signal reception states of the second and third communication ports are the same as the previous signal reception states, the first operation is not performed. The first operation is performed because the signal reception states of the second and third communication ports are different from the previous signal reception states.

11. The method of operating the encoder according to claim 9 or 10, characterized in that, The first operation includes: Obtain a second relationship between the signal reception status of the second communication port and the third communication port and the historical signal reception status; Based on the fact that the signal reception status of the second communication port and the third communication port is the same as the historical signal reception status, the number of cycles is recorded. Based on the fact that the signal reception states of the second communication port and the third communication port are different from the historical signal reception states, the signal reception states of the first communication port, the second communication port, and the third communication port are recorded.

12. The encoder operation method according to claim 11, characterized in that, The step of recording the number of cycles based on the fact that the signal reception status of the second communication port and the third communication port is the same as the historical signal reception status includes: Obtain a third relationship between the signal reception state changes of the second communication port and the third communication port and the preset signal reception state changes; Based on the fact that the signal reception status changes of the second communication port and the third communication port are the same as the preset signal reception status changes, the number of cycles is incremented by one. Since the signal reception status changes of the second communication port and the third communication port are different from the preset signal reception status changes, the number of cycles is reduced by one.

13. A control device for an encoder, used in any one of claims 1 to 7, characterized in that, include: The first acquisition module is used to acquire the signal reception status of the first communication port, the second communication port and the third communication port in response to the wake-up port being triggered by the wake-up signal. The first execution module is used to execute the target operation based on the signal reception status of the first communication port, the second communication port and the third communication port.

14. A control device for an encoder, characterized in that, include: Memory, which stores programs or instructions; Processor, which executes the program or instructions; Wherein, when the processor executes the program or instructions, it implements the steps of the encoder operation method as described in any one of claims 8 to 12.

15. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the encoder operation method as described in any one of claims 8 to 12.

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