Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. In the display panel, a pixel circuit includes a first reset module and a second reset module. An input end of the first reset module receives a first reset voltage, and an output end of the first reset module is electrically connected with a first electrode of a light emitting device. An input end of the second reset module receives a second reset voltage, and an output end of the second reset module is electrically connected with the first electrode of the light emitting device. The first reset voltage has the same potential as the second reset voltage. One working cycle of the pixel circuit includes a first reset stage and a second reset stage. The first reset module is turned on in the first reset stage, and the second reset module is turned on in the second reset stage. The present application can avoid the problem that the first reset voltage and the second reset voltage have different loads when resetting the light emitting device, thereby facilitating the avoidance of the problem that the display panel has a split screen in brightness in one frame of picture, and further facilitating the improvement of the display effect of the display panel.

Description

[Technical Field]

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. [Background Technology]

[0002] Organic light-emitting diode (OLED) display panels possess excellent photoelectric characteristics such as low power consumption, high resolution, and fast response, leading to their widespread application in the market. Among these, the pixel circuitry used to control the emission of light from the light-emitting devices is the core technology of OLED display panels and is of significant research importance.

[0003] In display panels, in order to increase the adjustment range of display frequency, the frequency of resetting the light-emitting device in the pixel circuit is usually increased. However, in the existing pixel circuit, increasing the reset frequency of the light-emitting device will cause the display panel to have brightness splitting in one frame, affecting the display effect, especially in the low grayscale and low frequency display state of the display panel, the impact is very obvious.

[0004] [Application Content]

[0005] In view of this, embodiments of this application provide a display panel and a display device to solve the above problems.

[0006] In a first aspect, embodiments of this application provide a display panel, including a pixel circuit and a light-emitting device electrically connected. The pixel circuit includes a driving transistor, a data writing module, a first reset module, and a second reset module. The driving transistor is used to provide a light-emitting driving current to the light-emitting device. The input terminal of the data writing module is electrically connected to a first signal line, and the output terminal is electrically connected to the driving transistor. The input terminal of the first reset module receives a first reset voltage, and the output terminal is electrically connected to a first electrode of the light-emitting device. The input terminal of the second reset module receives a second reset voltage, and the output terminal is electrically connected to a first electrode of the light-emitting device.

[0007] One operating cycle of the pixel circuit includes a first stage, which includes a first sub-stage and a second sub-stage performed sequentially. The first sub-stage includes a data writing stage, a first reset stage, and a subsequent light emission stage. The second sub-stage includes a second reset stage and a subsequent light emission stage. In the data writing stage, the data writing module transmits a data voltage to the driving transistor. In the first reset stage, the first reset module transmits a first reset voltage to the first electrode of the light-emitting device. In the second reset stage, the second reset module transmits a second reset voltage to the first electrode of the light-emitting device. The potential of the first reset voltage is the same as the potential of the second reset voltage.

[0008] In one implementation of the first aspect, the first reset phase coincides with the data writing phase.

[0009] In one implementation of the first aspect, the control terminal of the data writing module and the control terminal of the first reset module are both electrically connected to the first scan line, and the signal transmitted by the first scan line controls the switching states of the data writing module and the first reset module to be the same.

[0010] In one implementation of the first aspect, the data writing module includes a first transistor, the first terminal of the first transistor being electrically connected to the first signal line, the second terminal being electrically connected to the driving transistor, and the gate being electrically connected to the first scan line; the first reset module includes a second transistor, the first terminal of the second transistor receiving a first reset voltage, the second terminal being electrically connected to the first terminal of the light-emitting device, and the gate being electrically connected to the first scan line; wherein the first transistor and the second transistor have the same channel type.

[0011] In one implementation of the first aspect, the pixel circuit further includes a third reset module, the input of which receives a third reset voltage and the output of which is electrically connected to the gate of the driving transistor.

[0012] The first sub-stage also includes a gate reset stage, which is performed before the data write stage;

[0013] During the gate reset phase, the third reset module transmits a third reset voltage to the gate of the driving transistor.

[0014] In one implementation of the first aspect, the third reset voltage has the same potential as the first reset voltage.

[0015] In one implementation of the first aspect, the third reset voltage has a different potential than the first reset voltage.

[0016] In one implementation of the first aspect, the output terminal of the data writing module is electrically connected to the first electrode of the driving transistor, and the pixel circuit further includes a threshold voltage capture module, the input terminal of the threshold voltage capture module is electrically connected to the second electrode of the driving transistor, and the output terminal is electrically connected to the gate of the driving transistor.

[0017] During the data writing phase, the threshold voltage capture module is activated.

[0018] In one implementation of the first aspect, the pixel circuit includes an adjustment module, the input terminal of which is electrically connected to the second signal line and the output terminal of which is electrically connected to the first electrode of the driving transistor.

[0019] The first sub-stage includes a first adjustment stage that occurs after the data writing stage, in which the adjustment module transmits an adjustment voltage to the drive transistor.

[0020] In one implementation of the first aspect, the first sub-stage further includes a second adjustment stage performed prior to the gate reset stage, in which the adjustment module transmits an adjustment voltage to the driving transistor and the threshold capture module is activated.

[0021] In one implementation of the first aspect, the control terminal of the adjustment module and the control terminal of the second reset module are both electrically connected to the second scan line, and the signal transmitted by the second scan line controls the switching states of the adjustment module and the second reset module in the same way.

[0022] The first sub-stage also includes a first reset stage that precedes the second adjustment stage.

[0023] In one implementation of the first aspect, the adjustment module includes a third transistor, the first terminal of the third transistor being electrically connected to a second signal line, the second terminal being electrically connected to the first terminal of a driving transistor, and the gate being electrically connected to a second scan line.

[0024] The second reset module includes a fourth transistor, the first terminal of the fourth transistor receives a second reset voltage, the second terminal is electrically connected to the first terminal of the light-emitting device, and the gate is electrically connected to the second scan line.

[0025] The third transistor has the same channel type as the fourth transistor.

[0026] In one implementation of the first aspect, the pixel circuit includes an adjustment module, the input terminal of which is electrically connected to a second signal line and the output terminal of which is electrically connected to the first electrode of a driving transistor; an operating cycle of the pixel circuit further includes a second stage following the first stage, the second stage including a third sub-stage and a fourth sub-stage performed sequentially, the third sub-stage including a third adjustment stage and a subsequent light emission stage, and the fourth sub-stage including a fourth adjustment stage and a subsequent light emission stage; in the third adjustment stage, a first scan line transmits an enable signal and an adjustment voltage is transmitted on the first signal line; in the fourth adjustment stage, a second reset module and the adjustment module are turned on, and the second signal line transmits the adjustment voltage.

[0027] Secondly, embodiments of this application provide a display device, including a display panel as provided in the first aspect.

[0028] In this embodiment, within one frame of the display panel, a first reset module transmits a first reset voltage to the first electrode of the light-emitting device during the first reset phase, completing one reset of the light-emitting device; a second reset module transmits a second reset voltage to the first electrode of the light-emitting device during the second reset phase, completing one reset of the light-emitting device. Since the first reset voltage and the second reset voltage are the same, it is equivalent to resetting the first electrode of the light-emitting device twice within one frame of the display panel. This application increases the reset frequency of the light-emitting device while avoiding the problem of different loads when the first reset voltage and the second reset voltage reset the light-emitting device, thereby helping to avoid the problem of brightness splitting in one frame of the display panel, and thus improving the display effect of the display panel. [Attached Image Description]

[0029] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A schematic diagram of a display panel provided in an embodiment of this application;

[0031] Figure 2 for Figure 1 A schematic diagram of a mid-pixel circuit;

[0032] Figure 3 for Figure 2 A schematic diagram of a pixel circuit is shown.

[0033] Figure 4 A timing diagram of a pixel circuit provided for an embodiment of this application;

[0034] Figure 5 A schematic diagram of yet another pixel circuit provided in an embodiment of this application;

[0035] Figure 6 for Figure 1 Another schematic diagram of a mid-pixel circuit;

[0036] Figure 7 for Figure 6 A schematic diagram of a pixel circuit is shown.

[0037] Figure 8 A timing diagram of yet another pixel circuit provided in an embodiment of this application;

[0038] Figure 9 A timing diagram of yet another pixel circuit provided in an embodiment of this application;

[0039] Figure 10 This is a schematic diagram of a display device provided in an embodiment of this application.

Detailed Implementation Methods

[0040] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0041] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0042] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0043] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0044] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely", etc., used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0045] It should be understood that although the terms "first," "second," etc., may be used to describe signal lines, stages, scan lines, transistors, etc. in the embodiments of this application, these signal lines, stages, scan lines, transistors, etc., should not be limited to these terms. These terms are only used to distinguish signal lines, stages, scan lines, transistors, etc., from each other. For example, without departing from the scope of the embodiments of this application, a first signal line may also be referred to as a second signal line, and similarly, a second signal line may also be referred to as a first signal line.

[0046] Through meticulous and in-depth research, the applicant in this case has provided a solution to the problems existing in the prior art.

[0047] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application. Figure 2 for Figure 1 A schematic diagram of a mid-pixel circuit. Figure 3 for Figure 2 The diagram shows a schematic of a pixel circuit. Figure 4 This is a timing diagram of a pixel circuit provided in an embodiment of this application.

[0048] This application embodiment provides a display panel 100, combined with... Figures 1-3 As shown, the display panel 100 includes a pixel circuit 200 and a light-emitting device 300 that are electrically connected. The pixel circuit 200 can drive the light-emitting device 300 in the display panel 100 to emit light.

[0049] The pixel circuit 200 includes a driving transistor Md, a data writing module 10, a first reset module 20, and a second reset module 30. The driving transistor Md is used to provide light-emitting driving current to the light-emitting device 300.

[0050] The input terminal 101 of the data writing module 10 is electrically connected to the first signal line DL1, and the output terminal 102 is electrically connected to the driving transistor Md. The data writing module 10 is used to write the signal transmitted by the first signal line DL1 to the driving transistor Md.

[0051] The input terminal 201 of the first reset module 20 is used to receive the first reset voltage Vref1, and the output terminal 202 is electrically connected to the first electrode 3001 of the light-emitting device 300. The first reset module 20 is used to write the first reset voltage Vref1 into the first electrode 3001 of the light-emitting device 300.

[0052] The input terminal 301 of the second reset module 30 is used to receive the second reset voltage Vref2, and the output terminal 302 is electrically connected to the first electrode 3001 of the light-emitting device 300. The second reset module 30 is used to write the second reset voltage Vref2 into the first electrode of the light-emitting device 300.

[0053] The light-emitting device 300 can be an organic light-emitting diode, and the first electrode 3001 of the light-emitting device 300 can be its anode.

[0054] Combination Figure 4 As shown, one operating cycle of the pixel circuit 200 includes a first stage T1, which includes a first sub-stage t1 and a second sub-stage t2 performed sequentially, i.e., the second sub-stage t2 is performed after the first sub-stage t1. The first sub-stage t1 includes a data writing stage E0, a first reset stage E1, and a subsequent light emission stage E2. The second sub-stage t2 includes a second reset stage E3 and a subsequent light emission stage E2.

[0055] It is understandable that one working cycle of the pixel circuit 200 can be the process of displaying one frame of an image on the display panel 100.

[0056] During the data writing phase E0, the data writing module 10 transmits the data voltage Vdata to the driving transistor Md.

[0057] Specifically, during the data writing phase E0, the data writing module 10 is turned on. At this time, the first signal line DL1 transmits the data voltage Vdata, which is transmitted to the driving transistor Md through the turned-on data writing module 10.

[0058] In the first reset phase E1, the first reset module 20 transmits the first reset voltage Vref1 to the first electrode 3001 of the light-emitting device 300.

[0059] Specifically, in the first reset phase E1, the first reset module 20 is turned on, and the first reset voltage Vref1 is transmitted to the first electrode 3001 of the light-emitting device 300 through the turned-on first reset module 20.

[0060] In the second reset phase E3, the second reset module 30 transmits the second reset voltage Vref2 to the first electrode 3001 of the light-emitting device 300.

[0061] Specifically, in the second reset phase E3, the second reset module 30 is turned on, and the second reset voltage Vref2 is transmitted to the first electrode 3001 of the light-emitting device 300 through the turned-on second reset module 30.

[0062] The potential of the first reset voltage Vref1 is the same as the potential of the second reset voltage Vref2.

[0063] To meet the requirements of multiple display frequencies of the display panel, the pixel circuit is usually set to reset the light-emitting device multiple times within a frame. However, in the prior art, the pixel circuit only includes a reset module for resetting the light-emitting device. In the display panel, this reset module resets the light-emitting device row by row.

[0064] The inventors of this application discovered through research that if a reset module is used to reset the light-emitting device multiple times in a single frame of a display panel, there will be a problem that the load will be different when the reset module resets the light-emitting device line by line.

[0065] For example, if a reset module resets the light-emitting devices twice within a single frame, it may reset both rows of light-emitting devices simultaneously during certain time periods, and only one row during other periods. This results in inconsistent reset levels for the light-emitting devices in different rows of the display panel, potentially causing brightness splitting and affecting the display's overall performance.

[0066] In view of this, a solution is to use different reset modules to reset the light-emitting device once in each frame of the display panel, thereby achieving the effect of resetting the light-emitting device multiple times.

[0067] In this embodiment, within one frame of the display panel 100, the first reset module 20 transmits a first reset voltage Vref1 to the first electrode 3001 of the light-emitting device 300 during the first reset phase E1, completing one reset of the light-emitting device 300; the second reset module 30 transmits a second reset voltage Vref2 to the first electrode 3001 of the light-emitting device 300 during the second reset phase E3, completing one reset of the light-emitting device 300. Since the first reset voltage Vref1 and the second reset voltage Vref2 are the same, it is equivalent to resetting the first electrode 3001 of the light-emitting device 300 twice within one frame of the display panel 100. This application utilizes the first reset module 20 and the second reset module 30 to perform one reset of the light-emitting device 300 within one frame of the display panel 100. This increases the reset frequency of the light-emitting device 300 while avoiding the problem of different loads when the first reset voltage Vref1 and the second reset voltage Vref2 reset the light-emitting device 300, thereby helping to avoid brightness splitting issues within one frame of the display panel and improving the display effect of the display panel 100.

[0068] In one embodiment of this application, please continue to refer to Figure 4 The first reset phase E1 and the data writing phase E0 occur at the same time.

[0069] In this embodiment, the first reset stage E1 and the data writing stage E0 are both performed before the light emission stage E2. During the first reset stage E1 and the data writing stage E0, the first reset module 20 and the data writing module 10 are turned on. The first reset voltage Vref1 is transmitted to the first electrode of the light emission device 300 through the turned-on first reset module 20. At the same time, the data voltage Vdata is transmitted to the driving transistor Md through the turned-on data writing module 10.

[0070] The first reset phase E1 and the data writing phase E0 are performed at the same time, which can reduce the redundancy of the pixel circuit 200 and effectively shorten the working cycle of the pixel circuit 200, thus meeting the higher display frequency requirements of the display panel 100.

[0071] In one technical solution of this application embodiment, please continue to refer to Figure 2 and Figure 3The control terminal 103 of the data writing module 10 and the control terminal 203 of the first reset module 20 are both electrically connected to the first scan line SP. The signal transmitted by the first scan line SP controls the switching states of the data writing module 10 and the first reset module 20 in the same way.

[0072] It should be noted that in some other embodiments, the control terminal 103 of the data writing module 10 and the control terminal 203 of the first reset module 20 may also be electrically connected to different scan lines respectively.

[0073] In this technical solution, the signal transmitted by the first scan line SP simultaneously controls the data writing module 10 and the first reset module 20 to turn on or off, which not only ensures that the data writing module 10 and the first reset module 20 have the same switching state at the same time, but also reduces the number of scan lines and reduces the fabrication difficulty of the pixel circuit 200.

[0074] For details, please continue to refer to Figure 3 The data writing module 10 includes a first transistor M1, the first electrode 101 of the first transistor M1 is electrically connected to the first signal line DL1, the second electrode 102 is electrically connected to the driving transistor Md, and the gate 103 is electrically connected to the first scan line SP.

[0075] The first reset module 20 includes a second transistor M2. The first terminal 201 of the second transistor M2 receives the first reset voltage Vref1, the second terminal 202 is electrically connected to the first terminal 3001 of the light-emitting device 300, and the gate 203 is electrically connected to the first scan line SP.

[0076] The first transistor M1 and the second transistor M2 have the same channel type.

[0077] Since the first transistor M1 and the second transistor M2 have the same channel type, they require the same control signal. The signal transmitted by the first scan line SP can simultaneously control the first transistor M1 and the second transistor M2 to be turned on or off. That is, the first scan line SP can simultaneously control the switching states of the data writing module 10 and the first reset module 20 to be the same.

[0078] In one embodiment of this application, please continue to combine Figures 2-4 The pixel circuit 200 also includes a third reset module 40. The input terminal 401 of the third reset module 40 receives the third reset voltage Vref3, and the output terminal 402 is electrically connected to the gate of the driving transistor Md. The third reset module 40 is used to reset the gate of the driving transistor Md.

[0079] The first sub-stage t1 also includes a gate reset stage E4, which occurs before the data write stage E0.

[0080] During the gate reset phase E4, the third reset module 40 transmits the third reset voltage Vref3 to the gate of the driving transistor Md.

[0081] Specifically, during the gate reset phase E4, the third reset module 40 is turned on, and the third reset voltage Vref3 is transmitted to the gate of the driving transistor Md through the activated third reset module 40, thus completing the reset of the gate of the driving transistor Md and ensuring the accuracy of the subsequent data voltage Vdata written to the gate of the driving transistor Md.

[0082] Optionally, the third reset voltage Vref3 has the same potential as the first reset voltage Vref1. Figure 5 This is a schematic diagram of yet another pixel circuit provided in an embodiment of this application. (See attached diagram.) Figure 5 As shown, the third reset voltage Vref3 and the first reset voltage Vref1 can be transmitted through the same signal line. That is, the input terminal 201 of the first reset module 20 and the input terminal 401 of the third reset module 40 can be connected to the same signal line. This helps to further reduce the number of signal lines and reduce the manufacturing difficulty of the display panel 100.

[0083] Optionally, the third reset voltage Vref3 and the first reset voltage Vref1 have different potentials. In this way, the third reset voltage Vref3 and the first reset voltage Vref1 can be flexibly set according to the different reset requirements of the gate of the driving transistor Md and the first electrode 3001 of the light-emitting device 300.

[0084] In one embodiment of this application, such as Figure 2 , Figure 3 As shown, the output terminal 102 of the data writing module 10 is electrically connected to the first electrode of the driving transistor Md. The pixel circuit 200 also includes a threshold voltage capture module 50. The input terminal 501 of the threshold voltage capture module 50 is electrically connected to the second electrode of the driving transistor Md, and the output terminal 502 of the threshold voltage capture module 50 is electrically connected to the gate of the driving transistor Md. The threshold voltage capture module 50 is used to compensate the threshold voltage of the driving transistor Md to the gate of the driving transistor Md.

[0085] Optionally, the first terminal of the driving transistor Md is its source, and the second terminal of the driving transistor Md is its drain.

[0086] Combination Figure 4 As shown, during the data writing phase E0, the threshold voltage capture module 50 is activated.

[0087] Specifically, during the data writing stage E0, the data writing module 10 is turned on, and the data voltage Vdata is written to the first terminal of the driving transistor Md through the output terminal 102 of the data writing module 10, so that the potential of the first terminal of the driving transistor Md is greater than its gate potential, thereby turning on the driving transistor Md. The data voltage Vdata is transmitted to the gate of the driving transistor Md through the turned-on driving transistor Md and the threshold voltage capture module 50.

[0088] Figure 6 for Figure 1 Another schematic diagram of a mid-pixel circuit. Figure 7 for Figure 6 The diagram shows a schematic of a pixel circuit. Figure 8 This is a timing diagram of another pixel circuit provided in an embodiment of this application.

[0089] In one embodiment of this application, such as Figure 6 , Figure 7 As shown, the pixel circuit 200 also includes an adjustment module 60, which can be used to correct the bias state of the driving transistor Md. The input terminal 601 of the adjustment module 60 is electrically connected to the second signal line DL2, and the output terminal 602 is electrically connected to the first pole of the driving transistor Md.

[0090] Combination Figure 8 As shown, the first sub-stage t1 includes a first adjustment stage E5 that occurs after the data writing stage E0. Of course, the first adjustment stage E5 occurs before the light emission stage E2 of the first sub-stage t1. In the first adjustment stage E5, the adjustment module 60 transmits the adjustment voltage Vdvh to the driving transistor Md.

[0091] In this embodiment, after the data writing stage E0 and before the light emission stage E2, the pixel circuit 200 enters the first adjustment stage E5. At this time, the adjustment module 60 is turned on, and the second signal line DL2 transmits the adjustment voltage Vdvh. The adjustment voltage Vdvh is transmitted to the first pole of the driving transistor Md through the turned-on adjustment module 60, which helps to improve the hysteresis effect of the driving transistor Md, reduce the generation of image retention problems, and improve the display effect.

[0092] In one embodiment of this application, please continue to combine Figures 6-8 The first sub-stage t1 also includes a second adjustment stage E6 performed before the gate reset stage E4. In the second adjustment stage E6, the adjustment module 60 transmits the adjustment voltage Vdvh to the driving transistor Md, and the threshold capture module 50 is turned on.

[0093] Specifically, before resetting the gate of the driving transistor Md, the pixel circuit 200 transmits a valid signal from the second scan line SP* to the control terminal 603 of the adjustment module 60. The adjustment voltage Vdvh is transmitted to the first electrode of the driving transistor Md through the activated adjustment module 60, making the potential of the first electrode of the driving transistor Md greater than its gate potential, thereby driving the transistor Md to turn on. At the same time, the threshold grasping module 50 is activated, and the adjustment voltage Vdvh is transmitted to the gate of the driving transistor Md through the activated driving transistor Md and the threshold grasping module 50, which helps to further improve the hysteresis effect of the driving transistor and improve the display effect.

[0094] In one embodiment of this application, please continue to combine Figures 6-8 The control terminal 603 of the adjustment module 60 and the control terminal 301 of the second reset module 30 are both electrically connected to the second scan line SP*. The signal transmitted by the second scan line SP* controls the switching states of the adjustment module 60 and the second reset module 30 in the same way.

[0095] It should be noted that in some other embodiments, the control terminal 603 of the adjustment module 60 and the control terminal 301 of the second reset module 30 may also be connected to different scan signal lines.

[0096] The first sub-stage t1 also includes a first reset stage E1 that occurs before the second adjustment stage E6.

[0097] As can be seen from the above analysis, in the first reset stage E1, the first scan line SP transmits a valid signal to the control terminal 203 of the first reset module 20, and the first reset voltage Vref1 is transmitted to the first electrode 3001 of the light-emitting device 300 through the activated first reset module 20, thus completing a reset of the light-emitting device 300.

[0098] Since the control terminal 603 of the adjustment module 60 and the control terminal 301 of the second reset module 30 are both electrically connected to the second scan line SP*, the second reset module 30 will also reset the light-emitting device 300 once during the second adjustment stage E6. Furthermore, since the second reset module 30 will reset the light-emitting device 300 once during the second reset stage E3 of the second sub-stage t2, to avoid the second reset module 30 resetting the light-emitting device 300 multiple times within a single frame of the display panel 100, a first reset stage E1 is set before the second adjustment stage E6. The first reset module 20 completes the reset of the light-emitting device 300 in the first sub-stage t1. At this time, even if the first reset module 20 or the second reset module 30 is activated multiple times during the first sub-stage t1, the light-emitting device 300 will not be reset again, thus avoiding the situation where the light-emitting device 300 is reset multiple times within a single frame using the first reset module 20 or the second reset module 30.

[0099] In one implementation of the embodiments of this application, such as Figure 7 As shown, the adjustment module 60 includes a third transistor M3. The first terminal of the third transistor M3 is electrically connected to the second signal line DL2, the second terminal is electrically connected to the first terminal of the driving transistor Md, and the gate is electrically connected to the second scan line SP*.

[0100] The second reset module 30 includes a fourth transistor M4. The first terminal of the fourth transistor M4 receives the second reset voltage Vref2, the second terminal is electrically connected to the first terminal 3001 of the light-emitting device 300, and the gate is electrically connected to the second scan line SP*.

[0101] The third transistor M3 and the fourth transistor M4 have the same channel type. Since the third transistor M3 and the fourth transistor M4 have the same channel type, they require the same control signal. The signal transmitted by the second scan line SP* can simultaneously control the third transistor M3 and the fourth transistor M4 to be turned on or off. That is, the second scan line SP* can simultaneously control the switching state of the adjustment module 60 and the second reset module 30 to be the same.

[0102] Figure 9 This is a timing diagram of another pixel circuit provided in an embodiment of this application.

[0103] In one embodiment of this application, combined with Figure 6 , Figure 7 and Figure 9 As shown, the pixel circuit 200 includes an adjustment module 60. The input terminal 601 of the adjustment module 60 is electrically connected to the second signal line DL2, and the output terminal 602 is electrically connected to the first electrode of the driving transistor Md.

[0104] One operating cycle of the pixel circuit 200 also includes a second stage T2 following the first stage T1. The second stage T2 includes a third sub-stage t3 and a fourth sub-stage t4 performed sequentially. The third sub-stage t3 includes a third adjustment stage E7 and a subsequent light emission stage E2. The fourth sub-stage t4 includes a fourth adjustment stage E8 and a subsequent light emission stage E2. In the second stage T2, the pixel circuit 200 no longer performs the data writing stage E0.

[0105] In the third adjustment stage E7, the first scan line SP transmits the enable signal, and the first signal line DL1 transmits the adjustment voltage Vdvh.

[0106] Specifically, in the third adjustment stage E7, the first scan line SP transmits an enable signal (such as a low-level signal), and the data writing module 10 is turned on. At this time, the first signal line DL1 transmits the adjustment voltage Vdvh. The adjustment voltage Vdvh is transmitted to the first terminal of the driving transistor Md through the turned-on data writing module 10. It can be used to correct the bias state of the driving transistor Md, reduce the difference in the bias state of the driving transistor Md between the third sub-stage t3 and the first sub-stage t1, and reduce the speed difference of the driving transistor Md in generating the light-emitting driving current.

[0107] Meanwhile, the first scan line SP transmission enable signal can also control the first reset module 20 to turn on, and the first reset voltage Vref1 is transmitted to the first electrode 3001 of the light-emitting device 300 through the turned-on first reset module 20 to complete a reset of the light-emitting device 300.

[0108] In the fourth adjustment stage E8, the second reset module 30 and the adjustment module 60 are turned on, and the second signal line DL2 transmits the adjustment voltage Vdvh.

[0109] Specifically, in the fourth adjustment stage E8, the second scan line SP* transmits an enable signal (such as a low-level signal), and the adjustment module 60 is turned on. At this time, the second signal line DL2 transmits the adjustment voltage Vdvh. The adjustment voltage Vdvh is transmitted to the first terminal of the driving transistor Md through the turned-on adjustment module 60. It can be used to correct the bias state of the driving transistor Md, reduce the difference in the bias state of the driving transistor in the fourth sub-stage t4 and the first sub-stage t1, and reduce the speed difference of the driving transistor Md in generating the light-emitting driving current.

[0110] Meanwhile, the enable signal transmitted by the second scan line SP* can also control the second reset module 30 to turn on, and the second reset voltage Vref2 is transmitted to the first electrode 3001 of the light-emitting device 300 through the turned-on second reset module 30, completing another reset of the light-emitting device 300.

[0111] In this embodiment of the application, during the second stage T2, while the bias of the driving transistor Md is adjusted, the first reset module 20 is used to reset the light-emitting device 300 once, and the second reset module 30 is used to reset the light-emitting device 300 once. This increases the reset frequency of the light-emitting device 300 and avoids the problem of different loads when the first reset voltage Vref1 and the second reset voltage Vref2 reset the light-emitting device 300.

[0112] It should be noted that within one working cycle, the regulation voltage Vdvh transmitted by the first signal line DL1 and the second signal line DL2 in the second stage T2 can be the same as or different from the regulation voltage Vdvh received by the driving transistor Md in the first stage T1.

[0113] To illustrate the technical solution of this application more clearly, the following will be combined with... Figure 8 and Figure 9 The working process of the pixel circuit is explained as follows:

[0114] like Figure 8 As shown, the threshold voltage capture module 50 includes a fifth transistor M5, the first terminal of the fifth transistor M5 is electrically connected to the second terminal of the driving transistor Md, the second terminal is electrically connected to the gate of the driving transistor Md, and the gate is electrically connected to the third scan line S2N; the third reset module 40 includes a sixth transistor M6, the first terminal of the sixth transistor M6 is used to receive the third reset voltage Vref3, the second terminal is electrically connected to the gate of the driving transistor Md, and the gate is electrically connected to the fourth scan line S1N.

[0115] In addition, the pixel circuit also includes a seventh transistor M7 and an eighth transistor M8. The first terminal of the seventh transistor M7 is used to receive the power supply voltage PVDD, the second terminal is electrically connected to the first terminal of the driving transistor Md, and the gate is electrically connected to the light-emitting signal line Emit. The first terminal of the eighth transistor M8 is electrically connected to the second terminal of the driving transistor Md, the second terminal is electrically connected to the first terminal 3001 of the light-emitting device 300, and the gate is electrically connected to the light-emitting signal line Emit.

[0116] Among them, the fifth transistor M5 and the sixth transistor M6 can be N-type transistors including a metal oxide active layer. The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 can be P-type transistors.

[0117] Combination Figure 9 As shown, the operation of the pixel circuit 200 in one cycle includes a first stage T1 and a second stage T2 performed sequentially. The first stage T1 includes a first sub-stage t1 and a second sub-stage t2 performed sequentially, and the second stage T2 includes a third sub-stage t3 and a fourth sub-stage t4 performed sequentially.

[0118] The first sub-stage t1 includes the following sequentially performed stages: first reset stage E1, second adjustment stage E6, gate reset stage E4, data writing stage E0, first adjustment stage E5, and light emission stage E2.

[0119] The second sub-stage t2 includes the second reset stage E3 and the light emission stage E2, which are performed sequentially.

[0120] The third sub-stage t3 includes the third regulation stage E7 and the luminescence stage E2, which proceed sequentially.

[0121] The fourth sub-stage t4 includes the fourth regulation stage E8 and the luminescence stage E2, which are performed sequentially.

[0122] In the first reset phase E1, the first scan line SP transmits a conduction signal, such as a low-level signal, and the second transistor M2 is turned on. The first reset voltage Vref1 is transmitted to the first electrode 3001 of the light-emitting device 300 through the turned-on second transistor M2, completing a reset of the light-emitting device 300.

[0123] In the second adjustment stage E6, the second scan line SP* transmits a turn-on signal, such as a low-level signal, and the third transistor M3 and the fourth transistor M4 are turned on. The adjustment voltage Vdvh is transmitted to the first terminal of the driving transistor Md through the turned-on third transistor M3. At the same time, the third scan line S2N transmits a turn-on signal (such as a high-level signal) to control the fifth transistor M5 to turn on. The adjustment voltage Vdvh is transmitted to the gate of the driving transistor Md through the turned-on driving transistor Md and the fifth transistor M5 to improve the hysteresis effect of the driving transistor Md.

[0124] At this time, although the fourth transistor M4 is turned on, that is, the second reset module 30 is turned on, since the light-emitting device 300 has been reset in the first reset stage E1, the voltage of its first electrode 3001 is the first reset voltage Vref1, and the second reset module 30 no longer performs a reset function on the first electrode 3001 of the light-emitting device 300.

[0125] During the gate reset phase E4, the fourth scan line S1N transmits a turn-on signal, such as a high-level signal. The sixth transistor M6 turns on, and the third reset voltage Vref3 is transmitted to the gate of the driving transistor Md through the turned-on sixth transistor M6, thus completing the gate reset of the driving transistor Md.

[0126] During the data writing phase E0, the first scan line SP transmits a turn-on signal, such as a low-level signal, turning on the first transistor M1 and the second transistor M2. At this time, the first signal line DL1 transmits the data voltage Vdata. The data voltage Vdata is transmitted to the first terminal of the driving transistor Md through the turned-on first transistor M1, making the potential of the first terminal of the driving transistor Md greater than its gate potential, thereby turning on the driving transistor Md. At the same time, the third scan line S2N transmits a turn-on signal (such as a high-level signal) to control the fifth transistor M5 to turn on. The data voltage Vdata is written to the gate of the driving transistor Md through the turned-on driving transistor Md and the fifth transistor M5.

[0127] At this time, although the second transistor M2 is turned on, that is, the first reset module 20 is turned on, since the light-emitting device 300 has been reset in the first reset stage E1, the voltage of its first electrode 3001 is the first reset voltage Vref1, and the first reset module 20 no longer performs a reset function on the first electrode 3001 of the light-emitting device 300.

[0128] In the first adjustment stage E5, the second scan line SP* transmits a turn-on signal, such as a low-level signal. The third transistor M3 and the fourth transistor M4 are turned on, and the adjustment voltage Vdvh is written to the first terminal of the driving transistor Md through the turned-on third transistor M3 to improve the hysteresis effect of the driving transistor Md.

[0129] At this time, although the fourth transistor M4 is turned on, that is, the second reset module 30 is turned on, since the light-emitting device 300 has been reset in the first reset stage E1, the voltage of its first electrode 3001 is the first reset voltage Vref1, and the second reset module 30 no longer performs a reset function on the first electrode 3001 of the light-emitting device 300.

[0130] In the first sub-stage t1, during the light-emitting stage E2, the light-emitting signal line Emit transmits a conduction signal, such as a low-level signal, turning on the seventh transistor M7 and the eighth transistor M8. The power supply voltage PVDD is transmitted to the first terminal of the driving transistor Md through the conducting seventh transistor M7. Since the potential of the power supply voltage PVDD is greater than the potential of the data voltage Vdata, the driving transistor Md generates a light-emitting driving current, which is transmitted to the light-emitting device 300 through the conducting eighth transistor M8, driving the light-emitting device 300 to emit light.

[0131] In the second reset phase E3, the second scan line SP* transmits a turn-on signal, such as a low-level signal, and the third transistor M3 and the fourth transistor M4 are turned on. The second signal line DL2 transmits the adjustment voltage Vdvh. The adjustment voltage Vdvh is written to the first terminal of the driving transistor Md through the turned-on third transistor M3, reducing the difference in the bias state of the driving transistor Md between the second sub-phase t2 and the first sub-phase t1.

[0132] At the same time, the second reset voltage Vref2 is written to the first electrode 3001 of the light-emitting device 300 through the fourth transistor M4, completing another reset of the light-emitting device 300.

[0133] The luminescence stage E2 of the second sub-stage t2 works in the same way as the luminescence stage E2 of the first sub-stage t1, and will not be described again here.

[0134] In the third adjustment stage E8 of the second stage T2, the first scan line SP transmits a conduction signal, such as a low-level signal, and the first transistor M1 and the second transistor M2 are turned on. At this time, the first signal line DL1 transmits the adjustment voltage Vdvh. The adjustment voltage Vdvh is written to the first terminal of the driving transistor Md through the turned-on first transistor M1, reducing the difference in the bias state of the driving transistor Md between the third sub-stage t3 and the first sub-stage t1. At the same time, the first reset voltage Vref1 is written to the first terminal 3001 of the light-emitting device 300 through the turned-on second transistor M2, completing a reset of the light-emitting device 300.

[0135] The luminescence stage E2 of the third sub-stage t2 works in the same way as the luminescence stage E2 of the first sub-stage t1, and will not be described again here.

[0136] In the fourth adjustment stage E9, the second scan line SP* transmits a conduction signal, such as a low-level signal, and the third transistor M3 and the fourth transistor M4 are turned on. The second signal line DL2 transmits the adjustment voltage Vdvh. The adjustment voltage Vdvh is written to the first terminal of the driving transistor Md through the turned-on third transistor M3, reducing the difference in the bias state of the driving transistor Md between the fourth sub-stage t4 and the first sub-stage t1. At the same time, the second reset voltage Vref2 is written to the first terminal 3001 of the light-emitting device 300 through the turned-on fourth transistor M4, completing another reset of the light-emitting device 300.

[0137] The luminescence stage E2 of the fourth sub-stage t4 works in the same way as the luminescence stage E2 of the first sub-stage t1, and will not be described again here.

[0138] Figure 10 This is a schematic diagram of a display device provided in an embodiment of this application.

[0139] This application embodiment also provides a display device 400, such as... Figure 10 As shown, the display device 400 includes the display panel 100 provided in the above embodiments. The display device 400 provided in this application embodiment can be a mobile phone; in addition, the display device 400 provided in this application embodiment can also be a computer, television, or other display device.

[0140] In the display device 400, during one frame of the display panel 100, a first reset module 20 transmits a first reset voltage Vref1 to the first electrode 3001 of the light-emitting device 300 during the first reset phase E1, completing one reset of the light-emitting device 300; a second reset module 30 transmits a second reset voltage Vref2 to the first electrode 3001 of the light-emitting device 300 during the second reset phase E3, completing one reset of the light-emitting device 300. Since the first reset voltage Vref1 and the second reset voltage Vref2 are the same, it is equivalent to resetting the first electrode 3001 of the light-emitting device 300 twice during one frame of the display panel 100. This application increases the reset frequency of the light-emitting device 300 while avoiding the problem of different loads when the first reset voltage Vref1 and the second reset voltage Vref2 reset the light-emitting device 300, thereby helping to avoid brightness splitting in one frame of the display panel and thus improving the display effect of the display panel 100.

[0141] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, The pixel circuit includes an electrically connected pixel circuit and a light-emitting device, the pixel circuit comprising: A driving transistor is used to provide light-emitting driving current to the light-emitting device; A data writing module, wherein the input terminal of the data writing module is electrically connected to the first signal line and the output terminal is electrically connected to the driving transistor; A first reset module and a second reset module, wherein the input terminal of the first reset module receives a first reset voltage and the output terminal is electrically connected to the first electrode of the light-emitting device; the input terminal of the second reset module receives a second reset voltage and the output terminal is electrically connected to the first electrode of the light-emitting device. One working cycle of the pixel circuit includes a first stage, which includes a first sub-stage and a second sub-stage performed sequentially. The first sub-stage includes a data writing stage, a first reset stage, and a subsequent light emission stage. The second sub-stage includes a second reset stage and the subsequent light emission stage. During the data writing phase, the data writing module transmits a data voltage to the driving transistor; During the first reset phase, the first reset module transmits the first reset voltage to the first electrode of the light-emitting device; During the second reset phase, the second reset module transmits the second reset voltage to the first electrode of the light-emitting device; Wherein, the potential of the first reset voltage is the same as the potential of the second reset voltage; The output terminal of the data writing module is electrically connected to the first electrode of the driving transistor. The pixel circuit also includes a threshold voltage capture module, the input terminal of which is electrically connected to the second electrode of the driving transistor, and the output terminal of which is electrically connected to the gate of the driving transistor. During the data writing phase, the threshold voltage capture module is turned on. The pixel circuit includes an adjustment module, the input terminal of which is electrically connected to a second signal line and the output terminal of which is electrically connected to the first electrode of the driving transistor; the first sub-stage includes a first adjustment stage performed after the data writing stage, in which the adjustment module transmits an adjustment voltage to the driving transistor; The first sub-stage further includes a gate reset stage, which is performed before the data writing stage; the first sub-stage further includes a second adjustment stage performed before the gate reset stage, in which the adjustment module transmits the adjustment voltage to the driving transistor, and the threshold voltage capture module is turned on. The control terminal of the adjustment module and the control terminal of the second reset module are both electrically connected to the second scan line. The signal transmitted by the second scan line controls the switching states of the adjustment module and the second reset module to be the same. The first sub-stage also includes the first reset stage performed prior to the second adjustment stage.

2. The display panel according to claim 1, characterized in that, The control terminal of the data writing module and the control terminal of the first reset module are both electrically connected to the first scan line. The signal transmitted by the first scan line controls the switching states of the data writing module and the first reset module to be the same.

3. The display panel according to claim 2, characterized in that, The data writing module includes a first transistor, wherein the first terminal of the first transistor is electrically connected to the first signal line, the second terminal is electrically connected to the driving transistor, and the gate is electrically connected to the first scan line. The first reset module includes a second transistor, wherein the first terminal of the second transistor receives the first reset voltage, the second terminal is electrically connected to the first terminal of the light-emitting device, and the gate is electrically connected to the first scan line; The first transistor and the second transistor have the same channel type.

4. The display panel according to claim 1, characterized in that, The pixel circuit also includes a third reset module, the input of which receives a third reset voltage and the output of which is electrically connected to the gate of the driving transistor. During the gate reset phase, the third reset module transmits the third reset voltage to the gate of the driving transistor.

5. The display panel according to claim 4, characterized in that, The third reset voltage has the same potential as the first reset voltage.

6. The display panel according to claim 4, characterized in that, The third reset voltage has a different potential than the first reset voltage.

7. The display panel according to claim 1, characterized in that, The adjustment module includes a third transistor, wherein the first terminal of the third transistor is electrically connected to the second signal line, the second terminal is electrically connected to the first terminal of the driving transistor, and the gate is electrically connected to the second scan line. The second reset module includes a fourth transistor, wherein the first terminal of the fourth transistor receives the second reset voltage, the second terminal is electrically connected to the first terminal of the light-emitting device, and the gate is electrically connected to the second scan line; The third transistor has the same channel type as the fourth transistor.

8. The display panel according to claim 2, characterized in that, The pixel circuit includes an adjustment module, the input terminal of which is electrically connected to the second signal line and the output terminal of which is electrically connected to the first electrode of the driving transistor. One operating cycle of the pixel circuit also includes a second stage performed after the first stage. The second stage includes a third sub-stage and a fourth sub-stage performed sequentially. The third sub-stage includes a third adjustment stage and the subsequent light emission stage. The fourth sub-stage includes a fourth adjustment stage and the subsequent light emission stage. In the third adjustment phase, the first scan line transmits an enable signal, and the first signal line transmits an adjustment voltage; In the fourth adjustment phase, the second reset module and the adjustment module are turned on, and the second signal line transmits the adjustment voltage.

9. A display device, characterized in that, Includes the display panel as described in any one of claims 1-8.

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