Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof, which comprises the following steps: an epitaxial layer, the epitaxial layer comprising an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer which are arranged in a stack, an opening is formed in the epitaxial layer, the opening divides the epitaxial layer into multiple light-emitting units; an isolation dielectric layer is located on the surface of the opening and the upper surface of the epitaxial layer; multiple spaced gate structures comprising a gate and a gate dielectric layer which are arranged in a stack on the isolation dielectric layer, the gate structures are arranged one by one corresponding to the light-emitting units, and the gate structures extend from the side wall of the isolation dielectric layer to the surface of the isolation dielectric layer located on both sides of the side wall; an active layer is located on the gate dielectric layer and exposes the isolation dielectric layer on at least one side of the side wall of the opening; an interlayer dielectric layer covers the active layer, the gate structure and the isolation dielectric layer; and an electrode layer is located on the interlayer dielectric layer and comprises a source and a drain which are connected to both sides of the active layer respectively. The transistor structure is embedded between the light-emitting units, so that the two are combined.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] In response to the requirements of a micro display screen for screen pixel density, refresh frequency, gray scale development and brightness uniformity, a driving circuit needs to use high-performance thin film transistors (for example, low-temperature polysilicon thin film transistors are used in analog circuits), which have the characteristics of high electron mobility, low off-state current and good uniformity.

[0003] However, the current thin film transistors cannot be well combined with light emitting units. SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor structure and a preparation method thereof for the problem that the thin film transistors in the prior art cannot be well combined with light emitting units.

[0005] To achieve the above-mentioned purpose, in one aspect, the present application provides a semiconductor structure, comprising:

[0006] An epitaxial layer, the epitaxial layer comprises an N-type semiconductor layer, a light emitting layer and a P-type semiconductor layer which are stacked, an opening is formed in the epitaxial layer, and the opening divides the epitaxial layer into a plurality of light emitting units;

[0007] An isolation dielectric layer is located on the surface of the opening and the upper surface of the epitaxial layer;

[0008] A plurality of spaced gate structures, comprising a gate and a gate dielectric layer which are stacked in sequence on the isolation dielectric layer, the gate structure is arranged one by one corresponding to the light emitting unit, and the gate structure extends from the side wall of the isolation dielectric layer to the surface of the isolation dielectric layer located on both sides of the side wall;

[0009] An active layer is located on the gate dielectric layer and exposes the isolation dielectric layer on at least one side of the opening side wall;

[0010] An interlayer dielectric layer covers the active layer, the gate structure and the isolation dielectric layer;

[0011] An electrode layer is located on the interlayer dielectric layer and comprises a source and a drain connected to both sides of the active layer, respectively.

[0012] In the above semiconductor structure, the transistor structure composed of the gate structure, the active layer, the interlayer dielectric layer and the electrode layer is embedded between the light emitting units, so that the transistor structure is combined with the light emitting units.

[0013] Meanwhile, the isolation medium layer effectively isolates the transistor structure from the light emitting unit, so that the device performance is stable.

[0014] In one embodiment, the active layer exposes the isolation medium layer within the opening.

[0015] In one embodiment, the gate structure and the active layer surround the light emitting unit.

[0016] In one embodiment, the semiconductor structure further comprises:

[0017] A planarization medium layer is on the electrode layer and the interlayer medium layer;

[0018] A gate interconnect structure is through the planarization medium layer to the gate;

[0019] A source interconnect structure is through the planarization medium layer to the source;

[0020] A drain interconnect structure is through the planarization medium layer to the drain;

[0021] An anode is through the planarization medium layer to the P-type semiconductor layer on the top surface of the light emitting unit.

[0022] In one embodiment, the semiconductor structure further comprises:

[0023] A planarization medium layer is on the electrode layer and the interlayer medium layer;

[0024] A gate interconnect structure is through the planarization medium layer to the gate;

[0025] A source interconnect structure is through the planarization medium layer to the source;

[0026] A drain interconnect structure is through the planarization medium layer to the drain and the P-type semiconductor layer, and the drain interconnect structure is disposed opposite to the top surface of the light emitting unit.

[0027] In one embodiment, the semiconductor structure further comprises:

[0028] A driving substrate is bonded to the side of the planarization medium layer away from the electrode layer, and connects the gate interconnect structure, the source interconnect structure, and the drain interconnect structure;

[0029] A cathode is on the side of the N-type semiconductor layer away from the light emitting layer.

[0030] The application also provides a preparation method of a semiconductor structure, comprising:

[0031] A chip substrate is provided, which includes a substrate and an epitaxial layer including an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer formed in sequence on the substrate, and an opening formed in the epitaxial layer to expose the substrate and divide the epitaxial layer into a plurality of light-emitting units;

[0032] An isolation medium layer is formed on the surface of the opening and the epitaxial layer;

[0033] A plurality of spaced gate structures including a gate and a gate medium layer formed in sequence are formed on the isolation medium layer, the gate structures are arranged one-to-one corresponding to the light-emitting units, and the gate structures extend from the side wall of the isolation medium layer to the surface of the isolation medium layer on both sides of the side wall;

[0034] An active layer is formed on the gate medium layer, and the active layer exposes the isolation medium layer on at least one side of the side wall of the opening;

[0035] An interlayer medium layer covering the active layer, the gate structure, and the isolation medium layer is formed;

[0036] An electrode layer including a source and a drain respectively connected to both sides of the active layer is formed on the interlayer medium layer.

[0037] In the preparation method of the semiconductor structure, the gate structure, the active layer, the interlayer medium layer, the source, and the drain collectively form a transistor structure and are embedded between the light-emitting units, so that the transistor structure is combined with the light-emitting units, the process flows of the two are compatible, the process steps are simplified, the process efficiency is improved, and the production capacity is increased.

[0038] At the same time, the isolation medium layer formed on the surface of the opening and the epitaxial layer effectively isolates the transistor structure from the light-emitting units, thereby stabilizing the performance of the device.

[0039] In one embodiment, the preparation method of the semiconductor structure further includes:

[0040] A planarization medium layer is formed on the electrode layer and the interlayer medium layer;

[0041] A gate interconnection structure extending through the planarization medium layer to the gate is formed;

[0042] A source interconnection structure extending through the planarization medium layer to the source is formed;

[0043] A drain interconnection structure extending through the planarization medium layer to the drain is formed;

[0044] forming an anode of the P-type semiconductor layer extending through the planarization dielectric layer to the top surface of the light emitting unit.

[0045] In one embodiment, the method for preparing the semiconductor structure further comprises:

[0046] forming a planarization dielectric layer on the electrode layer and the interlayer dielectric layer;

[0047] forming a gate interconnect structure extending through the planarization dielectric layer to the gate electrode;

[0048] forming a source interconnect structure extending through the planarization dielectric layer to the source electrode;

[0049] forming a drain interconnect structure extending through the planarization dielectric layer to the drain electrode and the P-type semiconductor layer, the drain interconnect structure being disposed opposite to the top surface of the light emitting unit.

[0050] In one embodiment, the method for preparing the semiconductor structure further comprises:

[0051] bonding a driving substrate to the side of the planarization dielectric layer away from the electrode layer, the driving substrate being connected to the gate interconnect structure, the source interconnect structure and the drain interconnect structure;

[0052] removing the substrate and forming a cathode on the side of the N-type semiconductor layer away from the light emitting layer. BRIEF DESCRIPTION OF DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort based on these drawings.

[0054] Figure 1 a flow chart of the method for preparing the semiconductor structure provided in an embodiment;

[0055] Figures 2 to 10 a cross-sectional structure schematic diagram of the structure obtained in different steps of the method for preparing the semiconductor structure provided in an embodiment;

[0056] Figures 11 to 14 a top view structure schematic diagram of the structure obtained in different steps of the method for preparing the semiconductor structure provided in an embodiment.

[0057] Reference numerals: 100 - substrate, 200 - epitaxial layer, 210 - N-type semiconductor layer, 220 - light emitting layer, 230 - P-type semiconductor layer, 300 - isolation dielectric layer, 400 - gate structure, 410 - gate, 420 - gate dielectric layer, 500 - active layer, 600 - interlayer dielectric layer, 700 - electrode layer, 710 - source, 720 - drain, 800 - planarization dielectric layer, 810 - source interconnect hole, 820 - drain interconnect hole, 830 - gate interconnect hole, 840 - anode interconnect hole, 910 - source interconnect structure, 920 - drain interconnect structure, 930 - gate interconnect structure, 940 - anode. DETAILED DESCRIPTION

[0058] For the purposes of this application, a more complete description of the application will be presented with reference to the associated drawings. Embodiments of the application are illustrated in the drawings. However, the application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0060] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present.

[0061] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction, and the spatially relative terms used herein are intended to encompass such additional orientations. It is to be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction, and the spatially relative terms used herein are intended to encompass such additional orientations.

[0062] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that the term "comprising" or "having" etc., specifies the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0063] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

[0064] In one embodiment, referring to Figure 1 , a method for manufacturing a semiconductor structure is provided, comprising:

[0065] In step S110, a chip substrate is provided, the chip substrate comprising a substrate 100 and an epitaxial layer 200, the epitaxial layer 200 comprising an N-type semiconductor layer 210, a light-emitting layer 220 and a P-type semiconductor layer 230 formed on the substrate 100 in sequence, and an opening is formed in the epitaxial layer 200, the opening exposing the substrate 100 and dividing the epitaxial layer 200 into a plurality of light-emitting units;

[0066] In step S120, an isolation dielectric layer 300 is formed on the surface of the opening and the epitaxial layer 200;

[0067] In step S130, a plurality of gate structures 400 are formed on the isolation dielectric layer 300, the plurality of gate structures 400 being arranged at intervals, the gate structure 400 comprising a gate 410 and a gate dielectric layer 420 formed in sequence, the gate structure 400 being arranged one-to-one corresponding to the light-emitting units, and the gate structure 400 extending from the side wall of the isolation dielectric layer 300 to the surface of the isolation dielectric layer 300 on both sides of the side wall;

[0068] In step S140, an active layer 500 is formed on the gate dielectric layer 420, the active layer 500 exposing the isolation dielectric layer 300 on at least one side of the side wall of the opening;

[0069] In step S150, an interlayer dielectric layer 600 covering the active layer 500, the gate structure 400 and the isolation dielectric layer 300 is formed;

[0070] In step S160, an electrode layer 700 is formed on the interlayer dielectric layer 600, the electrode layer 700 comprising a source electrode 710 and a drain electrode 720 connected to both sides of the active layer 500, respectively.

[0071] In step S110, referring to Figure 2 and Figure 11 The chip substrate includes a substrate 100 and an epitaxial layer 200 formed on the substrate 100. For example, the substrate 100 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrate or II / VI semiconductor substrate. Alternatively, for example, the substrate 100 can be a semiconductor substrate including, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator. Therefore, the type of the substrate 100 should not limit the scope of protection of the present application.

[0072] The epitaxial layer 200 includes an N-type semiconductor layer 210, a light-emitting layer 220, and a P-type semiconductor layer 230. The N-type semiconductor layer 210 is formed on the substrate 100, the light-emitting layer 220 is formed on the N-type semiconductor layer 210, and the P-type semiconductor layer 230 is formed on the light-emitting layer 220. Among them, the P-type semiconductor layer 230 can be selected from semiconductor materials with a composition formula of In x Al y Ga 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and can be doped with P-type dopants such as Mg, Zn, Ca, Sr, Ba, etc. The N-type semiconductor layer 210 can be selected from semiconductor materials with a composition formula of In x Al y Ga 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and can be doped with N-type dopants such as Si, Ge, Sn, etc.

[0073] Etching the epitaxial layer 200 can form a MESA step, and based on the bottom of the MESA step and the step sidewalls on both sides thereof, an opening can be formed in the epitaxial layer 200, a recess is formed in the chip substrate, the surface of the substrate 100 is used as the bottom surface of the recess, and the bottom area of the recess is greater than zero. The opening divides the epitaxial layer 200 into a plurality of light-emitting units. For example, dry etching can be used for MESA etching, specifically, dry etching at least includes any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-density plasma etching (HDP).

[0074] Before forming the opening in the epitaxial layer 200, a transparent conductive layer can also be formed on the epitaxial layer 200, specifically, a full-surface Tin-doped Indium Oxide (ITO) layer can be formed by electron beam evaporation. The transparent conductive layer can form a good ohmic contact with the P-type semiconductor layer 230. At this time, when forming the opening in the epitaxial layer 200, the transparent conductive layer and the epitaxial layer 200 can be etched in sequence.

[0075] In addition, in other embodiments, before forming the opening in the epitaxial layer 200, a nickel (Ni) layer or a platinum (Pt) layer can also be formed on the epitaxial layer 200.

[0076] In step S120, referring to Figure 3 and Figure 12 a separation medium layer 300 is formed on the upper surface of the epitaxial layer 200, the surface of the substrate 100 exposed by the opening, and the sidewall of the opening, for example, the separation medium layer 300 can be formed by plasma enhanced chemical vapor deposition (PECVD), and the material of the separation medium layer 300 can be selected as silicon oxide (SiO).

[0077] In step S130, referring to Figure 4 and Figure 13 a gate structure 400 is formed on the separation medium layer 300, a plurality of gate structures 400 are arranged at intervals, the gate structure 400 includes a gate 410 layer and a gate medium layer 420, the gate structure 400 is arranged one-to-one corresponding to the light-emitting unit, and the gate structure 400 extends from the sidewall of the separation medium layer 300 to the surface of the separation medium layer 300 on both sides of the sidewall.

[0078] As an example, when forming the gate structure 400 on the separation medium layer 300, the gate 410 material can be formed on the separation medium layer 300 first, specifically, the gate 410 material can be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD) or sputtering (Sputter), and the gate 410 material can be selected as a metal material. Then a gate medium material layer is formed on the gate 410 material, specifically, the gate medium material layer can be formed by plasma enhanced chemical vapor deposition (PECVD), and the material of the gate medium material layer can be selected as silicon oxide (SiO). The gate medium material layer and the gate 410 material form a gate 410 material structure. Then the gate 410 material structure is subjected to steps such as exposure, development, and etching to form the gate medium layer 420 and the gate 410, and the gate medium layer 420 and the gate 410 form a plurality of gate structures 400 arranged at intervals.

[0079] The gate structure 400 is arranged one-to-one corresponding to the light emitting unit, and the gate structure 400 extends from the sidewall of the isolation medium layer 300 to the surface of the isolation medium layer 300 on both sides of the sidewall. The gate 410 and the gate medium layer 420 are both arranged one-to-one corresponding to the light emitting unit, and both extend from the sidewall of the isolation medium layer 300 to the surface of the isolation medium layer 300 on both sides of the sidewall. As an example, the gate structure 400 surrounds the light emitting unit. It can be understood that the gate 410 and the gate medium layer 420 both surround the light emitting unit.

[0080] In step S140, referring to Figure 5 and Figure 14 The active layer 500 is formed on the gate medium layer 420, and the active layer 500 exposes the isolation medium layer 300 on at least one side of the opening sidewall. For example, an active material layer can be first formed on the gate medium layer 420 and the isolation medium layer 300. Specifically, an indium gallium zinc oxide (IGZO) layer can be formed by sputtering. Then, by exposing, developing, etching and other steps on the active material layer, the active material layer exposes the isolation medium layer 300 on at least one side of the opening sidewall, thereby forming the active layer 500. Specifically, the active layer 500 can expose the isolation medium layer 300 in the opening. The active layer 500 has a notch, which can separate each transistor structure.

[0081] As an example, from the top view, the active layer 500 can surround the light emitting unit.

[0082] In step S150, referring to Figure 6 The interlayer dielectric layer 600 covering the active layer 500, the gate structure 400 and the isolation medium layer 300 is formed. For example, the interlayer dielectric material layer can be formed by plasma enhanced chemical vapor deposition (PECVD), and the material of the interlayer dielectric material layer can be selected as silicon oxide (SiO). Then, by exposing, developing, etching and other steps on the interlayer dielectric material layer, a via hole is formed in the interlayer dielectric material layer, and the via hole exposes the active layer 500, thereby forming the interlayer dielectric layer 600.

[0083] In step S160, referring to Figure 7An electrode layer 700 is formed on the interlayer dielectric layer 600, and the electrode layer 700 includes a source electrode 710 and a drain electrode 720 connected to the two sides of the active layer 500 respectively. For example, the electrode material layer can be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD) or sputtering (Sputter), and the material of the electrode material layer can be selected from metal materials. Then, the electrode material layer is exposed, developed, etched and the like to form the source electrode 710 and the drain electrode 720, and the source electrode 710 and the drain electrode 720 are connected to the two sides of the active layer 500 through the via holes respectively.

[0084] In the embodiment, the gate structure 400, the active layer 500, the interlayer dielectric layer 600, the source electrode 710 and the drain electrode 720 jointly form a transistor structure and are embedded between the light emitting units, so that the transistor structure is combined with the light emitting units, the process flows of the two are compatible, the process steps are simplified, the process efficiency is improved, and the production capacity is increased.

[0085] Meanwhile, the isolation dielectric layer 300 formed on the opening surface and the upper surface of the epitaxial layer 200 effectively isolates the transistor structure from the light emitting units, so that the device performance is stable.

[0086] In one embodiment, referring to Figures 8 to 9 The preparation method of the semiconductor structure further includes:

[0087] In step S211, a planarization dielectric layer 800 is formed on the electrode layer 700 and the interlayer dielectric layer 600.

[0088] In step S212, a gate interconnection structure 930 extending through the planarization dielectric layer 800 to the gate 410 is formed.

[0089] In step S213, a source interconnection structure 910 extending through the planarization dielectric layer 800 to the source electrode 710 is formed.

[0090] In step S214, a drain interconnection structure 920 extending through the planarization dielectric layer 800 to the drain electrode 720 is formed.

[0091] In step S215, an anode 940 extending through the planarization dielectric layer 800 to the P-type semiconductor layer 230 on the top surface of the light emitting unit is formed.

[0092] In step S211, a planarization dielectric layer 800 is formed on the electrode layer 700 and the interlayer dielectric layer 600. For example, a planarization dielectric layer 800 can be first formed on the entire surface by plasma enhanced chemical vapor deposition (PECVD), and then the planarization dielectric layer 800 is polished by chemical mechanical polishing (CMP) to flatten the surface of the planarization dielectric layer 800. The material of the planarization dielectric layer 800 can be selected from silicon oxide (SiO).

[0093] In step S212, as an example, in forming the gate interconnection structure 930, first, a gate interconnection hole 830 extending through the planarization dielectric layer 800, the interlayer dielectric layer 600 and the gate dielectric layer 420 to the gate 410 is formed. Then the gate interconnection hole 830 is filled, for example, by depositing metal copper (Cu) using an electrochemical plating copper (ECP) process. Finally, the interconnection hole is planarized (e.g. CMP) to the same height as the planarization dielectric layer 800, thereby forming the gate interconnection structure 930.

[0094] In step S213, as an example, in forming the source interconnection structure 910, first, a source interconnection hole 810 extending through the planarization dielectric layer 800 to the source 710 is formed. Then the source interconnection hole 810 is filled, for example, by depositing metal copper (Cu) using an electrochemical plating copper (ECP) process. Finally, the interconnection hole is planarized (e.g. CMP) to the same height as the planarization dielectric layer 800, thereby forming the source interconnection structure 910.

[0095] In step S214, as an example, in forming the drain interconnection structure 920, first, a drain interconnection hole 820 extending through the planarization dielectric layer 800 to the drain 720 is formed. Then the drain interconnection hole 820 is filled, for example, by depositing metal copper (Cu) using an electrochemical plating copper (ECP) process. Finally, the interconnection hole is planarized (e.g. CMP) to the same height as the planarization dielectric layer 800, thereby forming the drain interconnection structure 920.

[0096] In step S215, as an example, in forming the anode 940, first, an anode interconnection hole 840 extending through the planarization dielectric layer 800 and the interlayer dielectric layer 600 to the P-type semiconductor layer 230 is formed. The anode interconnection hole 840 is located above the top surface of the light emitting unit. Then the anode interconnection hole 840 is filled, for example, by depositing metal copper (Cu) using an electrochemical plating copper (ECP) process. Finally, the interconnection hole is planarized (e.g. CMP) to the same height as the planarization dielectric layer 800, thereby forming the anode 940.

[0097] Before filling the gate interconnection hole 830, the source interconnection hole 810, the drain interconnection hole 820 and the anode interconnection hole 840, a barrier layer is formed in the interconnection hole using a chemical vapor deposition (CVD) process. Specifically, the material of the barrier layer can be selected from titanium (Ti) or tantalum (Ta).

[0098] As an example, the active layer 500 surrounds the light emitting unit, the source electrode 710 or the drain electrode 720 can be formed on opposite sides of the light emitting unit. When forming the source electrode interconnection structure 910, the source electrode interconnection structure 910 can be connected to the source electrode 710 in the vertical direction within the opening. When etching the planarization dielectric layer 800 to form the source electrode interconnection hole 810, the source electrode interconnection hole 810 can be formed on opposite sides of the light emitting unit. Specifically, the source electrode interconnection hole 810 is formed on opposite sides of the anode interconnection hole 840. After filling the source electrode interconnection hole 810 and the anode interconnection hole 840 to form the source electrode interconnection structure 910 and the anode 940, the source electrode interconnection structure 910 is located on opposite sides of the anode 940.

[0099] Meanwhile, when forming the drain electrode interconnection structure 920, the drain electrode interconnection structure 920 can be connected to the drain electrode 720 in the vertical direction on the top surface of the light emitting unit. When etching the planarization dielectric layer 800 to form the drain electrode interconnection hole 820, the drain electrode interconnection hole 820 can be formed on opposite sides of the anode interconnection hole 840. After filling the drain electrode interconnection hole 820 and the anode interconnection hole 840 to form the drain electrode interconnection structure 920 and the anode 940, the drain electrode interconnection structure 920 is located on opposite sides of the anode 940.

[0100] In other examples, the source electrode interconnection structure 910 or the drain electrode interconnection structure 920 can be located on only one side of the anode 940, which is not limited herein.

[0101] In one embodiment, referring to Figure 10 The method for manufacturing the semiconductor structure further comprises:

[0102] In step S221, a planarization dielectric layer 800 is formed on the electrode layer 700 and the interlayer dielectric layer 600.

[0103] In step S222, a gate interconnection structure 930 extending through the planarization dielectric layer 800 to the gate 410 is formed.

[0104] In step S223, a source electrode interconnection structure 910 extending through the planarization dielectric layer 800 to the source electrode 710 is formed.

[0105] In step S224, a drain electrode interconnection structure 920 extending through the planarization dielectric layer 800 to the drain electrode 720 and the P-type semiconductor layer 230 is formed, and the drain electrode interconnection structure 920 is located opposite to the top surface of the light emitting unit.

[0106] In step S221, a planarization dielectric layer 800 is formed on the electrode layer 700 and the interlayer dielectric layer 600. For example, a planarization dielectric layer 800 can be first formed by plasma enhanced chemical vapor deposition (PECVD) to form a planar surface, and then the planarization dielectric layer 800 is polished by chemical mechanical polishing (CMP) to planarize the surface of the planarization dielectric layer 800. The material of the planarization dielectric layer 800 can be selected as silicon oxide (SiO).

[0107] In step S222, as an example, when the gate interconnect structure 930 is formed, a gate interconnect hole 830 extending through the planarization dielectric layer 800, the interlayer dielectric layer 600 and the gate dielectric layer 420 to the gate 410 layer can be first formed. Then the gate interconnect hole 830 is filled, for example, by depositing metal copper (Cu) by electroplated copper (ECP) process. Finally, the interconnect hole is polished (e.g. CMP) to the same height as the planarization dielectric layer 800, thereby forming the gate interconnect structure 930.

[0108] In step S223, as an example, when the source interconnect structure 910 is formed, a source interconnect hole 810 extending through the planarization dielectric layer 800 to the source 710 can be first formed. Then the source interconnect hole 810 is filled, for example, by depositing metal copper (Cu) by electroplated copper (ECP) process. Finally, the interconnect hole is polished (e.g. CMP) to the same height as the planarization dielectric layer 800, thereby forming the source interconnect structure 910.

[0109] In step S224, as an example, when the drain interconnect structure 920 is formed, a drain interconnect hole 820 extending through the planarization dielectric layer 800 to the drain 720 and the P-type semiconductor layer 230 can be first formed. Then the drain interconnect hole 820 is filled, for example, by depositing metal copper (Cu) by electroplated copper (ECP) process. Finally, the interconnect hole is polished (e.g. CMP) to the same height as the planarization dielectric layer 800, thereby forming the drain interconnect structure 920. The drain interconnect structure 920 is disposed opposite to the light emitting unit. At this time, the drain interconnect structure 920 can also be used as the anode 940 of the light emitting unit.

[0110] Before filling the gate interconnect hole 830, the source interconnect hole 810 and the drain interconnect hole 820, a barrier layer is formed in the interconnect hole by chemical vapor deposition (CVD) process. Specifically, the material of the barrier layer can be selected as titanium (Ti) or tantalum (Ta).

[0111] As an example, the active layer 500 surrounds the light emitting unit, and the source 710 is located on opposite sides of the light emitting unit. At this time, the source interconnect structure 910 is also located on opposite sides of the light emitting unit.

[0112] The source interconnection structure 910 can be connected to the source 710 in the vertical direction of the opening. When the planarization medium layer 800 is etched to form the source interconnection hole 810, the source interconnection hole 810 can be formed on the opposite sides of the light emitting unit.

[0113] Meanwhile, the drain interconnection structure 920 can be connected to the drain 720 in the vertical direction of the top surface of the light emitting unit, which can be the drain interconnection hole 820, and the drain interconnection structure 920 can be formed. At this time, the drain interconnection structure 920 can also be the anode 940 of the light emitting unit. The drain interconnection structure 920 is arranged opposite to the light emitting unit.

[0114] In one embodiment, the method for manufacturing the semiconductor structure further comprises:

[0115] In step S230, a driving substrate is bonded to the planarization medium layer 800 away from the interlayer medium layer 600, and the driving substrate is connected to the gate interconnection structure 930, the source interconnection structure 910, and the drain interconnection structure 920.

[0116] In step S240, the substrate 100 is removed, and a cathode is formed on the side of the N-type semiconductor layer 210 away from the light emitting layer 220.

[0117] In step S230, a driving substrate is bonded to the planarization medium layer 800 away from the interlayer medium layer 600, and the driving substrate covers and is connected to the gate interconnection structure 930, the source interconnection structure 910, and the drain interconnection structure 920. The driving substrate forms an integral whole with the chip substrate, and the driving substrate is used to supply power to the chip substrate.

[0118] In step S260, the substrate 100 covering the N-type semiconductor layer 210 in the chip substrate is removed, so as to expose the N-type semiconductor layer 210. For example, the substrate 100 of the chip substrate can be removed by using a laser lift-off method. A cathode is formed on the side of the N-type semiconductor layer 210 away from the light emitting layer 220.

[0119] It should be understood that, although Figure 1 The steps in the flowchart of FIG. 10 are displayed in sequence according to the arrows, but these steps are not necessarily executed in sequence according to the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, Figure 1 At least part of the steps in the flowchart of FIG. 10 can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times. The execution sequence of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0120] In one embodiment, please refer to Figure 9 A semiconductor structure is also provided, comprising: an epitaxial layer 200, an isolation dielectric layer 300, a plurality of spaced-apart gate structures 400, an active layer 500, an interlayer dielectric layer 600, and an electrode layer 700.

[0121] The epitaxial layer 200 comprises an N-type semiconductor layer 210, a light-emitting layer 220, and a P-type semiconductor layer 230 stacked in sequence. The light-emitting layer 220 is located on the N-type semiconductor layer 210, and the P-type semiconductor layer 230 is located on the light-emitting layer 220. The P-type semiconductor layer 230 can be selected from semiconductor materials with a composition formula of In x Al y Ga 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and can be doped with P-type dopants such as Mg, Zn, Ca, Sr, Ba, etc. The N-type semiconductor layer 210 can be selected from semiconductor materials with a composition formula of In x Al y Ga 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and can be doped with N-type dopants such as Si, Ge, Sn, etc.

[0122] The openings are located in the epitaxial layer 200, dividing the epitaxial layer 200 into a plurality of light-emitting units.

[0123] The isolation dielectric layer 300 is located on and covers the surface of the epitaxial layer 200 and the surface of the openings.

[0124] The plurality of gate structures 400 are spaced apart, each comprising a gate 410 and a gate 410 dielectric layer, wherein the gate 410 is located on the isolation dielectric layer 300, and the gate 410 dielectric layer is located on the gate 410. The gate structures 400 are arranged one-to-one corresponding to the light-emitting units, and the gate structures 400 extend from the sidewalls of the isolation dielectric layer 300 to the surfaces of the isolation dielectric layer 300 on both sides of the sidewalls.

[0125] The active layer 500 is located on the gate dielectric layer 420, exposing the isolation dielectric layer 300 on at least one side of the opening sidewall.

[0126] The interlayer dielectric layer 600 covers the active layer 500, the gate structures 400, and the isolation dielectric layer 300.

[0127] The electrode layer 700 is located on the interlayer dielectric layer 600, and the electrode layer 700 includes a source electrode 710 and a drain electrode 720, which are respectively connected to two sides of the active layer 500.

[0128] In the embodiment, the transistor structure composed of the gate structure 400, the active layer 500, the interlayer dielectric layer 600 and the electrode layer 700 is embedded between the light emitting units, so that the transistor structure is combined with the light emitting units.

[0129] Meanwhile, the isolation dielectric layer 300 effectively isolates the transistor structure from the light emitting units, so that the device performance is stable.

[0130] In one embodiment, the active layer 500 can expose the isolation dielectric layer 300 located in the opening.

[0131] In other embodiments, the active layer 500 can expose the isolation dielectric layer 300 located on the top surface of the light emitting unit. The active layer 500 forms an opening therein, so that the active layer 500 is separated, thereby forming a plurality of transistor structures.

[0132] In one embodiment, the gate structure 400 and the active layer 500 surround the light emitting unit.

[0133] From the top view, the gate structure 400 surrounds the light emitting unit. It can be understood that the gate electrode 410 and the gate dielectric layer 420 surround the light emitting unit.

[0134] Meanwhile, the active layer 500 surrounds the light emitting unit, for example, the source electrode 710 and the drain electrode 720 can be located on opposite sides of the light emitting unit, and the source interconnection structure 910 connected to the source electrode 710 can also be located on opposite sides of the light emitting unit, and the drain interconnection structure 920 connected to the drain electrode 720 can also be located on opposite sides of the light emitting unit.

[0135] In other examples, the source electrode 710 and the drain electrode 720 can also be located on only one side of the light emitting unit, and the source interconnection structure 910 and the drain interconnection structure 920 connected thereto can also be located on only one side of the light emitting unit, which is not limited herein.

[0136] In one embodiment, the semiconductor structure further includes a planarization dielectric layer 800, a gate interconnection structure 930, a source interconnection structure 910, a drain interconnection structure 920 and an anode 940 interconnection structure.

[0137] The planarization dielectric layer 800 is located on the electrode layer 700 and the interlayer dielectric layer 600, and completely covers the electrode layer 700 and the interlayer dielectric layer 600.

[0138] The gate interconnect structure 930 penetrates through the planarization dielectric layer 800 to the gate 410, connecting the gate 410 to external structures.

[0139] The source interconnect structure 910 penetrates through the planarization dielectric layer 800 to the source 710, connecting the source 710 to external structures.

[0140] The drain interconnect structure 920 penetrates through the planarization dielectric layer 800 to the drain 720, connecting the drain 720 to external structures.

[0141] The anode 940 penetrates through the planarization dielectric layer 800 to the P-type semiconductor layer 230 on the top surface of the light emitting cell, connecting the P-type semiconductor layer 230 to external structures.

[0142] In one embodiment, the semiconductor structure further comprises the planarization dielectric layer 800, the gate interconnect structure 930, the source interconnect structure 910, the drain interconnect structure 920, and the anode 940 interconnect structure.

[0143] The planarization dielectric layer 800 is located on the electrode layer 700 and the interlayer dielectric layer 600, completely covering the electrode layer 700 and the interlayer dielectric layer 600.

[0144] The gate interconnect structure 930 penetrates through the planarization dielectric layer 800 to the gate 410, connecting the gate 410 to external structures.

[0145] The source interconnect structure 910 penetrates through the planarization dielectric layer 800 to the source 710, connecting the source 710 to external structures.

[0146] The drain interconnect structure 920 penetrates through the planarization dielectric layer 800 to the drain 720 and the P-type semiconductor layer 230, connecting the drain 720 to external structures. At this time, the drain interconnect structure 920 can also serve as the anode 940 of the light emitting cell, which is arranged directly opposite to the top surface of the light emitting cell.

[0147] In one embodiment, the semiconductor structure further comprises a driving substrate and a cathode.

[0148] The driving substrate is bonded to the side of the planarization dielectric layer 800 away from the interlayer dielectric layer 600, connecting the gate interconnect structure 930, the source interconnect structure 910, and the drain interconnect structure 920.

[0149] The cathode is located on the side of the N-type semiconductor layer 210 away from the light emitting layer 220, connecting the N-type semiconductor layer 210 to external structures.

[0150] In this embodiment, the driving substrate forms an integral whole with the light emitting cell and the transistor structure, and is used to supply power to the light emitting cell.

[0151] In addition, a switching transistor structure can be formed in the opening formed by etching the epitaxial layer 200, and the active layer 500 and the gate 410 of the switching transistor structure are located in the vertical direction of the bottom of the groove.

[0152] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0153] The technical features of the above-described embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features of the above-described embodiments are not described, however, as long as the combinations of the technical features do not contradict each other, they should be considered as within the scope of the present specification.

[0154] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A semiconductor structure, characterized by, include: Substrate; An epitaxial layer is formed on the substrate. The epitaxial layer includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer stacked together. An opening is formed in the epitaxial layer, which exposes the substrate and divides the epitaxial layer into multiple light-emitting units. An isolation dielectric layer is located on the opening surface and the upper surface of the epitaxial layer; Multiple spaced gate structures include gate and gate dielectric layers stacked sequentially on the isolation dielectric layer. The gate structures are arranged in one-to-one correspondence with the light-emitting units, and the gate structures extend from the sidewall of the isolation dielectric layer to the surface of the isolation dielectric layer located on both sides of the sidewall. An active layer, located on the gate dielectric layer, exposes the isolation dielectric layer located on at least one side of the opening sidewall; An interlayer dielectric layer covers the active layer, the gate structure, and the isolation dielectric layer; An electrode layer, located on the interlayer dielectric layer, includes a source electrode and a drain electrode respectively connected to both sides of the active layer.

2. The semiconductor structure of claim 1, wherein, The active layer is exposed within the isolation medium layer located in the opening.

3. The semiconductor structure of claim 1, wherein, The gate structure and the active layer surround the light-emitting unit.

4. The semiconductor structure of claim 1, wherein, The semiconductor structure also includes: A planarization dielectric layer is located on the electrode layer and the interlayer dielectric layer; A gate interconnect structure extends from the planarized dielectric layer to the gate; The source interconnect structure extends from the planarized dielectric layer to the source. A drain interconnect structure extends from the planarized dielectric layer to the drain. The anode is the P-type semiconductor layer that extends from the planarized dielectric layer to the top surface of the light-emitting unit.

5. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The semiconductor structure also includes: A planarization dielectric layer is located on the electrode layer and the interlayer dielectric layer; A gate interconnect structure extends from the planarized dielectric layer to the gate; The source interconnect structure extends from the planarized dielectric layer to the source. The drain interconnect structure extends from the planarized dielectric layer to the drain and the P-type semiconductor layer, and the drain interconnect structure is disposed opposite to the top surface of the light-emitting unit.

6. The semiconductor structure of claim 4 or 5, wherein, The semiconductor structure also includes: A driving substrate is bonded to the side of the planarized dielectric layer away from the electrode layer, connecting the gate interconnect structure, the source interconnect structure, and the drain interconnect structure. The cathode is located on the side of the N-type semiconductor layer away from the light-emitting layer.

7. A method of fabricating a semiconductor structure, characterized by, include: A chip substrate is provided, the chip substrate including a substrate and an epitaxial layer, the epitaxial layer including an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially formed on the substrate, and an opening is formed in the epitaxial layer to expose the substrate and divide the epitaxial layer into multiple light-emitting units; An isolation dielectric layer is formed on the opening surface and on the epitaxial layer; Multiple gate structures are formed on the isolation dielectric layer at intervals. Each gate structure includes a gate and a gate dielectric layer formed sequentially. Each gate structure is arranged in a one-to-one correspondence with the light-emitting unit, and the gate structure extends from the sidewall of the isolation dielectric layer to the surface of the isolation dielectric layer on both sides of the sidewall. An active layer is formed on the gate dielectric layer, the active layer exposing the isolation dielectric layer located on at least one side of the opening sidewall; An interlayer dielectric layer is formed covering the active layer, the gate structure, and the isolation dielectric layer; An electrode layer is formed on the interlayer dielectric layer, the electrode layer including a source electrode and a drain electrode respectively connected to both sides of the active layer.

8. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: The method for preparing the semiconductor structure further includes: A planarization dielectric layer is formed on the electrode layer and the interlayer dielectric layer; A gate interconnect structure is formed that extends through the planarized dielectric layer to the gate. A source interconnect structure is formed that extends through the planarized dielectric layer to the source electrode; A drain interconnect structure is formed that extends through the planarized dielectric layer to the drain electrode; An anode is formed in the P-type semiconductor layer that extends through the planarized dielectric layer to the top surface of the light-emitting unit.

9. The method for preparing a semiconductor structure according to claim 7, characterized in that, The method for preparing the semiconductor structure further includes: A planarization dielectric layer is formed on the electrode layer and the interlayer dielectric layer; A gate interconnect structure is formed that extends through the planarized dielectric layer to the gate. A source interconnect structure is formed that extends through the planarized dielectric layer to the source electrode; A drain interconnect structure is formed that extends through the planarized dielectric layer to the drain and the P-type semiconductor layer, and the drain interconnect structure is disposed opposite to the top surface of the light-emitting unit.

10. The method for preparing a semiconductor structure according to claim 8 or 9, characterized in that, The method for preparing the semiconductor structure further includes: A driving substrate is bonded to the side of the planarized dielectric layer away from the electrode layer, and the driving substrate connects the gate interconnect structure, the source interconnect structure and the drain interconnect structure. Remove the substrate and form a cathode on the side of the N-type semiconductor layer away from the light-emitting layer.

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