A cross-polarization interference cancellation device based on intermediate frequency sampling

Abstract

The present invention discloses a cross-polarization interference cancellation device based on intermediate frequency sampling, belonging to the field of communication and data transmission. It includes a carrier source, a mixing and filtering unit I, a mixing and filtering unit II, a clock source, ADI, ADII, a delay module I, a delay module II, a convolution operation module, a subtraction operation module, a convolution coefficient generation module, a carrier error conversion, a sampling error conversion, a digital down-conversion module, a polarization error synthesis module, a carrier error extraction module, a timing error extraction module, a matched filtering module I1, a matched filtering module II, a digital AGC, a polarization error extraction module I, a polarization error extraction module II, and a decimation module. The present invention has the characteristics of high implementation reliability, high stability, and low implementation complexity.

Description

Technical Field

[0001] The present invention relates to the field of communication and data transmission, and is particularly applicable to cross-polarization interference cancellation between left- and right-handed received signals in a data receiving subsystem of a satellite communication and data ground receiving station. Background Art

[0002] Traditional cross-polarization interference cancellation devices are mainly divided into three types. The first type of cross-polarization interference cancellation device is implemented through an all-analog signal link before AD sampling. Its advantage is that it eliminates the influence of cross-polarization interference before digital demodulation, improves the demodulation performance, and reduces the resource utilization rate of digital devices. The disadvantage is that it is difficult to implement and has poor performance. The second type of cross-polarization interference cancellation device performs cross-polarization interference cancellation on the cross-polarization interference cancellation results of the two-channel symbol synchronization outputs after completing the demodulation and symbol synchronization of the two channels. The advantage is excellent performance. The disadvantage is that it consumes a huge amount of resources of digital devices, and can only be applied to scenarios where the symbol rates of the two signals are exactly the same, and it can only be implemented after both signals are successfully demodulated, so the scope of use is limited. The third type of cross-polarization interference cancellation device is based on the intermediate frequency sampling data of the two signals and realizes cross-polarization interference cancellation through all-digital signal processing. However, before realizing cross-polarization interference cancellation, both input signals have undergone a large amount of digital signal processing, thereby introducing a large amount of operation errors, reducing the cross-polarization interference cancellation accuracy, and at the same time consuming a large amount of digital device resources.

[0003] Compared with traditional cross-polarization interference cancellation devices, the present invention finally realizes cross-polarization interference cancellation of the input radio frequency signal by combining digital signal processing and analog signal processing, thereby greatly reducing the resource utilization rate of digital devices and the complexity of analog signal processing, and facilitating implementation and popularization. The present invention uses multi-stage digital signal processing to generate polarization errors, and uses this error to directly perform cross-polarization interference cancellation processing on the signal after intermediate frequency sampling of the signal, avoiding additional error interference brought by subsequent digital signal processing to cross-polarization interference cancellation processing, thereby improving the accuracy of cross-polarization interference cancellation, and further improving the system performance. The present invention completes the preliminary processing of the radio frequency modulation signal two while respectively completing the timing synchronization and carrier synchronization of the radio frequency modulation signal one by adopting the methods of analog variable sampling clock and analog mixing filtering, so that when performing cross-polarization interference cancellation, it can adapt to the situation where the symbol rates of the two signals are inconsistent and the carrier frequencies are inconsistent, and has a wide range of applications. Summary of the Invention

[0004] The purpose of the present invention is to provide a cross-polarization interference cancellation device based on intermediate frequency sampling to avoid the deficiencies in the above background art. The present invention also has the characteristics of high implementation reliability, high stability, and low implementation complexity.

[0005] The purpose of the present invention is achieved as follows:

[0006] A cross-polarization interference cancellation device based on intermediate-frequency sampling, comprising a carrier source 1, a mixing and filtering unit I 2-1, a mixing and filtering unit II 2-2, a clock source 3, an ADI 4-1, an ADII 4-2, a delay module I 5-1, a delay module II 5-2, a convolution operation module 6, a subtraction operation module 7, a convolution coefficient generation module 8, a carrier error conversion DDS 9, a sampling error conversion DDS 10, a digital down-conversion module 11, a polarization error synthesis module 12, a carrier error extraction module 13, a timing error extraction module 14, a matched filtering module I 15-1, a matched filtering module II 15-2, a digital AGC 16, a polarization error extraction module I 17-1, a polarization error extraction module II 17-2, and a decimation module 18;

[0007] The mixing and filtering unit I 2-1 and the mixing and filtering unit II 2-2 respectively perform mixing and filtering processing on two input radio frequency modulated signals to generate two analog intermediate-frequency modulated signals. The two analog intermediate-frequency modulated signals are respectively sampled by the ADI 4-1 and the ADII 4-2 and converted into two intermediate-frequency sampled digital signals. The first intermediate-frequency sampled digital signal is delayed by the delay module I 5-1 and then transmitted to the subtraction operation module 7. The second intermediate-frequency sampled digital signal is split and then transmitted to the delay module II 5-2 and the convolution operation module 6 respectively. The convolution operation module 6 performs convolution operation processing on the input signal and transmits the processed signal to the subtraction operation module 7. The subtraction operation module 7 performs subtraction operation on the two received intermediate-frequency sampled digital signals to generate an intermediate-frequency sampled digital signal and transmits it to the digital down-conversion module 11. The digital down-conversion module 11 performs digital down-conversion processing on the input intermediate-frequency sampled digital signal to generate two digital baseband signals of I / Q, which respectively enter the digital AGC 16 through the matched filtering module I 15-1 and the matched filtering module II 15-2, and are split to generate two groups of I / Q digital baseband signals;

[0008] The first group of I / Q digital baseband signals is transmitted to the timing error extraction module 14. The timing error extraction module 14 generates an AD sampling timing error value, and the current generated error value is used to adjust and output an accumulated step signal in real time. The accumulated step signal is transmitted to the sampling error conversion DDS 10. The signal output by the sampling error conversion DDS 10 is transmitted to the clock source 3. The clock source 3 sets parameters according to the symbol rate, adjusts the frequency value of the internally generated clock signal, and performs mixing and filtering processing on the internally generated clock signal and the received signal output by the sampling error conversion DDS 10 to generate an AD sampling clock signal and transmit it to the ADI 4-1 and the ADII 4-2, thereby directly realizing signal timing synchronization through AD sampling;

[0009] The second group of I / Q two-way digital baseband signals are transmitted to the decimation module 18. The decimation module 18 extracts the peak points of the input signal according to one-time sampling and outputs I / Q two-way peak point signals. The I / Q two-way peak point signals are then split to generate two groups of I / Q two-way peak point signals;

[0010] The first group of I / Q two-way peak point signals are transmitted to the carrier error extraction module 13. The carrier error extraction module 13 receives the I / Q two-way peak point signals and generates a carrier error value. Then, it adjusts the accumulation step value according to the currently generated error value and transmits the real-time updated accumulation step value to the carrier error conversion DDS9. The signal output by the carrier error conversion DDS9 is transmitted to the carrier source 1. The carrier source 1 performs mixing and filtering processing on the internally generated fixed-frequency signal and the received signal output by the carrier error conversion DDS9 to generate a carrier signal, and transmits the carrier signal to the mixing and filtering unit I2-1 and the mixing and filtering unit II2-2 respectively, thereby completing the carrier synchronization of the RF modulation signal through mixing and filtering processing;

[0011] The second group of I / Q two-way peak point signals are respectively transmitted to the polarization error extraction module I17-1 and the polarization error extraction module II17-2. The polarization error extraction module I17-1 and the polarization error extraction module II17-2 process the input I / Q two-way peak point signals respectively according to the input modulation system indication signal, generate I / Q two-way polarization error signals and output them to the polarization error synthesis module 12 respectively. The polarization error synthesis module 12 synthesizes the input I / Q two-way polarization error signals, generates a polarization error signal and transmits it to the convolution coefficient generation module 8. The convolution coefficient generation module 8 receives the polarization error signal output by the polarization error synthesis module 12, and at the same time receives the second intermediate frequency sampled digital signal processed by the delay module II5-2, calculates and generates a convolution coefficient signal and transmits the convolution coefficient signal to the convolution operation module 6;

[0012] The second intermediate frequency sampled digital signal processed by the convolution operation module 6 and the first intermediate frequency sampled digital signal processed by the delay module I5-1 are respectively transmitted to the subtraction operation module 7. The subtraction operation module 7 performs subtraction operation on the two received signals to complete the cross-polarization interference cancellation processing of the first intermediate frequency sampled digital signal.

[0013] The present invention has the following advantages compared with the background technology:

[0014] 1. Compared with the traditional cross-polarization interference cancellation device, the present invention finally realizes the cross-polarization interference cancellation of the input RF signal by combining digital signal processing and analog signal processing, thereby greatly reducing the resource utilization rate of digital devices and the complexity of analog signal processing, and facilitating implementation and popularization.

[0015] 2. The present invention generates polarization error by using multi-stage digital signal processing, and uses this error to directly perform cross-polarization interference cancellation processing on the signal after intermediate frequency sampling of the signal, avoiding the additional error interference brought by subsequent digital signal processing to the cross-polarization interference cancellation processing, thereby improving the accuracy of cross-polarization interference cancellation and further improving the system performance.

[0016] 3. By adopting the methods of analog variable sampling clock and analog mixing filtering, the present invention completes the timing synchronization and carrier synchronization of the radio frequency modulation signal 1 respectively, and at the same time completes the preliminary processing of the radio frequency modulation signal 2, so that it can adapt to the situations of inconsistent symbol rates and inconsistent carrier frequencies of the two signals during cross-polarization interference cancellation, and has a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is the principle block diagram of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0018] Refer to Figure 1, this embodiment includes a cross-polarization interference cancellation device based on intermediate frequency sampling, which consists of a carrier source 1, a mixing and filtering unit I 2-1 and a mixing and filtering unit II 2-2, a clock source 3, an ADI 4-1 and an ADII 4-2, a delay module I 5-1 and a delay module II 5-2, a convolution operation module 6, a subtraction operation module 7, a convolution coefficient generation module 8, a carrier error conversion DDS 9, a sampling error conversion DDS 10, a digital down-conversion module 11, a polarization error synthesis module 12, a carrier error extraction module 13, a timing error extraction module 14, a matching filtering module I 15-1 and a matching filtering module II 15-2, a digital AGC 16, a polarization error extraction module I 17-1 and a polarization error extraction module II 17-2, and a decimation module 18. Among them, the mixing and filtering unit I 2-1 and the mixing and filtering unit II 2-2 respectively perform mixing and filtering processing on the two input RF modulated signals to generate two analog intermediate frequency modulated signals. The two analog intermediate frequency modulated signals are respectively sampled by the ADI 4-1 and the ADII 4-2 and converted into two intermediate frequency sampled digital signals. The first intermediate frequency sampled digital signal is transmitted to the subtraction operation module 7 after being delayed by the delay module I 5-1. The second intermediate frequency sampled digital signal is branched and transmitted to the delay module II 5-2 and the convolution operation module 6 respectively. The convolution operation module 6 performs convolution operation processing on the input signal and transmits the processed signal to the subtraction operation module 7. The subtraction operation module 7 performs subtraction operation on the two received intermediate frequency sampled digital signals to generate an intermediate frequency sampled digital signal and transmits it to the digital down-conversion module 11. The digital down-conversion module 11 performs digital down-conversion processing on the input intermediate frequency sampled digital signal to generate I / Q two digital baseband signals, which are respectively processed by the matching filtering module I 15-1 and the matching filtering module II 15-2 and the digital AGC 16, and then branched to generate two groups of I / Q two digital baseband signals. The first group of I / Q two digital baseband signals is transmitted to the timing error extraction module 14. The timing error extraction module 14 generates an AD sampling timing error value, and the current generated error value is used to adjust and output an accumulated step signal in real time. The accumulated step signal is transmitted to the sampling error conversion DDS 10. The signal output by the sampling error conversion DDS 10 is transmitted to the clock source 3. The clock source 3 sets parameters according to the symbol rate, adjusts the frequency value of the internally generated clock signal, and performs mixing and filtering processing on the internally generated clock signal and the received signal output by the sampling error conversion DDS 10 to generate an AD sampling clock signal and transmit it to the ADI 4-1 and the ADII 4-2, so as to directly realize the timing synchronization of the signal through AD sampling.The second group of I / Q two-way digital baseband signals are transmitted to the decimation module 18. The decimation module 18 extracts the peak points of the input signal according to one-time sampling and outputs I / Q two-way peak point signals. The I / Q two-way peak point signals are then split to generate two groups of I / Q two-way peak point signals. The first group of I / Q two-way peak point signals are transmitted to the carrier error extraction module 13. The carrier error extraction module 13 receives the I / Q two-way peak point signals and generates a carrier error value, then adjusts the accumulation step value according to the currently generated error value, and transmits the real-time updated accumulation step value to the carrier error conversion DDS9. The signal output by the carrier error conversion DDS9 is transmitted to the carrier source 1. The carrier source 1 performs mixing and filtering processing on the internally generated fixed-frequency signal and the received signal output by the carrier error conversion DDS9 to generate a carrier signal, and transmits the carrier signal to the mixing and filtering unit I2-1 and the mixing and filtering unit II2-2 respectively, and then completes the carrier synchronization of the radio frequency modulation signal through the mixing and filtering processing. The second group of I / Q two-way peak point signals are transmitted to the polarization error extraction module I17-1 and the polarization error extraction module II17-2 respectively. The polarization error extraction module I17-1 and the polarization error extraction module II17-2 process the input I / Q two-way peak point signals according to the input modulation system indication signal respectively, generate I / Q two-way polarization error signals and output them to the polarization error synthesis module 12 respectively. The polarization error synthesis module 12 synthesizes the input I / Q two-way polarization error signals, generates a polarization error signal and transmits it to the convolution coefficient generation module 8. The convolution coefficient generation module 8 receives the polarization error signal output by the polarization error synthesis module 12, and at the same time receives the second intermediate frequency sampling digital signal processed by the delay module II5-2, calculates and generates a convolution coefficient signal and transmits the convolution coefficient signal to the convolution operation module 6.

[0019] The second intermediate frequency sampling digital signal processed by the convolution operation module 6 and the first intermediate frequency sampling digital signal processed by the delay module I5-1 are transmitted to the subtraction operation module 7 respectively. The subtraction operation module 7 performs subtraction operation on the two received signals to complete the cross-polarization interference cancellation processing of the first intermediate frequency sampling digital signal. In the embodiment, the delay module I5-1, the delay module II5-2, the convolution operation module 6, the subtraction operation module 7, the convolution coefficient generation module 8, the digital down-conversion module 11, the polarization error synthesis module 12, the carrier error extraction module 13, the timing error extraction module 14, the matched filtering module I15-1 and the matched filtering module II15-2, the digital AGC16, the polarization error extraction module I17-1 and the polarization error extraction module II17-2, and the decimation module 18 are all implemented by using the Virtex7 type FPGA produced by XILINX Corporation of the United States.

[0020] The brief working principle of the present invention is as follows:

[0021] When a cross-polarization interference cancellation device based on intermediate frequency sampling is working, first, the mixing and filtering unit I2-1 and the mixing and filtering unit II2-2 respectively perform mixing and filtering processing on two input radio frequency modulated signals to generate two analog intermediate frequency modulated signals. The two analog intermediate frequency modulated signals are respectively sampled by ADI4-1 and ADII4-2 and converted into two intermediate frequency sampled digital signals. Among them, the first intermediate frequency sampled digital signal is transmitted to the subtraction operation module 7 after being delayed by the delay module I5-1. The second intermediate frequency sampled digital signal is divided and then transmitted to the delay module II5-2 and the convolution operation module 6 respectively. The convolution operation module 6 performs convolution operation processing on the input signal and transmits the processed signal to the subtraction operation module 7. The subtraction operation module 7 performs subtraction operation on the two received intermediate frequency sampled digital signals to generate an intermediate frequency sampled digital signal and transmits it to the digital down-conversion module 11. The digital down-conversion module 11 performs digital down-conversion processing on the input intermediate frequency sampled digital signal to generate I / Q two digital baseband signals, which are respectively processed by the matching filtering module I15-1, the matching filtering module II15-2 and the digital AGC16, and then divided to generate two groups of I / Q two digital baseband signals. The first group of I / Q two digital baseband signals is transmitted to the timing error extraction module 14. The timing error extraction module 14 generates an AD sampling timing error value, and the current generated error value is used to adjust and output an accumulated step signal in real time. The accumulated step signal is transmitted to the sampling error conversion DDS10. The signal output by the sampling error conversion DDS10 is transmitted to the clock source 3. The clock source 3 sets parameters according to the symbol rate, adjusts the frequency value of the internally generated clock signal, and performs mixing and filtering processing on the internally generated clock signal and the received signal output by the sampling error conversion DDS10 to generate an AD sampling clock signal and transmit it to ADI4-1 and ADII4-2, thereby directly realizing signal timing synchronization through AD sampling.The second group of I / Q two-way digital baseband signals are transmitted to the decimation module 18. The decimation module 18 extracts the peak points of the input signal at a single sampling rate and outputs I / Q two-way peak point signals. The I / Q two-way peak point signals are then split to generate two groups of I / Q two-way peak point signals. The first group of I / Q two-way peak point signals are transmitted to the carrier error extraction module 13. The carrier error extraction module 13 receives the I / Q two-way peak point signals and generates a carrier error value. Then, it adjusts the accumulation step value according to the currently generated error value and transmits the real-time updated accumulation step value to the carrier error conversion DDS9. The signal output by the carrier error conversion DDS9 is transmitted to the carrier source 1. The carrier source 1 performs a mixing and filtering process on the internally generated fixed-frequency signal and the received signal output by the carrier error conversion DDS9 to generate a carrier signal, and transmits the carrier signal to the mixing and filtering unit I2-1 and the mixing and filtering unit II2-2 respectively, thereby completing the carrier synchronization of the radio frequency modulation signal through the mixing and filtering process. The second group of I / Q two-way peak point signals are respectively transmitted to the polarization error extraction module I17-1 and the polarization error extraction module II17-2. The polarization error extraction module I17-1 and the polarization error extraction module II17-2 process the input I / Q two-way peak point signals according to the input modulation system indication signal, generate I / Q two-way polarization error signals and output them to the polarization error synthesis module 12 respectively. The polarization error synthesis module 12 synthesizes the input I / Q two-way polarization error signals, generates a polarization error signal and transmits it to the convolution coefficient generation module 8. The convolution coefficient generation module 8 receives the polarization error signal output by the polarization error synthesis module 12 and simultaneously receives the second intermediate frequency sampled digital signal processed by the delay module II5-2, calculates and generates a convolution coefficient signal and transmits the convolution coefficient signal to the convolution operation module 6.

[0022] The second intermediate frequency sampled digital signal processed by the convolution operation module 6 and the first intermediate frequency sampled digital signal processed by the delay module I5-1 are respectively transmitted to the subtraction operation module 7. The subtraction operation module 7 performs a subtraction operation on the two received signals, thereby completing the cross-polarization interference cancellation process for the first intermediate frequency sampled digital signal.

Claims

1. A cross-polarization interference cancellation device based on intermediate frequency sampling, characterized in that It includes a carrier source (1), a mixing and filtering unit I (2-1), a mixing and filtering unit II (2-2), a clock source (3), ADI (4-1), ADII (4-2), a delay module I (5-1), a delay module II (5-2), a convolution operation module (6), a subtraction operation module (7), a convolution coefficient generation module (8), a carrier error conversion DDS (9), a sampling error conversion DDS (10), a digital down-conversion module (11), a polarization error synthesis module (12), a carrier error extraction module (13), a timing error extraction module (14), a matched filtering module I (15-1), a matched filtering module II (15-2), a digital AGC (16), a polarization error extraction module I (17-1), a polarization error extraction module II (17-2), and a decimation module (18); The mixing and filtering unit I (2-1) and the mixing and filtering unit II (2-2) respectively perform mixing and filtering processing on two input RF modulated signals to generate two analog intermediate-frequency modulated signals. The two analog intermediate-frequency modulated signals are respectively sampled by ADI (4-1) and ADI (4-2) and converted into two intermediate-frequency sampled digital signals. Among them, the first intermediate-frequency sampled digital signal is transmitted to the subtraction operation module (7) after being delayed by the delay module I (5-1). The second intermediate-frequency sampled digital signal is split and then transmitted to the delay module II (5-2) and the convolution operation module (6) respectively. The convolution operation module (6) performs convolution operation processing on the input signal and transmits the processed signal to the subtraction operation module (7). The subtraction operation module (7) performs subtraction operation on the two received intermediate-frequency sampled digital signals to generate an intermediate-frequency sampled digital signal and transmits it to the digital down-conversion module (11). The digital down-conversion module (11) performs digital down-conversion processing on the input intermediate-frequency sampled digital signal to generate two digital baseband signals of I / Q, which respectively enter the digital AGC (16) through the matched filtering module I (15-1) and the matched filtering module II (15-2), and are split to generate two groups of I / Q digital baseband signals; The first group of I / Q digital baseband signals is transmitted to the timing error extraction module (14). The timing error extraction module (14) generates an AD sampling timing error value, and the current generated error value is used to adjust and output an accumulated step signal in real time. The accumulated step signal is transmitted to the sampling error conversion DDS (10). The signal output by the sampling error conversion DDS (10) is transmitted to the clock source (3). The clock source (3) sets parameters according to the symbol rate, adjusts the frequency value of the internally generated clock signal, and performs mixing and filtering processing on the internally generated clock signal and the received signal output by the sampling error conversion DDS (10) to generate an AD sampling clock signal and transmit it to ADI (4-1) and ADII (4-2), thereby directly realizing signal timing synchronization through AD sampling; The second group of I / Q two-way digital baseband signals are transmitted to the decimation module (18). The decimation module (18) extracts the peak points of the input signal according to one-time sampling and outputs I / Q two-way peak point signals. The I / Q two-way peak point signals are then split to generate two groups of I / Q two-way peak point signals; The first group of I / Q two-way peak point signals are transmitted to the carrier error extraction module (13). The carrier error extraction module (13) receives the I / Q two-way peak point signals and generates a carrier error value. Then, it adjusts the accumulation step value according to the currently generated error value and transmits the real-time updated accumulation step value to the carrier error conversion DDS (9). The signal output by the carrier error conversion DDS (9) is transmitted to the carrier source (1). The carrier source (1) performs mixing and filtering processing on the internally generated fixed-frequency signal and the received signal output by the carrier error conversion DDS (9) to generate a carrier signal, and transmits the carrier signal to the mixing and filtering unit I (2-1) and the mixing and filtering unit II (2-2) respectively, thereby completing the carrier synchronization of the radio frequency modulation signal through the mixing and filtering processing; The second group of I / Q two-way peak point signals are respectively transmitted to the polarization error extraction module I (17-1) and the polarization error extraction module II (17-2). The polarization error extraction module I (17-1) and the polarization error extraction module II (17-2) process the input I / Q two-way peak point signals respectively according to the input modulation system indication signal, generate I / Q two-way polarization error signals and output them to the polarization error synthesis module (12) respectively. The polarization error synthesis module (12) synthesizes the input I / Q two-way polarization error signals, generates a polarization error signal and transmits it to the convolution coefficient generation module (8). The convolution coefficient generation module (8) receives the polarization error signal output by the polarization error synthesis module (12) and simultaneously receives the second intermediate frequency sampled digital signal processed by the delay module II (5-2), calculates and generates a convolution coefficient signal and transmits the convolution coefficient signal to the convolution operation module (6); The second intermediate frequency sampled digital signal processed by the convolution operation module (6) and the first intermediate frequency sampled digital signal processed by the delay module I (5-1) are respectively transmitted to the subtraction operation module (7). The subtraction operation module (7) performs subtraction operation on the two received signals to complete the cross-polarization interference cancellation processing of the first intermediate frequency sampled digital signal.

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