Display device

Abstract

The present application relates to a display device capable of realizing seamless border between a display region and a non-display region. The display device has: a first substrate having a display region including pixels, and a peripheral region surrounding the display region and including peripheral circuits; a second substrate disposed in opposition to the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate, in the peripheral circuits of the first substrate, having a plurality of gate wirings arranged at intervals in a first direction, and a plurality of signal lines arranged at intervals in a second direction intersecting the first direction, the second substrate having a black matrix at a position opposed to the display region and the peripheral circuits, the black matrix having a lattice region, the lattice region of the black matrix being configured so as to overlap the plurality of gate wirings and the plurality of signal lines of the peripheral circuits.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device. Background Technology

[0002] In recent years, the development of transparent displays capable of visually recognizing a background on the opposite side from one side has been ongoing (see Patent Document 1). In transparent displays, various inspection circuits and wiring are arranged between the display area and the gate wiring area located on the array substrate side. A black matrix located on the opposing substrate side is formed only in the display area (see Patent Document 2).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2020-160254

[0006] Patent Document 2: Japanese Patent Application Publication No. 2021-92702 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] By setting a black matrix in the display area, light reflection caused by wiring in the display area can be suppressed. On the other hand, in order to visually identify the background, the black matrix is ​​not covered in the surrounding area (non-display area). Various inspection circuits not covered by the black matrix do not suppress light reflection from wiring, etc. The material of the outer surface of the various inspection circuits provided on the array substrate is different from the material of the black matrix provided on the opposing substrate. Therefore, when visually identifying from the opposing substrate side, the color tone changes due to the difference in materials.

[0009] Alternatively, it is also considered that the display area is formed into a grid shape, like a typical LCD with a backlight, and a black matrix is ​​formed on the entire surface of the peripheral area (non-display area). However, when used as a transparent display, the frame edge becomes a light-blocking area, which may hinder its design. As a transparent display, it is preferable that the peripheral area is also transparent as the display area.

[0010] Therefore, in one embodiment of the present invention, one objective is to achieve seamless boundary between the display area and the non-display area of ​​the display device.

[0011] Methods for solving problems

[0012] A display device according to one embodiment of the present invention includes: a first substrate having a display area including pixels and a peripheral area surrounding the display area and including peripheral circuitry; a second substrate disposed opposite to the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate. In the peripheral circuitry of the first substrate, there are a plurality of gate wirings arranged at intervals in a first direction and a plurality of signal lines arranged at intervals in a second direction intersecting the first direction. The second substrate has a black matrix with a grid area at a position opposite to the display area and the peripheral circuitry, and the grid area of ​​the black matrix is ​​arranged to overlap with the plurality of gate wirings and the plurality of signal lines of the peripheral circuitry. Attached Figure Description

[0013] Figure 1 This is a perspective view illustrating a display device according to one embodiment of the present invention.

[0014] Figure 2 It is shown that... Figure 1 A cross-sectional schematic diagram of the corresponding structure between A1 and A2 of the display device shown.

[0015] Figure 3 This is a plan view illustrating the configuration of the first substrate of a display device according to one embodiment of the present invention.

[0016] Figure 4 This is a plan view illustrating the configuration of the second substrate of a display device according to one embodiment of the present invention.

[0017] Figure 5 This is a cross-sectional view of a pixel in a display device according to one embodiment of the present invention.

[0018] Figure 6 It is a planar layout of a black matrix set on the second substrate.

[0019] Figure 7 This is an enlarged diagram of the pixel, gate inspection circuit, short ring, common wiring, and gate wiring disposed on the first substrate.

[0020] Figure 8 This is an enlarged view of the pixel, gate inspection circuit, short-circuit ring, common wiring, and planarization film disposed on the first substrate.

[0021] Figure 9 This is an enlarged view of the pixel, gate inspection circuit, short-circuit ring, common wiring, and transparent conductive layer and fourth conductive layer disposed on the first substrate.

[0022] Figure 10 This is a circuit diagram of a gate inspection circuit located in the peripheral area.

[0023] Figure 11 It is a planar layout of the gate inspection circuit.

[0024] Figure 12 yes Figure 11 An enlarged view of the area in the gate inspection circuit shown.

[0025] Figure 13 It includes Figure 11 The planar layout of the area of ​​the gate inspection circuit is shown.

[0026] Figure 14 It is a circuit diagram of a short-circuit ring set in the surrounding area.

[0027] Figure 15 It is a planar layout of short-circuit rings.

[0028] Figure 16 yes Figure 15 An enlarged view of the region within the short-circuit loop is shown.

[0029] Figure 17 It includes Figure 15 The planar layout of the short-circuit loop region is shown.

[0030] Explanation of reference numerals in the attached figures

[0031] 10: Display device; 11: Display panel; 12: Display area; 14: Peripheral area; 16: Common wiring; 18: Common wiring; 22: Common wiring area; 24: Flexible printed circuit; 26: Terminal portion; 28: Gate drive circuit; 32: Gate wiring area; 34: Flexible printed circuit; 36: Terminal portion; 38: Source drive circuit; 42: Source wiring area; 46: ESD protection circuit; 48: Gate inspection circuit; 52: Source inspection circuit; 54: Inspection line; 56: QD pad; 58: ESD protection circuit; 59: ESD protection circuit; 102: Display area; 104: Light source; 150: Array substrate; 152: Opposing substrate; 202: First conductor. 203: Gate insulating film; 204: Oxide semiconductor layer; 205: Insulating film; 206: Second conductive layer; 207: Planarization film; 208: Third conductive layer; 209: Insulating film; 210: First grid region; 211: Liquid crystal layer; 212: Transparent conductive layer; 213: Opening; 214: Fourth conductive layer; 215: Opening; 216: Pixel electrode; 217: Opening; 218: Common electrode; 219: Light-shielding layer; 220: Second grid region; 221: Seal; GL: Gate wiring; SL: Source wiring; S: Signal line; SG; SR: Short-circuit ring; CL: Common wiring; CW: Capacitor wiring; C: Holding capacitor; LE: Liquid crystal element; PIX: Pixel. Detailed Implementation

[0032] The various embodiments of the present invention will be described below with reference to the accompanying drawings. It should be noted that the present invention can be implemented in many ways without departing from its spirit and is not limited to the embodiments illustrated below. Furthermore, regarding the drawings, to make the description clearer, the width, thickness, shape, etc., of each part are sometimes schematically shown compared to the actual embodiment; however, these schematic diagrams are examples and do not limit the interpretation of the present invention. In addition, in this specification and the drawings, elements that are the same as or similar to elements described with respect to previously mentioned drawings are sometimes labeled with the same reference numerals and repeated descriptions are omitted. It should be noted that in this specification, ordinal numbers are added for the convenience of distinguishing parts, portions, etc., and do not indicate priority or order.

[0033] In this invention, when a single membrane is processed to form multiple membranes, these multiple membranes may sometimes have different functions or effects. However, these multiple membranes originate from a membrane formed as the same layer in the same process, and have the same layer structure and the same material. Therefore, these multiple membranes are defined as having a structure existing in the same layer. Furthermore, in the case of processing a single membrane to form multiple membranes, this specification may distinguish them as -1, -2, etc.

[0034] It should be noted that in this specification, terms such as "upper" and "lower" indicate the relative positional relationship between the structure of interest and other structures. In this specification, when viewed from the side, the direction from the first substrate (described later) toward the pixel electrode is defined as "upper," and the opposite direction is defined as "lower." In this specification and claims, when describing a manner in which other structures are disposed on top of a certain structure, the term "upper," unless otherwise specified, includes both the case where other structures are disposed directly above a certain structure in contact with it, and the case where other structures are disposed above a certain structure, further separated by another structure.

[0035] Furthermore, in this specification, "bottom-gate driving" refers to controlling the transistor's on / off state using a gate electrode disposed below the semiconductor layer. "Top-gate driving" refers to controlling the transistor's on / off state using a gate electrode disposed above the semiconductor layer. "Dual-gate driving" refers to controlling the transistor's on / off state by inputting the same control signal to both gate electrodes disposed above and below the semiconductor layer.

[0036] (First Embodiment)

[0037] Reference Figures 1 to 17 This invention describes a display device 10 according to one embodiment of the present invention.

[0038] <Overview of the display device>

[0039] Figure 1 This is a perspective view illustrating a display device 10 according to one embodiment of the present invention. The display device 10 includes a display panel 102, a light source 104, a first transparent substrate 151A and a second transparent substrate 151B sandwiching the display panel 102. The display panel 102 includes an array substrate 150, an opposing substrate 152, a liquid crystal layer (not shown) between the array substrate 150 and the opposing substrate 152, a gate driving circuit 28, and a source driving circuit 38. (See the following references...) Figure 1 In the description, one direction in the plane of the display panel 102 is designated as direction D1, the direction orthogonal to direction D1 is designated as direction D2, and the direction orthogonal to the plane D1-D2 is designated as direction D3.

[0040] The array substrate 150 and the opposing substrate 152 are transparent. Preferably, the array substrate 150 and the opposing substrate 152 are transparent to visible light. The opposing substrate 152 is arranged opposite to the array substrate 150 in the D3 direction. The array substrate 150 and the opposing substrate 152 are bonded together by a sealing material 154 in a state of being arranged opposite each other with a gap. A liquid crystal layer (not shown) is provided in the gap between the array substrate 150 and the opposing substrate 152.

[0041] The display panel 102 has a display area 12 and a peripheral area 14 outside the display area 12. In the display area 12, a plurality of pixels are arranged in the row direction and the column direction. Here, the row direction refers to the direction parallel to the D1 direction, and the column direction refers to the direction parallel to the D2 direction. In the display area 12, m pixels are arranged in the row direction and n pixels are arranged in the column direction. Furthermore, the values ​​of m and n are appropriately set corresponding to the display resolution in the vertical direction and the display resolution in the horizontal direction. In the display area 12, gate wiring (also called scan signal lines) is arranged along the D1 direction, and source wiring (also called data signal lines) is arranged along the D2 direction.

[0042] A gate drive circuit 28 and a source drive circuit 38 are provided in the peripheral region 14 of the array substrate 150. Figure 1 The diagram illustrates a case where the gate drive circuit 28 and source drive circuit 38 are provided by an integrated circuit (IC) and mounted on the array substrate 150 in a COG (Chip on Glass) manner. The gate drive circuit 28 and source drive circuit 38 are not limited to the illustrated configuration; they can be mounted in a COF (Chip on Film) manner or formed from thin-film transistors (TFTs) of the array substrate 150.

[0043] A gate wiring region 32, a common wiring region 22, and a source wiring region 42 are disposed in the peripheral region 14. The gate wiring region 32 is a region having a pattern formed by wiring connecting the gate driving circuit 28 to the gate wiring GL disposed in the display region 12. The common wiring region 22 is a region having a pattern formed by common wiring. In terms of the circuitry, the common wiring region 22 serves as a common electrode 218 disposed in the opposing substrate 152 (see...). Figure 5 It is used for wiring that applies a common voltage. The source wiring area 42 is an area with a pattern formed by wiring that connects the source drive circuit 38 to the source wiring SL arranged in the display area 12.

[0044] The light source 104 has a structure along the D1 direction. The light source 104 is, for example, composed of light-emitting diodes (LEDs) arranged along the D1 direction. The detailed structure of the light source 104 is not limited; in addition to LEDs arranged along the D1 direction, it may also include optical components such as reflectors, diffusers, and lenses. The light source 104 and the light-emitting control circuit 110 that controls the light source 104 can also be configured as separate components independent of the display panel 102. Furthermore, the timing of light emission of the light source 104 can be controlled by the light-emitting control circuit 110, which is synchronized with the gate driving circuit 28 and the source driving circuit 38. The light-emitting control circuit 110 that controls the light source 104 can be configured as a separate component independent of the display panel 102, like the light source 104, or it can be mounted as a separate component on the array substrate 150, or it can be assembled into the gate driving circuit 28 or the source driving circuit 38.

[0045] The first transparent substrate 151A and the second transparent substrate 151B are disposed such that they are sandwiched between the display area 12 and the peripheral area 14. The first transparent substrate 151A and the second transparent substrate 151B function as protective components for the display panel 102. Additionally, as shown in reference... Figure 2 As explained, the first transparent substrate 151A and the second transparent substrate 151B function as light guide plates that guide light emitted from the light source 104 into the display panel 102.

[0046] Figure 2 Showing with Figure 1 The cross-sectional structure of the display device 10 corresponding to A1-A2 is shown. Figure 2As shown, a first transparent substrate 151A is provided on the array substrate 150 side of the display panel 102, and a second transparent substrate 151B is provided on the opposing substrate 152 side. The first transparent substrate 151A and the second transparent substrate 151B are made of glass or plastic substrates. Preferably, the first transparent substrate 151A and the second transparent substrate 151B have the same refractive index as the array substrate 150 and the opposing substrate 152. The array substrate 150 is bonded to the first transparent substrate 151A, and the opposing substrate 152 is bonded to the second transparent substrate 151B by a transparent adhesive (not shown).

[0047] The display panel 102 is arranged with an array substrate 150 and an opposing substrate 152 facing each other, and a liquid crystal layer 211 is provided between them. The array substrate 150 is larger than the opposing substrate 152, and a portion of the peripheral region 14 is exposed from the opposing substrate 152. A driving circuit is mounted in the array substrate 150. Figure 2 (The source drive circuit is 38). In addition, a flexible printed circuit 34 is mounted on the periphery of the array substrate 150.

[0048] The light source 104 is arranged adjacent to one side of the first transparent substrate 151A or the second transparent substrate 151B. Figure 2 The diagram shows a configuration in which the light source 104 is arranged along one side of the second transparent substrate 151B. Additionally, Figure 2 The diagram shows a configuration in which the light source 104 is mounted on the array substrate 150, but the configuration of the light source 104 is not limited. As long as the mounting position can be fixed, the mounting structure is not limited. For example, the light source 104 may also be supported by a frame surrounding the display panel 102.

[0049] like Figure 2 As shown, the light source 104 is arranged along the first side surface 15C of the second transparent substrate 151B. Figure 2 As shown, light source 104 irradiates light L onto the first side surface 15C of the second transparent substrate 151B. Since light source 104 emits light L toward the first side surface 15C, it is also referred to as a side light source. The first side surface 15C of the second transparent substrate 151B, which is opposite to light source 104, becomes the light incident surface.

[0050] like Figure 2As schematically shown, light L incident from the first side surface 15C of the second transparent substrate 151B propagates in a direction away from the first side surface 15C (D2 direction) while being reflected by the second plane 15B of the second transparent substrate 151B and the first plane 15A of the first transparent substrate 151A. If light L moves outward from the first plane 15A of the first transparent substrate 151A and the second plane 15B of the second transparent substrate 151B, it enters a medium with a lower refractive index from a medium with a higher refractive index. At this time, if the angle of incidence of light L incident on the first plane 15A and the second plane 15B is greater than the critical angle, light L undergoes total internal reflection and is guided in the D2 direction while being reflected by the first plane 15A and the second plane 15B.

[0051] The liquid crystal layer 211 is formed of a polymer-dispersed liquid crystal. The liquid crystal layer 211, formed of a polymer-dispersed liquid crystal, is arranged in pixels (see...). Figure 1 This is used to control the scattering and non-scattering states. For example... Figure 2 As shown, if there are pixels in the liquid crystal layer 211 that are in a scattering state, at least a portion of the light L propagating while being reflected by the first plane 15A and the second plane 15B is scattered, and the incident angle of the scattered light becomes an angle less than the critical angle. The scattered light LA ​​and LB are emitted to the outside from the first plane 15A and the second plane 15B, respectively, and the emitted scattered light LA ​​and LB are observed by the observer. In the display panel 102, since the array substrate 150 and the opposing substrate 152, as well as the first transparent substrate 151A and the second transparent substrate 151B, are transparent (transparent relative to visible light), and the liquid crystal layer 211 is in a non-scattering state, the area outside from which the scattered light LA ​​and LB are emitted is substantially transparent, and the observer can visually identify the back side through the display panel 102.

[0052] Figure 3 This is a plan view illustrating the configuration of the array substrate 150 of a display device 10 according to one embodiment of the present invention. Figure 3 As shown, the array substrate 150 includes a display area 12 and a peripheral area 14.

[0053] Display area 12 has multiple pixels arranged in a matrix. Each pixel has multiple transistors and liquid crystal elements.

[0054] The peripheral region 14 is provided in a manner that surrounds the display region 12. It should be noted that the peripheral region 14 refers to the area in the array substrate 150 from the display region 12 to the end of the array substrate 150. In other words, the peripheral region 14 refers to the area on the array substrate 150 other than the display region 12 (i.e., the area outside the display region 12).

[0055] In the peripheral area 14, in addition to the gate drive circuit 28 and the source drive circuit 38, there are also a gate wiring area 32, a source wiring area 42, common wirings 16 and 18, terminal portions 26 and 36, flexible printed circuits 24 and 34, and various inspection circuits. The terminal portions 26 and 36 are arranged along one edge of the array substrate 150.

[0056] Terminal 26 is connected to flexible printed circuit 24. Flexible printed circuit 24 supplies various signals to gate drive circuit 28, common wirings 16, 18, ESD protection circuit 59 (including short-circuit ring SR), and QD pad 56. Gate drive circuit 28 is connected to multiple gate wirings GL, which are electrically connected to multiple pixels (PIX) in display area 12. Figure 3 In this diagram, the area with multiple gate wirings GL is designated as gate wiring region 32. Detailed configuration of the multiple gate wirings GL is omitted from the illustration. The number of gate wirings GL connected to the two gate drive circuits 28 is approximately equal to the number of rows of pixels (PIX) in the display area 12. It should be noted that... Figure 3 The image shows a configuration where the gate wiring region 32 is separated from the display region 12, but in reality, the gate wiring GL is electrically connected to the pixel PIX.

[0057] Terminal 36 is connected to flexible printed circuit 34. Flexible printed circuit 34 supplies image signals to source drive circuit 38. Source drive circuit 38 is connected to multiple source wirings SL, and the multiple source wirings SL are electrically connected to each of the multiple pixels (PIX) in display area 12. Figure 3 In this diagram, the area with multiple source routing lines (SL) is designated as source routing area 42. Detailed configuration diagrams for the multiple source routing lines (SL) are omitted. It should be noted that... Figure 3 The image shows a scenario where the source wiring region 42 is separated from the display region 12, but in reality, the source wiring SL is electrically connected to the pixel PIX.

[0058] A common wiring 18, an ESD protection circuit 46, a gate inspection circuit 48, and an inspection line 54 are provided between the gate wiring region 32 and the display region 12. A common wiring 18, an ESD protection circuit 46, a source inspection circuit 52, and an inspection line 54 are also provided between the source wiring region 42 and the display region 12. The inspection line 54 is connected to the ESD protection circuit 58 and the QD pad 56. Additionally, the common wiring 18 is connected to the ESD protection circuit 59. It should be noted that, in this specification, the gate inspection circuit 48, the source inspection circuit 52, the inspection line 54, and the ESD protection circuit 46 located in the peripheral region 14 are referred to as peripheral circuits.

[0059] The common wiring 16 is arranged to surround the peripheral region 14 in the array substrate 150 and is supplied with signals from the two flexible printed circuits 24. Furthermore, the common wiring 16 is electrically connected to a grid-like common wiring area 22. Connection portions 17 are provided on the common wiring 16 at the four corners of the array substrate 150. The common wiring 16 of the array substrate 150 is connected to a common electrode disposed on the entire surface of the opposing substrate 152 via the connection portions 17.

[0060] The display device 10 can be applied to high-speed driving panels and large, high-resolution panels such as transparent displays. Here, a transparent display refers to a display that, when visually recognizing the panel from the array substrate 150 side, can visually recognize the background on the opposing substrate 152 side in superimposed form with the displayed image, and when visually recognizing the panel from the opposing substrate 152 side, can visually recognize the background on the array substrate 150 side in superimposed form with the displayed image.

[0061] In a transparent display, peripheral circuitry is disposed between the display area and the gate wiring area on the array substrate side. Patent Document 2 shows a black matrix disposed on the opposing substrate side, formed only in the display area. By providing the black matrix in the display area, light reflection caused by wiring in the display area can be suppressed. On the other hand, in order to visually distinguish the background, the peripheral area (non-display area) is not covered by the black matrix. The peripheral circuitry not covered by the black matrix does not suppress light reflection from wiring. The material disposed on the outer surface of the peripheral circuitry on the array substrate is different from the material of the black matrix disposed on the opposing substrate. Therefore, when visually distinguished from the opposing substrate side, the hue changes according to the material difference. Furthermore, the wiring density of the peripheral circuitry is higher than that of the display area. Thus, in a transparent display, the area of ​​the peripheral circuitry becomes more prominent.

[0062] Therefore, in the display device 10 of one embodiment of the present invention, one objective is to achieve seamless boundary between the display area and the non-display area. Specifically, the wiring density in the display area 12 is set to the same level as the wiring density of the peripheral circuits (various inspection circuits and protection circuits), and the peripheral circuits are covered with a grid-like black matrix identical to that of the display area. Furthermore, the peripheral circuits are arranged to overlap with the grid-like black matrix BM. As a result, the transparency of the peripheral area 14 can be increased to be the same as that of the display area 12.

[0063] Next, refer to Figure 4 This section explains the structure of the black matrix BM when the panel is visually recognized from the side of the opposing substrate 152. Figure 4 This is a plan view illustrating the configuration of the opposing substrate 152 of a display device 10 according to one embodiment of the present invention. Figure 4 As shown, the black matrix BM in the opposing substrate 152 is configured in a lattice shape.

[0064] The black matrix BM has a first grid region 210 and a second grid region 220. A grid region is formed by the intersection of two sets of parallel straight lines extending in opposite directions. Furthermore, within a grid region, the intersection of two straight lines extending in opposite directions is called a grid point. Additionally, the area between two adjacent grid points within a grid region is called a straight section. The first grid region 210 overlaps with the display area 12, various inspection circuits, and common wiring 18 in the array substrate 150. The second grid region 220 overlaps with the gate wiring area 32 and the common wiring area 22.

[0065] exist Figure 4 The diagram shows an example where the first grid region 210 in the black matrix BM overlaps with the ESD protection circuit 46, the gate inspection circuit 48, the inspection line 54, and the common wiring 18, but does not overlap with the source inspection circuit 52 and the ESD protection circuit 46, but this configuration is not limited to this. The first grid region 210 may also overlap with the source inspection circuit 52 and the ESD protection circuit 46.

[0066] <Pixel cross-sectional structure>

[0067] Reference Figure 5 The configuration of a display device 10 according to one embodiment of the present invention will be described. Figure 5 This is a cross-sectional view of a pixel PIX in a display device 10 according to an embodiment of the present invention.

[0068] like Figure 5 As shown, a transistor Tr is provided on the array substrate 150. The transistor Tr has: a first conductive layer 202-1 disposed on the array substrate 150; an oxide semiconductor layer 204-1 disposed opposite to the first conductive layer 202-1; a gate insulating film 203 disposed between the first conductive layer 202-1 and the oxide semiconductor layer 204-1; and a second conductive layer 206-3 and a second conductive layer 206-4 disposed on the oxide semiconductor layer 204-1. Here, the first conductive layer 202-1 functions as a gate wiring GL (gate electrode), and the second conductive layer 206-4 functions as a source wiring SL (source electrode).

[0069] An insulating film 205 is provided on the transistor Tr. Furthermore, a third conductive layer 208-1 is provided on the insulating film 205, opposite to the oxide semiconductor layer 204-1. The third conductive layer 208-1 functions as a back gate. In this embodiment, the transistor Tr is described as a bottom-gate driven transistor, but it is not limited to this; it could also be a top-gate driven transistor or a dual-gate driven transistor.

[0070] A planarization film 207 is provided above the third conductive layer 208-1 and the insulating layer 205. The planarization film 207 is provided to mitigate the unevenness of the various wirings constituting the transistor Tr. When the display device 10 is applied to a transparent display, it is preferable to remove the planarization film 207 in the opening region of the pixel PIX. This can suppress the absorption of light by the planarization film 207 in the opening region.

[0071] A transparent conductive layer 212 is provided on the planarization film 207 and the insulating film 205. A fourth conductive layer 214 is provided on the transparent conductive layer 212. The transparent conductive layer 212 and the fourth conductive layer 214 function as capacitor wiring. An insulating film 209 is provided on the transparent conductive layer 212 and the fourth conductive layer 214. A pixel electrode 216-1 is provided on the insulating film 209. The pixel electrode 216-1 is connected to the second conductive layer 206-3 through an opening provided in the insulating films 205 and 209.

[0072] The opposing substrate 152 is disposed opposite to the array substrate 150. A light-shielding layer 219 and a common electrode 218 are provided in the opposing substrate 152. The light-shielding layer 219 functions as a black matrix (BM). Figure 5 In the illustrated configuration, a light-shielding layer 219 is disposed in the region overlapping with the conductive layer 206-4. The light-shielding layer 219 is arranged in a grid pattern to cover the gate wiring GL and source wirings SL1 to SL4. The common electrode 218 has a size extending to the entire surface of the display area 112. The light-shielding layer 219 may also be formed of a metal film. The light-shielding layer 219 functions as an auxiliary electrode because it is disposed in contact with the common electrode 218, which is formed of a transparent conductive film. A liquid crystal layer 211 is disposed between the array substrate 150 and the opposing substrate 152, and is sealed by a sealing member 154 (see [link to documentation]). Figure 1 The liquid crystal element LE is composed of pixel electrode 216-1, liquid crystal layer 211, and common electrode 218.

[0073] <Composition of the surrounding area>

[0074] Next, refer to Figures 6-9 This describes the structure of enlarging the first grid region 210 and the second grid region 220 in the surrounding area 14.

[0075] Figure 6 The black matrix BM (and) set on the opposing substrate 152 Figure 5 The image shows an enlarged view of the first grid region 210 and the second grid region 220 (corresponding to the light-shielding layer 219 shown). It should be noted that... Figure 6 This is a plan view of the opposing substrate 152 viewed from the side opposite to the side where the black matrix BM is formed. (Example) Figure 6As shown, the first grid region 210 in the black matrix BM overlaps with the pixel PIX in the display area 12, the gate inspection circuit 48 in the peripheral area 14, the short-circuit ring SG (ESD protection circuit 46), and the common wiring 18. The second grid region 220 overlaps with the gate wiring area 32.

[0076] In the first grid region 210, the distance between two adjacent grid points P1 and P2 in the D1 direction is equivalent to the distance between two adjacent wirings extending along the D2 direction on the array substrate 150. Similarly, in the first grid region 210, the distance between two adjacent grid points P1 and P3 in the D2 direction is equivalent to the distance between two adjacent wirings extending along the D1 direction on the array substrate 150. In the second grid region 220, the distance between two adjacent grid points P4 and P5 in the D1 direction is equivalent to the distance between two gate wirings GL in the D2 direction on the array substrate 150. Furthermore, in the second grid region 220, the distance between two adjacent grid points P4 and P6 in the D2 direction is equivalent to the distance between two gate wirings GL in the D1 direction on the array substrate 150.

[0077] In the first grid region 210, the distance between two adjacent grid points P1 and P2 in the D1 direction can be greater than the distance between two adjacent grid points P4 and P5 in the second grid region 220. In other words, the length of the straight section extending along the first direction of a grid in the first grid region 210 can be longer than the length of the straight section extending along the first direction of a grid in the second grid region.

[0078] Detailed information is not shown, but multiple gate wirings GL and multiple source wirings SL are provided in display area 12. The gate wirings GL extend along direction D1, and the source wirings SL extend along direction D2. The gate wirings GL and source wirings SL are arranged in a grid pattern in display area 12. The gate wirings GL and source wirings SL are arranged to overlap with the first grid region 210 of the black matrix BM.

[0079] The distance between two adjacent source wirings SL is approximately equal to the length of a straight section extending along the D1 direction in the lattice region 210 of the black matrix BM. Similarly, the distance between two adjacent gate wirings GL is approximately equal to the length of a straight section extending along the D2 direction in the lattice region 210 of the black matrix BM.

[0080] The distance between two adjacent source wirings SL can be the same as or different from the distance between two adjacent signal lines S. It is preferable that the distance between the two adjacent source wirings SL is approximately the same as the distance between the two adjacent signal lines S, so that the wiring density in the display area 12 is approximately the same as the wiring density in the peripheral area 14. In other words, it is preferable that the difference between the density of the black matrix BM in the display area 12 and the density of the black matrix BM in the peripheral area 14 is 10% or less. For example, it is preferable that the difference between the density of the black matrix BM in the display area 12 and the density of the black matrix BM in the first grid area 210 is 10% or less. Regarding the width of the straight portion of the black matrix BM, there are cases where it differs between the display area 12 and the peripheral area 14. For example, the width of the straight portion extending along the D1 direction in the display area 12 is 10 μm or less, and the width of the straight portion extending along the D2 direction is 25 μm or less, preferably 10 μm or less. Furthermore, the width of the straight portion extending along the D1 direction in the peripheral region 14 is 10 μm or less, and the width of the straight portion extending along the D2 direction is 25 μm or less, preferably 10 μm or less. Regarding the density of the black matrix BM, it can also be determined based on the area occupied by the black matrix BM within a 1 mm × 1 mm range in the display region 12 or the peripheral region 14.

[0081] Furthermore, the second grid region 220 overlaps with the gate wiring region 32 and the mesh common wiring region 22 formed in the array substrate 150. The wiring density of the gate wiring region 32 and the mesh common wiring region 22 can also be higher than the wiring density of the gate inspection circuit and the ESD protection circuit. Therefore, the density of the black matrix BM in the second grid region 220 can also be higher than the density of the black matrix BM in the first grid region 210. For example, the difference between the density of the black matrix BM in the first grid region 210 and the density of the black matrix BM in the second grid region 220 is not limited to within 10%, but can also exceed 10%.

[0082] Figure 7 This is an enlarged view of the pixel PIX, gate inspection circuit 48, short-circuit ring SG, common wiring 18, and gate wiring GL (gate wiring region 32) disposed on the array substrate 150. It should be noted that... Figure 7 This is a plan view of the array substrate 150 as seen from the surface where the pixel PIX, gate inspection circuit 48, short-circuit ring SG, common wiring 18, and gate wiring GL are formed. To make the explanation clearer, in... Figure 7 The middle diagram shows that the wiring extending along the D1 direction is located on a different layer than the wiring extending along the D2 direction. Detailed configurations of the pixel PIX, gate inspection circuit 48, short-circuit ring SG, and common wiring 18 are shown in [the diagram]. Figures 10-17 The text is described in the middle.

[0083] like Figure 7 As shown, in the peripheral region 14, multiple gate wirings GL extend along the D1 direction at intervals, and multiple signal lines S extend along the D2 direction at intervals. In the display region 12, multiple source wirings SL extend along the D2 direction at intervals, but detailed illustrations are omitted. For example, the gate inspection circuit 48 has a transistor at the intersection of the gate wiring GL and the signal line S. In addition, a short-circuit ring SG is provided along the D2 direction as a signal line S. The first grid region 210 in the black matrix BM overlaps with the pixel PIX in the display region 12, the gate inspection circuit 48 in the peripheral region 14, the short-circuit ring SG, and the common wiring 18. The second grid region 220 overlaps with the gate wiring region 32. Therefore, the straight portion extending along the D1 direction in the black matrix BM overlaps with the gate wiring GL extending along the D1 direction in the array substrate 150, and the straight portion extending along the D2 direction in the black matrix BM overlaps with the signal line S extending along the D2 direction in the array substrate 150.

[0084] Detailed information is not illustrated, but in the black matrix BM, the linewidth (length in the D1 direction) of the grid of straight sections extending along the D2 direction is longer than the length in the D1 direction of the wiring extending along the D2 direction in the array substrate 150. Similarly, in the black matrix BM, the linewidth (length in the D2 direction) of the grid of straight sections extending along the D1 direction is greater than the length in the D2 direction of the wiring extending along the D1 direction in the array substrate 150. In other words, the wiring disposed on the array substrate 150 is covered by the black matrix BM.

[0085] Figure 8 This is an enlarged view of the planarization film 207 disposed on the pixel PIX, gate inspection circuit 48, short-circuit ring SG, common wiring 18 and gate wiring GL (gate wiring area 32). Figure 8 This is a planar view of the array substrate 150 viewed from the surface on which the planarization film 207 is formed on the pixel PIX, gate inspection circuit 48, short-circuit ring SG, common wiring 18, and gate wiring GL. Figure 8 As shown, the planarization film 207 is configured in the same grid pattern as the black matrix BM. That is, the planarization film 207 is not provided in the area other than the various wirings that constitute the pixel PIX, the gate inspection circuit 48, the short-circuit ring SG, the common wiring 18, and the gate wiring GL.

[0086] Regarding the planarization film 207, it is arranged in a grid pattern in the display area 12, overlapping with the areas where gate wiring GL and source wiring SL are provided. Furthermore, the grid areas of the planarization film 207 overlap with the grid areas of the black matrix BM. In this way, by removing the areas of the planarization film 207 in the display area 12 where no wiring is provided, it is possible to suppress the absorption of light emitted from the light source 104 by the planarization film 207. Similarly, in the peripheral area 14, as in the display area 12, the areas of the planarization film 207 where no wiring is provided are also removed, thereby suppressing tone variations in both the display area 12 and the peripheral area 14.

[0087] Figure 9 This is an enlarged view of the transparent conductive layer 212 and the fourth conductive layer 214 disposed on the pixel PIX, the gate inspection circuit 48, the short-circuit ring SG, the common wiring 18 and the gate wiring GL (gate wiring region 32). Figure 9 This is a plan view of the array substrate 150 viewed from the surface on which the transparent conductive layer 212 and the fourth conductive layer 214 are formed on the pixel PIX, gate inspection circuit 48, short-circuit ring SG, common wiring 18, and gate wiring GL. Figure 9 As shown, the transparent conductive layer 212 is disposed on the entire surface of the array substrate 150. Furthermore, the fourth conductive layer 214 is configured in the same lattice pattern as the black matrix BM. That is, the fourth conductive layer 214 is not disposed in areas other than the various wirings constituting the pixel PIX, gate inspection circuit 48, short-circuit ring SG, common wiring 18, and gate wiring GL.

[0088] like Figure 9 As shown, the first grid region 210 in the black matrix BM overlaps with the pixel PIX in the display area 12, the gate inspection circuit 48 in the peripheral area 14, the short-circuit ring SG, and the fourth conductive layer 214 in the common wiring 18. That is, the grid region of the fourth conductive layer 214 overlaps with the grid region of the black matrix BM. The second grid region 220 overlaps with the fourth conductive layer 214 in the gate wiring area 32.

[0089] Detailed information is not illustrated, but the length of the region extending along the D2 direction in the black matrix BM in the D1 direction is greater than the length of the fourth conductive layer 214 extending along the D2 direction in the array substrate 150 in the D1 direction. Similarly, the length of the region extending along the D1 direction in the black matrix BM in the D2 direction is greater than the length of the fourth conductive layer 214 extending along the D1 direction in the array substrate 150 in the D2 direction. In other words, the fourth conductive layer 214 disposed on the array substrate 150 is covered by the black matrix BM.

[0090] Next, refer to Figures 10-17The configuration of the gate inspection circuit 48 and the short-circuit ring SG located in the peripheral area 14 is described in detail.

[0091] <Construction of the gate inspection circuit>

[0092] Figure 10 This is a circuit diagram of the gate inspection circuit 48 located in the peripheral area. The gates of transistors Tr11 and Tr12 are connected to wiring TEN. Wiring TEN controls the on / off state of transistors Tr11 and Tr12. Additionally, the source of transistor Tr11 is connected to wiring TG1. Wiring TG1 supplies signals to transistors arranged in odd-numbered rows. Therefore, if a signal is supplied from signal TG1 when transistor Tr11 is on, current can flow to the gate wiring GL(2n-1) (n≥1). Furthermore, the source of transistor Tr12 is connected to wiring TG2. Wiring TG2 supplies signals to transistors arranged in even-numbered rows. Therefore, if a signal is supplied from signal TG2 when transistor Tr12 is on, current can flow to the gate wiring GL(2n) (n≥1). Therefore, in the gate inspection circuit 48, transistors Tr11 arranged in odd-numbered rows can be inspected at the same time, and transistors Tr12 arranged in even-numbered rows can be inspected at the same time.

[0093] Figure 11 It is a planar layout of the gate inspection circuit 48. Figure 11 In the transistor Tr11, gate wirings GL(2n-1) and GL(2n) are arranged in the D1 direction, and wirings TG1 and TEN are arranged in the D2 direction. In addition, the gate 202-11 of transistor Tr11 is connected to wiring TEN, the source 206-11 is connected to wiring TG1, and the drain 206-12 is connected to gate wiring GL(2n-1).

[0094] Figure 11 It is a planar layout of the first conductive layer 202, the oxide semiconductor layer 204, and the second conductive layer 206. Figure 11The openings provided on the gate insulating film 203 are omitted from the diagram. In the region where the first conductive layer 202 and the second conductive layer 206 overlap, the first conductive layer 202 and the second conductive layer 206 are connected via the openings provided on the gate insulating film 203. For example, in wiring TG1, the first conductive layer 202-14 and the second conductive layer 206-11 are connected via the openings provided on the gate insulating film 203. Furthermore, in gate wiring GL(2n-1), the first conductive layer 202-12 and the second conductive layer 206-12 are connected via the openings provided on the gate insulating film 203. By configuring it in this way, the wiring resistance in the peripheral region 14 can be uniformized. The straight lines extending along the D1 direction in the lattice region of the black matrix BM overlap with the gate wirings GL(2n-1) and GL(2n). Additionally, the straight lines extending along the D2 direction in the lattice region of the black matrix BM overlap with wiring TG1 and wiring TEN. The linewidth of the straight section extending along the D1 direction in the grid region of the black matrix BM is greater than the linewidth of the gate wirings GL(2n-1) and GL(2n). Furthermore, the linewidth of the straight section extending along the D2 direction in the grid region of the black matrix BM is greater than the linewidth of wiring TG1 or wiring TEN.

[0095] like Figure 12 As shown, the gate wiring GL (2n-1) is constructed by stacking conductive layers 202-12, 206-12, and 206-13. Furthermore, in the region where the gate wiring GL (2n-1) intersects with wiring TG1, only conductive layer 202-12 is provided, while conductive layers 206-12 and 206-13 are separately disposed. Similarly, wiring TG1 is constructed by stacking conductive layers 202-13, 202-14, and conductive layer 206-11. In the region where wiring TG1 intersects with the gate wiring GL (2n-1), only conductive layer 206-11 is provided, while conductive layers 202-13 and 202-14 are separately disposed. Therefore, even if static electricity is generated during the manufacturing process of the display area 12 and surrounding area 14 in the array substrate 150, the static electricity can be released, thus suppressing problems caused by static electricity.

[0096] like Figure 11 As shown, transistor Tr11 is covered by a straight section extending along the D2 direction in the grid region of the black matrix. Similarly, although not shown, transistor Tr12 is also covered by a straight section extending along the D2 direction in the grid region of the black matrix. In this embodiment, the case where the straight section covering transistor Tr11 is parallel to the straight section covering transistor Tr12 is described, but it is not a limitation. The straight sections covering transistor Tr11 and Tr12 may also intersect (or be orthogonal).

[0097] Figure 12 and Figure 13 It is Figure 11 An enlarged view of region 120 containing transistor Tr11 in the gate inspection circuit 48 shown. Figure 12 It is a planar arrangement of a first conductive layer 202, an oxide semiconductor layer 204, a second conductive layer 206, and a third conductive layer 208. A gate insulating film 203 is provided between the first conductive layer 202 and the oxide semiconductor layer 204 (see [link]). Figure 5 An insulating film 205 is provided between the second conductive layer 206 and the third conductive layer 208 (see [reference]). Figure 5 ).in addition, Figure 13 It is a planar layout of the planarization film 207 and the fourth conductive layer 214. The transparent conductive layer 212 is disposed on the entire surface of the array substrate 150, therefore... Figure 13 Illustrations omitted.

[0098] like Figure 12 As shown, the first conductive layer 202-11 has a region extending along the D1 direction and a region bent towards the D2 direction. The region bent towards the D1 direction in the first conductive layer 202-11 functions as a wiring TEN, and the region bent towards the D2 direction functions as the gate electrode of transistor Tr11. An oxide semiconductor layer 204-11 is provided above the region bent towards the D2 direction in the first conductive layer 202-11. Second conductive layers 206-11 and 206-12 are provided above the oxide semiconductor layer 204-11. The second conductive layers 206-11 and 206-12 are connected to the oxide semiconductor layer 204-11.

[0099] The second conductive layers 206-12 and 206-13 extend along the D1 direction. The second conductive layer 206-12 is connected to the first conductive layer 202-12 via an opening 213-11 provided in the gate insulating film 203, and the second conductive layer 206-13 is connected to the first conductive layer 202-12 via an opening 213-12 provided in the gate insulating film 203. The first conductive layer 202-12, the second conductive layer 206-12, and 206-13 function as gate wiring GL(2n-1).

[0100] The first conductive layers 202-13 and 202-14 and the second conductive layer 206-11 extend along the D2 direction. The first conductive layer 202-13 is connected to the second conductive layer 206-11 via an opening 213-13 provided in the gate insulating film 203, and the first conductive layer 202-14 is connected to the second conductive layer 206-11 via an opening 213-14 provided in the gate insulating film 203. The first conductive layers 202-13, 202-14 and the second conductive layer 206-11 function as wiring TG1.

[0101] A second conductive layer 206-14 is provided above the first conductive layer 202-11. Furthermore, a third conductive layer 208-11 is provided above the oxide semiconductor layer 204-11 and the second conductive layers 206-11, 206-12, and 206-14. The third conductive layer 208-11 functions as the back gate of transistor Tr11. The third conductive layer 208-11 is connected to the second conductive layer 206-14 via an opening 217-11, and the second conductive layer 206-14 is connected to the first conductive layer 202-11 via an opening 213-15 provided on the gate insulating film 203. Thus, the third conductive layer 208-11 is electrically connected to the first conductive layer 202-11. Therefore, the signal supplied to the wiring TEN is supplied to the gate and back gate of transistor Tr11.

[0102] Reference Figure 8 and Figure 13 The planarization film 207 is configured in a lattice pattern. The planarization film 207 is arranged to cover gate wirings GL(2n-1), GL(2n), wirings TG1, TG2, and wiring TEN. That is, the planarization film 207 is not present in areas other than the gate wirings GL(2n-1), GL(2n), wirings TG1, TG2, and wiring TEN. The planarization film 207 also covers transistor Tr11. (Refer to...) Figure 8 and Figure 13 A transparent conductive layer 212 is disposed on the entire surface of the planarization film 207. Additionally, refer to... Figure 8 and Figure 13 The fourth conductive layer 214-11 is configured in a lattice shape. The fourth conductive layer 214-11 is configured to cover the gate wiring GL(2n-1), GL(2n), wiring TG1, TG2 and wiring TEN.

[0103] <Construction of a short-circuit loop>

[0104] Figure 14 This is the circuit diagram of the short-circuit ring SG. Figure 14 The short-circuit ring SG shown is set in Figure 3 In the ESD protection circuit 46 shown, the short-circuit ring SG is configured to handle ESD (Electro-Static Discharge). Short-circuit rings SR1 to SR3 are shown as the short-circuit ring SG.

[0105] like Figure 14As shown, one end of the short-circuit ring SR3 is connected to the common wiring 18, and the other end of the short-circuit ring SR1 is connected to the gate wiring GL(2n). The sources and drains of transistors Tr21 and Tr22 are interconnected, and one of the sources and drains of transistors Tr21 and Tr22 is connected to the gate of transistor Tr21. The other of the sources and drains of transistors Tr21 and Tr22 is connected to the gate of transistor Tr22. The gate of transistor Tr21 is connected to the gate wiring GL(2n), and the gate of transistor Tr22 is connected to the gate of transistor Tr23. This forms the short-circuit ring SR1.

[0106] The sources and drains of transistors Tr23 and Tr24 are interconnected. One of the sources and drains of transistors Tr23 and Tr24 is connected to the gate of transistor Tr23. The other of the sources and drains of transistors Tr23 and Tr24 is connected to the gate of transistor Tr24. The gate of transistor Tr24 is connected to the gate of transistor Tr25. This forms a short-circuit ring SR2.

[0107] The sources and drains of transistors Tr25 and Tr26 are interconnected. One of the sources and drains of transistors Tr25 and Tr26 is connected to the gate of transistor Tr25. The other of the sources and drains of transistors Tr25 and Tr26 is connected to the gate of transistor Tr26. The gate of transistor Tr26 is connected to common wiring 18. This forms a short-circuit ring SR3. Figure 14 In the middle, three short-circuit rings SR1 to SR3 are connected in series.

[0108] Therefore, when a large current suddenly flows into the gate wiring GL(2n) due to static electricity, the charge can be escaped through the common wiring 18 by using the three short-circuit rings SR1 to SR3.

[0109] Figure 15 It is a planar layout of short-circuit rings SR1 to SR3. Short-circuit rings SR1 to SR3 are connected in series, and short-circuit ring SR3 is connected in series with resistors R1 and R2. Short-circuit ring SR1 is connected to the gate wiring GL (2n). Resistor R2 is connected to the common wiring 18.

[0110] Figure 15It is a planar layout of the first conductive layer 202, the oxide semiconductor layer 204, and the second conductive layer 206. The straight sections extending along the D1 direction in the grid region of the black matrix BM overlap with the gate wirings GL(2n-1) and GL(2n). Additionally, the straight sections extending along the D2 direction in the grid region of the black matrix BM overlap with the short-circuit rings SR1 to SR3 or the common wiring 18. The linewidth of the straight sections extending along the D1 direction in the grid region of the black matrix BM is greater than the linewidth of the gate wirings GL(2n-1) and GL(2n). Furthermore, the linewidth of the straight sections extending along the D2 direction in the grid region of the black matrix BM is greater than the linewidth of the short-circuit ring SG or the linewidth of the common wiring 18.

[0111] according to Figure 15 The planar layout shown is consistent with... Figure 12 Similarly, a wiring region is formed by the stacked structure of the first conductive layer 202 and the second conductive layer 206. The first conductive layer 202 and the second conductive layer 206 are interconnected in the stacked structure. For example, there may also be a region where the second conductive layer 206 is separated in the gate wiring GL(2n-1). Therefore, even if static electricity is generated during the manufacturing process of the display area 12 and the peripheral area 14 in the array substrate 150, the static electricity can be released, thus suppressing problems caused by static electricity.

[0112] Figure 16 and Figure 17 It is Figure 14 The diagram shows an enlarged view of region 130 in the short-circuit ring SG, which contains transistors Tr21 to Tr24. Figure 16 The diagram shows a first conductive layer, an oxide semiconductor layer, a second conductive layer, and a third conductive layer. Additionally, Figure 17 The planarization film 207 and the fourth conductive layer 214 are shown. Additionally, a transparent conductive layer 212 is disposed across the entire surface of the array substrate 150, therefore... Figure 15 Illustrations omitted.

[0113] A first conductive layer 202-21 and 202-22 are provided on the array substrate 150. For example... Figure 16 As shown, the first conductive layer 202-21 has a region extending along the D1 direction and a region bent towards the D2 direction. The region of the first conductive layer 202-21 extending along the D1 direction functions as a gate wiring GL(2n). Additionally, the region of the first conductive layer 202-21 bent towards the D2 direction functions as the gate electrode of transistor Tr21. The first conductive layer 202-22 extends along the D2 direction and is separated from the region of the first conductive layer 202-21 bent towards the D2 direction.

[0114] An oxide semiconductor layer 204-21 is provided on the region of the first conductive layer 202-21 that bends in the D2 direction. Additionally, oxide semiconductor layers 204-22 and 204-23 are provided on the first conductive layer 202-22. Second conductive layers 206-21 and 206-22 are provided on the oxide semiconductor layers 204-21 and 204-22.

[0115] The second conductive layer 206-21 has a region extending along the D1 direction and a region bending towards the D2 direction. The region of the second conductive layer 206-21 extending along the D1 direction is connected to the oxide semiconductor layer 204-21, and the region bending towards the D2 direction is connected to the oxide semiconductor layer 204-22. The second conductive layer 206-22 is connected to the oxide semiconductor layers 204-21 and 204-22. Furthermore, the second conductive layer 206-21 is connected to the first conductive layer 202-21 via an opening 213-21 provided in the gate insulating film 203. The second conductive layer 206-22 is connected to the first conductive layer 202-22 via an opening 213-22 provided in the gate insulating film 203.

[0116] A third conductive layer 208-21 is provided above the oxide semiconductor layer 204-21 and the second conductive layers 206-21 and 206-22. The third conductive layer 208-21 is connected to the second conductive layer 206-21 through an opening 215-21 provided in the insulating film 205. A third conductive layer 208-22 is provided above the oxide semiconductor layer 204-22 and the second conductive layers 206-21 and 206-22. The third conductive layer 208-22 is connected to the second conductive layer 206-22 through an opening 215-22 provided in the insulating film 205.

[0117] The gates of transistor Tr21 and Tr22 can be connected using the first conductive layer 202-22. The configurations of short-circuit rings SR2 and SR3 are the same as those of short-circuit ring SR1, so detailed descriptions are omitted.

[0118] Reference Figure 8 and Figure 17 The planarization film 207 is configured in a lattice shape. The planarization film 207 is arranged to cover the gate wirings GL(2n-1), GL(2n), and short-circuit rings SR1 to SR3. That is, the planarization film 207 is not provided in the areas outside the gate wirings GL(2n-1), GL(2n), and short-circuit rings SR1 to SR3. (Refer to...) Figure 8 and Figure 17 A transparent conductive layer 212 is provided on the entire surface of the planarization film 207. Additionally, refer to... Figure 8 and Figure 17The fourth conductive layer 214-11 is configured in a lattice shape. The fourth conductive layer 214-11 is disposed on the gate wiring GL(2n-1), GL(2n), and short-circuit rings SR1 to SR3.

[0119] By setting Figure 16 and Figure 17 The planar layout shown allows for the formation of a short-circuit ring SR1 where the sources and drains of transistors Tr21 and Tr22 are interconnected, and one of the sources and drains of transistors Tr21 and Tr22 is connected to the gate of transistor Tr21. Furthermore, short-circuit rings SR1 to SR3 can be arranged in series along the D2 direction. Therefore, the straight sections of the black matrix BM can be used to conceal the short-circuit rings SR1 to SR3.

[0120] As explained above, in a display device 10 according to one embodiment of the present invention, a black matrix BM is provided in the peripheral region 14 (non-display region) to cover a plurality of wirings arranged along the D1 and D2 directions and transistors formed close together. Therefore, light reflection caused by the plurality of wirings arranged in the peripheral region 14 can be suppressed. Furthermore, in the display region 12 and the peripheral region 14, when visually recognized from the opposing substrate side, color variations due to material differences can be suppressed. Therefore, in the display device 10, seamlessness can be achieved at the boundary between the display region 12 and the peripheral region 14.

[0121] Furthermore, by making the wiring density in the display area 12 approximately the same as that in the peripheral area 14, the transparency of the peripheral area 14 can be improved in the same way as that in the display area 12. Moreover, by setting peripheral circuits such as the gate inspection circuit 48 and the short-circuit ring SG to overlap with the lattice-shaped black matrix BM, the transparency of the peripheral area 14 can be improved in the same way as that in the display area 12.

[0122] <Materials of the 10 components of the display device>

[0123] As the array substrate 150 and the opposing substrate 152, rigid substrates that are transparent but not flexible, such as glass substrates, quartz substrates, and sapphire substrates, can be used. On the other hand, when flexibility is required for the array substrate 150 and the opposing substrate 152, flexible substrates containing resin and having flexibility, such as polyimide substrates, acrylic substrates, siloxane boards, or fluororesin substrates, can be used as the array substrate 150 and the opposing substrate 152. To improve the heat resistance of the array substrate 150 and the opposing substrate 152, impurities can be introduced into the aforementioned resins. In addition, when the display device 10 is applied to a transparent display or a large high-resolution display, glass substrates are preferably used as the array substrate 150 and the opposing substrate 152. Furthermore, a first transparent substrate 151A and a second transparent substrate 151B are provided to protect the array substrate 150 and the opposing substrate 152. Therefore, for example, transparent glass substrates, plastic substrates, etc., are preferred.

[0124] Common metallic materials can be used as the first conductive layer 202, the second conductive layer 206, the third conductive layer 208, and the fourth conductive layer 214. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), and alloys or compounds of these metals can be used. These materials can be used either as a single layer or in a stack. For example, an Al / Ti stack can be used as the first conductive layer 202. For example, a TiN / Ti / Al / Ti / TiN stack can be used as the second conductive layer 206. For example, Mo can be used as the third conductive layer 208. For the fourth conductive layer, a Mo / Al stack can be used.

[0125] Conventional insulating materials can be used as gate insulating films 203, 205, and 209. For example, silicon oxide (SiO2) can be used as gate insulating films 203, 205, and 209. x ), silicon oxynitride (SiO) x N y Silicon nitride (SiN) x ), silicon oxynitride (SiN) x O y ), aluminum oxide (AlO) x ), aluminum oxynitride (AlO) x N y ), aluminum oxynitride (AlN) x O y Aluminum nitride (AlN) xInorganic insulating layers such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin, or siloxane resin can be used as the insulating layer. It should be noted that the above-mentioned organic insulating materials can also be used as the gate insulating film 203, insulating film 205, and insulating film 209. The above-mentioned materials can be used as single layers or in layers as the components. For example, a layered structure of silicon nitride and silicon oxide can be used as the gate insulating film 203. For example, a layered structure of silicon oxide and silicon nitride can be used as the insulating film 205. Furthermore, silicon nitride is used as the insulating film 209.

[0126] The above SiO x N y and AlO x N y These are silicon and aluminum compounds in which the nitrogen (N) ratio is less than the oxygen (O) ratio (x > y). Additionally, SiN... x O y and AlN x O y Silicon and aluminum compounds in which the oxygen ratio is less than the nitrogen ratio (x > y).

[0127] As the oxide semiconductor layer 204, a metal oxide with semiconductor properties can be used. The oxide semiconductor layer 204 is transparent. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) can be used. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O = 1:1:1:4 can be used. It should be noted that the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition, and an oxide semiconductor with a different composition can be used. For example, in order to improve mobility, the In ratio can be greater than the above ratio. In addition, in order to increase the band gap and reduce the influence of light irradiation, the Ga ratio can be greater than the above ratio.

[0128] It should be noted that in this embodiment, an example of using an oxide semiconductor layer as the semiconductor layer has been described, but amorphous silicon or polycrystalline silicon semiconductor layers may also be used.

[0129] The transparent conductive layer 212, pixel electrode 216, and common electrode 218 can be made of a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO). Other materials can also be used as the transparent conductive layer.

[0130] The black matrix BM (light-shielding layer 219) can be formed from black resin or metal material. The black matrix BM is grounded with the common electrode 218 (see...). Figure 7 For the common electrode 218 formed of a transparent conductive film, by forming a black matrix BM from a metallic material, it can function as an auxiliary electrode to reduce resistance loss. As the metallic material for forming the black matrix BM, chromium, molybdenum, titanium, etc., which have relatively low reflectivity compared to aluminum, are preferably used.

[0131] When the display device 10 is applied to a transparent display, a polymer-dispersed liquid crystal is preferably used as the liquid crystal layer 211. The polymer-dispersed liquid crystal comprises bulk particles and microparticles. Within the bulk particles, the orientation of the microparticles varies corresponding to the potential difference between the pixel electrode 216 and the common electrode 218. By individually controlling the potential of the pixel electrode 216 per pixel, the degree of at least light transmission and dispersion can be controlled per pixel. The scattering degree of the liquid crystal layer (microparticles) is controlled corresponding to the voltage of each pixel electrode 216 and the voltage of the common electrode 218. For example, a polymer-dispersed liquid crystal can be used where the scattering degree is greater when the voltage between each pixel electrode 216 and the common electrode 218 is higher, or vice versa.

[0132] In the liquid crystal layer 211, the refractive indices of the bulk particles and microparticles are equal. When no voltage is applied between the pixel electrode 216 and the common electrode 218, the refractive index difference between the bulk particles and microparticles becomes zero in all directions. The liquid crystal layer 211 becomes a non-scattering state that does not scatter light emitted from the light source. Light emitted from the light source propagates away from the light source 104 (light-emitting portion) while being reflected by the first main surface of the array substrate 150 and the first main surface of the opposing substrate 152. If the liquid crystal layer 211 is in a non-scattering state that does not scatter light L emitted from the light source, the background of the opposing substrate 152 is visually recognized from the array substrate 150, and the background of the array substrate 150 is visually recognized from the opposing substrate 152.

[0133] Between the pixel electrode 216 and the common electrode 218, where a voltage is applied, the optical axis of the microparticles is tilted due to the electric field generated between the pixel electrode 216 and the common electrode 218. The optical axis of the block does not change due to the electric field; therefore, the orientations of the optical axis of the block and the optical axis of the microparticles are different. In the pixel PIX where the voltage-applied pixel electrode 216 is located, light emitted from the light source is scattered. A portion of the light emitted from the light source, scattered in the manner described above, is emitted from the first main surface of the array substrate 150 or the first main surface of the opposing substrate 152 and is observed by an observer.

[0134] In the pixel PIX where the pixel electrode 216 is not subjected to voltage, the background on the first main surface side of the opposing substrate 152 is visually identified from the first main surface of the array substrate 150, and the background on the first main surface side of the array substrate 150 is visually identified from the first main surface of the opposing substrate 152. Furthermore, in the display device 10 of this embodiment, when an image signal is input, the pixel electrode 216 of the pixel PIX displaying the image is subjected to voltage, and the image and background are visually identified together based on the image signal. In this way, when the polymer-dispersed liquid crystal is in a scattering state, an image is displayed in the display area.

[0135] In this embodiment, the planar layout of the black matrix BM, gate inspection circuit, short-circuit ring, and common wiring has been described, but one embodiment of the present invention is not limited thereto. The planar layout of the source inspection circuit of the grid-shaped black matrix BM can also be configured to be the same as that of the gate inspection circuit. For example, the first grid region of the black matrix BM can be configured to overlap with the source wiring and signal lines constituting the source inspection circuit. Alternatively, a planarization film having a grid region that overlaps with the first grid region and also overlaps with the source wiring and signal lines constituting the source inspection circuit can be provided.

[0136] The preferred embodiments have been described above, but this disclosure is not limited to the above embodiments. The content disclosed in the embodiments is merely an example, and various modifications can be made without departing from the spirit of this disclosure. Appropriate modifications made without departing from the spirit of this disclosure are of course also within the technical scope of this disclosure.

Claims

1. A display device, having: The first substrate has a display area containing pixels and a peripheral area surrounding the display area and containing peripheral circuitry. A second substrate, which is disposed opposite to the first substrate; and A liquid crystal layer is disposed between the first substrate and the second substrate. The peripheral circuit of the first substrate includes a plurality of gate wirings arranged at intervals in a first direction and a plurality of signal lines arranged at intervals in a second direction intersecting the first direction. The second substrate has a black matrix with a grid area at a position opposite to the display area and the peripheral circuit. The grid regions of the black matrix are configured to overlap with the multiple gate wirings and multiple signal lines of the surrounding circuitry. The peripheral circuitry further includes a first transistor and a second transistor. The plurality of gate wirings includes a first gate wiring and a second gate wiring. The plurality of signal lines includes signal lines 1 to 3. The first signal line is electrically connected to the gate of the first transistor, the second signal line is electrically connected to the source of the first transistor, and the first gate wiring is electrically connected to the drain of the first transistor. The first signal line is electrically connected to the gate of the second transistor, the third signal line is electrically connected to the source of the second transistor, and the second gate wiring is electrically connected to the drain of the second transistor.

2. The display device according to claim 1, further comprising a planarization film having a grid region overlapping the plurality of gate wirings and the plurality of signal lines. The grid region of the planarization film overlaps with the grid region of the black matrix.

3. The display device according to claim 2, further comprising: A transparent conductive layer is disposed on the planarization film; and A conductive layer having a grid region overlapping the plurality of gate wirings and the plurality of signal lines on top of the transparent conductive layer. The grid region of the transparent conductive layer and the grid region of the conductive layer overlap with the grid region of the black matrix.

4. The display device according to claim 1, wherein, In the surrounding area, the line width of the grid in the black matrix is ​​greater than the line width of each of the multiple gate wirings and also greater than the line width of each of the multiple signal lines.

5. The display device according to claim 1, wherein, The first straight line portion of the grid in the grid region of the black matrix overlaps with the first transistor. The second straight section of the grid in the grid region of the black matrix overlaps with the second transistor.

6. The display device according to claim 5, wherein, The first transistor is covered by the first linear portion. The second transistor is covered by the second straight section.

7. The display device according to claim 5, wherein, The first straight section is parallel to the second straight section.

8. The display device according to claim 5, wherein, The first straight section intersects with the second straight section.

9. The display device according to claim 1, wherein, The peripheral circuitry further includes at least one short-circuit loop. The plurality of gate wirings includes a third gate wiring. The short-circuit ring has a third transistor and a fourth transistor. The plurality of signal lines includes a fourth signal line. The source and drain of the third transistor are electrically connected to the source and drain of the fourth transistor. One of the source and drain terminals and the gate of the third transistor are electrically connected to the third gate wiring. The other of the source and drain of the third transistor is electrically connected to the fourth signal line.

10. The display device according to claim 9, wherein, The at least one short-circuit ring is configured along the second direction. The at least one short-circuit loop is covered by the third straight section of the grid in the grid region of the black matrix.

11. The display device according to claim 1, wherein, The black matrix's grid region includes the first grid region and the second grid region. The length of the straight section of the grid in the first grid region is longer than the length of the straight section of the grid in the second grid region.

12. The display device according to claim 1, further comprising a light source configured such that light is incident on a side surface of the first substrate or on a side surface of the second substrate.

13. The display device according to claim 12, wherein, The liquid crystal layer is a polymer-dispersed liquid crystal. When the polymer-dispersed liquid crystal is in a scattering state, an image is displayed in the display area. When the polymer-dispersed liquid crystal is in a non-scattering state, in the display area, the background of the second substrate is visually identifiable from the first substrate, and the background of the first substrate is visually identifiable from the second substrate.

14. A display device, having: The first substrate has a display area containing pixels and a peripheral area surrounding the display area and containing peripheral circuitry. A second substrate, which is disposed opposite to the first substrate; and A liquid crystal layer is disposed between the first substrate and the second substrate. The peripheral circuit of the first substrate includes a plurality of gate wirings arranged at intervals in a first direction and a plurality of signal lines arranged at intervals in a second direction intersecting the first direction. The second substrate has a black matrix with a grid area at a position opposite to the display area and the peripheral circuit. The grid regions of the black matrix are configured to overlap with the multiple gate wirings and multiple signal lines of the surrounding circuitry. The peripheral circuitry further includes at least one short-circuit loop. The plurality of gate wirings includes a third gate wiring. The short-circuit ring has a third transistor and a fourth transistor. The plurality of signal lines includes a fourth signal line. The source and drain of the third transistor are electrically connected to the source and drain of the fourth transistor. One of the source and drain terminals and the gate of the third transistor are electrically connected to the third gate wiring. The other of the source and drain of the third transistor is electrically connected to the fourth signal line.

15. The display device according to claim 14, wherein, The at least one short-circuit ring is configured along the second direction. The at least one short-circuit loop is covered by the third straight section of the grid in the grid region of the black matrix.

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