Display substrate and display device

Abstract

The display substrate and the display device are provided. The display substrate comprises a display area and a frame area located at the periphery of the display area; the frame area comprises a sealant, and a plurality of normal shift register units and a plurality of virtual shift register units arranged in sequence; the display substrate further comprises a plurality of gate lines, at least part of the gate lines being located in the display area; in the extension direction of the gate lines, at least one virtual shift register unit is staggered with the normal shift register unit, and the at least one virtual shift register unit is staggered with the normal shift register unit in the direction away from the sealant.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] With the continuous development of display technology, ultra-narrow bezel displays have become a popular choice among users, and achieving ultra-narrow bezels has become a research hotspot for designers. Currently, the bezel area of ​​a display mainly houses virtual pixels, virtual gate drive circuits, fan-out lines, driver chips, signal traces, etc., resulting in a large layout space required in the bezel area. Summary of the Invention

[0003] The purpose of this disclosure is to provide a display substrate and a display device.

[0004] To achieve the above objectives, this disclosure provides the following technical solution:

[0005] A first aspect of this disclosure provides a display substrate, comprising: a display area and a border area surrounding the display area; the border area includes a sealing adhesive and a plurality of normal shift register units and a plurality of virtual shift register units arranged sequentially.

[0006] The display substrate further includes a plurality of gate lines, at least a portion of which are located in the display area;

[0007] In the extension direction of the gate line, at least one of the virtual shift register units is offset from the normal shift register unit, and the at least one virtual shift register unit is offset from the normal shift register unit in a direction away from the sealing adhesive.

[0008] Optionally, the plurality of virtual shift register units includes at least a first virtual shift register unit and a second virtual shift register unit; in the extension direction of the gate line, the distance between the first virtual shift register unit and the normal shift register unit is greater than the distance between the second virtual shift register unit and the normal shift register unit.

[0009] Optionally, along the direction away from the normal shift register unit, in the extension direction of the gate line, the distance between the plurality of virtual shift register units and the normal shift register unit gradually increases.

[0010] Optionally, the virtual shift register unit includes a virtual output transistor, the orthographic projection of which on the substrate does not overlap with the orthographic projection of the sealing adhesive on the substrate.

[0011] Optionally, the minimum distance between the orthographic projection of the virtual output transistor on the substrate and the orthographic projection of the sealing adhesive on the substrate is greater than or equal to 50 micrometers.

[0012] Optionally, the border area further includes cascaded signal lines connected between two virtual shift register units for transmitting signals between the two virtual shift register units. The orthographic projection of the cascaded signal lines on the substrate does not overlap with the orthographic projection of the sealing adhesive on the substrate.

[0013] Optionally, the minimum distance between the orthographic projections of at least two adjacent virtual shift register units on the substrate is greater than the minimum distance between the orthographic projections of two adjacent normal shift register units on the substrate.

[0014] Optionally, among the plurality of virtual shift register units, the distance between two adjacent virtual shift register units that are farther away from the normal shift register unit is larger.

[0015] Optionally, the display area includes multiple normal scan lines, which are coupled to corresponding normal shift register units;

[0016] The border area also includes multiple virtual scan lines, which are coupled to corresponding virtual shift register units;

[0017] The display substrate also includes multiple data lines; the overlap area between the orthographic projection of the virtual scan line on the substrate and the orthographic projection of the data line on the substrate is greater than the overlap area between the orthographic projection of the normal scan line on the substrate and the orthographic projection of the data line on the substrate.

[0018] Optionally, the linewidth of the virtual scan line is between 8 micrometers and 15 micrometers, and the linewidth of the overlapping portion between the orthographic projection of the data line on the substrate and the orthographic projection of the virtual scan line on the substrate is between 6 micrometers and 15 micrometers.

[0019] Optionally, the virtual shift register unit includes a virtual output transistor, and the normal shift register unit includes a normal output transistor; the size of the virtual output transistor is smaller than the size of the normal output transistor.

[0020] Optionally, the size of the virtual output transistor is 1 / 2 or 1 / 3 of the size of the normal output transistor.

[0021] Optionally, the virtual output transistor includes a plurality of sub-transistors connected in series.

[0022] Optionally, the border area further includes multiple fan-out lines, each fan-out line comprising a first part and a second part. The orthographic projection of the first part on the substrate overlaps with the orthographic projection of the sealing adhesive on the substrate, while the orthographic projection of the second part on the substrate does not overlap with the orthographic projection of the sealing adhesive on the substrate.

[0023] The minimum distance between the orthographic projections of adjacent first portions on the substrate is greater than the minimum distance between the orthographic projections of adjacent second portions on the substrate.

[0024] Optionally, the linewidth of the first portion is between 2.2 micrometers and 4 micrometers, and the minimum distance between the orthographic projections of adjacent first portions on the substrate is between 1 micrometer and 1.2 micrometers.

[0025] Based on the above-described display substrate technical solution, a second aspect of this disclosure provides a display device including the above-described display substrate. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0027] Figure 1 This is a schematic diagram of the display substrate structure provided in an embodiment of the present disclosure;

[0028] Figure 2 Circuit diagrams of a normal shift register unit and a virtual shift register unit provided in embodiments of this disclosure;

[0029] Figure 3 This is a schematic diagram of the layout of virtual scan lines and virtual transistors in related technologies;

[0030] Figure 4 This is a schematic diagram of the layout of virtual scan lines and data lines provided in an embodiment of the present disclosure;

[0031] Figure 5 This is a first layout schematic diagram of a normal output transistor and a virtual output transistor provided in an embodiment of the present disclosure;

[0032] Figure 6 This is a second layout schematic diagram of the normal output transistor and the virtual output transistor provided in an embodiment of the present disclosure;

[0033] Figure 7 This is a schematic diagram of the fan-outline layout provided in an embodiment of the present disclosure;

[0034] Figure 8 This is an enlarged schematic diagram of the first portion of the fan-out line provided in an embodiment of this disclosure. Detailed Implementation

[0035] To further illustrate the display substrate and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0036] This disclosure provides a display substrate in which a virtual shift register unit is disposed in the border area of ​​the display substrate. The virtual shift register unit is used to provide reset signals for some pixels in the display area, particularly for resetting the last few stages of normal shift registers. The border area of ​​the display substrate is also provided with a sealing adhesive for bonding the display substrate top and bottom, for example, bonding an array substrate and a color filter substrate for a liquid crystal display. The orthographic projection of the sealing adhesive onto the substrate and the orthographic projection of the virtual shift register unit onto the substrate form a large overlap area.

[0037] Since the curing of the sealant has certain requirements on the transmittance of the area it is in, the sealant's orthographic projection on the substrate of the display substrate and the virtual shift register unit's orthographic projection on the substrate of the display substrate form a large overlap area, which will result in low transmittance in the area where the sealant is located. This will lead to incomplete curing of the sealant and affect its sealing effect.

[0038] Please see Figure 1 and Figure 7 This disclosure provides a display substrate, including: a display area 10 and a border area surrounding the display area 10; the border area includes a sealing adhesive 201, and a plurality of normal shift register units 202 and a plurality of virtual shift register units 203 arranged in sequence;

[0039] The display substrate further includes a plurality of gate lines, at least a portion of which are located in the display area 10;

[0040] In the extension direction of the gate line, at least one of the virtual shift register units 203 is offset from the normal shift register unit 202, and the at least one virtual shift register unit 203 is offset from the normal shift register unit 202 in a direction away from the sealing adhesive 201.

[0041] For example, the display substrate includes a display area 10 and a border area. The border area surrounds the display area 10 and includes a lower border area. The lower border area may be provided with virtual pixels, a virtual shift register unit 203, a fan-out line 207, a driver chip, traces between the driver chip and the flexible circuit board, and a pre-cut area, etc.

[0042] For example, the frame area is provided with a sealing adhesive 201, which surrounds the display area 10. The sealing adhesive 201 includes a portion located on the lower frame, used to seal the display substrate. The sealing adhesive 201 has certain requirements for the transmittance of its area to ensure the sealing effect of the sealing adhesive 201 during the curing process.

[0043] For example, the border region further includes a plurality of normal shift register units 202 and a plurality of virtual shift register units 203 arranged sequentially. The border region may also include a left border and a right border, and at least some of the plurality of normal shift register units 202 and the plurality of virtual shift register units 203 may be arranged in the left border and / or the right border. For example, the plurality of normal shift register units 202 and the plurality of virtual shift register units 203 may be arranged along the extension direction of the long boundaries of the left border and the right border.

[0044] For example, the display substrate further includes multiple gate lines that extend from the display area 10 to the border area. The extension direction of the gate lines intersects the extension direction of the long boundary. For example, the extension direction of the gate lines is horizontal, and the extension direction of the long boundary is vertical.

[0045] For example, in the direction of extension of the gate line, at least one of the virtual shift register units 203 is offset from the normal shift register unit 202, including, but not limited to, in the direction of extension of the gate line, at least one of the virtual shift register units 203 is offset from the last normal shift register unit 202 closest to the virtual shift register unit 203.

[0046] For example, in the extension direction of the gate line, the orthographic projection of at least one of the virtual shift register units 203 on the substrate of the display substrate is offset from the orthographic projection of the normal shift register unit 202 on the substrate of the display substrate.

[0047] It should be noted that, in the aforementioned direction of extension of the gate line, at least one of the virtual shift register units 203 is offset from the normal shift register unit 202. Specifically, one of the transistors in the virtual shift register unit 203 and the normal shift register unit 202 can be selected for measurement. For example, the output transistors in the virtual shift register unit 203 and the normal shift register unit 202 can be used for measurement.

[0048] As can be seen from the specific structure of the display substrate described above, in the display substrate provided in this embodiment, by setting at least one virtual shift register unit 203 to be offset from the normal shift register unit 202 in the extension direction of the gate line, and the at least one virtual shift register unit 203 to be offset from the normal shift register unit 202 in a direction away from the sealing adhesive 201, at least one virtual shift register unit 203 can be shifted inward in a direction away from the sealing adhesive 201, so that most of the structure in the virtual shift register unit 203 can be moved out of the area where the sealing adhesive 201 is located, thereby effectively improving the metal transmittance in the area where the sealing adhesive 201 is located and ensuring the sealing effect of the sealing adhesive 201.

[0049] like Figure 1 As shown, in some embodiments, the plurality of virtual shift register units 203 include at least a first virtual shift register unit 2031 and a second virtual shift register unit 2032; in the extension direction of the gate line, the distance between the first virtual shift register unit 2031 and the normal shift register unit 202 is greater than the distance between the second virtual shift register unit 2032 and the normal shift register unit 202. Here, the first virtual shift register unit 2031 is farther from the normal shift register than the second virtual shift register unit 2032 in the data line extension direction along the display area.

[0050] For example, the orthographic projection of the second virtual shift register unit 2032 on the substrate is located between the orthographic projection of the first virtual shift register unit 2031 on the substrate and the orthographic projection of the normal shift register unit 202 on the substrate.

[0051] For example, in the extension direction of the gate line, the distance between the orthographic projection of the first virtual shift register unit 2031 on the substrate and the orthographic projection of the normal shift register unit 202 on the substrate is greater than the distance between the orthographic projection of the second virtual shift register unit 2032 on the substrate and the orthographic projection of the normal shift register unit 202 on the substrate.

[0052] For example, the lower frame includes a corner area, in which the sealing adhesive 201 includes a curved portion, and the first virtual shift register unit 2031 and the second virtual shift register unit 2032 are closer to the curved portion than other virtual shift register units and normal shift register units.

[0053] For example, the first virtual shift register unit 2031 is offset inward by 60 micrometers, and the second virtual shift register unit 2032 is offset inward by 51 micrometers.

[0054] In the display substrate provided in the above embodiment, by setting the distance between the first virtual shift register unit 2031 and the normal shift register unit 202 in the extension direction of the gate line to be greater than the distance between the second virtual shift register unit 2032 and the normal shift register unit 202, both the first virtual shift register unit 2031 and the second virtual shift register unit 2032 can be shifted inward away from the sealing adhesive 201. This allows most of the structure in the first virtual shift register unit 2031 and the second virtual shift register unit 2032 to be moved out of the area where the sealing adhesive 201 is located, thereby effectively improving the metal transmittance in the area where the sealing adhesive 201 is located and ensuring the sealing effect of the sealing adhesive 201.

[0055] Moreover, the above-mentioned configuration allows the layout of the virtual shift register unit 203 to better match the curved portion of the sealing adhesive 201, ensuring the metal transmittance in the area where the curved portion is located and guaranteeing the sealing effect of the sealing adhesive 201.

[0056] like Figure 1 As shown, in some embodiments, the distance between the plurality of virtual shift register units 203 and the normal shift register unit 202 gradually increases along the direction away from the normal shift register unit 202 in the extension direction of the gate line.

[0057] The above configuration allows all the virtual shift register units 203 to shift inward in a direction away from the sealing adhesive 201. This moves most of the structure included in each virtual shift register unit 203 out of the area where the sealing adhesive 201 is located, thereby effectively improving the metal transmittance of the area where the sealing adhesive 201 is located and ensuring the sealing effect of the sealing adhesive 201.

[0058] Moreover, the above-mentioned configuration allows the layout of the virtual shift register unit 203 to better match the curved portion of the sealing adhesive 201, ensuring the metal transmittance in the area where the curved portion is located and guaranteeing the sealing effect of the sealing adhesive 201.

[0059] It is worth noting that in the display substrate provided in the above embodiments, all of the virtual shift register units 203 in the display substrate can be internally offset, or only a portion of the virtual shift register units 203 can be internally offset, for example... Figure 1The design shown includes six clock signal lines and four levels of virtual shift register units. The last two levels of virtual shift register units are offset in the gate line extension direction. Specifically, the last level is offset relative to the penultimate level towards the display area away from the sealing adhesive, and the penultimate level is offset relative to the third-to-last level. The third-to-last and fourth-to-last levels are arranged sequentially with the last normal shift register unit in the data line extension direction without misalignment. Of course, all virtual shift register units could be misaligned, as shown in the diagram with all four levels of virtual shift register units misaligned; this is not a limitation.

[0060] like Figure 1 As shown, in some embodiments, the virtual shift register unit 203 includes a virtual output transistor M32, the orthographic projection of the virtual output transistor M32 on the substrate not overlapping with the orthographic projection of the sealing adhesive 201 on the substrate.

[0061] like Figure 2 As shown, by way of example, both the virtual shift register unit 203 and the normal shift register unit 202 can adopt the following structure: specifically including the first transistor M1 to the eleventh transistor M11.

[0062] The first transistor M1 forms an input module. The gate of the first transistor M1 is coupled to the input signal line Input, and the first electrode of the first transistor M1 is coupled to the first signal line VDS. Under the control of the input signal line Input, the first signal provided by the first signal line VDS is transmitted to the pull-up node PU.

[0063] The second transistor M2 forms the first reset module. The gate of the second transistor M2 is coupled to the first reset line Reset. The first terminal of the second transistor M2 is coupled to the pull-up node PU. The second terminal of the second transistor M2 is coupled to the second signal line VSD. Under the control of the first reset line Reset, the second signal provided by the second signal line VSD is transmitted to the pull-up node PU for resetting the pull-up node.

[0064] The third transistor M3 (i.e., virtual output transistor M32 or normal output transistor M31) forms the output module. The gate of the third transistor M3 is coupled to the pull-up node PU, the first terminal of the third transistor M3 is coupled to the clock signal line CLK, and the second terminal of the third transistor M3 is coupled to the drive signal output terminal Output. This is used to control the output of the drive signal output terminal to output a drive signal.

[0065] The fourth transistor M4 forms a second reset module. The gate of the fourth transistor M4 is coupled to the frame reset line STV0, the first terminal of the fourth transistor is coupled to the pull-up node PU, and the second terminal of the fourth transistor M4 is coupled to the third signal line VGL. It is used to reset the pull-up node PU under the control of the frame reset line STV0.

[0066] The fifth transistor M5, the sixth transistor M6, the eighth transistor M8, and the ninth transistor M9 together form a pull-down control module. This module is coupled to the fourth signal line GCH, the third signal line VGL, the pull-up node PU, and the pull-down node PD. It is used to control the potential of the pull-down node PD.

[0067] The tenth transistor M10 forms the third reset module. The gate of the tenth transistor M10 is coupled to the pull-down node PD, the first terminal of the tenth transistor M10 is coupled to the pull-up node PU, and the second terminal of the tenth transistor M10 is coupled to the third signal line VGL. This module is used to reset the pull-up node PU under the control of the pull-down node PD.

[0068] The eleventh transistor M11 forms the fourth reset module. The gate of the eleventh transistor M11 is coupled to the pull-down node PD, the first terminal of the eleventh transistor M11 is coupled to the drive signal output terminal Output, and the second terminal of the eleventh transistor M11 is coupled to the third signal line VGL. This module is used to reset the drive signal output terminal Output under the control of the pull-down node PD.

[0069] The seventh transistor T7 forms the fifth reset module. The gate of the seventh transistor T7 is coupled to the fifth signal line GCL, the first terminal of the seventh transistor T7 is coupled to the drive signal output terminal Output, and the second terminal of the seventh transistor T7 is coupled to the third signal line VGL. This module is used to reset the drive signal output terminal Output under the control of the fifth signal line GCL.

[0070] For example, the virtual output transistor M32 is relatively large in size and occupies a large layout space.

[0071] For example, the orthographic projection of the virtual output transistor M32 on the substrate does not overlap with the orthographic projection of the curved portion of the sealing adhesive 201 on the substrate.

[0072] In the display substrate provided in the above embodiments, by setting the virtual shift register unit 203 to include a virtual output transistor M32, the orthographic projection of the virtual output transistor M32 on the substrate does not overlap with the orthographic projection of the sealant 201 on the substrate, so that the virtual output transistor M32, which occupies a large layout space, can be moved out of the area where the sealant 201 is located, thus avoiding the impact on the metal transmittance of the virtual output transistor M32 to the area where the sealant 201 is located.

[0073] In some embodiments, the minimum distance between the orthographic projection of the virtual output transistor M32 on the substrate and the orthographic projection of the sealing adhesive 201 on the substrate is greater than or equal to 50 micrometers.

[0074] The above configuration fully considers the precision of the production line equipment, ensuring that the orthographic projection of the virtual output transistor M32 on the substrate does not overlap with the orthographic projection of the sealing adhesive 201 on the substrate. This allows most of the structure included in each virtual shift register unit 203 to be moved out of the area where the sealing adhesive 201 is located, thereby effectively improving the metal transmittance in the area where the sealing adhesive 201 is located and ensuring the sealing effect of the sealing adhesive 201.

[0075] like Figure 1 As shown, in some embodiments, the border area further includes a cascaded signal line 204 connected between two virtual shift register units 203 for transmitting signals between the two virtual shift register units 203. The orthographic projection of the cascaded signal line 204 on the substrate does not overlap with the orthographic projection of the sealing adhesive 201 on the substrate.

[0076] For example, the display substrate further includes multiple buses and multiple cascaded signal lines 204. These buses are coupled to the multiple virtual shift register units 203 and the multiple normal shift register units 202, respectively. The types of buses are varied, such as clock signal lines, common signal lines, high-level signal lines, and low-level signal lines. The cascaded signal lines 204 connect between two virtual shift register units 203, allowing the upper-level virtual shift register unit 203 to provide input signals to the lower-level virtual shift register unit 203, or the lower-level virtual shift register unit 203 to provide reset signals to the upper-level virtual shift register unit 203.

[0077] It is worth noting that the cascaded signal line 204 can also be set between the two normal shift register units 202, or between the normal shift register unit 202 and the virtual shift register unit 203.

[0078] The cascaded signal line 204 is made of metal. The above-mentioned arrangement ensures that the orthographic projection of the cascaded signal line 204 on the substrate does not overlap with the orthographic projection of the sealing adhesive 201 on the substrate. This avoids the cascaded signal line 204 affecting the metal transmittance of the area where the sealing adhesive 201 is located, thereby effectively improving the metal transmittance of the area where the sealing adhesive 201 is located and ensuring the sealing effect of the sealing adhesive 201.

[0079] like Figure 1 As shown, in some embodiments, the minimum distance between at least two adjacent virtual shift register units 203 orthogonal projections on the substrate is greater than the minimum distance between two adjacent normal shift register units 202 orthogonal projections on the substrate.

[0080] For example, the minimum distance between the orthographic projections of two adjacent virtual shift register units 203 on the substrate includes 45.05 micrometers, but is not limited to this.

[0081] For example, the minimum distance between the orthographic projections of two adjacent normal shift register units 202 on the substrate includes 5.05 micrometers, but is not limited to this.

[0082] The minimum distance between the orthographic projections of at least two adjacent virtual shift register units 203 on the substrate is greater than the minimum distance between the orthographic projections of two adjacent normal shift register units 202 on the substrate. This ensures that sufficient trace space is maintained between adjacent virtual shift register units 203 and between adjacent virtual shift register units 203 and normal shift register units 202 during the inward movement of the virtual shift register units 203. This not only effectively improves the metal transmittance in the area where the sealing adhesive 201 is located, ensuring the sealing effect of the sealing adhesive 201, but also avoids the problem of short circuits between traces and shift register units due to insufficient trace space, effectively improving the stability and reliability of the display substrate.

[0083] In some embodiments, among the plurality of virtual shift register units 203, the distance between two adjacent virtual shift register units 203 that are farther away from the normal shift register unit 202 is greater.

[0084] Among the plurality of virtual shift register units 203, the virtual shift register unit 203 that is farther away from the normal shift register unit 202 is closer to the arc portion of the sealing adhesive 201, and the greater the distance that needs to be moved inward.

[0085] In the display substrate provided in the above embodiments, by setting the distance between two adjacent virtual shift register units 203 that are farther away from the normal shift register unit 202, it can not only effectively improve the metal transmittance in the area where the sealing adhesive 201 is located and ensure the sealing effect of the sealing adhesive 201, but also ensure that there is sufficient trace space between adjacent virtual shift register units 203. Moreover, it avoids the problem of short circuit between traces and shift register units due to insufficient trace space, effectively improving the stability and reliability of the display substrate.

[0086] like Figure 4 As shown, in some embodiments, the display area 10 includes multiple normal scan lines, which are coupled to corresponding normal shift register units 202;

[0087] The border area also includes multiple virtual scan lines 205, which are coupled to the corresponding virtual shift register units 203;

[0088] The display substrate also includes multiple data lines 206; the overlap area between the orthographic projection of the virtual scan line 205 on the substrate and the orthographic projection of the data line 206 on the substrate is greater than the overlap area between the orthographic projection of the normal scan line on the substrate and the orthographic projection of the data line 206 on the substrate.

[0089] For example, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixel pixels are arranged in an array. The plurality of sub-pixel driving circuits are divided into multiple rows of sub-pixel driving circuits and multiple columns of sub-pixel driving circuits. The multiple rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The multiple columns of sub-pixel driving circuits are arranged along the first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. For example, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0090] For example, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to the anode of the light-emitting element and is used to provide a driving signal to the light-emitting element to drive it to emit light.

[0091] For example, the display area 10 includes multiple normal scan lines, which are coupled to each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits, and are used to provide scan signals to each sub-pixel driving circuit.

[0092] For example, the normal scan line includes a gate line, but is not limited to this. For instance, the normal scan line can also be a light emission control line, a reset line, etc.

[0093] For example, the border area also includes multiple virtual scan lines 205, which are coupled to corresponding virtual shift register units 203 and serve as the load of the virtual shift register units 203. By controlling the shape, size, and layout of the virtual scan lines 205, the load of the virtual shift register units 203 can be adjusted.

[0094] For example, the display area 10 further includes multiple data lines 206, each of which corresponds to one of the multiple columns of sub-pixel driving circuits. Each data line 206 is coupled to each sub-pixel driving circuit in the corresponding column of sub-pixel driving circuits to provide data signals to each sub-pixel driving circuit.

[0095] For example, both the normal scan line and the virtual scan line 205 extend along the first direction, and the data line 206 extends along the second direction.

[0096] like Figure 3 As shown, exemplarily, in a conventional display substrate, virtual pixels can be provided in the border area. Each virtual pixel includes a virtual transistor 301, which is coupled to a corresponding virtual scan line 205 and serves as the load of the virtual shift register unit 203. In the display substrate provided in the above embodiment, the virtual transistor 301 can be removed, leaving only the virtual scan line 205.

[0097] In the display substrate provided in the above embodiments, the virtual transistor 301 can be removed. Simultaneously, the overlap area between the orthographic projection of the virtual scan line 205 on the substrate and the orthographic projection of the data line 206 on the substrate is set to be greater than the overlap area between the orthographic projection of the normal scan line on the substrate and the orthographic projection of the data line 206 on the substrate. This way, by removing the virtual transistor 301, a larger amount of layout space for the lower bezel can be freed up. At the same time, the virtual scan line 205 can be widened, so that the widened portion of the virtual scan line 205 occupies part of the freed-up space, compensating for the load generated by the virtual transistor 301. The remaining freed-up space can be directly saved, thus better achieving a narrow lower bezel solution. The display substrate provided in the above embodiments can compress the lower bezel width by at least 30 micrometers, saving approximately 50% of wiring space.

[0098] In the display substrate provided in the above embodiments, the line width of the portion of the data line 206 located in the lower border area can be widened, and the line width of the virtual scan line 205 can also be widened, thereby making the overlap area between the orthographic projection of the virtual scan line 205 on the substrate and the orthographic projection of the data line 206 on the substrate larger than the overlap area between the orthographic projection of the normal scan line on the substrate and the orthographic projection of the data line 206 on the substrate, thus increasing the capacitance value of the overlap capacitance formed between the virtual scan line 205 and the data line 206.

[0099] In the display substrate provided in the above embodiments, by reasonably setting the line width of the portion of the data line 206 located in the lower frame area and the line width of the virtual scan line 205, it is ensured that the virtual shift register unit 203 and the normal shift register unit 202 have the same or similar load.

[0100] In some embodiments, the linewidth of the virtual scan line 205 is between 8 micrometers and 15 micrometers, and the linewidth of the portion overlapping between the orthographic projection of the data line 206 on the substrate and the orthographic projection of the virtual scan line 205 on the substrate is between 6 micrometers and 15 micrometers.

[0101] For example, the line width of the normal scan line includes 5 micrometers, and the line width of the data line 206 located in the portion of the display area 10 includes 3.5 micrometers.

[0102] For example, the linewidth of the virtual scan line 205 can be 8 micrometers, 10 micrometers, 12 micrometers, or 15 micrometers.

[0103] For example, the linewidth of the portion overlapping between the orthographic projection of the data line 206 on the substrate and the orthographic projection of the virtual scan line 205 on the substrate can be 8 micrometers, 10 micrometers, 12 micrometers, or 14 micrometers.

[0104] In the display substrate provided in the above embodiments, setting the line width of the virtual scan line 205 and the line width of the data line 206 within the above range can ensure that the virtual shift register unit 203 and the normal shift register unit 202 have the same or similar load.

[0105] like Figure 5 and Figure 6 As shown, in some embodiments, the virtual shift register unit 203 includes a virtual output transistor M32, and the normal shift register unit 202 includes a normal output transistor M31; the size of the virtual output transistor M32 is smaller than the size of the normal output transistor M31.

[0106] For example, the virtual scan lines 205 and virtual transistors 301 included in the display substrate can be removed to increase the width of the lower bezel.

[0107] For example, setting the size of the virtual output transistor M32 to be smaller than the size of the normal output transistor M31 includes: the size of the channel portion of the virtual output transistor M32 being smaller than the size of the channel portion of the normal output transistor M31; or the aspect ratio of the virtual output transistor M32 being smaller than the aspect ratio of the normal output transistor M31; but not limited to this.

[0108] In the display substrate provided in the above embodiments, by setting the size of the virtual output transistor M32 to be smaller than the size of the normal output transistor M31, the virtual shift register unit 203 can have the same or similar signal delay as the normal shift register unit 202 when the virtual scan line 205 and the virtual transistor 301 are not connected, thus ensuring that a normal reset signal is provided to the pixels of the display area 10.

[0109] like Figure 5 and Figure 6 As shown, in some embodiments, the size of the virtual output transistor M32 is set to 1 / 2 or 1 / 3 of the size of the normal output transistor M31, but it is not limited to this.

[0110] The above configuration allows the virtual shift register unit 203 to have the same or similar signal delay as the normal shift register unit 202 without being connected to the virtual scan line 205 and the virtual transistor 301, thus ensuring that the pixels of the display area 10 are provided with a normal reset signal.

[0111] like Figure 5 and Figure 6 As shown, in some embodiments, the virtual output transistor M32 is configured to include a plurality of sub-transistors M320 connected in series.

[0112] For example, the plurality of sub-transistors M320 are evenly distributed.

[0113] The above configuration allows the virtual shift register unit 203 to have the same or similar signal delay as the normal shift register unit 202 without being connected to the virtual scan line 205 and the virtual transistor 301, thus ensuring that the pixels of the display area 10 are provided with a normal reset signal.

[0114] like Figure 7 and Figure 8As shown, in some embodiments, the border area further includes multiple fan-out lines 207, each fan-out line 207 including a first portion 2071 and a second portion 2072. The orthographic projection of the first portion 2071 on the substrate at least partially overlaps with the orthographic projection of the sealing adhesive 201 on the substrate, while the orthographic projection of the second portion 2072 on the substrate does not overlap with the orthographic projection of the sealing adhesive 201 on the substrate.

[0115] The minimum distance between the orthographic projections of adjacent first portions 2071 on the substrate is greater than the minimum distance between the orthographic projections of adjacent second portions 2072 on the substrate.

[0116] For example, the plurality of fan-out lines 207 includes a plurality of first fan-out lines 207 and a plurality of second fan-out lines 207, which are alternately arranged. Each of the first fan-out lines 207 and the second fan-out lines 207 includes a first portion 2071 and a second portion 2072.

[0117] For example, the first fan-out line 207 is fabricated using the first gate metal layer in the display substrate, and the second fan-out line 207 is fabricated using the source / drain metal layer in the display substrate. The source / drain metal layer may be a first source / drain metal layer or a second source / drain metal layer.

[0118] For example, each fan-out line 207 includes a first portion 2071 and two second portions 2072, with the first portion 2071 located between the two second portions 2072 and coupled to each of the two second portions 2072. The first portion 2071 closer to the display area 10 is coupled to the data line 206 in the display area 10, while the first portion 2071 farther from the display area 10 can be coupled to a driver chip for receiving data signals.

[0119] For example, the first portion 2071 includes a broken line structure with multiple broken line corners. The second portion 2072 includes a diagonal line structure, the extension direction of which intersects both the first direction and the second direction.

[0120] In the display substrate provided in the above embodiment, the fan-out line 207 is segmented, and the minimum distance between the orthographic projections of adjacent first portions 2071 on the substrate is set to be greater than the minimum distance between the orthographic projections of adjacent second portions 2072 on the substrate. This results in a larger spacing between the first portions 2071 located within the area where the sealing adhesive 201 is located, which is beneficial to improving the metal transmittance in the area where the sealing adhesive 201 is located, and can meet the requirement of a transmittance greater than or equal to 35%. At the same time, it ensures that the second portions 2072 not located within the area where the sealing adhesive 201 is located have a smaller spacing, which can occupy a smaller bottom bezel space.

[0121] The display substrate provided in the above embodiments can achieve a transmittance of 42.85%.

[0122] In some embodiments, the linewidth of the first portion 2071 is between 2.2 micrometers and 4 micrometers, and the minimum distance between the orthographic projections of adjacent first portions 2071 on the substrate is between 1 micrometer and 1.2 micrometers.

[0123] For example, the linewidth of the first portion 2071 includes 3.5 micrometers, and the minimum spacing between the orthographic projections of adjacent first portions 2071 on the substrate includes 1.5 micrometers.

[0124] For example, the linewidth of the second portion 2072 includes 3.5 micrometers, and the minimum spacing between the orthographic projections of adjacent second portions 2072 on the substrate includes 1.0 micrometer. The transmittance of the region where the second portion 2072 is located can reach 28.5%.

[0125] This disclosure also provides a display device, including the display substrate provided in the above embodiments.

[0126] In the display substrate provided in the above embodiments, by configuring at least one virtual shift register unit 203 to be offset from the normal shift register unit 202 in the extension direction of the gate line, and by offsetting the at least one virtual shift register unit 203 from the normal shift register unit 202 in a direction away from the sealant 201, at least one virtual shift register unit 203 can be shifted inward in a direction away from the sealant 201. This allows most of the structure in the virtual shift register unit 203 to be moved out of the area where the sealant 201 is located, thereby effectively improving the metal transmittance in the area where the sealant 201 is located and ensuring the sealing effect of the sealant 201. Therefore, the display device provided in the embodiments of this disclosure, when including the above-described display substrate, also has the above-described beneficial effects.

[0127] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0128] For example, the display device includes a liquid crystal display device. The liquid crystal display device may be manufactured using a 6-mask process or an 8-mask process.

[0129] The 6Mask process includes: sequentially fabricating a first gate metal layer, an active layer, a first indium tin oxide layer (forming a pixel electrode), a source / drain metal layer, a passivation layer, and a second indium tin oxide layer (forming a common electrode).

[0130] The 8Mask process flow includes: sequentially fabricating a first gate metal layer, a gate insulating layer, an indium gallium zinc oxide layer (IGZO), a source / drain metal layer, an insulating layer, a first indium tin oxide layer (forming a common electrode), a passivation layer, and a second indium tin oxide layer (forming a pixel electrode).

[0131] It should be noted that the signal line extending along the X direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along the X direction, and the length of the main part extending along the X direction is greater than the length of the secondary part extending in other directions.

[0132] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0133] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0134] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0135] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0136] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0137] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0138] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: The display area and the border area surrounding the display area; the border area includes a sealing adhesive, and a plurality of normal shift register units and a plurality of virtual shift register units arranged in sequence; The display substrate further includes a plurality of gate lines, at least a portion of which are located in the display area; In the extending direction of the gate line, at least one of the virtual shift register units is offset from the normal shift register unit, and the at least one virtual shift register unit is offset from the normal shift register unit in a direction away from the sealing adhesive; The display area includes multiple normal scan lines, and the normal scan lines are coupled to corresponding normal shift register units; The border area also includes multiple virtual scan lines, which are coupled to corresponding virtual shift register units; The display substrate also includes multiple data lines; the overlap area between the orthographic projection of the virtual scan line on the substrate and the orthographic projection of the data line on the substrate is greater than the overlap area between the orthographic projection of the normal scan line on the substrate and the orthographic projection of the data line on the substrate.

2. The display substrate according to claim 1, wherein, The plurality of virtual shift register units includes at least a first virtual shift register unit and a second virtual shift register unit; in the extension direction of the gate line, the distance between the first virtual shift register unit and the normal shift register unit is greater than the distance between the second virtual shift register unit and the normal shift register unit.

3. The display substrate according to claim 1, wherein, Along the direction away from the normal shift register unit, in the direction of extension of the gate line, the distance between the plurality of virtual shift register units and the normal shift register unit gradually increases.

4. The display substrate according to claim 1, wherein, The virtual shift register unit includes a virtual output transistor, and the orthographic projection of the virtual output transistor on the substrate does not overlap with the orthographic projection of the sealing adhesive on the substrate.

5. The display substrate according to claim 4, wherein, The minimum distance between the orthographic projection of the virtual output transistor on the substrate and the orthographic projection of the sealing adhesive on the substrate is greater than or equal to 50 micrometers.

6. The display substrate according to claim 1, wherein, The border area also includes cascaded signal lines connected between two virtual shift register units for transmitting signals between the two virtual shift register units. The orthographic projection of the cascaded signal lines on the substrate does not overlap with the orthographic projection of the sealing adhesive on the substrate.

7. The display substrate according to claim 1, wherein, The minimum distance between the orthographic projections of at least two adjacent virtual shift register units on the substrate is greater than the minimum distance between the orthographic projections of two adjacent normal shift register units on the substrate.

8. The display substrate according to claim 7, wherein, Among the plurality of virtual shift register units, the greater the distance between two adjacent virtual shift register units that are farther away from the normal shift register unit, the larger the distance between them.

9. The display substrate according to claim 1, wherein, The linewidth of the virtual scan line is between 8 micrometers and 15 micrometers, and the linewidth of the overlapping portion between the orthographic projection of the data line on the substrate and the orthographic projection of the virtual scan line on the substrate is between 6 micrometers and 15 micrometers.

10. The display substrate according to claim 1, wherein, The virtual shift register unit includes a virtual output transistor, and the normal shift register unit includes a normal output transistor; the size of the virtual output transistor is smaller than the size of the normal output transistor.

11. The display substrate according to claim 10, wherein, The size of the virtual output transistor is 1 / 2 or 1 / 3 of the size of the normal output transistor.

12. The display substrate according to claim 10, wherein, The virtual output transistor comprises multiple sub-transistors connected in series.

13. The display substrate according to claim 1, wherein, The border area also includes multiple fan-out lines, each fan-out line comprising a first part and a second part. The orthographic projection of the first part on the substrate overlaps with the orthographic projection of the sealing adhesive on the substrate, while the orthographic projection of the second part on the substrate does not overlap with the orthographic projection of the sealing adhesive on the substrate. The minimum distance between the orthographic projections of adjacent first portions on the substrate is greater than the minimum distance between the orthographic projections of adjacent second portions on the substrate.

14. The display substrate according to claim 13, wherein, The linewidth of the first portion is between 2.2 micrometers and 4 micrometers, and the minimum distance between the orthographic projections of adjacent first portions on the substrate is between 1 micrometer and 1.2 micrometers.

15. A display device comprising a display substrate as claimed in any one of claims 1 to 14.

Images