Reference current generation circuit, method and chip

Abstract

The application discloses a kind of reference current generating circuit, method and chip, circuit includes: first current generating unit, second current generating unit and fourth current mirror, first current generating unit includes first buffer, first current mirror and first resistance;Second current generating unit includes second buffer, second current mirror, third current mirror and second resistance;Fourth current mirror is connected with first current mirror and third current mirror to output reference current.According to the reference current generating circuit, method and chip of the application, first current is generated based on first resistance by first current generating unit, second current is generated based on second resistance by second current generating unit, by selecting first resistance and second resistance of different width, the resistance value change of second resistance under each process angle is n times of the resistance value change of first resistance, different proportions of first current and second current are subtracted by fourth current mirror to obtain reference current not changing with resistance process angle.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and in particular to a reference current generating circuit, method and chip. BACKGROUND

[0002] Reference voltage and current generating circuit is a basic module in most chips, reference voltage can be generated by bandgap reference circuit, and reference current can be obtained by reference voltage and resistance, the principle is shown in Figure 1 , the voltage at node VFB is clamped at reference voltage VREF by error amplifier EA, so that the saturation current of MOS tube M2 is Ib=k*VREF / R1, where k represents the width-length ratio of MOS tube M2 to MOS tube M1, it can be seen that the reference current thus obtained is directly related to the resistance value of the resistance.

[0003] In practice, the resistance in each chip is randomly made of a process corner, and the resistance value of the resistance in the chip has a large variation range with the process corner of the resistance, resulting in a large variation of the obtained reference current with the process corner of the resistance. In some application scenarios, it is necessary to obtain a reference current independent of the process corner of the resistance, so a corresponding test circuit is needed to read the size of the Bias current in the test, so as to trim the resistance value of the resistance R1 in Figure 1 , which greatly increases the cost.

[0004] In addition to the above scheme of trimming the resistance R1 in Figure 1 , the design can also greatly reduce the variation range of Bias current with the process corner of resistance R1 by increasing the Width of resistance R1. Taking poly resistance as an example, the larger the Width value, the smaller the variation range of resistance value with process corner.

[0005] Taking a certain BCD process as an example, the square resistance of poly with Width of 180 nm has a variation range of about ±50% in the process corners of ss (slow nmos and slow pmos) and ff (fast nmos and fast pmos) compared with tt (typical nmos and typical pmos) process corner; when the Width increases to 420 nm, the variation range of square resistance is reduced to about ±20%; and when the Width increases to 2 um, the variation range of square resistance is further reduced to about ±10%; it can be seen that increasing the Width of resistance can effectively reduce the variation range of reference current, but the effect is still relatively limited.

[0006] The information disclosed in this Background section is only for the purpose of increasing an understanding of the general context of the present application and does not therefore constitute SUMMARY

[0007] The present application aims to provide a reference current generating circuit, method and chip, which can prevent the output terminal of an operational amplifier from overshooting during a power supply voltage power-on stage.

[0008] To achieve the above-mentioned purpose, an embodiment of the present application provides a reference current generating circuit, comprising: a first current generating unit and a second current generating unit.

[0009] The first current generating unit comprises: a first buffer, a first current mirror and a first resistor, a first input terminal of the first buffer is used to receive a first reference voltage, a second input terminal of the first buffer is connected with a first terminal of the first resistor, a second terminal of the first resistor is connected with a ground voltage, and the first current mirror is connected with an output terminal of the first buffer and the first terminal of the first resistor to output a first current in proportion to a current on the first resistor.

[0010] The second current generating unit comprises: a second buffer, a second current mirror, a third current mirror and a second resistor, a first input terminal of the second buffer is used to receive the first reference voltage, a second input terminal of the second buffer is connected with a first terminal of the second resistor, a second terminal of the second resistor is connected with the ground voltage, the second current mirror is connected with an output terminal of the second buffer and the first terminal of the second resistor, the third current mirror is connected with the second current mirror, and the second current mirror and the third current mirror output a second current in proportion to a current on the second resistor.

[0011] The reference current generating circuit further comprises a fourth current mirror, the fourth current mirror is connected with the first current mirror and the third current mirror to output a reference current irrelevant to a process angle of a resistor in proportion to a difference between the first current and the second current.

[0012] In one or more embodiments of the present application, the first current mirror comprises a first MOS transistor and a second MOS transistor, a control terminal of the first MOS transistor and a control terminal of the second MOS transistor are connected and simultaneously connected with the output terminal of the first buffer, a first terminal of the first MOS transistor is connected with the first terminal of the first resistor and the second input terminal of the first buffer, a second terminal of the first MOS transistor is connected with a power supply voltage, a first terminal of the second MOS transistor is connected with the fourth current mirror, and a second terminal of the second MOS transistor is connected with the power supply voltage.

[0013] In one or more embodiments of the present application, the second current mirror comprises a third MOS transistor and a fourth MOS transistor, a control terminal of the third MOS transistor and a control terminal of the fourth MOS transistor are connected and simultaneously connected to an output terminal of the second buffer, a first terminal of the third MOS transistor is connected to a first terminal of the second resistor and a second input terminal of the second buffer, a second terminal of the third MOS transistor is connected to a power supply voltage, a first terminal of the fourth MOS transistor is connected to the third current mirror, and a second terminal of the fourth MOS transistor is connected to the power supply voltage.

[0014] In one or more embodiments of the present application, the third current mirror comprises a fifth MOS transistor and a sixth MOS transistor, a control terminal of the fifth MOS transistor and a control terminal of the sixth MOS transistor are connected, a first terminal of the fifth MOS transistor is connected to the second current mirror and the control terminal of the fifth MOS transistor, a second terminal of the fifth MOS transistor is connected to a ground voltage, a first terminal of the sixth MOS transistor is connected to the fourth current mirror, and a second terminal of the sixth MOS transistor is connected to the ground voltage.

[0015] In one or more embodiments of the present application, the fourth current mirror comprises a seventh MOS transistor and an eighth MOS transistor, a control terminal of the seventh MOS transistor and a control terminal of the eighth MOS transistor are connected, a first terminal of the seventh MOS transistor, the control terminal of the seventh MOS transistor, the first current mirror and the third current mirror are connected, a second terminal of the seventh MOS transistor and a second terminal of the eighth MOS transistor are connected to a ground voltage, and a first terminal of the eighth MOS transistor is used to output a reference current.

[0016] In one or more embodiments of the present application, a mirror ratio of the first current mirror is 1:k1, a mirror ratio of the second current mirror is 1:k2, a mirror ratio of the third current mirror is 1:m2, and a mirror ratio of the fourth current mirror is 1:m1.

[0017] In one or more embodiments of the present application, k1>k2m2≥1.

[0018] The present application also discloses a reference current generation method based on the reference current generation circuit, the method comprising:

[0019] clamping a voltage at a first terminal of the first resistor to a first reference voltage by the first buffer, and generating a current based on the first reference voltage by the first resistor;

[0020] proportionally copying the current on the first resistor by the first current mirror based on a mirror ratio of the first current mirror to obtain a first current;

[0021] clamping a voltage at a first terminal of the second resistor to the first reference voltage by the second buffer, and generating a current based on the first reference voltage by the second resistor;

[0022] The second current is obtained by the second current mirror and the third current mirror proportionally copying the current on the second resistance based on the mirror ratio of itself;

[0023] The reference current is obtained by the fourth current mirror obtaining the difference between the first current and the second current and proportionally copying the difference based on the mirror ratio of itself.

[0024] In one or more embodiments of the present application, the mirror ratio of the first current mirror is set as 1:k1, the mirror ratio of the second current mirror is set as 1:k2, the mirror ratio of the third current mirror is set as 1:m2, the mirror ratio of the fourth current mirror is set as 1:m1, and k1>k2m2≥1.

[0025] The present application also discloses a chip comprising the reference current generating circuit.

[0026] Compared with the prior art, the reference current generating circuit, method and chip according to the embodiments of the present application generate the first current based on the first resistance by the first current generating unit, generate the second current based on the second resistance by the second current generating unit, select the first resistance and the second resistance with different widths, so that the resistance value change of the second resistance under each process angle is n times of the resistance value change of the first resistance, and subtract the first current and the second current with different proportions by the fourth current mirror to obtain the reference current which does not change with the resistance process angle. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a circuit schematic diagram of the reference current generating circuit of the prior art.

[0028] Figure 2 is a circuit schematic diagram of the reference current generating circuit according to the first embodiment of the present application.

[0029] Figure 3 is a flow chart of the reference current generating method according to the first embodiment of the present application. DETAILED DESCRIPTION

[0030] The specific embodiments of the present application are described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present application is not limited by the specific embodiments.

[0031] Unless otherwise clearly indicated, in the entire specification and claims, the term "comprise" or its variants such as "comprises" or "comprising" will be understood to encompass the stated elements or components, but not to exclude the presence of other elements or components.

[0032] "coupled" or "connected" or "linked" in the specification include both direct connection and indirect connection. The indirect connection is the connection through an intermediate medium, such as the connection through an electrically conductive medium, which can have a parasitic inductance or a parasitic capacitance; the indirect connection can also include the connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as the connection through a circuit or component such as a switch, a follower circuit, etc. In addition, in the present application, words such as "first", "second", etc. are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply a certain actual relationship, quantity or sequence between the technical features.

[0033] As shown in Figure 2 A reference current generating circuit includes a first current generating unit, a second current generating unit and a fourth current mirror 30.

[0034] The first current generating unit includes a first buffer EA1, a first current mirror 11 and a first resistor R1. The first input terminal of the first buffer EA1 is configured to receive a first reference voltage VREF, the second input terminal of the first buffer EA1 is connected to the first terminal of the first resistor R1, the second terminal of the first resistor R1 is connected to a ground voltage, and the first current mirror 11 is connected to the output terminal of the first buffer EA1 and the first terminal of the first resistor R1 to proportionally copy and output a first current based on the current on the first resistor R1. In an embodiment, the first input terminal of the first buffer EA1 is a negative input terminal, and the second input terminal of the first buffer EA1 is a positive input terminal.

[0035] In addition, the second current generating unit includes a second buffer EA2, a second current mirror 21, a third current mirror 22 and a second resistor R2. The first input terminal of the second buffer EA2 is configured to receive the first reference voltage VREF, the second input terminal of the second buffer EA2 is connected to the first terminal of the second resistor R2, the second terminal of the second resistor R2 is connected to the ground voltage, the second current mirror 21 is connected to the output terminal of the second buffer EA2 and the first terminal of the second resistor R2, and the third current mirror 22 is connected to the second current mirror 21. The second current mirror 21 and the third current mirror 22 proportionally copy and output a second current based on the current on the second resistor R2. In an embodiment, the first input terminal of the second buffer EA2 is a negative input terminal, and the second input terminal of the second buffer EA2 is a positive input terminal.

[0036] In an embodiment, the fourth current mirror 30 is connected to the first current mirror 11 and the third current mirror 22 to proportionally copy the difference between the first current and the second current and output a reference current independent of the process angle of the first resistor R1 and the second resistor R2.

[0037] As shown in Figure 2As shown, the first current mirror 11 includes a first MOSFET M1 and a second MOSFET M2. The control terminals of the first MOSFET M1 and the second MOSFET M2 are connected and simultaneously connected to the output terminal of the first buffer EA1. The first terminal of the first MOSFET M1 is connected to the first terminal of the first resistor R1 and the second input terminal of the first buffer EA1. The second terminal of the first MOSFET M1 is connected to the power supply voltage. The first terminal of the second MOSFET M2 is connected to the fourth current mirror 30, and the second terminal of the second MOSFET M2 is also connected to the power supply voltage. In one embodiment, the first MOSFET M1 and the second MOSFET M2 are P-channel MOSFETs, the control terminals of the first MOSFET M1 and the second MOSFET M2 are the gates, the first terminals of the first MOSFET M1 and the second MOSFET M2 are the drains, and the second terminals of the first MOSFET M1 and the second MOSFET M2 are the sources. In other embodiments, the first MOSFET M1 and the second MOSFET M2 can be N-channel MOSFETs.

[0038] In one embodiment, the mirror ratio of the first current mirror 11 is 1:k1, that is, the ratio of the width to length of the first MOS transistor M1 and the second MOS transistor M2 is 1:k1, where k1 > 0.

[0039] like Figure 2 As shown, the voltage at the first terminal VFB1 of the first resistor R1 is clamped to the first reference voltage VREF by the first buffer EA1, thus the current through the first resistor R1 can be obtained as the first reference voltage VREF divided by the resistance of the first resistor R1. At this time, the first current I through the second MOSFET M2 is... b1 It equals the current in the first resistor R1 multiplied by k1.

[0040] like Figure 2 As shown, the second current mirror 21 includes a third MOSFET M3 and a fourth MOSFET M4. The control terminals of the third MOSFET M3 and the fourth MOSFET M4 are connected and simultaneously connected to the output terminal of the second buffer EA2. The first terminal of the third MOSFET M3 is connected to the first terminal of the second resistor R2 and the second input terminal of the second buffer EA2. The second terminal of the third MOSFET M3 is connected to the power supply voltage. The first terminal of the fourth MOSFET M4 is connected to the third current mirror 22, and the second terminal of the fourth MOSFET M4 is also connected to the power supply voltage. In one embodiment, the third MOSFET M3 and the fourth MOSFET M4 are P-channel MOSFETs, with the control terminals of the third MOSFET M3 and the fourth MOSFET M4 serving as gates, the first terminals of the third MOSFET M3 and the fourth MOSFET M4 serving as drains, and the second terminals of the third MOSFET M3 and the fourth MOSFET M4 serving as sources. In other embodiments, the third MOSFET M3 and the fourth MOSFET M4 can be N-channel MOSFETs.

[0041] In one embodiment, the mirror ratio of the second current mirror 21 is 1:k2, that is, the ratio of the width to length of the third MOS transistor M3 and the fourth MOS transistor M4 is 1:k2, where k2 > 0.

[0042] like Figure 2 As shown, the third current mirror 22 includes a fifth MOSFET M5 and a sixth MOSFET M6. The control terminals of the fifth MOSFET M5 and the sixth MOSFET M6 are connected. The first terminal of the fifth MOSFET M5 is connected to the first terminal of the fourth MOSFET M4 of the second current mirror 21 and the control terminal of the fifth MOSFET M5. The second terminal of the fifth MOSFET M5 is connected to ground. The first terminal of the sixth MOSFET M6 is connected to the fourth current mirror 30, and the second terminal of the sixth MOSFET M6 is connected to ground. In one embodiment, the fifth MOSFET M5 and the sixth MOSFET M6 are N-channel MOSFETs. The control terminals of the fifth MOSFET M5 and the sixth MOSFET M6 are the gates, the first terminals of the fifth MOSFET M5 and the sixth MOSFET M6 are the drains, and the second terminals of the fifth MOSFET M5 and the sixth MOSFET M6 are the sources. In other embodiments, the fifth MOSFET M5 and the sixth MOSFET M6 can be P-channel MOSFETs.

[0043] In one embodiment, the mirror ratio of the third current mirror 22 is 1:m2, that is, the width-to-length ratio of the fifth MOS transistor M5 and the sixth MOS transistor M6 is 1:m2, where m2>0.

[0044] like Figure 2 As shown, the voltage at the first terminal VFB2 of the second resistor R2 is clamped to the first reference voltage VREF by the second buffer EA2. Therefore, the current across the second resistor R2 is the first reference voltage VREF divided by the resistance of the second resistor R2. At this time, the current I across the fourth MOSFET M4 is... b2 The current is equal to the current through the second resistor R2 multiplied by k2, while the second current through the sixth MOSFET M6 is equal to the current I. b2 Multiply by m2.

[0045] like Figure 2As shown, the fourth current mirror 30 comprises a seventh MOS transistor M7 and an eighth MOS transistor M8. The control terminal of the seventh MOS transistor M7 and the control terminal of the eighth MOS transistor M8 are connected, the first terminal of the seventh MOS transistor M7, the control terminal of the seventh MOS transistor M7 and the first terminal of the sixth MOS transistor M6 of the third current mirror 22 are connected to the first terminal of the second MOS transistor M2 of the first current mirror 11, the second terminal of the seventh MOS transistor M7 and the second terminal of the eighth MOS transistor M8 are connected to the ground voltage, and the first terminal of the eighth MOS transistor M8 is used to output the reference current. In an embodiment, the seventh MOS transistor M7 and the eighth MOS transistor M8 are N-channel MOS transistors, the control terminal of the seventh MOS transistor M7 and the control terminal of the eighth MOS transistor M8 are gates, the first terminal of the seventh MOS transistor M7 and the first terminal of the eighth MOS transistor M8 are drains, and the second terminal of the seventh MOS transistor M7 and the second terminal of the eighth MOS transistor M8 are sources. In other embodiments, the seventh MOS transistor M7 and the eighth MOS transistor M8 can be P-channel MOS transistors.

[0046] In an embodiment, the mirror ratio of the fourth current mirror 30 is 1: m1, that is, the width-length ratio of the seventh MOS transistor M7 and the eighth MOS transistor M8 is 1: m1, and m1> 0.

[0047] As shown, Figure 2 Based on the first current I b1 on the second MOS transistor M2 and the second current on the sixth MOS transistor M6, the reference current is the product of the difference between the first current I b1 and the second current and m1.

[0048] As shown, Figure 3 The application also discloses a reference current generation method based on the above-mentioned reference current generation circuit, which comprises the following steps:

[0049] The voltage at the first terminal of the first resistor R1 is clamped to the first reference voltage VREF by the first buffer EA1, and a current is generated based on the first reference voltage VREF by the first resistor R1;

[0050] The first current is obtained by the first current mirror 11 based on the mirror ratio of itself to proportionally copy the current on the first resistor R1;

[0051] The voltage at the first terminal of the second resistor R2 is clamped to the first reference voltage VREF by the second buffer EA2, and a current is generated based on the first reference voltage VREF by the second resistor R2;

[0052] The second current is obtained by the second current mirror 21 and the third current mirror 22 based on the mirror ratio of itself to proportionally copy the current on the second resistor R2;

[0053] The difference between the first current and the second current is obtained by the fourth current mirror 30, and the difference is replicated proportionally based on its own mirror ratio to obtain the reference current.

[0054] In one embodiment, the mirror ratio of the first current mirror 11 is set to 1:k1, the mirror ratio of the second current mirror 21 is set to 1:k2, the mirror ratio of the third current mirror 22 is set to 1:m2, and the mirror ratio of the fourth current mirror 30 is set to 1:m1, and k1>k2m2≥1 is satisfied.

[0055] In one embodiment, a second resistor R2 and a first resistor R1 with different widths are selected so that the resistance value of the second resistor R2 changes by n times the resistance value of the first resistor R1 at each process angle.

[0056] As is well known, in integrated circuits, the resistance value of a resistor varies with the process corner and is strongly related to its width. Resistors with the same resistance value but different widths at the tt process corner will have their resistance value change directly depending on the size of their respective widths at the ss and ff process corners. The larger the width, the smaller the resistance value change. Based on this characteristic of resistors, we can obtain the absolute size of the bias current.

[0057] like Figure 2 As shown, the first current I can be seen b1 The current I on the fourth MOSFET M4 b2 These are the currents generated by the first resistor R1 and the second resistor R2, respectively, and their magnitudes are I. b1 =k1*VREF / R1, I b2 =k2*VREF / R2, from which the reference current I can be obtained. b :

[0058] I b =m1*(I b1 -m2*I b2 )=m1* (k1*VREF / R1-k2m2*VREF / R2) (1)

[0059] Now, assuming that the resistance values ​​of the first resistor R1 and the second resistor R2 are equal at process angle tt (i.e., R1 = R2 = R), and that the change in the second resistor R2 (ΔR2 / R) at process angles ss and ff is exactly n times the change in the first resistor R1 (ΔR1 / R), i.e., ΔR2 = nΔR1, then the reference current I at process angle ss or ff is... b It can be represented as:

[0060]

[0061] According to formula (1), I bAs the reference current, k1>k2m2≥1 should be satisfied, preferably k1=2, k2m2=1, and the reference current I b = m1*VREF / R, then according to formula (2) formula can be obtained:

[0062]

[0063] From formula (3) can be obtained If take Then n=2.5, that is The reference current I b is independent of the process angle variation of the resistor, for Different values, according to the relationship formula corresponding adjustment n value, that is, adjust the width of the second resistor R2, can make Figure 2 The circuit shown in the reference current I b is independent of the process angle variation of the resistor.

[0064] The application also discloses a chip comprising the reference current generating circuit.

[0065] The foregoing description of specific exemplary embodiments of the application is intended to be illustrative only and is not intended to limit the application to the precise forms described. Many modifications and variations are possible in light of the above teachings without departing from the spirit and scope of the application. The exemplary embodiments are chosen and described in order to explain the principles of the application and its practical application to thereby enable others skilled in the art to best utilize the application and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the application be defined by the claims and their equivalents.

Claims

1. A reference current generating circuit characterized by comprising: The application relates to a reference current generating circuit. The first current generating unit comprises a first buffer, a first current mirror and a first resistor, the first input end of the first buffer is used for receiving a first reference voltage, the second input end of the first buffer is connected with the first end of the first resistor, the second end of the first resistor is connected with a ground voltage, and the first current mirror is connected with the output end of the first buffer and the first end of the first resistor to proportionally copy a first current based on the current on the first resistor. The second current generating unit comprises a second buffer, a second current mirror, a third current mirror and a second resistor, the first input end of the second buffer is used for receiving the first reference voltage, the second input end of the second buffer is connected with the first end of the second resistor, the second end of the second resistor is connected with the ground voltage, the second current mirror is connected with the output end of the second buffer and the first end of the second resistor, the third current mirror is connected with the second current mirror, and the second current mirror and the third current mirror proportionally copy a second current based on the current on the second resistor. The reference current generating circuit further comprises a fourth current mirror, the fourth current mirror is connected with the first current mirror and the third current mirror to proportionally copy the difference between the first current and the second current and output a reference current irrelevant to the process angle of the resistor. The first current mirror comprises a first MOS tube and a second MOS tube, the control ends of the first MOS tube and the second MOS tube are connected and simultaneously connected with the output end of the first buffer, the first end of the first MOS tube is connected with the first end of the first resistor and the second input end of the first buffer, the second end of the first MOS tube is connected with a power supply voltage, the first end of the second MOS tube is connected with the fourth current mirror, and the second end of the second MOS tube is connected with the power supply voltage.

2. The reference current generating circuit according to claim 1, wherein The second current mirror comprises a third MOS tube and a fourth MOS tube, the control ends of the third MOS tube and the fourth MOS tube are connected and simultaneously connected with the output end of the second buffer, the first end of the third MOS tube is connected with the first end of the second resistor and the second input end of the second buffer, the second end of the third MOS tube is connected with the power supply voltage, the first end of the fourth MOS tube is connected with the third current mirror, and the second end of the fourth MOS tube is connected with the power supply voltage.

3. The reference current generating circuit according to claim 1, wherein The third current mirror comprises a fifth MOS tube and a sixth MOS tube, the control ends of the fifth MOS tube and the sixth MOS tube are connected, the first end of the fifth MOS tube is connected with the second current mirror and the control end of the fifth MOS tube, the second end of the fifth MOS tube is connected with the ground voltage, the first end of the sixth MOS tube is connected with the fourth current mirror, and the second end of the sixth MOS tube is connected with the ground voltage.

4. The reference current generating circuit according to claim 1, wherein ​ 5. The reference current generating circuit of claim 1, wherein The fourth current mirror comprises a seventh MOS transistor and an eighth MOS transistor, a control end of the seventh MOS transistor is connected with a control end of the eighth MOS transistor, a first end of the seventh MOS transistor, the control end of the seventh MOS transistor and the first current mirror and the third current mirror are connected, a second end of the seventh MOS transistor and a second end of the eighth MOS transistor are connected with a ground voltage, and a first end of the eighth MOS transistor is used for outputting a reference current.

6. The reference current generating circuit of claim 1, wherein The mirror ratio of the first current mirror is 1:k1, the mirror ratio of the second current mirror is 1:k2, the mirror ratio of the third current mirror is 1:m2, and the mirror ratio of the fourth current mirror is 1:m1.

7. The reference current generating circuit according to claim 6, wherein The k1>k2m2≥1.

8. A reference current generating method characterized by comprising: The method comprises the following steps of: clamping the voltage of the first end of the first resistor at a first reference voltage through a first buffer, and generating a current based on the first reference voltage through the first resistor; proportionally copying the current on the first resistor based on the mirror ratio of the first current mirror to obtain the first current; clamping the voltage of the first end of the second resistor at the first reference voltage through a second buffer, and generating a current based on the first reference voltage through the second resistor; proportionally copying the current on the second resistor based on the mirror ratio of the second current mirror and the third current mirror to obtain the second current; obtaining the difference between the first current and the second current through the fourth current mirror, and proportionally copying the difference based on the mirror ratio of the fourth current mirror to obtain the reference current.

9. The reference current generating method of claim 8, wherein, The mirror ratio of the first current mirror is set to 1:k1, the mirror ratio of the second current mirror is set to 1:k2, the mirror ratio of the third current mirror is set to 1:m2, and the mirror ratio of the fourth current mirror is set to 1:m1, and k1>k2m2≥1.

10. A chip, characterized by The reference current generation circuit comprises the reference current generation circuit according to any one of claims 1 to 7. The reference current generation circuit comprises the reference current generation circuit according to any one of claims 1 to 7.

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