Reference current source circuit with second order temperature compensation based on triode beta parameter
By using second-order temperature compensation technology based on the transistor's β parameter, a stable reference current source is generated, which solves the problem that traditional first-order temperature compensation cannot reduce the current temperature coefficient, improves the accuracy of the digital-to-analog converter, reduces power consumption, and simplifies circuit design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING MICROELECTRONICS TECH INST
- Filing Date
- 2023-07-14
- Publication Date
- 2026-06-02
AI Technical Summary
The first-order temperature compensation method used in traditional bandgap reference circuits cannot effectively reduce the temperature coefficient of the current, resulting in increased circuit power consumption and area, which limits the application range of digital-to-analog converters.
A second-order temperature compensation technique based on the transistor's β parameter is adopted. By combining the positive temperature coefficient current generation circuit, the negative temperature coefficient current generation circuit, and the first-order temperature compensation synthesis circuit with the exponential characteristics of the transistor's β parameter, a stable reference current source is generated.
It achieves a temperature coefficient of reference current close to 0, improves the conversion accuracy of digital-to-analog converters, reduces chip area and power consumption, simplifies circuit design complexity, and is suitable for high-precision applications.
Smart Images
Figure CN117111675B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of digital-to-analog converter technology, and specifically relates to a reference current source circuit based on the β parameter of a transistor for second-order temperature compensation. Background Technology
[0002] In the fields of wireless communication and radar detection, the conversion accuracy of digital-to-analog converters is particularly important. A stable reference current has become a major factor restricting the conversion accuracy of digital-to-analog converters, and the design complexity of high-precision digital-to-analog converters is increasing.
[0003] In some special application scenarios, digital-to-analog converters require a reference current with lower temperature drift to provide output amplifier bias in order to cope with more complex temperature environments and application requirements for higher precision and higher reliability. This makes second-order compensation of the reference current necessary.
[0004] Traditional bandgap reference circuits often employ only first-order temperature compensation, which simply adds the positive and negative temperature coefficient currents, failing to reduce the current's temperature coefficient further. Increased circuit size leads to increased chip power consumption and area, consequently raising design costs. This increased power consumption severely limits the application range of digital-to-analog converter chips. Summary of the Invention
[0005] To address the aforementioned problems in the prior art, namely that existing bandgap reference circuits only employ a simple first-order temperature compensation method using positive and negative temperature coefficient currents, resulting in insufficient temperature coefficients of the current and increased power consumption and area of the circuit, this invention provides a reference current source circuit based on the β parameters of a transistor for second-order temperature compensation. The reference current source circuit includes a positive temperature coefficient current generation circuit, a negative temperature coefficient current generation circuit, and a first-order temperature compensation synthesis circuit.
[0006] The positive temperature coefficient current generating circuit is connected to the first Ip input terminal of the negative temperature coefficient current generating circuit and the second Ip input terminal of the first-order temperature compensation synthesis circuit through the Ip output terminal; it is also connected to the U1 input terminal of the negative temperature coefficient current generating circuit through the U1 output terminal; the U1 output terminal is the second common node G2 where the base of PNP transistor B1, the base of transistor B2, the drain of M5 and the gate of M5 converge.
[0007] The negative temperature coefficient current generating circuit includes a first Ip input terminal, a U1 input terminal, an In output terminal, and a U2 output terminal; the In output terminal is connected to the In input terminal of the first-order temperature compensation synthesis circuit, and the U2 output terminal is connected to the U2 input terminal of the first-order temperature compensation synthesis circuit.
[0008] The first-order temperature compensation synthesis circuit includes a second Ip input terminal, an In input terminal, a U2 input terminal, and an I output terminal.
[0009] In some preferred embodiments, the current source circuit operates as follows:
[0010] The positive temperature coefficient current generating circuit generates a positive temperature coefficient current Ip and a first bias voltage U1.
[0011] The negative temperature coefficient current generation circuit generates a negative temperature coefficient current In and a second bias voltage U2 based on the first bias voltage U1 and through second-order temperature compensation of the β parameter.
[0012] The first-order temperature compensation synthesis circuit generates a stable current I based on the positive temperature coefficient current Ip, the negative temperature coefficient current In, and the second bias voltage U2, thus forming a current source.
[0013] In some preferred embodiments, the positive temperature coefficient current generating circuit has the following specific circuit structure:
[0014] Metal-oxide-semiconductor (MOS) transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, and M11, PNP transistors B1 and B2, resistors R1 and R2, and capacitors C1 and C2; among which, M1, M2, M3, and M4 are P-type MOS transistors, and M5, M6, M7, M8, M9, M10, and M11 are N-type MOS transistors.
[0015] The connection structure of the positive temperature coefficient current generation circuit is as follows: the gates of M1, M2, M3, and M4 are connected to the first common node G1, which is connected to the drain of M11; the source of M1 is connected to the power supply voltage VDD, the source of M2 is connected to the power supply voltage VDD, the drain of M1 is connected to the source of M3, and the source of M2 is connected to the source of M4; the drain of M3 is simultaneously connected to the gate of M10 and, through resistor R1, to the emitter of B1; the drain of M4 is simultaneously connected to the gate of M11 and the emitter of transistor B2; the collector of B1 is connected to the power supply ground, and the collector of B2 is connected to the power supply ground; the bases of B1 and B2 are connected to the second common node, and the drain and gate of M5 are connected to the second common node G2; M The source of M5 is connected to the power supply ground; the source of M6 and the source of M7 are connected to the power supply voltage VDD; the gates of M6, M7, M8, M8, and M9 are connected to the third common node G3; the drain of M6 is connected to the source of M8, and the drain of M7 is connected to the source of M9. The intermediate point is designated as the fourth common node G4; the drain of M8 is also connected to the drain of M10; the drain of M9 is connected to the third common node G3 through capacitor C1, and the drain of M9 is also connected to the drain of M11; the fourth common node G4 is connected to the gate of M11 through capacitor C2; the sources of M10 and M11 are connected to the fifth common node G5; the fifth common node G5 is connected to the power supply ground through resistor R2.
[0016] In the positive temperature coefficient current generation circuit, the second common node G2 is designated as the output terminal of U1, and the first common node G1 is designated as the output terminal of Ip. The output terminal of U1 is connected to the input terminal of U1 in the negative temperature coefficient current generation circuit, and the output terminal of Ip is connected to the first input terminal of the negative temperature coefficient current generation circuit and the second input terminal of the first-order temperature compensation synthesis branch.
[0017] In some preferred embodiments, the negative temperature coefficient current generating circuit specifically includes:
[0018] Metal-oxide-semiconductor transistors M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, and M22, and PNP transistor B3, and resistor R3; among which M12, M13, M14, M15, M19, and M20 are PMOS transistors, and M16, M17, M18, M21, and M22 are NMOS transistors;
[0019] The connection structure of the negative temperature coefficient current generation circuit is as follows: the first Ip input terminal is simultaneously connected to the gate of M12 and the gate of M14; the source of M12 is connected to the power supply voltage VDD, and the drain of M12 is connected to the source of M14; the drain of M14 is connected to the sixth common node G6; the source of M13 is connected to the power supply voltage VDD, the gate of M13 is connected to the seventh common node G7, and the drain of M13 is connected to the source of M15; the gate of M15 is connected to the sixth common node G6; the sixth common node G6 is connected to the eighth common node G8 through resistor R3; the eighth common node G8 is simultaneously connected to the drain of M16 and M14. The drain of M17, the gate of M17, the gate of M18, the gate of M21, the gate of M22, and the base of B3 are connected; the gate of M16 is connected to the input terminal of U1, and the source of M16 is connected to the power supply ground; the source of M17 is connected to the drain of M18; the source of M18 is connected to the power supply ground; the collector of B3 is connected to the power supply ground; the seventh common node G7 is also connected to the gate of M19, the gate of M20, and the drain of M20; the source of M19 is connected to the power supply voltage VDD, and the drain of M19 is connected to the source of M20; the drain of M20 is connected to the source of M21; the drain of M21 is connected to the source of M22; the drain of M22 is connected to the power supply ground;
[0020] In the negative temperature coefficient current generation circuit, the sixth common node G6 is designated as the output terminal of U2, and is connected to the input terminal of the first-order temperature compensation synthesis branch through the output terminal of U2; the seventh common node G7 is designated as the output terminal of In, and is connected to the input terminal of the first-order temperature compensation synthesis branch through the output terminal of In.
[0021] In some preferred embodiments, the first-order temperature-compensated synthesis branch specifically includes:
[0022] Metal-oxide-semiconductor transistors M23, M24, M25, M26, M27, M28, M29, M30, M31, M32, M33, and M34, of which M23, M24, M27, M28, M29, M30, M33, and M34 are PMOS transistors, and M25, M26, M31, and M32 are NMOS transistors;
[0023] The circuit structure of the first-order temperature-compensated synthesis branch is as follows: the second Ip input terminal is simultaneously connected to the gates of M23 and M24; the source of M23 is connected to the power supply voltage VDD, and the drain of M23 is connected to the source of M24; the drain of M24 is connected to the ninth common node G9; the ninth common node G9 is simultaneously connected to the drain of M25, the gate of M25, the gate of M26, and the gate of M32; the source of M25 is connected to the drain of M26; the source of M26 is connected to the power supply ground; the source of M32 is connected to the power supply ground; the source of M31 is connected to the drain of M32, and the gate of M31 is connected to the U2 input terminal. The drain of M21 is connected to the tenth common node G10; the tenth common node G10 is simultaneously connected to the drain of M29, the drain of M30, the gate of M30, the gate of M28, the gate of M33, and the gate of M34; the source of M27 is connected to the power supply voltage VDD, the drain of M27 is connected to the source of M29, and the gates of M27 and M29 are simultaneously connected to the In input terminal; the source of M28 is connected to the power supply voltage VDD, and the drain of M28 is connected to the source of M30; the source of M33 is connected to the power supply voltage VDD, and the drain of M33 is connected to the source of M34; the drain of M34 is connected to the I output terminal.
[0024] The beneficial effects of this invention are:
[0025] (1) The present invention performs second-order temperature compensation by using the first bias voltage U1 generated based on the transistor β parameter in the positive temperature coefficient current generation circuit, and combined with the second bias voltage U2 in the negative temperature coefficient current generation circuit, thereby generating a stable current I and obtaining a stable and reliable current source circuit.
[0026] (2) The reference current source circuit of the present invention uses the transistor β parameter for exponential second-order temperature compensation. It utilizes the exponential characteristic of the transistor β parameter with respect to temperature to perform second-order temperature compensation on the current, so that the temperature coefficient of the reference current is close to 0, which improves the stability of the reference current and thus improves the conversion accuracy of the digital-to-analog converter, making it more suitable for high-precision application scenarios; at the same time, it eliminates the influence of process parameter fluctuations during chip manufacturing.
[0027] (3) The reference current source circuit of the present invention, which uses the β parameter of the transistor for exponential second-order temperature compensation, can realize the second-order compensation technology by using some transistors of the positive temperature coefficient current generation circuit and some transistors of the negative temperature coefficient current generation circuit. This simplifies the design complexity of the circuit, makes the circuit more stable, and reduces the chip area.
[0028] (4) The reference current source circuit of the present invention uses the transistor β parameter for exponential second-order temperature compensation. The first-order temperature compensation synthesis circuit uses low power consumption technology to limit the reference current to the μA level, which greatly reduces the power consumption of the entire reference current source circuit and digital-to-analog converter.
[0029] (5) The reference current source circuit of the present invention can stably output bias current within a specific operating voltage and temperature range. It is suitable for the output operational amplifier of digital-to-analog converter, which significantly improves the bias accuracy and stability of the output operational amplifier, thereby improving the conversion accuracy of digital-to-analog converter, greatly simplifying the design complexity of digital-to-analog converter, and reducing the area and power consumption of digital-to-analog converter. Attached Figure Description
[0030] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0031] Figure 1 This is a circuit connection diagram of the positive temperature coefficient current generation circuit in an embodiment of the present invention;
[0032] Figure 2 This is a circuit connection diagram of the negative temperature coefficient current generation circuit in an embodiment of the present invention;
[0033] Figure 3 This is a circuit connection diagram of the first-order temperature compensation synthesis circuit in an embodiment of the present invention;
[0034] Figure 4 This is a schematic diagram of the working principle of the reference current source circuit based on the β parameter of the transistor for second-order temperature compensation in an embodiment of the present invention. Detailed Implementation
[0035] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.
[0036] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0037] To more clearly explain the reference current source circuit of the present invention based on the second-order temperature compensation of the transistor β parameter, the following will be combined with... Figures 1 to 3 The circuit elements in the embodiments of the present invention will be described in detail.
[0038] The reference current source circuit for second-order temperature compensation based on the transistor's β parameter, as described in the first embodiment of the present invention, includes a positive temperature coefficient current generation circuit, a negative temperature coefficient current generation circuit, and a first-order temperature compensation synthesis circuit; the circuit components are described in detail below:
[0039] The positive temperature coefficient current generating circuit is connected to the first Ip input terminal of the negative temperature coefficient current generating circuit and the second Ip input terminal of the first-order temperature compensation synthesis circuit through the Ip output terminal; it is also connected to the U1 input terminal of the negative temperature coefficient current generating circuit through the U1 output terminal; the U1 output terminal is the second common node G2 where the base of PNP transistor B1, the base of transistor B2, the drain of M5 and the gate of M5 converge.
[0040] Positive temperature coefficient current generation circuit, such as Figure 1 As shown, its specific circuit structure includes:
[0041] Metal-oxide-semiconductor transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, and M11, and PNP transistors B1 and B2, and resistors R1 and R2, and capacitors C1 and C2; among which M1, M2, M3, and M4 are P-type metal-oxide-semiconductor transistors, and M5, M6, M7, M8, M9, M10, and M11 are N-type metal-oxide-semiconductor transistors;
[0042] The connection structure of the positive temperature coefficient current generation circuit is as follows: the gates of M1, M2, M3, and M4 are connected to the first common node G1, which is connected to the drain of M11; the source of M1 is connected to the power supply voltage VDD, the source of M2 is connected to the power supply voltage VDD, the drain of M1 is connected to the source of M3, and the source of M2 is connected to the source of M4; the drain of M3 is simultaneously connected to the gate of M10 and, through resistor R1, to the emitter of B1; the drain of M4 is simultaneously connected to the gate of M11 and the emitter of transistor B2; the collector of B1 is connected to the power supply ground, and the collector of B2 is connected to the power supply ground; the bases of B1 and B2 are connected to the second common node, and the drain and gate of M5 are connected to the second common node G2; M The source of M5 is connected to the power supply ground; the source of M6 and the source of M7 are connected to the power supply voltage VDD; the gates of M6, M7, M8, M8, and M9 are connected to the third common node G3; the drain of M6 is connected to the source of M8, and the drain of M7 is connected to the source of M9. The intermediate point is designated as the fourth common node G4; the drain of M8 is also connected to the drain of M10; the drain of M9 is connected to the third common node G3 through capacitor C1, and the drain of M9 is also connected to the drain of M11; the fourth common node G4 is connected to the gate of M11 through capacitor C2; the sources of M10 and M11 are connected to the fifth common node G5; the fifth common node G5 is connected to the power supply ground through resistor R2.
[0043] In the positive temperature coefficient current generation circuit, the second common node G2 is designated as the output terminal U1, and the first common node G1 is designated as the output terminal Ip. The output terminal U1 is connected to the input terminal U1 in the negative temperature coefficient current generation circuit, and the output terminal Ip is connected to the first input terminal Ip of the negative temperature coefficient current generation circuit and the second input terminal Ip in the first-order temperature compensation synthesis branch. The output terminal Ip outputs the positive temperature coefficient current Ip.
[0044] The negative temperature coefficient current generating circuit, such as Figure 2 As shown, it includes a first Ip input terminal, a U1 input terminal, an In output terminal, and a U2 output terminal; the In output terminal is connected to the In input terminal of the first-order temperature compensation synthesis circuit, and the U2 output terminal is connected to the U2 input terminal of the first-order temperature compensation synthesis circuit.
[0045] The negative temperature coefficient current generating circuit specifically includes:
[0046] Metal-oxide-semiconductor transistors M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, and M22, and PNP transistor B3, and resistor R3; among which M12, M13, M14, M15, M19, and M20 are PMOS transistors, and M16, M17, M18, M21, and M22 are NMOS transistors;
[0047] The connection structure of the negative temperature coefficient current generation circuit is as follows: the first Ip input terminal is simultaneously connected to the gate of M12 and the gate of M14; the source of M12 is connected to the power supply voltage VDD, and the drain of M12 is connected to the source of M14; the drain of M14 is connected to the sixth common node G6; the source of M13 is connected to the power supply voltage VDD, the gate of M13 is connected to the seventh common node G7, and the drain of M13 is connected to the source of M15; the gate of M15 is connected to the sixth common node G6; the sixth common node G6 is connected to the eighth common node G8 through resistor R3; the eighth common node G8 is simultaneously connected to the drain of M16 and M14. The drain of M17, the gate of M17, the gate of M18, the gate of M21, the gate of M22, and the base of B3 are connected; the gate of M16 is connected to the input terminal of U1, and the source of M16 is connected to the power supply ground; the source of M17 is connected to the drain of M18; the source of M18 is connected to the power supply ground; the collector of B3 is connected to the power supply ground; the seventh common node G7 is also connected to the gate of M19, the gate of M20, and the drain of M20; the source of M19 is connected to the power supply voltage VDD, and the drain of M19 is connected to the source of M20; the drain of M20 is connected to the source of M21; the drain of M21 is connected to the source of M22; the drain of M22 is connected to the power supply ground;
[0048] In the negative temperature coefficient current generation circuit, the sixth common node G6 is designated as the output terminal of U2, and is connected to the input terminal of the first-order temperature compensation synthesis branch through the output terminal of U2; the seventh common node G7 is designated as the output terminal of In, and is connected to the input terminal of the first-order temperature compensation synthesis branch through the output terminal of In.
[0049] The first-order temperature compensation synthesis circuit includes a second Ip input terminal, an In input terminal, a U2 input terminal, and an I output terminal.
[0050] The first-order temperature-compensated synthesis branch, such as Figure 3 As shown, it specifically includes:
[0051] Metal-oxide-semiconductor transistors M23, M24, M25, M26, M27, M28, M29, M30, M31, M32, M33, and M34, of which M23, M24, M27, M28, M29, M30, M33, and M34 are PMOS transistors, and M25, M26, M31, and M32 are NMOS transistors;
[0052] The circuit structure of the first-order temperature-compensated synthesis branch is as follows: the second Ip input terminal is simultaneously connected to the gates of M23 and M24; the source of M23 is connected to the power supply voltage VDD, and the drain of M23 is connected to the source of M24; the drain of M24 is connected to the ninth common node G9; the ninth common node G9 is simultaneously connected to the drain of M25, the gate of M25, the gate of M26, and the gate of M32; the source of M25 is connected to the drain of M26; the source of M26 is connected to the power supply ground; the source of M32 is connected to the power supply ground; the source of M31 is connected to the drain of M32, and the gate of M31 is connected to the U2 input terminal. The drain of M21 is connected to the tenth common node G10; the tenth common node G10 is simultaneously connected to the drain of M29, the drain of M30, the gate of M30, the gate of M28, the gate of M33, and the gate of M34; the source of M27 is connected to the power supply voltage VDD, the drain of M27 is connected to the source of M29, and the gates of M27 and M29 are simultaneously connected to the In input terminal; the source of M28 is connected to the power supply voltage VDD, and the drain of M28 is connected to the source of M30; the source of M33 is connected to the power supply voltage VDD, and the drain of M33 is connected to the source of M34; the drain of M34 is connected to the I output terminal.
[0053] The second embodiment of the present invention, as follows: Figure 4 As shown, the working principle of the current source circuit is disclosed as follows:
[0054] The positive temperature coefficient current generating circuit generates a positive temperature coefficient current Ip and a first bias voltage U1.
[0055] The negative temperature coefficient current generation circuit generates a negative temperature coefficient current In and a second bias voltage U2 based on the first bias voltage U1 and through second-order temperature compensation of the β parameter.
[0056] The first-order temperature compensation synthesis circuit generates a stable current I based on the positive temperature coefficient current Ip, the negative temperature coefficient current In, and the second bias voltage U2, thus forming a current source.
[0057] Because the transistor β parameter is used in M5 and M16 to generate the exponential characteristic of temperature, a second-order compensation for the negative temperature coefficient current In is formed, thereby obtaining the near-zero temperature coefficient current I, ensuring the high conversion accuracy of the digital-to-analog converter.
[0058] In the first-order temperature compensation synthesis circuit, the positive temperature coefficient current Ip and the negative temperature coefficient current In are summed. Taking advantage of the approximately complementary nature of the negative temperature coefficient current In and the positive temperature coefficient current Ip, the current I is obtained. The entire circuit constitutes a current source circuit.
[0059] The terms “first”, “second”, etc., are used to distinguish similar objects, not to describe or indicate a specific order or sequence.
[0060] The term "comprising" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent in such process, method, article, or apparatus / device.
[0061] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of the present invention.
Claims
1. A reference current source circuit for second-order temperature compensation based on the β parameter of a transistor, characterized in that, The reference current source circuit includes a positive temperature coefficient current generation circuit, a negative temperature coefficient current generation circuit, and a first-order temperature compensation synthesis circuit. The positive temperature coefficient current generating circuit is connected to the first Ip input terminal of the negative temperature coefficient current generating circuit and the second Ip input terminal of the first-order temperature compensation synthesis circuit through the Ip output terminal; it is also connected to the U1 input terminal of the negative temperature coefficient current generating circuit through the U1 output terminal; the U1 output terminal is the second common node G2 where the base of PNP transistor B1, the base of transistor B2, the drain of N-type metal-oxide-semiconductor transistor M5 and the gate of M5 converge. The negative temperature coefficient current generating circuit includes a first Ip input terminal, a U1 input terminal, an In output terminal, and a U2 output terminal; the In output terminal is connected to the In input terminal of the first-order temperature compensation synthesis circuit, and the U2 output terminal is connected to the U2 input terminal of the first-order temperature compensation synthesis circuit. The first-order temperature compensation synthesis circuit includes a second Ip input terminal, an In input terminal, a U2 input terminal, and an I output terminal; The working principle of the current source circuit is as follows: The positive temperature coefficient current generating circuit generates a positive temperature coefficient current Ip and a first bias voltage U1. The negative temperature coefficient current generation circuit generates a negative temperature coefficient current In and a second bias voltage U2 based on the first bias voltage U1 and through second-order temperature compensation of the β parameter. The first-order temperature compensation synthesis circuit generates a stable current I based on the positive temperature coefficient current Ip, the negative temperature coefficient current In, and the second bias voltage U2, thus forming a current source.
2. The reference current source circuit based on second-order temperature compensation of transistor β parameters according to claim 1, characterized in that, The positive temperature coefficient current generating circuit has the following specific circuit structure: Metal-oxide-semiconductor transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, and M11, and PNP transistors B1 and B2, and resistors R1 and R2, and capacitors C1 and C2; among which M1, M2, M3, and M4 are P-type metal-oxide-semiconductor transistors, and M5, M6, M7, M8, M9, M10, and M11 are N-type metal-oxide-semiconductor transistors; The connection structure of the positive temperature coefficient current generation circuit is as follows: the gates of M1, M2, M3, and M4 are connected to the first common node G1, which is connected to the drain of M11; the source of M1 is connected to the power supply voltage VDD, the source of M2 is connected to the power supply voltage VDD, the drain of M1 is connected to the source of M3, and the source of M2 is connected to the source of M4; the drain of M3 is simultaneously connected to the gate of M10 and, through resistor R1, to the emitter of B1; the drain of M4 is simultaneously connected to the gate of M11 and the emitter of transistor B2; the collector of B1 is connected to the power supply ground, and the collector of B2 is connected to the power supply ground; the bases of B1 and B2 are connected to the second common node, and the drain and gate of M5 are connected to the second common node G2. The source of M5 is connected to power supply ground; the source of M6 is connected to power supply voltage VDD, and the source of M7 is connected to power supply voltage VDD; the gates of M6, M7, M8, M8, and M9 are connected to the third common node G3; the drain of M6 is connected to the source of M8, and the drain of M7 is connected to the source of M9. The intermediate point is designated as the fourth common node G4; the drain of M8 is also connected to the drain of M10; the drain of M9 is connected to the third common node G3 through capacitor C1, and the drain of M9 is also connected to the drain of M11; the fourth common node G4 is connected to the gate of M11 through capacitor C2; the sources of M10 and M11 are connected to the fifth common node G5; the fifth common node G5 is connected to power supply ground through resistor R2. In the positive temperature coefficient current generation circuit, the second common node G2 is designated as the output terminal of U1, and the first common node G1 is designated as the output terminal of Ip. The output terminal of U1 is connected to the input terminal of U1 in the negative temperature coefficient current generation circuit, and the output terminal of Ip is connected to the first input terminal of the negative temperature coefficient current generation circuit and the second input terminal of the first-order temperature compensation synthesis branch.
3. The reference current source circuit for second-order temperature compensation based on transistor β parameters according to claim 1, characterized in that, The negative temperature coefficient current generation circuit specifically includes: metal-oxide-semiconductor transistors M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, and M22, a PNP transistor B3, and a resistor R3; wherein M12, M13, M14, M15, M19, and M20 are PMOS transistors, and M16, M17, M18, M21, and M22 are NMOS transistors; The connection structure of the negative temperature coefficient current generation circuit is as follows: the first Ip input terminal is simultaneously connected to the gate of M12 and the gate of M14; the source of M12 is connected to the power supply voltage VDD, and the drain of M12 is connected to the source of M14; the drain of M14 is connected to the sixth common node G6; the source of M13 is connected to the power supply voltage VDD, the gate of M13 is connected to the seventh common node G7, and the drain of M13 is connected to the source of M15; the gate of M15 is connected to the sixth common node G6; the sixth common node G6 is connected to the eighth common node G8 through resistor R3; the eighth common node G8 is simultaneously connected to the drain of M16 and M14. The drain of M17, the gate of M17, the gate of M18, the gate of M21, the gate of M22, and the base of B3 are connected; the gate of M16 is connected to the input terminal of U1, and the source of M16 is connected to the power supply ground; the source of M17 is connected to the drain of M18; the source of M18 is connected to the power supply ground; the collector of B3 is connected to the power supply ground; the seventh common node G7 is also connected to the gate of M19, the gate of M20, and the drain of M20; the source of M19 is connected to the power supply voltage VDD, and the drain of M19 is connected to the source of M20; the drain of M20 is connected to the source of M21; the drain of M21 is connected to the source of M22; the drain of M22 is connected to the power supply ground; In the negative temperature coefficient current generation circuit, the sixth common node G6 is designated as the output terminal of U2, and is connected to the input terminal of the first-order temperature compensation synthesis branch through the output terminal of U2; the seventh common node G7 is designated as the output terminal of In, and is connected to the input terminal of the first-order temperature compensation synthesis branch through the output terminal of In.
4. The reference current source circuit for second-order temperature compensation based on transistor β parameters according to claim 1, characterized in that, The first-order temperature-compensated synthesis branch specifically includes: Metal-oxide-semiconductor transistors M23, M24, M25, M26, M27, M28, M29, M30, M31, M32, M33, and M34, of which M23, M24, M27, M28, M29, M30, M33, and M34 are PMOS transistors, and M25, M26, M31, and M32 are NMOS transistors; The circuit structure of the first-order temperature-compensated synthesis branch is as follows: the second Ip input terminal is simultaneously connected to the gates of M23 and M24; the source of M23 is connected to the power supply voltage VDD, and the drain of M23 is connected to the source of M24; the drain of M24 is connected to the ninth common node G9; the ninth common node G9 is simultaneously connected to the drain of M25, the gate of M25, the gate of M26, and the gate of M32; the source of M25 is connected to the drain of M26; the source of M26 is connected to the power supply ground; the source of M32 is connected to the power supply ground; the source of M31 is connected to the drain of M32, and the gate of M31 is connected to the U2 input terminal. The drain of M21 is connected to the tenth common node G10; the tenth common node G10 is simultaneously connected to the drain of M29, the drain of M30, the gate of M30, the gate of M28, the gate of M33, and the gate of M34; the source of M27 is connected to the power supply voltage VDD, the drain of M27 is connected to the source of M29, and the gates of M27 and M29 are simultaneously connected to the In input terminal; the source of M28 is connected to the power supply voltage VDD, and the drain of M28 is connected to the source of M30; the source of M33 is connected to the power supply voltage VDD, and the drain of M33 is connected to the source of M34; the drain of M34 is connected to the I output terminal.