Method for realizing signal mask preprocessing based on self-selection RRAM array and application

Abstract

The application discloses a method for realizing signal MASK preprocessing based on a self-selection RRAM array and application, and belongs to the field of novel storage and calculation. The application utilizes the fact that devices in the self-selection RRAM device array are initially in a high resistance state, and after inputting a pulse with a fixed pulse width and amplitude to each row of devices in the array in turn, the devices are switched to a RRAM mode or an IMT mode under the action of the same pulse, threshold conversion voltages corresponding to the two modes are different, the threshold conversion voltage (V set ) in the RRAM mode is greater than the threshold conversion voltage (V th ) in the IMT mode, and thus a random MASK matrix is generated. The application improves the efficiency of input signal processing, and is of great significance to reservoir computing.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of new storage and computing technology, and particularly relates to a method for realizing signal MASK preprocessing based on self-selection RRAM array and application. BACKGROUND

[0002] The rapid development of artificial intelligence and machine learning technology greatly promotes the progress of fields such as finance, engineering, natural language processing, but at the same time, the time series information to be processed also increases rapidly. Static data is largely independent of each other, while time data has considerable correlation between them, and it is extremely important to choose the right analysis tool.

[0003] Reservoir computing is an improved recurrent neural network that can effectively process time series data, while having the advantages of high performance and low power consumption. However, the traditional reservoir of reservoir computing is composed of a large number of randomly interconnected nonlinear nodes, which is not easy to implement and integrate in hardware, and the development of reservoir computing has encountered a bottleneck. These challenges have further promoted the development of reservoir computing, that is, to replace the traditional reservoir with a simplified structure of a single nonlinear node plus a delay feedback loop. Since time delay characteristics exist in many practical systems, nonlinear systems with delay feedback are widely concerned dynamic systems. The input of the delay feedback system is preprocessed and then transmitted to a nonlinear node. This preprocessing is usually called the MASK process. After the input is injected into the nonlinear node, the signal stays in the delay loop for a period of time. Different states of the delay loop are called virtual nodes or neurons of the system. Finally, the instantaneous dynamic response of the node is read out at the output layer, and the response is combined into a weighted sum. In single-node reservoir computing, the input signal is excited to be transmitted to the reservoir composed of nonlinear nodes, and the instantaneous response of the reservoir excited by the input signal helps to decode the time information, which can be effectively analyzed by the subsequent readout layer. The advantage of using such a delay feedback system is that the entire recurrent network system is replaced by a nonlinear node, greatly simplifying the hardware implementation of reservoir computing. The reservoir is composed of virtual nodes, each of which represents a different value to achieve high-dimensional space mapping. The number of virtual nodes is related to the MASK preprocessing process. Therefore, the circuit for constructing a reliable and efficient MASK process plays a crucial role in reservoir computing.

[0004] The CMOS-based MASK processing circuit usually utilizes a circuit structure composed of an amplifier-inverter-multiplexer chain, an analog / digital converter chain, etc., to realize the processing of the input signal in a time-division multiplexing manner, which is generally realized in a manner controlled by a sequence with a certain pulse width plus an input voltage bias. The CMOS-based MASK processing circuit structure is complex, consumes a large amount of hardware cost and power consumption, and at the same time, due to the implementation manner of time-division multiplexing, the efficiency of signal processing is greatly reduced, which weakens the advantage brought by the delay feedback. Therefore, it is of great significance to realize a more high-speed, reliable and simple circuit structure MASK process. SUMMARY

[0005] In view of the problems in the prior art, the present application provides a method and application for realizing signal MASK preprocessing based on a self-selecting RRAM array, which utilizes the non-volatile resistance change characteristic and selection characteristic of the self-selecting RRAM device to realize the generation of a random MASK matrix and complete the preprocessing of the input signal.

[0006] The technical scheme of the present application is as follows:

[0007] A method for realizing signal MASK preprocessing based on a self-selecting RRAM array, comprising the following steps:

[0008] 1) The devices in the array are initially in a high resistance state, and after a fixed pulse width and amplitude pulse is input to each row of the array in turn, the devices are randomly switched to the RRAM mode or the IMT mode under the action of the same pulse, the threshold conversion voltages corresponding to the two modes are different, the threshold conversion voltage (V set ) in the RRAM mode is greater than the threshold conversion voltage (V th ) in the IMT mode. Thus, a random MASK (N x ML) matrix with a MASK length of ML and a parallel reserve pool number of N corresponding to the size of the array can be generated;

[0009] 2) Since the switching probability of the device is related to the applied pulse amplitude, the input can be encoded into pulses with different pulse amplitudes according to the actual application requirements, so as to control the proportion of 0 (or -1) / 1 in the finally generated MASK sequence. Through parallel pulse writing, the devices in the IMT mode are turned on, while the devices in the RRAM mode cannot be turned on and are still in a high resistance state. Each time a row is turned on, after the current signal is processed by the post-processing circuit, the input pulse with a fixed amplitude and width can be converted into a random pulse signal with a length of ML;

[0010] 3) The above step 2) is completed for the input in turn, and the MASK preprocessing of the input signal is completed.

[0011] The application further provides a reserve pool computing system for implementing MASK processing based on a self-selection RRAM array, and a hardware architecture of the system mainly comprises:

[0012] A MASK preprocessing module, which comprises a pre-writing circuit, a row / column selection module, a self-selection RRAM array and a MASK post-processing circuit, is used to complete MASK preprocessing of an input signal, and the specific process is as follows:

[0013] A pulse with a certain pulse width and amplitude is applied to a device in the self-selection RRAM array through the pre-writing circuit, and the device is randomly set to an IMT mode or an RRAM mode after the pulse is applied; then the input pulse signal is applied to the self-selection RRAM array through the row / column selection module, the self-selection RRAM array generates a random MASK matrix, and the processing of the array response signal is completed through the MASK post-processing circuit;

[0014] A parallel reserve pool module, which is composed of a plurality of dynamic memristors, is used to apply the MASK-preprocessed input signal to the dynamic memristors, and the dynamic memristors generate transient dynamic responses as a reserve pool;

[0015] An output module, which comprises a weighted sum calculation circuit and an output signal processing circuit, is used to complete the specific process as follows: the transient dynamic responses of the dynamic memristors are transmitted to the weighted sum calculation circuit to realize a last full connection network, and the identification or classification of a time sequence signal is completed according to the final output result of the output signal processing circuit.

[0016] The application uses the probabilistic switching of the self-selection RRAM device to generate a random MASK matrix, that is, the self-selection RRAM device used is randomly set to an IMT mode or an RRAM mode under a pulse stimulation, the threshold conversion voltages corresponding to the two modes are different, the threshold conversion voltage (V set ) in the RRAM mode is greater than the threshold conversion voltage (V th ) in the IMT mode. Therefore, the MASK matrix can be randomly generated by using this characteristic, the input signal subjected to the MASK transformation can be input into a single dynamic memristor to obtain a transient dynamic response through the subsequent circuit signal processing, and then the readout result is transmitted to a next layer of output network to complete the classification or identification of an image or audio.

[0017] The application selects a memristor array structure with cross-over stacked integration, the memristor in the array has a reconfigurable resistive switching mode characteristic, and the memristor device adopts a two-terminal device structure or a three-terminal field effect transistor structure with a resistive switching layer and a phase change layer stacked. The device in the array is in a high resistance in an initial state, which corresponds to the RRAM mode. After a forward pulse is applied to the device, the device is randomly switched to the IMT mode or still stays in the RRAM mode. The threshold voltage V thThreshold voltage V less than the threshold voltage in RRAM mode set The MASK matrix is randomly generated in the self-selecting RRAM array by using this characteristic, and the MASK processing of the input signal can be completed according to the above operation steps.

[0018] The resistive switching layer and the phase change layer of the device in the memristor array of the application are composed of two materials, which have storage characteristics and selection characteristics, respectively. When the storage characteristic material is in a high resistance state, the self-selecting memristor exhibits typical non-volatile resistive switching characteristics, mainly due to the resistive switching of the storage characteristic material; when the storage characteristic material is in a low resistance state, the self-selecting memristor exhibits typical threshold switching characteristics, mainly due to the resistive switching of the selection material. The device with storage characteristics and selection characteristics is included in the scope of the self-selecting RRAM described in the patent.

[0019] The resistive switching layer can use metal oxides with resistive switching characteristics, such as HfO2, TaO x , etc.; the phase change layer can use materials with threshold switching characteristics such as VO x , NbO x , etc., such as IMT, MIEC, OTS, etc. Or use 1T1R or 1S1R structure memristor array structure, by adjusting the gate voltage of the transistor or the on / off of the selection device to control the on / off of the devices in the array, to generate a random MASK matrix.

[0020] Compared with the traditional CMOS-based MASK processing circuit, the application uses self-selecting RRAM devices to generate a random MASK matrix, has the advantages of simple circuit structure, can directly generate a random MASK matrix in the array, improves the efficiency of input signal processing, which is of great significance for reservoir computing. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 The device structure of the self-selecting RRAM used in the application is shown in the figure. Figure 1 (a) is a self-selecting RRAM device; Figure 1 (b) is Figure 1 (a) material description.

[0022] Figure 2 The schematic diagram of generating a random MASK matrix with a MASK length of ML and a parallel reservoir number of N based on a self-selecting RRAM array is shown.

[0023] Figure 3 The schematic diagram of completing the MASK preprocessing of the input signal based on the self-selecting RRAM array is shown.

[0024] Figure 4A schematic diagram of a hardware architecture of a reserve pool computing system based on a self-selecting RRAM array for implementing a MASK processing. DETAILED DESCRIPTION

[0025] The application is further described below by examples. It should be noted that the purpose of publishing the examples is to help further understand the application, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit of the application and the appended claims. Therefore, the application should not be limited to the disclosed examples, and the scope of the application claimed is defined by the scope of the claims.

[0026] The specific embodiments of the application select a cross-interleaved stacked integrated memristor array structure, and the medium layer of the device in the array is composed of two materials, such as Figure 1 As shown, the two materials have selection characteristics and storage characteristics, respectively, and have reconfigurable resistive switching mode characteristics. When the storage characteristic material is in a high resistance state, the self-selecting memristor exhibits typical non-volatile resistive switching characteristics, mainly due to the resistive switching of the storage characteristic material; when the storage characteristic material is in a low resistance state, the self-selecting memristor exhibits typical threshold switching characteristics, mainly due to the phase change of the selection material.

[0027] As shown in Figure 2 The application provides a method for implementing signal MASK preprocessing based on a self-selecting RRAM array, and the steps include:

[0028] 1) The device in the array is initially in a high resistance state, and after a fixed pulse width and amplitude pulse is input to each row of the array in turn, the device is randomly switched to an RRAM mode or an IMT mode under the action of the same pulse, and the threshold switching voltages corresponding to the two modes are different, the threshold switching voltage (V set ) in the RRAM mode is greater than the threshold switching voltage (V th ) in the IMT mode. Thus, a random MASK (N x ML) matrix with a MASK length of ML corresponding to the size of the array and a parallel reserve pool number of N can be generated;

[0029] 2) Since the switching probability of the device is related to the applied pulse amplitude, the input can be encoded as a pulse with different pulse amplitudes according to the actual application needs, so as to control the proportion of 0 (or -1) / 1 in the finally generated MASK sequence.

[0030] As shown in Figure 3As shown, after generating a random MASK matrix in the self-selecting RRAM array, the device in the IMT mode is turned on by parallel pulse writing, while the device in the non-volatile resistive mode cannot be turned on and remains in the high resistance state. Each time a row is turned on, the input pulse with a fixed amplitude and width can be converted into a random pulse signal with a length of ML after the current signal is processed by the post-processing circuit. The input sequence is input into the array in sequence according to the above steps, and the MASK preprocessing of the input signal is completed.

[0031] Based on the above principle, the application provides a reservoir computing system for implementing MASK processing based on a self-selecting RRAM array, as shown in Figure 4 As shown, the hardware architecture mainly includes:

[0032] The MASK preprocessing module is based on a self-selecting RRAM array and completes the MASK preprocessing of the input signal. The module includes a pre-writing circuit, a row / column selection module, a self-selecting RRAM array and a MASK post-processing circuit, and the specific processing process is as follows:

[0033] A pulse with a certain pulse width and amplitude is applied to the device in the self-selecting RRAM array through the pre-writing circuit, and the device is randomly set to the IMT mode or the RRAM mode after the pulse is applied. Then the input pulse signal is applied to the self-selecting RRAM array through the row / column selection module, the self-selecting RRAM array generates a random MASK matrix, and the processing of the array response signal is completed through the MASK post-processing circuit.

[0034] The parallel reservoir module is composed of a plurality of dynamic memristors. The input signal preprocessed by the MASK is applied to the dynamic memristor, and the dynamic memristor generates a transient dynamic response as a reservoir;

[0035] The output module includes a weighted sum calculation circuit and an output signal processing circuit, and the specific process is as follows: the transient dynamic response of the dynamic memristor is transmitted to the weighted sum calculation circuit through the post-processing circuit, the last full connection network is realized, and the identification or classification of the time sequence signal is finally output according to the output signal processing circuit.

[0036] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the application, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the application and the appended claims. Therefore, the application should not be limited to the disclosed content of the embodiments, and the scope of protection claimed by the application is subject to the scope defined by the claims.

Claims

1. A method for signal mask preprocessing based on a self-selected RRAM array, comprising the following steps: 1) The devices in the array are initially in a high-impedance state. After inputting pulses with fixed pulse width and amplitude to each row of the array, the devices randomly switch to RRAM mode or IMT mode under the action of the same pulse. The threshold switching voltages corresponding to the two modes are different. The threshold switching voltage in RRAM mode is greater than that in IMT mode. A random MASK matrix with a MASK length of ML and a number of parallel storage pools of N is generated, corresponding to the array size. 2) The input is encoded into pulses of different amplitudes according to the actual application requirements, which controls the proportion of 0 / 1 or -1 / 1 in the final generated MASK sequence. Through parallel pulse writing, devices in IMT mode are turned on, while devices in RRAM mode cannot be turned on and remain in a high impedance state. Each time one line is turned on, after the current signal is processed by the post-processing circuit, the input pulse with fixed amplitude and width is converted into a random pulse signal of length ML. 3) Perform steps 1) and 2) above sequentially on the input to complete the MASK preprocessing of the input signal.

2. The method for signal mask preprocessing based on a self-selected RRAM array as described in claim 1, characterized in that, The self-select RRAM array uses a dielectric layer composed of two materials, which have selection characteristics and storage characteristics respectively. When the storage material is in a high-resistivity state, the self-select RRAM device exhibits typical non-volatile resistive switching characteristics. When the storage material is in a low-resistivity state, self-selection RRAM devices exhibit typical threshold switching characteristics.

3. The method for signal mask preprocessing based on a self-selected RRAM array as described in claim 1, characterized in that, The self-selectable RRAM array is a memristor array with cross-shaped stacking integration. The memristors in the array adopt a two-terminal device structure with a resistive switching layer and a phase change layer superimposed or a three-terminal field-effect transistor structure. It has reconfigurable resistive switching mode characteristics, so that the device can be randomly set to IMT mode or RRAM mode after a pulse is applied.

4. The method for signal mask preprocessing based on a self-selected RRAM array as described in claim 3, characterized in that, The resistive switching layer is made of a metal oxide with resistive switching properties; the phase change layer is made of a material with threshold switching properties.

5. A reservoir computing system for implementing mask processing based on a self-selecting RRAM array, characterized in that, The hardware architecture includes: The MASK preprocessing module performs MASK preprocessing on the input signal using the method described in claim 1. This module includes a pre-write circuit, a row / column selection module, a self-selecting RRAM array, and a MASK post-processing circuit to complete the MASK preprocessing of the input signal. The specific process is as follows: A pulse with a certain pulse width and amplitude is applied to the devices in the self-selected RRAM array through a pre-write circuit. After the pulse is applied, the devices are randomly set to IMT mode or RRAM mode. Then, the input pulse signal is applied to the self-selected RRAM array through the row / column selection module. The self-selected RRAM array generates a random MASK matrix. The array response signal is processed by the MASK post-processing circuit. Parallel memory pool module: This module consists of multiple dynamic memristors. The input signal, which has been preprocessed by the MASK, is applied to the dynamic memristors, and the dynamic memristors act as a memory pool to generate an instantaneous dynamic response. Output module: This module includes a weighted sum calculation circuit and an output signal processing circuit. The specific process is as follows: The instantaneous dynamic response of the dynamic memristor is transmitted to the weighted sum calculation circuit to realize the last layer of fully connected network. The timing signal is identified or classified according to the final output result of the output signal processing circuit.

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