A display panel, a planarization layer thickness detection method, and a display

Abstract

This application provides a display panel, a planarization layer thickness detection method, and a display. The display panel includes a display area and a non-display area. The non-display area includes a first edge area and a second edge area, where the second edge area is the outer edge area of ​​the display panel, and the first edge area is located between the display area and the second edge area. The first edge area and the second edge area are separated by a dam structure. The first edge area includes multiple ground lines, which are disposed on the planarization layer of the first edge area on the side away from the substrate. The planarization layer of the first edge area is located on the cathode layer of the first edge area on the side away from the substrate. By disposing of multiple ground lines on the planarization layer, the thickness of the planarization layer is detected using the equivalent capacitance between the ground lines and the cathode layer.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a planarization layer thickness detection method, and a display. Background Technology

[0002] The planarization layer of the display panel (prepared by IJP, inkjet printing technology) has an edge top near the dam, and the height of the protrusion shows a gradual trend, resulting in unevenness in the planarization layer. Summary of the Invention

[0003] The purpose of this application is to provide a display panel, a planarization layer thickness detection method, and a display, so as to realize the detection of planarization layer thickness. The specific technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide a display panel, the display panel comprising:

[0005] The display area and the non-display area; the non-display area includes a first edge area and a second edge area, the second edge area being the outer edge area of ​​the display panel, and the first edge area being located between the display area and the second edge area; the first edge area and the second edge area are separated by a dam structure;

[0006] The first edge region includes multiple ground lines, which are disposed on the side of the planarization layer of the first edge region away from the substrate. The planarization layer of the first edge region is located on the side of the cathode layer of the first edge region away from the substrate.

[0007] In one possible implementation, the multiple ground lines include multiple row-direction ground lines and multiple column-direction ground lines; the row-direction ground lines extend along the row direction of the display panel, and the column-direction ground lines extend along the column direction of the display panel.

[0008] In one possible implementation, adjacent row-direction ground lines are parallel to each other, and adjacent column-direction ground lines are parallel to each other.

[0009] In one possible implementation, the ground wire is located on the side of the first edge region closer to the display area.

[0010] In one possible implementation, the first edge region is prepared by inkjet printing.

[0011] In a second aspect, embodiments of this application provide a planarization layer thickness detection method, applied to any of the display panels described in the first aspect above, the method comprising:

[0012] Obtain the equivalent capacitance value between each ground wire and the cathode layer;

[0013] Based on the equivalent capacitance value corresponding to each ground wire, the correspondence between the predetermined thickness value and the equivalent capacitance value is queried to determine the thickness value of the flat layer at the location of each ground wire.

[0014] In one possible implementation, obtaining the equivalent capacitance value between each of the ground wires and the cathode layer includes:

[0015] The equivalent capacitance between each ground wire and the cathode layer is detected by the capacitance detection module to obtain the equivalent capacitance value between each ground wire and the cathode layer.

[0016] In one possible implementation, the (i+1)th, ith, and (i-1)th ground lines among the plurality of ground lines are arranged sequentially along a direction away from the display area;

[0017] The method further includes:

[0018] If the (i+1)th thickness value is the same as the ith thickness value and the ith thickness value is less than the (i-1)th thickness value, then the structure from the flat layer at the location of the (i+1)th ground wire to the flat layer at the location of the ith ground wire is determined to be a flat structure, and the structure from the flat layer at the location of the ith ground wire to the flat layer at the location of the (i-1)th ground wire is determined to be a raised structure; wherein, the (i+1)th thickness value is the thickness value of the flat layer at the location of the (i+1)th ground wire, the ith thickness value is the thickness value of the flat layer at the location of the ith ground wire, and the (i-1)th thickness value is the thickness value of the flat layer at the location of the (i-1)th ground wire; and i is greater than or equal to 2.

[0019] In one possible implementation, the method further includes:

[0020] If the thickness value of the (i-1)th layer is the same as the thickness value of the ith layer, and the thickness value of the ith layer is greater than the thickness value of the (i+1)th layer, then the flat layer from the location of the (i-1)th ground wire to the location of the ith ground wire is determined to be a raised structure, and the flat layer at the location of the (i+1)th ground wire is determined to be a flat structure.

[0021] In one possible implementation, the method further includes:

[0022] If the thickness value of the i-th line is greater than the thickness value of the (i+1)-th line and the thickness value of the (i+1)-th line is greater than the thickness value of the (i-1)-th line, then the flat layer at the location of the (i+1)-th line is determined to be a flat structure, the flat layer at the location of the i-th line is determined to be a raised structure, and the flat layer at the location of the (i-1)-th line is determined to be a sunken structure.

[0023] Thirdly, embodiments of this application provide a display, the display including any of the display panels described in the first aspect above.

[0024] Beneficial effects of the embodiments in this application:

[0025] This application provides a display panel, a planarization layer thickness detection method, and a display. The display panel includes a display area and a non-display area. The non-display area includes a first edge area and a second edge area, where the second edge area is the outer edge area of ​​the display panel, and the first edge area is located between the display area and the second edge area. The first edge area and the second edge area are separated by a dam structure. The first edge area includes multiple ground lines, which are disposed on the planarization layer of the first edge area on the side away from the substrate. The planarization layer of the first edge area is located on the cathode layer of the first edge area on the side away from the substrate. By disposing of multiple ground lines on the planarization layer, the thickness of the planarization layer is detected using the equivalent capacitance between the ground lines and the cathode layer.

[0026] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0028] Figure 1 This is a schematic diagram of a first structure of a display panel provided in an embodiment of this application;

[0029] Figure 2 This is a schematic diagram of a second structure of the display panel provided in an embodiment of this application;

[0030] Figure 3 This is a schematic diagram of a third structure of the display panel provided in an embodiment of this application;

[0031] Figure 4 A schematic diagram of the first process of the planarization layer thickness detection method provided in the embodiments of this application;

[0032] Figure 5 This is a schematic diagram of a second process for the planarization layer thickness detection method provided in the embodiments of this application;

[0033] Figure 6a This is a schematic diagram of a fourth structure of the display panel provided in an embodiment of this application;

[0034] Figure 6b for Figure 6a A schematic diagram of the corresponding ground-capacitance curve;

[0035] Figure 7a A fifth structural schematic diagram of the display panel provided in an embodiment of this application;

[0036] Figure 7b for Figure 7a A schematic diagram of the corresponding ground-capacitance curve;

[0037] Figure 8a A sixth structural schematic diagram of the display panel provided in an embodiment of this application;

[0038] Figure 8b for Figure 8a A schematic diagram of the corresponding ground-capacitance curve;

[0039] Figure 9 This is a schematic diagram of a display provided in an embodiment of this application. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0041] First, a brief explanation of the problems existing in the relevant technology. The planarization layer of the display panel (prepared by IJP, Ink Jet Printing) has an edge top near the Dam (dam), and the height of the protrusion shows a gradual trend and extends towards the display area, which may cause unevenness at the edge of the display area and affect the uniformity of the display.

[0042] In related technologies, the thickness of planarized layers can be structurally confirmed using methods such as FIB (Focused Ion Beam). FIB utilizes gallium ions to cut and remove material at very high spatial resolution, allowing for the creation of cross-sections at desired locations on the sample. FIB slices provide cross-sectional views of the material, revealing its layered structure, nanoparticle distribution, fiber orientation, and other information. The basic principle of FIB slice analysis is the precise processing of material surfaces using a high-energy ion beam. The ion beam, emitted from an ion gun and focused and positioned by a system, can be precisely located and processed at the nanoscale. When the ion beam interacts with the material, collisions occur between ions and atoms or molecules, causing atoms or molecules on the material surface to detach and resulting in etching. By controlling the energy and injection dose of the ion beam, precise cutting of the material can be achieved.

[0043] The FIB section analysis process generally includes the following steps: 1. Sample preparation: First, the sample to be analyzed needs to be placed on the sample stage of the FIB sectioner, ensuring the sample surface is smooth and flat so that the ion beam can be accurately positioned and processed. 2. Sample cutting: By controlling the scanning trajectory and etching parameters of the ion beam, the ion beam cuts the sample. The ion beam starts cutting from the surface of the sample and gradually penetrates the sample, forming a very thin section. The thickness of this section is usually between a few nanometers and tens of nanometers, depending on the required analytical depth. 3. Section capture: The cut section is captured and transferred to a slide or grid for subsequent observation and analysis. The section capture process usually requires the use of micro-tweezers or similar tools to ensure the safe transfer of the section. 4. Refinement: Sometimes, the cut section may require further refinement to eliminate artifacts or other imperfections generated during the cutting process. This can be achieved by using a lower-energy ion beam or other nanofabrication techniques. 5. Observation and Analysis: Finally, the slices are placed in instruments such as transmission electron microscope (TEM) or scanning electron microscope (SEM) for observation and analysis. Transmission electron microscope can provide high-resolution material structure and composition information, and can observe details such as the microstructure, crystal structure, interface and defects of the slices. Scanning electron microscope can provide a wider range of surface morphology and composition distribution information.

[0044] FIB (Fiber Optic Injection) section analysis provides a wealth of useful information and data, including: Material structure characterization: FIB sections offer cross-sectional views of materials, allowing observation of layered structures, nanoparticle distribution, fiber orientation, and other information, crucial for studying the microstructure and organizational characteristics of materials; Elemental analysis: Transmission electron microscopy (TEM) enables energy dispersive spectroscopy (EDS). By analyzing the X-ray energy spectra of different regions on the section, the composition and distribution of elements in the material can be determined, which is invaluable for studying material composition and detecting impurities; Interface studies: FIB sections reveal the interface structure and interactions between different components in a material, allowing observation of interface morphology, crystallinity, and bonding states, which is significant for understanding the interface properties and reactions of materials; Defect analysis: FIB section analysis allows observation of defects, pores, grain boundaries, and other defect structures in the material, aiding in the evaluation of material quality and performance, and providing guidance for material improvement and optimization.

[0045] Regarding the thickness of the planarization layer, the main method is to use FIB to observe the layered structure of the planarization layer cross-section to determine whether the planarization layer is flat. However, the FIB method is time-consuming and does not meet the production rhythm of the factory.

[0046] To enable the detection of planarization layer thickness, this application embodiment provides a display panel 1, see [link to relevant documentation]. Figure 1 The display panel 1 includes:

[0047] The display area 11 and the non-display area 12; the non-display area 12 includes a first edge area 121 and a second edge area 122, the second edge area 122 being the outer edge area of ​​the display panel 1, and the first edge area 121 being located between the display area 11 and the second edge area 122; the first edge area 121 and the second edge area 122 are separated by a dam structure 123;

[0048] The first edge region 121 includes a plurality of ground lines 1211, which are disposed on the side away from the substrate 1214 on the planarization layer 1212 of the first edge region 121. The planarization layer 1212 of the first edge region 121 is located on the side away from the substrate 1214 on the cathode layer 1213 of the first edge region 121.

[0049] The dam structure is a barrier dam with a display panel.

[0050] Understandable Figure 1 The diagram only illustrates the structure of the first edge region between the display area and the second edge region in the top-view cross-section of the monitor; the structural diagrams from other perspectives are the same. Figure 1(Based on the main view of the display) Figure 1 The middle section is a schematic top-view cross-sectional view of the monitor.

[0051] In this embodiment, by setting multiple ground lines (GND traces) on the planarization layer, the thickness of the planarization layer is detected by utilizing the equivalent capacitance between the ground lines and the cathode layer.

[0052] In one possible implementation, the plurality of ground lines 1211 includes a plurality of row-direction ground lines 1211 and a plurality of column-direction ground lines 1211; the row-direction ground lines 1211 extend along the row direction of the display panel 1, and the column-direction ground lines 1211 extend along the column direction of the display panel 1.

[0053] In one example, see Figure 2 This is a front view of the monitor, showing the ground wire positioned around the display area.

[0054] In one possible implementation, adjacent row-direction ground lines 1211 are parallel to each other, and adjacent column-direction ground lines 1211 are parallel to each other.

[0055] In one example, see Figure 3 This is another front view of the monitor, illustrating the ground wire arrangement in the first edge area, primarily focusing on the right side of the display area. The column-direction ground wires extend along the column direction of the display panel. There can be three column-direction ground wires located on the right side of the display area. (See also...) Figure 6a The third ground line (GND3), the second ground line (GND2), and the first ground line (GND1) are arranged sequentially in a direction away from the display area (this direction points from the display area to the second edge area). The equivalent capacitances between the third ground line, the second ground line, the first ground line and the cathode layer are Cst3, Cst2, and Cst1, respectively. The planarization layer thickness at the location of the third ground line is the same as that at the location of the second ground line, while the planarization layer thickness at the location of the first ground line is larger (the planarization layer at the location of the first ground line is more prominent than the planarization layers at the locations of the second and third ground lines). For each ground line, the greater the distance (planarization layer thickness) between the ground line and the cathode layer, the smaller the equivalent capacitance value between the ground line and the cathode layer. Therefore, Cst1 < Cst2 = Cst3. The flatness of the planarization layer can be reflected in the change of the equivalent capacitance value between the ground wire and the cathode layer. That is, the flatness of the planarization layer can be judged based on the change of the equivalent capacitance value, without the need for additional time-consuming confirmation of the planarization layer film thickness, thus improving production efficiency.

[0056] In one possible implementation, the ground wire 1211 is disposed in the first edge area on the side close to the display area 11.

[0057] The ground wire can be designed on the side closest to the display area to detect the leveling (flatness) of the planarization layer around the display area. For example, in COE (Color On Encapsulation) products, the protrusions of the planarization layer extend to the edge of the display area, causing poor edge brightness and inconsistent light output. Therefore, the leveling around the display area is crucial for COE products. By detecting the thickness of the planarization layer, when unevenness is found, process parameters can be adjusted promptly to improve the display uniformity of the COE product.

[0058] In one possible implementation, the first edge region 121 is prepared by inkjet printing (IJP).

[0059] Inkjet printing is a non-contact, micrometer-scale printing process that directly jets nanoscale solutions onto flexible or rigid substrates. Because inkjet printing can directly form patterned thin films without a mask, it is considered a highly promising printing technology. An inkjet printing device typically includes an ink cartridge and an inkjet head capable of precisely depositing the solution onto the designed area. Inkjet printing is a non-contact deposition technology that offers precise control over the volume and position of solution deposition, easy patterning, high material utilization, and no contamination.

[0060] Generally, inkjet printing can be divided into three printing modes: piezoelectric inkjet, acoustic inkjet, and thermal inkjet. Compared with the etching process of traditional silicon-based microelectronics, inkjet printing has a lower resolution, which limits its applications. The resolution of inkjet printing is generally 20 micrometers, but it can be improved to 400 nm by selecting appropriate inkjet heads and inks. The ink jetting characteristics, solution evaporation behavior, ink viscosity, and nozzle diameter are all important parameters affecting resolution. At the same time, the coffee ring effect after solution deposition is also a major challenge in preparing uniform and dense films, mainly due to uncontrolled droplet diffusion and contact line blockage.

[0061] Currently, various technologies have been introduced into the inkjet printing process to improve the forming quality of inkjet-printed films: (1) ink design, using low surface tension materials (surfactants, dodecyl mercaptan) or high-boiling-point solvents, gelled polymers, or modified nanoparticle properties; (2) substrate treatment, improving substrate surface wettability, reducing surface temperature, or introducing corona treatment; (3) equipment improvement, such as customized nozzle diameter or improved planar movement accuracy. These methods have proven effective in improving the shape, thickness, and morphology of dried droplets, as well as the precision of printed films. In conclusion, inkjet printing is a digitally controllable patterning method suitable for film preparation of various materials, and is a reliable printing technology.

[0062] This application also provides a method for detecting planarization layer thickness, see [link to relevant documentation]. Figure 4 Applied to any of the display panels described in the above embodiments, the method includes the following steps:

[0063] Step S401: Obtain the equivalent capacitance value between each ground wire and the cathode layer;

[0064] Step S402: Based on the equivalent capacitance value corresponding to each ground wire, query the pre-determined correspondence between the thickness value and the equivalent capacitance value, and determine the thickness value of the flat layer at the location of each ground wire.

[0065] The correspondence between equivalent capacitance and thickness can be obtained through the accumulation of process data.

[0066] To more accurately and intuitively represent the flatness of the leveling layer, the correspondence between the ground wire and the capacitance value can be displayed in a coordinate system. That is, the flatness of the leveling layer is judged by the fitting curve of the capacitance value. When the detected fitting curve deviates from the fitting curve under normal process conditions, it is judged that there is a risk of uneven leveling of the leveling layer.

[0067] The specific analysis is the same as above, and will not be repeated here.

[0068] In this embodiment, the change in the flatness of the planarization layer is reflected in the change in the value of the equivalent capacitance between the ground wire and the cathode layer. That is, the flatness of the planarization layer is determined based on the change in the equivalent capacitance value. During production, the thickness change of the planarization layer can be monitored in real time, facilitating timely adjustments to process parameters. This eliminates the need for additional, time-consuming confirmation of the planarization layer thickness, thus improving production efficiency.

[0069] In one possible implementation, see Figure 5 ,based on Figure 4 Step S401 has been refined to include the following steps:

[0070] Step S501: The equivalent capacitance between each ground wire and the cathode layer is detected by the capacitance detection module to obtain the equivalent capacitance value between each ground wire and the cathode layer.

[0071] The capacitance detection module can be an external detection module for the display panel.

[0072] The specific analysis is the same as above, and will not be repeated here.

[0073] In one possible implementation, the (i+1)th, ith, and (i-1)th ground lines among the plurality of ground lines are arranged sequentially along the direction closest to the display area;

[0074] The method further includes:

[0075] If the (i+1)th thickness value is the same as the ith thickness value and the ith thickness value is less than the (i-1)th thickness value, then the structure from the flat layer at the location of the (i+1)th ground wire to the flat layer at the location of the ith ground wire is determined to be a flat structure, and the structure from the flat layer at the location of the ith ground wire to the flat layer at the location of the (i-1)th ground wire is determined to be a raised structure; wherein, the (i+1)th thickness value is the thickness value of the flat layer at the location of the (i+1)th ground wire, the ith thickness value is the thickness value of the flat layer at the location of the ith ground wire, and the (i-1)th thickness value is the thickness value of the flat layer at the location of the (i-1)th ground wire; and i is greater than or equal to 2.

[0076] In one example, see Figure 6a ,based on Figure 3 The third, second, and first ground lines are arranged sequentially away from the display area. The equivalent capacitances between the third, second, and first ground lines and the cathode layer are Cst3, Cst2, and Cst1, respectively. The planarization layer thickness at the location of the third ground line is the same as that at the location of the second ground line, while the planarization layer thickness at the location of the first ground line is larger (the planarization layer at the location of the first ground line protrudes compared to the planarization layers at the locations of the second and third ground lines). For each ground line, the greater the distance (planarization layer thickness) between the ground line and the cathode layer, the smaller the equivalent capacitance value between the ground line and the cathode layer. Therefore, Cst1 < Cst2 = Cst3. It can be understood that Cst2 = Cst3 here can be approximately equal to...

[0077] To more accurately and intuitively represent the flatness of the leveling layer, the correspondence between the ground wire and the capacitance value can be displayed in a coordinate system. That is, the flatness of the leveling layer is judged by the fitting curve of the capacitance value. When the detected fitting curve deviates from the fitting curve under normal process conditions, it is judged that there is a risk of uneven leveling of the leveling layer.

[0078] See Figure 6b ,for Figure 6aThe corresponding ground-capacitance curve diagram is shown. Thickness_1 represents the planarization layer thickness under the first process, and Thickness_2 represents the planarization layer thickness under the second process. The equivalent capacitance under the first process is generally greater than that under the second process. The equivalent capacitance is negatively correlated with the planarization layer thickness, indicating that Thickness_1 is thinner overall than Thickness_2. For the ground-capacitance curves under the first / second processes, for each ground line, the greater the planarization layer thickness at that location, the smaller the equivalent capacitance value corresponding to that ground line. The planarization layer thickness at that location is negatively correlated with the equivalent capacitance value corresponding to that ground line. The trend of change in capacitance value can reflect the trend of change in planarization layer thickness. The correspondence between equivalent capacitance value and thickness value can be obtained through the accumulation of process data.

[0079] In one possible implementation, the method further includes:

[0080] If the thickness value of the (i-1)th layer is the same as the thickness value of the ith layer, and the thickness value of the ith layer is greater than the thickness value of the (i+1)th layer, then the flat layer from the location of the (i-1)th ground wire to the location of the ith ground wire is determined to be a raised structure, and the flat layer at the location of the (i+1)th ground wire is determined to be a flat structure.

[0081] In one example, the width of the planarization layer protrusions may widen due to factors such as changes in IJP viscosity; see [link to relevant documentation]. Figure 7a ,based on Figure 3 The third, second, and first ground lines are arranged sequentially away from the display area. The equivalent capacitances between the third, second, and first ground lines and the cathode layer are Cst3, Cst2, and Cst1, respectively. The planarization layer thickness at the location of the second ground line is the same as that at the location of the first ground line, while the planarization layer thickness at the location of the third ground line is smaller (the planarization layer at the location of the first and second ground lines is more convex than that at the location of the third ground line). For each ground line, the greater the distance (planarization layer thickness) between the ground line and the cathode layer, the smaller the equivalent capacitance value between the ground line and the cathode layer. Therefore, Cst3 > Cst1 = Cst2. It can be understood that Cst1 = Cst2 at this point can be approximately equal to...

[0082] See Figure 7b ,for Figure 7a The corresponding ground-capacitance curve diagram shows that the equivalent capacitance value of GND1 is approximately the same as that of GND2. Figure 6b Compared to the trend of the ground-capacitance curve under the first process (Thickness_1), Figure 7b The change in the ground-capacitance curve under the second process (Thickness_2) indicates a risk of unevenness in the flat laminar flow. Understandably, this can be interpreted as... Figure 6b The ground-capacitance curve trend under the first process (Thickness_1) is used as a reference trend. Figure 7b The trend shift of the ground-capacitance curve under the second process (Thickness_2) is shown. Figure 6b When analyzing the ground-capacitance curve trend under the first process (Thickness_1), it can be determined that there is a risk of unevenness in the flat laminar flow.

[0083] In one possible implementation, the method further includes:

[0084] If the thickness value of the i-th line is greater than the thickness value of the (i+1)-th line and the thickness value of the (i+1)-th line is greater than the thickness value of the (i-1)-th line, then the flat layer at the location of the (i+1)-th line is determined to be a flat structure, the flat layer at the location of the i-th line is determined to be a raised structure, and the flat layer at the location of the (i-1)-th line is determined to be a sunken structure.

[0085] In one example, the planarization layer at the location of GND1 might be thinner due to an excessively large leveling distance between the planarization layer and Dam. See [link to relevant documentation]. Figure 8a ,based on Figure 3 The third, second, and first ground lines are arranged sequentially away from the display area. The equivalent capacitances between the third, second, and first ground lines and the cathode layer are Cst3, Cst2, and Cst1, respectively. The planarization layer at the location of the second ground line is thicker (the planarization layer at the location of the second ground line is more prominent than the planarization layer at the location of the third ground line), while the planarization layer at the location of the first ground line is thinner (the planarization layer at the location of the first ground line is more recessed than the planarization layer at the location of the third ground line). The thickness of the planarization layer at the location of the third ground line is... Figure 6a and Figure 7a The thickness of the planarization layer at the location of the third ground wire is consistent, and it can be taken as the planarization layer thickness under normal process. For each ground wire, the greater the distance between the ground wire and the cathode layer (planarization layer thickness), the smaller the equivalent capacitance value between the ground wire and the cathode layer. Therefore, Cst1 > Cst3 > Cst2.

[0086] See Figure 8b ,for Figure 8a The corresponding ground-capacitance curve diagram shows an abnormal increase in the equivalent capacitance value corresponding to GND1. Figure 6b Compared to the ground-capacitance curve under the first process (Thickness_1), Figure 8bThe change in the ground-capacitance curve under the second process (Thickness_2) indicates the risk of unevenness in the flat laminar flow.

[0087] The flatness of the planarization layer is judged by the fitting curve of the capacitance value. When the detected fitting curve deviates from the fitting curve under normal process, it is judged that there is a risk of unevenness in the planarization layer flow, which more accurately and intuitively shows the flatness of the planarization layer.

[0088] This application embodiment also provides a display 2, see [link] Figure 9 The display 2 includes any of the display panels 1 described in the above embodiments.

[0089] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0090] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0091] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, The display panel includes: The display area and the non-display area; the non-display area includes a first edge area and a second edge area, the second edge area being the outer edge area of ​​the display panel, and the first edge area being located between the display area and the second edge area; the first edge area and the second edge area are separated by a dam structure; The first edge region includes multiple ground lines, which are disposed on the side of the planarization layer of the first edge region away from the substrate. The planarization layer of the first edge region is located on the side of the cathode layer of the first edge region away from the substrate.

2. The display panel according to claim 1, characterized in that, The multiple ground lines include multiple row-direction ground lines and multiple column-direction ground lines; the row-direction ground lines extend along the row direction of the display panel, and the column-direction ground lines extend along the column direction of the display panel.

3. The display panel according to claim 2, characterized in that, The ground lines in adjacent rows are parallel to each other, and the ground lines in adjacent columns are parallel to each other.

4. The display panel according to claim 1, characterized in that, The ground wire is located on the side of the first edge area closer to the display area.

5. The display panel according to claim 1, characterized in that, The first edge region was prepared by inkjet printing.

6. A method for detecting the thickness of a planarization layer, characterized in that, Applied to the display panel according to any one of claims 1-5, the method includes: Obtain the equivalent capacitance value between each ground wire and the cathode layer; Based on the equivalent capacitance value corresponding to each ground wire, the correspondence between the predetermined thickness value and the equivalent capacitance value is queried to determine the thickness value of the flat layer at the location of each ground wire.

7. The method according to claim 6, characterized in that, The step of obtaining the equivalent capacitance value between each of the ground wires and the cathode layer includes: The equivalent capacitance between each ground wire and the cathode layer is detected by the capacitance detection module to obtain the equivalent capacitance value between each ground wire and the cathode layer.

8. The method according to claim 6, characterized in that, The (i+1)th, ith, and (i-1)th ground lines among the plurality of ground lines are arranged sequentially along the direction away from the display area; The method further includes: If the (i+1)th thickness value is the same as the ith thickness value and the ith thickness value is less than the (i-1)th thickness value, then the structure from the flat layer at the location of the (i+1)th ground wire to the flat layer at the location of the ith ground wire is determined to be a flat structure, and the structure from the flat layer at the location of the ith ground wire to the flat layer at the location of the (i-1)th ground wire is determined to be a raised structure; wherein, the (i+1)th thickness value is the thickness value of the flat layer at the location of the (i+1)th ground wire, the ith thickness value is the thickness value of the flat layer at the location of the ith ground wire, and the (i-1)th thickness value is the thickness value of the flat layer at the location of the (i-1)th ground wire; and i is greater than or equal to 2.

9. The method according to claim 8, characterized in that, The method further includes: If the thickness value of the (i-1)th layer is the same as the thickness value of the ith layer, and the thickness value of the ith layer is greater than the thickness value of the (i+1)th layer, then the flat layer from the location of the (i-1)th ground wire to the location of the ith ground wire is determined to be a raised structure, and the flat layer at the location of the (i+1)th ground wire is determined to be a flat structure.

10. The method according to claim 9, characterized in that, The method further includes: If the thickness value of the i-th line is greater than the thickness value of the (i+1)-th line and the thickness value of the (i+1)-th line is greater than the thickness value of the (i-1)-th line, then the flat layer at the location of the (i+1)-th line is determined to be a flat structure, the flat layer at the location of the i-th line is determined to be a raised structure, and the flat layer at the location of the (i-1)-th line is determined to be a sunken structure.

11. A display, characterized in that, The display includes the display panel described in any one of claims 1-5.

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