Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate and a capacitor structure. The substrate has a capacitor contact structure thereon. The capacitor structure is connected with the capacitor contact structure, and the capacitor structure comprises a plurality of capacitor units stacked in a direction perpendicular to the capacitor contact structure. The semiconductor structure and the preparation method thereof provided by the embodiments of the present disclosure can reduce the process difficulty of the capacitor structure, and ensure that the capacitor structure formed has a stable structure and a large capacitance, thereby improving the electrical performance and production yield of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory in computers and other electronic devices, consisting of multiple memory cells. Each memory cell includes a storage capacitor and a transistor electrically connected to the storage capacitor. The transistor includes a gate, a source region, and a drain region. The gate of the transistor is used to electrically connect to the word line. The source region of the transistor forms the bit line contact region to electrically connect to the bit line through a bit line contact structure. The drain region of the transistor forms the memory node contact region to electrically connect to the storage capacitor through a memory node contact structure.

[0003] However, with the development of semiconductor technology, the feature size of devices in integrated circuits is becoming smaller and smaller. After semiconductor processes entered the deep submicron stage, DRAM sizes became increasingly smaller. Correspondingly, transistors gradually evolved from buried gate structures to gate all-around (GAA) structures, which occupy even less area. The structure of storage capacitors also changed accordingly, evolving from hexagonal close-packing to quadrilateral packing. Furthermore, the radial dimension of storage capacitors continues to decrease; for example, storage capacitors have changed from cup-shaped structures to columnar structures.

[0004] However, while the radial dimension of storage capacitors is continuously decreasing, a higher aspect ratio increases etching difficulty and limits the height of the storage capacitor. This, in turn, can significantly reduce the surface area of ​​the storage capacitor, resulting in a smaller capacitance that is difficult to meet application requirements. Summary of the Invention

[0005] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, which can reduce the process difficulty of capacitor structure fabrication and ensure the formation of a stable capacitor structure with a large capacitance, thereby improving the electrical performance and production yield of the semiconductor structure.

[0006] To achieve the above objectives, in one aspect, some embodiments of this disclosure provide a semiconductor structure. The semiconductor structure includes a substrate and a capacitor structure. A capacitor contact structure is provided on the substrate. The capacitor structure is connected to the capacitor contact structure, and the capacitor structure includes a plurality of capacitor cells stacked in a direction perpendicular to the capacitor contact structure.

[0007] In some embodiments, a capacitor cell includes: a capacitor connection structure, a first electrode, a second electrode, and a high-k dielectric layer. The capacitor connection structure is located vertically above the capacitor contact structure, and in any two adjacent capacitor cells in the direction perpendicular to the capacitor contact structure, the capacitor connection structure is interconnected and connected to the capacitor contact structure. The first electrode is located on the sidewall of the capacitor connection structure, and in any two adjacent capacitor cells in the direction perpendicular to the capacitor contact structure, the first electrode is interconnected. The high-k dielectric layer is disposed on the sidewall of the first electrode, and in any two adjacent capacitor cells in the direction perpendicular to the capacitor contact structure, the high-k dielectric layer is interconnected. The second electrode is disposed on the sidewall of the high-k dielectric layer, and in any two adjacent capacitor cells in the direction perpendicular to the capacitor contact structure, the second electrode is interconnected.

[0008] In some embodiments, the semiconductor structure further includes: a top dielectric layer covering the capacitor structure, and a common source electrode layer located above the top dielectric layer. The top dielectric layer has an opening. The common source electrode layer is connected to a second electrode through the opening.

[0009] In some embodiments, a plurality of capacitive contact structures are arranged in an array on a substrate; wherein, in any two adjacent capacitive units in a direction parallel to the substrate, a second electrode is interconnected.

[0010] In some embodiments, in any two adjacent capacitor cells in a direction parallel to the substrate, the bottoms of the second electrodes are interconnected and form a groove. The semiconductor structure also includes a support structure located within the groove.

[0011] In some embodiments, the upper surface of the support structure away from the substrate is flush with the top surface of the second electrode away from the substrate.

[0012] In some embodiments, the support structure includes an auxiliary conductive portion connected to an adjacent second electrode. Alternatively, the support structure includes an auxiliary conductive portion and a support portion located above the auxiliary conductive portion. The auxiliary conductive portion is connected to the adjacent second electrode.

[0013] In some embodiments, a capacitor cell includes a first electrode, a second electrode, and a high-k dielectric layer. The first electrode is located vertically above the capacitor contact structure, and in any two adjacent capacitor cells in the direction perpendicular to the capacitor contact structure, the first electrodes are interconnected and connected to the capacitor contact structure. The high-k dielectric layer is disposed on the sidewall of the first electrode, and in any two adjacent capacitor cells in the direction perpendicular to the capacitor contact structure, the high-k dielectric layer is interconnected. The second electrode is disposed on the sidewall of the high-k dielectric layer, and in any two adjacent capacitor cells in the direction perpendicular to the capacitor contact structure, the second electrode is interconnected.

[0014] In some embodiments, a barrier layer is provided between the high-k dielectric layer and the first electrode.

[0015] In some embodiments, the high-k dielectric layer in the top capacitor cell further covers the top surface of the first electrode away from the substrate, and the second electrode in the top capacitor cell further covers the top surface of the high-k dielectric layer away from the substrate. The semiconductor structure also includes a common source electrode layer covering the sidewalls of the second electrode and the top surface of the second electrode away from the substrate.

[0016] In some embodiments, a plurality of capacitive contact structures are arranged in an array on a substrate; wherein, in any two adjacent capacitive units in a direction parallel to the substrate, a second electrode is interconnected.

[0017] On the other hand, some embodiments of this disclosure provide a method for fabricating a semiconductor structure, including the following steps.

[0018] A substrate is provided, on which a capacitive contact structure is provided.

[0019] Multiple capacitor units are stacked in a direction perpendicular to the capacitor contact structure to form a capacitor structure. The capacitor structure is connected to the capacitor contact structure.

[0020] In some embodiments, stacking multiple capacitor units in a direction perpendicular to the capacitor contact structure to form a capacitor structure includes the following steps.

[0021] A bottom capacitor unit is formed vertically above the capacitor contact structure, including: forming a capacitor connection structure vertically above the capacitor contact structure, and sequentially forming a first electrode, a high-K dielectric layer, and a second electrode on the sidewall of the capacitor connection structure.

[0022] Intermediate capacitor units are stacked vertically above the bottom capacitor unit; wherein, forming the N+1th intermediate capacitor unit includes: forming the N+1th capacitor connection structure vertically above the Nth capacitor connection structure, and sequentially forming a first electrode, a high-K dielectric layer, and a second electrode on the sidewall of the N+1th capacitor connection structure; wherein, N is a positive integer and 2≤N+1≤M.

[0023] Stacking top capacitor units vertically above intermediate capacitor units includes: forming an M+1 layer capacitor connection structure vertically above the M layer capacitor connection structure, and sequentially forming a first electrode, a high-K dielectric layer, and a second electrode on the sidewall of the M+1 layer capacitor connection structure.

[0024] In some embodiments, the preparation method further includes the following steps.

[0025] A top dielectric material layer is formed to cover the top capacitor unit.

[0026] The top dielectric material layer is patterned to form the top dielectric layer. The top dielectric layer has an opening, through which the second electrode of the top capacitor cell is exposed.

[0027] A common source electrode layer is formed to cover the top dielectric layer, and the common source electrode layer is connected to the second electrode.

[0028] In some embodiments, the step of sequentially forming a first electrode, a high-k dielectric layer, and a second electrode on the sidewall of the capacitor connection structure includes the following steps.

[0029] A first electrode is formed on the sidewall of the capacitor connection structure.

[0030] A high-k dielectric material layer and a second electrode material layer are deposited sequentially.

[0031] A portion of the high-K dielectric material layer and a portion of the second electrode material layer are removed to form a high-K dielectric layer located on the sidewall of the first electrode and a second electrode located on the sidewall of the high-K dielectric layer.

[0032] In some embodiments, before removing a portion of the high-K dielectric material layer and a portion of the second electrode material layer to form the high-K dielectric layer located on the sidewall of the first electrode and the second electrode located on the sidewall of the high-K dielectric layer, the preparation method further includes the following steps.

[0033] An auxiliary conductive material layer is deposited to cover the second electrode material layer.

[0034] A portion of the auxiliary conductive material layer is removed, and an auxiliary conductive portion is formed between any two adjacent capacitor cells in a direction parallel to the substrate.

[0035] In some embodiments, before removing a portion of the high-K dielectric material layer and a portion of the second electrode material layer to form the high-K dielectric layer located on the sidewall of the first electrode and the second electrode located on the sidewall of the high-K dielectric layer, the preparation method further includes the following steps.

[0036] A second electrode material layer and a support material layer for the auxiliary conductive part are deposited.

[0037] A portion of the support material layer is removed to form a support section between any two adjacent capacitor cells in a direction parallel to the substrate. The support section is located above the auxiliary conductive section and together with the auxiliary conductive section, constitutes a support structure.

[0038] In some embodiments, the capacitor connection structure is formed by an epitaxial growth process.

[0039] In some embodiments, stacking multiple capacitor units in a direction perpendicular to the capacitor contact structure to form a capacitor structure includes the following steps.

[0040] A bottom capacitor unit is formed vertically above the capacitor contact structure, including: forming a first electrode vertically above the capacitor contact structure, and sequentially forming a high-k dielectric layer and a second electrode on the sidewall of the first electrode.

[0041] Intermediate capacitor units are stacked vertically above the bottom capacitor unit; wherein, forming the N+1th intermediate capacitor unit includes: forming the N+1th first electrode vertically above the Nth first electrode, and sequentially forming a high-K dielectric layer and a second electrode on the sidewall of the N+1th first electrode; wherein, N is a positive integer and 2≤N+1≤M.

[0042] Stacking top capacitor cells vertically above intermediate capacitor cells includes: forming a first electrode of layer M+1 vertically above the first electrode of layer M, and sequentially forming a high-K dielectric layer and a second electrode at least on the sidewall of the first electrode of layer M+1.

[0043] Optionally, in the step of stacking intermediate capacitor units vertically above the bottom capacitor unit, a high-K dielectric layer and a second electrode are sequentially formed on the sidewall of the first electrode, including: depositing a high-K dielectric material layer and a second electrode material layer sequentially on the structure obtained by forming the first electrode; removing part of the high-K dielectric material layer and part of the second electrode material layer to form a high-K dielectric layer located on the sidewall of the first electrode and a second electrode located on the sidewall of the high-K dielectric layer.

[0044] Optionally, in the step of stacking the top capacitor cell vertically above the intermediate capacitor cell, a high-k dielectric layer and a second electrode are sequentially formed at least on the sidewall of the first electrode, including: depositing the high-k dielectric layer and the second electrode sequentially on the structure obtained by forming the first electrode; wherein the high-k dielectric layer at least covers the sidewall of the first electrode and the top surface of the first electrode away from the substrate, and the second electrode covers the sidewall of the high-k dielectric layer and the top surface of the high-k dielectric layer away from the substrate.

[0045] In some embodiments, before removing a portion of the high-K dielectric material layer and a portion of the second electrode material layer to form the high-K dielectric layer located on the sidewall of the first electrode and the second electrode located on the sidewall of the high-K dielectric layer, the preparation method further includes the following steps.

[0046] An auxiliary conductive material layer is deposited to cover the second electrode material layer.

[0047] A portion of the auxiliary conductive material layer is removed, and an auxiliary conductive portion is formed between any two adjacent capacitor cells in a direction parallel to the substrate.

[0048] In some embodiments, before removing a portion of the high-K dielectric material layer and a portion of the second electrode material layer to form the high-K dielectric layer located on the sidewall of the first electrode and the second electrode located on the sidewall of the high-K dielectric layer, the preparation method further includes the following steps.

[0049] A second electrode material layer and a support material layer for the auxiliary conductive part are deposited.

[0050] A portion of the support material layer is removed to form a support section between any two adjacent capacitor cells in a direction parallel to the substrate. The support section is located above the auxiliary conductive section and together with the auxiliary conductive section, constitutes a support structure.

[0051] In some embodiments, after stacking the top capacitor unit vertically above the intermediate capacitor unit, the fabrication method further includes: forming a common source electrode layer covering the sidewall of the second electrode in the top capacitor unit and the second electrode facing away from the top surface of the substrate.

[0052] In some embodiments, the first electrode is formed by an epitaxial growth process.

[0053] In some embodiments, before forming the high-k dielectric layer, the fabrication method further includes: forming a barrier layer covering the first electrode. Forming the high-k dielectric layer further includes: forming the high-k dielectric layer on the surface of the barrier layer facing away from the first electrode.

[0054] The semiconductor structure provided in this disclosure, as described above, allows for the stacking of multiple capacitor cells in a direction perpendicular to the capacitor contact structure to form a capacitor structure. This reduces the aspect ratio of each capacitor cell layer while continuously decreasing the radial dimension of the capacitor structure, and also avoids high aspect ratio etching, thus eliminating the problem of increased etching difficulty due to higher aspect ratios. This not only significantly reduces the manufacturing process difficulty of the capacitor structure but also effectively increases its stability, preventing stacking collapse. Furthermore, in this disclosure, the stacking of capacitor cells in the vertical direction of the capacitor contact structure using epitaxial growth and self-alignment reduces the number of photomasks used and effectively avoids stacking deviations, further reducing the manufacturing process difficulty of the capacitor structure.

[0055] Furthermore, by stacking capacitor cells multiple times, embodiments of this disclosure can obtain a capacitor structure with a high height, ensuring the formation of a capacitor structure with a large capacitor area. This allows for the formation of a stable capacitor structure with a large capacitance even as semiconductor structure dimensions continue to shrink. Consequently, it effectively improves the electrical performance and production yield of the semiconductor structure. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a schematic cross-sectional view of a semiconductor structure provided in one embodiment;

[0058] Figure 2 This is a schematic diagram of another semiconductor structure provided in one embodiment;

[0059] Figure 3 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0060] Figure 4 for Figure 1 A schematic diagram of the fabrication process of the semiconductor structure shown.

[0061] Figures 5 to 22 for Figure 1 A schematic cross-sectional view of the structure obtained in the step of the semiconductor structure fabrication method shown;

[0062] Figure 23 for Figure 2 A schematic diagram of the fabrication process of the semiconductor structure shown.

[0063] Figures 24-34 for Figure 2 A schematic cross-sectional view of the structure obtained in the step of the semiconductor structure fabrication method shown.

[0064] Explanation of reference numerals in the attached figures:

[0065] 1-Substrate, 11-Bit line, 12-Gate all-around transistor, 121-Channel pillar, 122-Gate insulating layer,

[0066] 123 - Gate word line, isolation layer, SNC - Capacitor contact structure, G - Groove

[0067] C0 - Capacitor structure, C D - Bottom capacitor unit, C M -Intermediate capacitor unit, C T -Top capacitor unit;

[0068] 2-Capacitor unit, 20-Capacitor connection structure, 21-First electrode, 22-High-K dielectric layer, 23-Second electrode.

[0069] 24-Barrier layer, 3-Support structure, 31-Auxiliary conductive part, 32-Support part

[0070] 4-Top dielectric layer, K-Opening, 5-Common source electrode layer. Detailed Implementation

[0071] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0072] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0073] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0074] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0075] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0076] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.

[0077] With the development of semiconductor technology, the feature size of devices in integrated circuits is becoming smaller and smaller. After semiconductor processes entered the deep submicron stage, DRAM sizes have become increasingly smaller. Correspondingly, transistors have gradually evolved from buried gate structures to gate all-around (GAA) structures, which occupy even less area. The structure of storage capacitors has also adjusted accordingly, evolving from hexagonal close-packing to quadrilateral packing. Furthermore, the radial dimension of storage capacitors continues to decrease; for example, storage capacitors have shifted from a cup-shaped structure to a columnar structure.

[0078] However, while the radial dimension of storage capacitors is continuously decreasing, a higher aspect ratio increases etching difficulty and limits the height of the storage capacitor. This, in turn, can significantly reduce the surface area of ​​the storage capacitor, resulting in a smaller capacitance that is difficult to meet application requirements.

[0079] In some embodiments, the insufficient capacitance can be compensated for by increasing the K value of the dielectric layer in the storage capacitor. However, dielectric materials with higher K values ​​tend to have narrower band gaps and are also more prone to greater leakage current, making the search for a suitable capacitor dielectric material a challenge.

[0080] Based on this, some embodiments of this disclosure provide a semiconductor structure in which capacitor cells are stacked in the vertical direction of the capacitor contact structure through epitaxial growth and self-alignment to obtain a capacitor structure with a high height. This ensures the formation of a capacitor with a stable structure and a large capacitance, thereby effectively improving the electrical performance and production yield of the semiconductor structure.

[0081] Please see Figure 1 and Figure 2 This disclosure provides a semiconductor structure in some embodiments. The semiconductor structure includes a substrate 1 and a capacitor structure C0. The substrate 1 has a capacitor contact structure SNC. The capacitor structure C0 is connected to the capacitor contact structure SNC, and the capacitor structure C0 includes a plurality of capacitor cells 2 stacked in a direction perpendicular to the capacitor contact structure SNC.

[0082] In some embodiments, substrate 1 may be composed of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 may be a single-layer structure or a multi-layer structure. For example, substrate 1 may be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 may be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0083] Optionally, substrate 1 is a silicon substrate or a silicon-based substrate. For example... Figure 1 or Figure 2 As shown, a buried bit line 11 and a gate all-around transistor (GAAtransistor) 12 connected to the buried bit line 11 can be disposed within the substrate 1. Multiple buried bit lines 11 can be arranged in parallel at intervals within the substrate 1, extending along a first direction. One buried bit line 11 can correspondingly connect to multiple gate all-around transistors 12 arranged along the first direction. The gate all-around transistor 12 is located above the buried bit line 11 and includes: a channel pillar 121, a gate insulating layer 122, and a gate word line 123. The channel pillar 121 includes: a conductive channel disposed perpendicular to the substrate 1, and a source and a drain located at opposite ends of the conductive channel. The channel pillar 121 can be formed by etching the substrate 1, and the source and drain can be formed by ion doping corresponding regions of the channel pillar 121. The drain is connected to the buried bit line 11. The source is located at one end of the conductive channel away from the bit line. The source can be directly used as a capacitor contact structure SNC, or the source can be connected to capacitor cell 2 through a capacitor contact structure SNC (i.e., a conductive structure can be formed on the source surface to serve as a capacitor contact structure). A gate insulating layer 122 is disposed around the sidewall of the channel pillar 121. A gate word line 123 is located on the surface of the gate insulating layer 122 opposite to the conductive channel and extends along a second direction. The second direction intersects, for example, the first direction.

[0084] The aforementioned gate-all-around transistor, also known as a vertical gate-all-around transistor, offers greater integration freedom in the vertical direction, effectively reducing the area occupied by the transistor and increasing its integration density. Furthermore, it facilitates the vertical stacking of multiple capacitor cells above, effectively enhancing the memory integration density of the semiconductor structure.

[0085] In this embodiment, the capacitor structure C0 is connected to the capacitor contact structure SNC, and the capacitor structure C0 includes multiple capacitor units 2 stacked in a direction perpendicular to the capacitor contact structure SNC. That is, the multiple capacitor units can be self-aligned and stacked based on the capacitor contact structure SNC. Furthermore, the stacking method of the multiple capacitor units 2 can be selected and set according to requirements.

[0086] In some embodiments, please refer to Figure 1 Depending on the stacking position of capacitor unit 2, capacitor unit 2 can be divided into bottom capacitor unit C. D Intermediate capacitor unit C M and top capacitor unit C T It is understood that although the stacking positions of the capacitor units 2 are different, each capacitor unit 2 includes: a capacitor connection structure 20, a first electrode 21, a high-k dielectric layer 22, and a second electrode 23. The first electrode 21 and the second electrode 23 can be formed using a metal or metal compound with excellent conductivity, such as titanium nitride (TiN) formed by atomic layer deposition. The high-k dielectric layer 22 can be selected according to actual needs, for example, a silicon nitride layer. This disclosure does not limit this aspect.

[0087] For example, the capacitor connection structure 20 is located vertically above the capacitor contact structure SNC, and in any two adjacent capacitor units 2 in a direction perpendicular to the capacitor contact structure SNC (e.g., the Z direction), the capacitor connection structure 20 is interconnected and connected to the capacitor contact structure SNC. That is, the bottom capacitor unit C D The capacitor connection structure 20 in the middle can be directly connected to the capacitor contact structure SNC, while the capacitor connection structures 20 in other stacked capacitor units 2 can be connected to the capacitor contact structure SNC by connecting the capacitor connection structures 20 below in series.

[0088] Optionally, the capacitor connection structure 20 is formed using an epitaxial growth process. The capacitor connection structure 20 can be a conductive structure made of silicon germanium (SiGe) or other conductive materials that can grow unidirectionally along the (100) crystal plane. The capacitor connection structure 20 is located vertically above the capacitor contact structure SNC, and the capacitor connection structure 20 can be formed based on the self-alignment of the capacitor contact structure SNC. That is, the orthographic projection of the capacitor connection structure 20 on the substrate 1 can overlap with the orthographic projection of the capacitor contact structure SNC on the substrate 1. The capacitor connection structure 20 is, for example, a conductive pillar, and the shape of the orthographic projection of the capacitor connection structure 20 on the substrate 1 can be circular, elliptical, or polygonal, etc., which is not limited in this embodiment.

[0089] For example, the first electrode 21 is located on the sidewall of the capacitor connection structure 20, and is interconnected in any two adjacent capacitor cells 2 in a direction perpendicular to the capacitor contact structure SNC (e.g., the Z direction). A high-k dielectric layer 22 is disposed on the sidewall of the first electrode 21, and is interconnected in any two adjacent capacitor cells 2 in a direction perpendicular to the capacitor contact structure SNC (e.g., the Z direction). The second electrode 23 is disposed on the sidewall of the high-k dielectric layer 22, and is interconnected in any two adjacent capacitor cells 2 in a direction perpendicular to the capacitor contact structure SNC.

[0090] In some embodiments, please continue reading Figure 1 The semiconductor structure also includes: a top dielectric layer 4 covering the capacitor structure C0, and a common source electrode layer 5 located above the top dielectric layer 4. The top dielectric layer 4 has an opening K. The common source electrode layer 5 is connected to the second electrode 23 through the opening K.

[0091] Here, the top dielectric layer 4 is formed of an insulating material, such as at least one layer selected from silicon oxide, silicon nitride, or silicon oxynitride. The top dielectric layer 4 has an opening K and a top capacitor cell C. T The second electrode 23 can be exposed within the aforementioned opening K. The common source electrode layer 5 covers the top dielectric layer 4 and is connected to the second electrode 23 through the opening K, enabling interconnection of the second electrodes 23 in multiple capacitor cells 2 in a direction parallel to the substrate 1 (e.g., the X direction) and providing electrical signals to each second electrode 23. The common source electrode layer 5 can be formed using a metal or metal compound with excellent conductivity, such as silicon germanium (SiGe).

[0092] It is worth mentioning that, please continue reading Figure 1 In some embodiments, multiple capacitive contact structures SNC are arranged in an array on the substrate 1. In any two adjacent capacitor cells 2 in a direction parallel to the substrate 1 (e.g., the X direction), the second electrode 23 is interconnected. That is, in multiple capacitor cells 2 located on the same layer in a direction parallel to the substrate 1 (e.g., the X direction), the second electrode 23 can be interconnected as a single electrode.

[0093] Please continue reading. Figure 1In some embodiments, in any two adjacent capacitor cells 2 in a direction parallel to the substrate 1 (e.g., the X direction), the bottoms of the second electrode 2 are interconnected to form a groove G. The semiconductor structure also includes a support structure 3 located within the groove G. The support structure 3, located within the groove G, can support the capacitor cells 2 formed in a direction perpendicular to the capacitor contact structure SNC (e.g., the Z direction) to enhance the structural stability of the capacitor cells 2, which is beneficial for stacking more layers of capacitor cells 2 to obtain a capacitor structure CO with a larger capacitance.

[0094] Optionally, the upper surface of the support structure 3 facing away from the substrate 1 is flush with the top surface of the second electrode 23 facing away from the substrate 1. That is, the support structure 3 can fill the groove G to ensure that adjacent capacitor units 2 located in the same layer can be effectively supported by the support structure 3 and form a flat surface to facilitate the continued stacking of capacitor units 2.

[0095] It is understandable that the shape and forming material of the support structure 3 can be designed to match the stacking position of the capacitor unit 2 and the structure of the groove G.

[0096] For example, in Figure 1 The top capacitor unit C shown T In this structure, the support structure 3 includes an auxiliary conductive portion 31 connected to the adjacent second electrode 23. That is, the support structure 3 can be composed solely of the auxiliary conductive portion 31. The auxiliary conductive portion 31 can be formed using a metal or metal compound with excellent conductivity, such as germanium-silicon (SiGe). The auxiliary conductive portion 31, connected to the second electrode 23, assists the second electrode 23 in providing an electrical signal, thereby improving the capacitance of the capacitor unit 2. Furthermore, in... Figure 1 The top capacitor unit C shown T In the middle, the support structure 3 is composed of an auxiliary conductive part 31, which can be exposed in the opening K of the top dielectric layer 4 and synchronously connected to the common source electrode layer 5 with the second electrode 23.

[0097] For example, in Figure 1 The bottom capacitor unit C shown D and intermediate capacitor unit C MIn this structure, the support structure 3 includes an auxiliary conductive portion 31 and a support portion 32 located above the auxiliary conductive portion 31; the auxiliary conductive portion 31 is connected to the adjacent second electrode 23. The auxiliary conductive portion 31 can be formed of a metal or metal compound with excellent conductivity, such as silicon germanium (SiGe). The auxiliary conductive portion 31, connected to the second electrode 23, assists the second electrode 23 in providing an electrical signal, thereby improving the capacitance of the capacitor unit 2. The support portion 32 can be formed of an insulating material, such as silicon nitride. The support portion 32 can have a high hardness, for example, a hardness greater than that of silicon germanium. The upper surface of the support portion 32 facing away from the substrate 1 is flush with the top surface of the second electrode 23 facing away from the substrate 1. This enhances the support capacity of the support structure 3.

[0098] In addition, Figure 1 The bottom capacitor unit C shown D and intermediate capacitor unit C M In the middle, the support structure 3 can also adopt a top capacitor unit C. T The supporting structure used in the middle is 3.

[0099] In other embodiments, please refer to Figure 2 Depending on the stacking position of capacitor unit 2, capacitor unit 2 can be divided into bottom capacitor unit C. D Intermediate capacitor unit C M and top capacitor unit C T It can be understood that although the stacking positions of the capacitor units 2 are different, the capacitor unit 2 at any position includes: a first electrode 21, a high-k dielectric layer 22, and a second electrode 23.

[0100] For example, such as Figure 2 As shown, capacitor unit 2 includes: a first electrode 21, a high-k dielectric layer 22, and a second electrode 23. The first electrode 21 is located vertically above the capacitor contact structure SNC, and in any two adjacent capacitor units 2 in a direction perpendicular to the capacitor contact structure SNC (e.g., the Z direction), the first electrode 21 is interconnected and connected to the capacitor contact structure SNC. That is, the bottom capacitor unit C... D The first electrode 21 in the capacitor can be directly connected to the capacitor contact structure SNC, while the first electrodes 21 in other stacked capacitor units 2 can be connected to the capacitor contact structure SNC by connecting them in series with the first electrodes 21 below.

[0101] Optionally, the first electrode 21 is formed using an epitaxial growth process. The first electrode 21 can be a conductive structure made of germanium silicon (SiGe) or other conductive materials that can grow unidirectionally along the (100) crystal plane. The first electrode 21 is located vertically above the capacitive contact structure SNC, and the first electrode 21 can be formed based on the self-alignment of the capacitive contact structure SNC. That is, the orthogonal projection of the first electrode 21 on the substrate 1 can overlap with the orthogonal projection of the capacitive contact structure SNC on the substrate 1. The first electrode 21 is, for example, a conductive pillar, and the shape of the orthogonal projection of the first electrode 21 on the substrate 1 can be circular, elliptical, or polygonal, etc., which is not limited in this embodiment.

[0102] For example, a high-k dielectric layer 22 is disposed on the sidewall of the first electrode 21, and the high-k dielectric layer 22 is interconnected in any two adjacent capacitor cells 2 in a direction perpendicular to the capacitor contact structure SNCC (e.g., the Z direction). A second electrode 23 is disposed on the sidewall of the high-k dielectric layer 22, and the second electrode 23 is interconnected in any two adjacent capacitor cells 2 in a direction perpendicular to the capacitor contact structure SNC (e.g., the Z direction).

[0103] In some embodiments, please continue reading Figure 2 A barrier layer 24 is also disposed between the first electrode 21 and the high-k dielectric layer 22. The barrier layer 24 is, for example, a titanium nitride layer, a titanium layer, a tantalum layer, or a tantalum nitride layer. The barrier layer 24 can prevent molecular diffusion between the first electrode 21 and the high-k dielectric layer 22 to ensure the electrical performance stability of the first electrode 21. For example, the first electrode 21 can be a conductive structure composed of germanium silicon (SiGe) or other conductive materials that can grow unidirectionally along the (100) crystal plane, and the high-k dielectric layer 22 is an oxide layer with a high dielectric constant. The barrier layer 24 can effectively prevent the first electrode 21 from being oxidized by the diffusion of oxygen ions in the high-k dielectric layer 22.

[0104] Furthermore, the second electrode 23 can be formed using a metal or metal compound with excellent conductivity, such as titanium nitride (TiN) formed by atomic layer deposition. The high-k dielectric layer 22 can be selected according to actual needs, for example, a silicon nitride layer. This disclosure does not limit this aspect.

[0105] In some embodiments, please continue reading Figure 2 The top-layer capacitor unit 2 (i.e., the aforementioned top-layer capacitor unit C) TThe high-k dielectric layer 22 in the capacitor cell 2 further covers the top surface of the first electrode 21 facing away from the substrate 1, and the second electrode 23 in the top capacitor cell 2 is also covered by the high-k dielectric layer 22 facing away from the top surface of the substrate 1. The semiconductor structure also includes a common source electrode layer 5 covering the sidewalls of the second electrode 23 and the top surface of the second electrode 23 facing away from the substrate 1. The common source electrode layer 5 covers the second electrode 23, enabling interconnection of the second electrodes 23 in multiple capacitor cells 2 in a direction parallel to the substrate 1 (e.g., the X direction), and providing electrical signals to each second electrode 23. The common source electrode layer 5 can be formed using a metal or metal compound with excellent conductivity, such as silicon germanium (SiGe).

[0106] It is worth mentioning that, please continue reading Figure 2 In some embodiments, multiple capacitive contact structures SNC are arranged in an array on the substrate 1. In any two adjacent capacitor cells 2 in a direction parallel to the substrate 1 (e.g., the X direction), the second electrode 23 is interconnected. That is, in multiple capacitor cells 2 located on the same layer in a direction parallel to the substrate 1 (e.g., the X direction), the second electrode 23 can be interconnected as a single electrode.

[0107] Please continue reading. Figure 2 In some embodiments, in any two adjacent capacitor cells 2 in a direction parallel to the substrate 1 (e.g., the X direction), the bottoms of the second electrode 2 are interconnected to form a groove G. The semiconductor structure also includes a support structure 3 located within the groove G. The support structure 3, located within the groove G, can support the capacitor cells 2 formed in a direction perpendicular to the capacitor contact structure SNC (e.g., the Z direction) to enhance the structural stability of the capacitor cells 2, which is beneficial for stacking more layers of capacitor cells 2 to obtain a capacitor structure CO with a larger capacitance.

[0108] Optionally, the upper surface of the support structure 3 facing away from the substrate 1 is flush with the top surface of the second electrode 23 facing away from the substrate 1. That is, the support structure 3 can fill the groove G to ensure that adjacent capacitor units 2 located in the same layer can be effectively supported by the support structure 3 and form a flat surface to facilitate the continued stacking of capacitor units 2.

[0109] It is understandable that the shape and forming material of the support structure 3 can be designed to match the stacking position of the capacitor unit 2 and the structure of the groove G.

[0110] For example, in Figure 2 The top capacitor unit C shown T In the middle, the common source electrode layer 5 covers the second electrode 23 and can fill the top capacitor unit C. T The groove G between adjacent second electrodes 23. That is, the top capacitor unit C. TThe groove G between adjacent second electrodes 23 does not need to be provided with a support structure 3, so that the filling part of the common source electrode layer 5 can be used for support.

[0111] For example, in Figure 2 The bottom capacitor unit C shown D and intermediate capacitor unit C M In this structure, the support structure 3 includes an auxiliary conductive portion 31 and a support portion 32 located above the auxiliary conductive portion 31; the auxiliary conductive portion 31 is connected to the adjacent second electrode 23. The auxiliary conductive portion 31 can be formed of a metal or metal compound with excellent conductivity, such as silicon germanium (SiGe). The auxiliary conductive portion 31, connected to the second electrode 23, assists the second electrode 23 in providing an electrical signal, thereby improving the capacitance of the capacitor unit 2. The support portion 32 can be formed of an insulating material, such as silicon nitride. The support portion 32 can have a high hardness, for example, a hardness greater than that of silicon germanium. The upper surface of the support portion 32 facing away from the substrate 1 is flush with the top surface of the second electrode 23 facing away from the substrate 1. This enhances the support capacity of the support structure 3.

[0112] In addition, Figure 2 The bottom capacitor unit C shown D and intermediate capacitor unit C M In this configuration, the support structure 3 can also employ another structure, for example, the support structure 3 may include an auxiliary conductive portion 31 connected to the adjacent second electrode 23. That is, the support structure 3 may consist solely of the auxiliary conductive portion 31. The auxiliary conductive portion 31 may be formed using a metal or metal compound with excellent conductivity, such as silicon germanium (SiGe). The auxiliary conductive portion 31 is connected to the second electrode 23, which can assist the second electrode 23 in providing an electrical signal, thereby improving the capacitance of the capacitor unit 2.

[0113] The semiconductor structure provided in this disclosure, as described above, allows for the stacking of multiple capacitor cells 2 in a direction perpendicular to the capacitor contact structure SNC (e.g., the Z direction) to form a capacitor structure C0. This reduces the aspect ratio of each capacitor cell 2 layer while continuously decreasing the radial dimension of the capacitor structure, avoiding high aspect ratio etching and eliminating the increased etching difficulty caused by higher aspect ratios. This not only significantly reduces the fabrication difficulty of the capacitor structure C0 but also effectively increases its stability, preventing stacking collapse. Furthermore, by using epitaxial growth and self-alignment to stack the capacitor cells 2 vertically above the capacitor contact structure SNC, this disclosure reduces the number of photomasks used and effectively avoids stacking deviations, further reducing the fabrication difficulty of the capacitor structure.

[0114] Furthermore, by repeatedly stacking the capacitor unit 2, this embodiment of the present disclosure can obtain a capacitor structure C0 with a relatively high height, ensuring the formation of a capacitor structure C0 with a large capacitor area. This allows for the formation of a stable capacitor structure C0 with a large capacitance even as semiconductor structure dimensions are repeatedly miniaturized. Consequently, it effectively improves the electrical performance and production yield of the semiconductor structure.

[0115] On the other hand, some embodiments of this disclosure provide a method for fabricating a semiconductor structure, used to prepare the semiconductor structures described in the above embodiments. This fabrication method also possesses all the technical advantages of the aforementioned semiconductor structures. These will not be repeated here. Please refer to [link to relevant documentation]. Figure 3 The preparation method includes the following steps.

[0116] S100 provides a substrate with a capacitive contact structure on it.

[0117] S200: Multiple capacitor units are stacked in a direction perpendicular to the capacitor contact structure to form a capacitor structure. The capacitor structure is connected to the capacitor contact structure.

[0118] It is understandable that different capacitor cell structures require different fabrication methods. The following sections will address these differences. Figure 1 and Figure 2 The fabrication methods for the two semiconductor structures shown are described in detail.

[0119] Please see Figure 4 In some embodiments, this preparation method is used to prepare, for example... Figure 1 The semiconductor structure is shown. In step S200, multiple capacitor units are stacked in a direction perpendicular to the capacitor contact structure to form a capacitor structure, including the following steps.

[0120] S210, a bottom capacitor unit is formed vertically above the capacitor contact structure.

[0121] For example, a capacitor connection structure is formed vertically above the capacitor contact structure, and a first electrode, a high-k dielectric layer, and a second electrode are sequentially formed on the sidewall of the capacitor connection structure.

[0122] S220, with intermediate capacitor units stacked vertically above the bottom capacitor unit.

[0123] For example, the intermediate capacitor unit can be one or more layers. Taking the bottom capacitor unit as the first layer capacitor unit, the number of intermediate capacitor unit layers can be N+1 layers, where N is a positive integer and 2≤N+1≤M. Accordingly, forming the N+1th layer intermediate capacitor unit includes: forming the N+1th layer capacitor connection structure vertically above the Nth layer capacitor connection structure, and sequentially forming a first electrode, a high-K dielectric layer, and a second electrode on the sidewall of the N+1th layer capacitor connection structure. That is, the stacking of intermediate capacitor units can start from the second layer and stop at the Mth layer.

[0124] In this embodiment of the disclosure, the capacitor connection structure can be repeatedly epitaxially grown to stack capacitor units in a self-aligned manner and increase the height of the capacitor structure. The number of stackings is unlimited and can be selected according to the requirements.

[0125] S230, with the top capacitor unit stacked vertically above the middle capacitor unit.

[0126] For example, a capacitor connection structure of layer M+1 is formed vertically above the capacitor connection structure of layer M, and a first electrode, a high-K dielectric layer and a second electrode are sequentially formed on the sidewall of the capacitor connection structure of layer M+1.

[0127] In some embodiments, please continue reading Figure 4 The preparation method further includes the following steps.

[0128] S300 forms the top dielectric material layer covering the top capacitor unit.

[0129] S400, the top dielectric material layer is patterned to form the top dielectric layer. The top dielectric layer has an opening, and the second electrode of the top capacitor unit is exposed within the opening.

[0130] S500, a common source electrode layer is formed covering the top dielectric layer, and the common source electrode layer is connected to the second electrode.

[0131] To more clearly illustrate the above preparation method, please refer to the following examples. Figure 4 and Figures 5 to 22 understand.

[0132] In step S100, please refer to Figure 5 A substrate 1 is provided, on which a capacitive contact structure SNC is provided.

[0133] Here, the arrangement of the substrate 1 and the capacitor contact structure SNC can be found in the relevant descriptions in some of the foregoing embodiments.

[0134] It is understandable that after the capacitor contact structure SNC is formed on the substrate 1, the surface of the substrate 1 is usually polished, for example, by chemical mechanical polishing, so that the surface of the substrate 1 has a better surface quality, which is conducive to the subsequent epitaxial growth of the capacitor connection structure 20 or the first electrode 21 on the substrate 1.

[0135] In step S210, please refer to Figures 6-10 A bottom capacitor unit C is formed vertically above the capacitor contact structure SNC. D This includes steps S210A to S210D.

[0136] S210A, please refer to Figure 6 A capacitor connection structure 20 is formed vertically above the capacitor contact structure SNC.

[0137] For example, the capacitor connection structure 20 is formed by an epitaxial growth process. That is, the capacitor connection structure 20 can be epitaxially grown on the surface of the capacitor contact structure SNC to achieve self-alignment between the capacitor connection structure 20 and the capacitor contact structure SNC.

[0138] S210B, please refer to Figure 7 A first electrode 21 is formed on the sidewall of the capacitor connection structure 20.

[0139] S210C, please refer to Figure 8 A high-k dielectric material layer 220 and a second electrode material layer 230 are deposited sequentially.

[0140] Optionally, in an example where the semiconductor structure also includes a support structure 3, please refer to... Figure 8 S210C also includes: an auxiliary conductive material layer 310 deposited over the second electrode material layer 230. See also [link to relevant documentation]. Figure 9 The aforementioned preparation method further includes: removing part of the auxiliary conductive material layer 310 and forming an auxiliary conductive part 31 between any two adjacent capacitor units 2 in a direction parallel to the substrate 1.

[0141] In some examples where the support structure 3 also includes a support portion 32, please refer to Figure 9 The aforementioned preparation method further includes: depositing a support material layer 320 covering the second electrode material layer 230 and the auxiliary conductive portion 31. Accordingly, please refer to... Figure 10 The aforementioned preparation method further includes: removing part of the support material layer 320, and forming a support portion 32 between any two adjacent capacitor units 2 in a direction parallel to the substrate 1. The support portion 32 is located above the auxiliary conductive portion 31 and together with the auxiliary conductive portion 31 constitutes the support structure 3.

[0142] Here, it can be understood that the preparation method of the support structure 3 can be adaptively adjusted according to the different support structures 3.

[0143] S210D, please refer to the following: Figure 10 Part of the high-k dielectric material layer 220 and part of the second electrode material layer 230 are removed to form a high-k dielectric layer 22 located on the sidewall of the first electrode 21 and a second electrode 23 located on the sidewall of the high-k dielectric layer 22. This completes the bottom capacitor unit C. D Preparation of .

[0144] In step S220, please refer to Figures 11-15 At the bottom capacitor unit C D The intermediate capacitor units C are stacked vertically upwards in layers. M This includes steps S220A to S220D.

[0145] S220A, please refer to Figure 11 At the bottom capacitor unit C D An intermediate capacitor unit C is formed vertically above the intermediate capacitor connection structure 20. M The first layer of capacitor connection structure 20.

[0146] For example, the capacitor connection structure 20 is formed by an epitaxial growth process. That is, the upper capacitor connection structure 20 can be epitaxially grown on the surface of the lower capacitor connection structure 20 to achieve self-alignment of the upper and lower capacitor connection structures 20.

[0147] It is understandable that after the capacitor connection structure 20 is formed, any intermediate capacitor unit C in any layer... M The fabrication methods for other structures are the same; therefore, the following will only focus on the fabrication of a single intermediate capacitor unit C. M The preparation of other structures was illustrated using examples.

[0148] S220B, please refer to Figure 12 A first electrode 21 is formed on the sidewall of the capacitor connection structure 20.

[0149] S220C, please refer to Figure 13 A high-k dielectric material layer 220 and a second electrode material layer 230 are deposited sequentially.

[0150] Optionally, in an example where the semiconductor structure also includes support structure 3, please refer to [link to relevant documentation]. Figure 13 S220C also includes: an auxiliary conductive material layer 310 deposited over the second electrode material layer 230. See also [link to relevant documentation]. Figure 14 The aforementioned preparation method further includes: removing part of the auxiliary conductive material layer 310 and forming an auxiliary conductive part 31 between any two adjacent capacitor units 2 in a direction parallel to the substrate 1.

[0151] In some examples where the support structure 3 also includes a support portion 32, please refer to Figure 14 The aforementioned preparation method further includes: depositing a support material layer 320 covering the second electrode material layer 230 and the auxiliary conductive portion 31. Accordingly, please refer to... Figure 15 The aforementioned preparation method further includes: removing part of the support material layer 320, and forming a support portion 32 between any two adjacent capacitor units 2 in a direction parallel to the substrate 1. The support portion 32 is located above the auxiliary conductive portion 31 and together with the auxiliary conductive portion 31 constitutes the support structure 3.

[0152] Here, it can be understood that the preparation method of the support structure 3 can be adaptively adjusted according to the different support structures 3.

[0153] S220D, please refer to the following: Figure 15 Part of the high-k dielectric material layer 220 and part of the second electrode material layer 230 are removed to form a high-k dielectric layer 22 located on the sidewall of the first electrode 21 and a second electrode 23 located on the sidewall of the high-k dielectric layer 22. This completes the intermediate capacitor unit C. M Preparation of .

[0154] In step S230, please refer to Figures 16-19 In the intermediate capacitor unit C M Vertically stacked top capacitor unit C T This includes steps S230A to S230D.

[0155] S230A, please refer to Figure 16 In the intermediate capacitor unit C M The top capacitor unit C is formed vertically above the top layer capacitor connection structure 20. T Capacitor connection structure 20.

[0156] For example, the capacitor connection structure 20 is formed by an epitaxial growth process. That is, the upper capacitor connection structure 20 can be epitaxially grown on the surface of the lower capacitor connection structure 20 to realize the top capacitor unit C. T and intermediate capacitor unit C M Self-alignment of the capacitor connection structure 20.

[0157] S230B, please refer to Figure 17 A first electrode 21 is formed on the sidewall of the capacitor connection structure 20.

[0158] S230C, please refer to Figure 18 A high-k dielectric material layer 220 and a second electrode material layer 230 are deposited sequentially.

[0159] Optionally, in an example where the semiconductor structure also includes support structure 3, please refer to [link to relevant documentation]. Figure 18S230C also includes: an auxiliary conductive material layer 310 deposited over the second electrode material layer 230. See also [link to relevant documentation]. Figure 19 The aforementioned preparation method further includes: removing a portion of the auxiliary conductive material layer 310, and forming an auxiliary conductive portion 31 between any two adjacent capacitor units 2 in a direction parallel to the substrate 1. Thus, the auxiliary conductive portion 31 can be used to construct a support structure 3.

[0160] Here, it can be understood that the preparation method of the support structure 3 can be adaptively adjusted according to the different support structures 3.

[0161] S230D, please refer to the following: Figure 19 Part of the high-k dielectric material layer 220 and part of the second electrode material layer 230 are removed to form a high-k dielectric layer 22 located on the sidewall of the first electrode 21 and a second electrode 23 located on the sidewall of the high-k dielectric layer 22. This completes the top capacitor unit C. T Preparation of .

[0162] In step S300, please refer to Figure 20 Forming a capacitor cell C covering the top T The top layer of dielectric material 40.

[0163] In step S400, please refer to Figure 21 The top dielectric material layer 40 is patterned to form the top dielectric layer 4. The top dielectric layer 4 has an opening K, in which the second electrode 23 of the top capacitor unit CT is exposed.

[0164] Alternatively, please continue reading Figure 21 The auxiliary conductive part 31 fills the top capacitor unit C T The auxiliary conductive part 31 is also simultaneously exposed in the opening K of the top dielectric layer 4 in the groove G between adjacent second electrodes 23.

[0165] In step S500, please refer to Figure 22 A common source electrode layer 5 is formed covering the top dielectric layer 4, and the common source electrode layer 5 and the top capacitor unit C are connected. T The second electrode 23 is connected.

[0166] Alternatively, please continue reading Figure 22 The common source electrode layer 5 is also connected to the auxiliary conductive part 31 exposed in the opening K of the top dielectric layer 4.

[0167] Please see Figure 23 In some embodiments, this preparation method is used to prepare, for example... Figure 2 The semiconductor structure is shown. In step S200, multiple capacitor units are stacked in a direction perpendicular to the capacitor contact structure to form a capacitor structure, including the following steps.

[0168] S210' forms a bottom capacitor unit vertically above the capacitor contact structure.

[0169] For example, a first electrode is formed vertically above the capacitive contact structure, and a high-k dielectric layer and a second electrode are sequentially formed on the sidewall of the first electrode.

[0170] S220' consists of stacking intermediate capacitor cells vertically above the bottom capacitor cell.

[0171] For example, the intermediate capacitor unit can be one or more layers. Taking the bottom capacitor unit as the first layer capacitor unit, the number of intermediate capacitor units can be N+1 layers, where N is a positive integer and 2≤N+1≤M. Accordingly, forming the N+1th intermediate capacitor unit includes: forming the N+1th first electrode vertically above the Nth first electrode, and sequentially forming a high-K dielectric layer and a second electrode on the sidewall of the N+1th first electrode. That is, the stacking of intermediate capacitor units can start from the second layer and stop at the Mth layer.

[0172] S230', with the top capacitor cell stacked vertically above the middle capacitor cell.

[0173] For example, a first electrode of layer M+1 is formed vertically above the first electrode of layer M, and a high-K dielectric layer and a second electrode are sequentially formed on the sidewall of the first electrode of layer M+1.

[0174] Optionally, before sequentially forming a high-k dielectric layer and a second electrode on the sidewall of the first electrode, the preparation method further includes: forming a barrier layer on the sidewall of the first electrode, and then sequentially forming a high-k dielectric layer and a second electrode in a direction away from the first electrode.

[0175] In some embodiments, please continue reading Figure 23 The preparation method further includes the following steps.

[0176] S300', forming a common source electrode layer covering the sidewall of the second electrode in the top capacitor cell and the second electrode facing away from the top surface of the substrate.

[0177] To more clearly illustrate the above preparation method, please refer to the following examples. Figures 23-34 understand.

[0178] In step S210', please refer to Figures 24-27 A bottom capacitor unit C is formed vertically above the capacitor contact structure SNC. D This includes steps S210'A to S210'C.

[0179] S210'A, please refer to Figure 24A first electrode 21 is formed vertically above the capacitive contact structure SNC.

[0180] For example, the first electrode 21 is formed by an epitaxial growth process. That is, the first electrode 21 can be epitaxially grown on the surface of the capacitor contact structure SNC to achieve self-aligned stacking of the first electrode 21 and the capacitor contact structure SNC.

[0181] S210'B, please refer to Figure 25 A high-k dielectric material layer 220 and a second electrode material layer 230 are sequentially deposited on the sidewall of the first electrode 21.

[0182] Alternatively, in an example where the semiconductor structure also includes a barrier layer 24, please refer to [link to relevant documentation]. Figure 25 Before sequentially depositing a high-K dielectric material layer 220 and a second electrode material layer 230 on the sidewall of the first electrode 21, the preparation method further includes: depositing a barrier material layer 240 on the sidewall of the first electrode 21, and then sequentially depositing a high-K dielectric material layer 220 and a second electrode material layer 230 on the barrier material layer 240 in a direction away from the first electrode 21.

[0183] Optionally, in an example where the semiconductor structure also includes support structure 3, please refer to [link to relevant documentation]. Figure 25 S210'B further includes: depositing an auxiliary conductive material layer 310 covering the second electrode material layer 230. See also [link to relevant documentation]. Figure 26 The aforementioned preparation method further includes: removing part of the auxiliary conductive material layer 310 and forming an auxiliary conductive part 31 between any two adjacent capacitor units 2 in a direction parallel to the substrate 1.

[0184] In some examples where the support structure 3 also includes a support part 32, please refer to [the relevant documentation]. Figure 26 The aforementioned preparation method further includes: depositing a support material layer 320 covering the second electrode material layer 230 and the auxiliary conductive portion 31. Accordingly, please refer to... Figure 27 The aforementioned preparation method further includes: removing part of the support material layer 320, and forming a support portion 32 between any two adjacent capacitor units 2 in a direction parallel to the substrate 1. The support portion 32 is located above the auxiliary conductive portion 31 and together with the auxiliary conductive portion 31 constitutes the support structure 3.

[0185] Here, it can be understood that the preparation method of the support structure 3 can be adaptively adjusted according to the different support structures 3.

[0186] S210'C, please refer to further details. Figure 27 Part of the high-K dielectric material layer 220 and part of the second electrode material layer 230 are removed to form a high-K dielectric layer 22 located on the sidewall of the first electrode 21 and a second electrode 23 located on the sidewall of the high-K dielectric layer 22.

[0187] Alternatively, please continue reading Figure 27 In an embodiment where a barrier material layer 240 is deposited, a portion of the barrier material layer 240 is removed to form a barrier layer 24 located on the sidewall of the first electrode 21.

[0188] Thus, the bottom capacitor unit C is completed. D Preparation of .

[0189] In step S220', please refer to Figures 28-31 At the bottom capacitor unit C D The intermediate capacitor units C are stacked vertically upwards in layers. M This includes steps S220'A to S220'C.

[0190] S220'A, please refer to Figure 28 At the bottom capacitor unit C D An intermediate capacitor unit C is formed vertically above the first electrode 21. M The first electrode 21 of the first layer.

[0191] For example, the first electrode 21 is formed by an epitaxial growth process. That is, the upper first electrode 21 can be epitaxially grown on the surface of the lower first electrode 21 to achieve self-aligned stacking of the upper and lower first electrodes 21.

[0192] It is understandable that after the formation of the first electrode 21, any intermediate capacitor unit C in any layer... M The fabrication methods for other structures are the same; therefore, the following will only focus on the fabrication of a single intermediate capacitor unit C. M The preparation of other structures was illustrated using examples.

[0193] S220'B, please refer to Figure 29 A high-k dielectric material layer 220 and a second electrode material layer 230 are sequentially deposited on the sidewall of the first electrode 21.

[0194] Alternatively, in an example where the semiconductor structure also includes a barrier layer 24, please refer to [link to relevant documentation]. Figure 29 Before sequentially depositing a high-K dielectric material layer 220 and a second electrode material layer 230 on the sidewall of the first electrode 21, the preparation method further includes: depositing a barrier material layer 240 on the sidewall of the first electrode 21, and then sequentially depositing a high-K dielectric material layer 220 and a second electrode material layer 230 on the barrier material layer 240 in a direction away from the first electrode 21.

[0195] Optionally, in an example where the semiconductor structure also includes support structure 3, please refer to [link to relevant documentation]. Figure 29 S220'B further includes: depositing an auxiliary conductive material layer 310 covering the second electrode material layer 230. See also [link to relevant documentation]. Figure 30 The aforementioned preparation method further includes: removing part of the auxiliary conductive material layer 310 and forming an auxiliary conductive part 31 between any two adjacent capacitor units 2 in a direction parallel to the substrate 1.

[0196] In some examples where the support structure 3 also includes a support part 32, please refer to [the relevant documentation]. Figure 30 The aforementioned preparation method further includes: depositing a support material layer 320 covering the second electrode material layer 230 and the auxiliary conductive portion 31. Accordingly, please refer to... Figure 31 The aforementioned preparation method further includes: removing part of the support material layer 320, and forming a support portion 32 between any two adjacent capacitor units 2 in a direction parallel to the substrate 1. The support portion 32 is located above the auxiliary conductive portion 31 and together with the auxiliary conductive portion 31 constitutes the support structure 3.

[0197] Here, it can be understood that the preparation method of the support structure 3 can be adaptively adjusted according to the different support structures 3.

[0198] S220'C, please refer to further details. Figure 31 Part of the high-K dielectric material layer 220 and part of the second electrode material layer 230 are removed to form a high-K dielectric layer 22 located on the sidewall of the first electrode 21 and a second electrode 23 located on the sidewall of the high-K dielectric layer 22.

[0199] Alternatively, please continue reading Figure 31 In an embodiment where a barrier material layer 240 is deposited, a portion of the barrier material layer 240 is removed to form a barrier layer 24 located on the sidewall of the first electrode 21.

[0200] Thus, the intermediate capacitor unit C is completed. M Preparation of .

[0201] In step S230, please refer to Figure 32 and Figure 33 In the intermediate capacitor unit C M Vertically stacked top capacitor unit C T This includes steps S230'A to S230'B.

[0202] S230'A, please refer to Figure 32 In the intermediate capacitor unit C M The top capacitor unit C is formed vertically above the first electrode 21 in the middle layer. T The first electrode 21.

[0203] For example, the first electrode 21 is formed by an epitaxial growth process. That is, the upper first electrode 21 can be epitaxially grown on the surface of the lower first electrode 21 to realize the top capacitor unit C. T and intermediate capacitor unit CM Self-aligned stacking of the first electrode 21.

[0204] S230'B, please refer to Figure 33 A high-k dielectric layer 22 and a second electrode layer 23 are sequentially deposited on the structure formed by the first electrode 21. The high-k dielectric layer 22 is located at least on the sidewall of the first electrode 21 and on the top surface of the first electrode 21 away from the substrate 1, and the second electrode 23 covers the sidewall of the high-k dielectric layer and the top surface of the high-k dielectric layer away from the substrate.

[0205] Alternatively, in an example where the semiconductor structure also includes a barrier layer 24, please refer to [link to relevant documentation]. Figure 33 Before sequentially depositing a high-K dielectric layer 22 and a second electrode layer 23 on the structure obtained for forming the first electrode 21, the preparation method further includes: depositing a barrier layer 24 on the structure obtained for forming the first electrode 21, and then sequentially depositing a high-K dielectric layer 22 and a second electrode layer 23 on the barrier layer 24 in a direction away from the first electrode 21.

[0206] Thus, the top capacitor unit C is completed. T Preparation of .

[0207] In step S300', please refer to Figure 34 Forming a capacitor cell C covering the top T The sidewall of the second electrode 23 and the common source electrode layer 5 of the second electrode 23 facing away from the top surface of the substrate 1.

[0208] The common source electrode layer 5 covers the second electrode 23, enabling interconnection of the second electrodes 23 in multiple capacitor cells 2 in a direction parallel to the substrate 1 and providing electrical signals to each second electrode 23. The common source electrode layer 5 can be formed by deposition of a metal or metal compound with excellent conductivity, such as silicon germanium (SiGe). Furthermore, the common source electrode layer 5, covering the second electrode 23, can fill the top capacitor cell C. T The groove G between adjacent second electrodes 23. That is, the top capacitor unit C. T The groove G between adjacent second electrodes 23 does not need to be provided with a support structure 3, so that the filling part of the common source electrode layer 5 can be used for support.

[0209] The semiconductor fabrication method provided in this disclosure is used to fabricate the semiconductor structures described in some of the above embodiments. This fabrication method also possesses all the technical advantages of the aforementioned semiconductor structures, and will not be detailed here.

[0210] Furthermore, the deposition processes mentioned in the embodiments of this disclosure include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0211] It should be understood that the execution of some steps in the embodiments of this disclosure is not strictly limited in order; these steps can be executed simultaneously or in other orders. Moreover, in the embodiments of this disclosure, at least some steps of each step of the preparation method may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0212] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0213] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a capacitive contact structure; A capacitor structure connected to the capacitor contact structure, the capacitor structure comprising a plurality of capacitor units stacked in a direction perpendicular to the capacitor contact structure; The capacitor unit includes: a capacitor connection structure, a first electrode, a second electrode, and a high-k dielectric layer; The capacitor connection structure is prepared layer by layer by epitaxial growth self-alignment and electrically connected to the capacitor contact structure. Each capacitor unit adopts a structure in which a first electrode, a high-K dielectric layer and a second electrode are sequentially wrapped around the sidewall of the capacitor connection structure.

2. The semiconductor structure according to claim 1, characterized in that, The capacitor connection structure is located vertically above the capacitor contact structure, and in any two adjacent capacitor units in the direction vertical to the capacitor contact structure, the capacitor connection structure is interconnected and connected to the capacitor contact structure. The first electrode is located on the sidewall of the capacitor connection structure, and in any two adjacent capacitor units in the direction perpendicular to the capacitor contact structure, the first electrode is interconnected. The high-K dielectric layer is disposed on the sidewall of the first electrode, and the high-K dielectric layer is interconnected in any two adjacent capacitor cells in the direction perpendicular to the capacitor contact structure. The second electrode is disposed on the sidewall of the high-k dielectric layer, and the second electrode is interconnected in any two adjacent capacitor cells in the direction perpendicular to the capacitor contact structure.

3. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure further includes: a top dielectric layer covering the capacitor structure, and a common source electrode layer located above the top dielectric layer; The top dielectric layer has an opening; the common source electrode layer is connected to the second electrode through the opening.

4. The semiconductor structure according to claim 2, characterized in that, The plurality of said capacitive contact structures are arranged in an array on the substrate; wherein, in any two adjacent said capacitive units in a direction parallel to the substrate, the second electrode is interconnected.

5. The semiconductor structure according to claim 4, characterized in that, In any two adjacent capacitor cells in a direction parallel to the substrate, the bottoms of the second electrodes are interconnected and form a groove; The semiconductor structure also includes a support structure located within the groove.

6. The semiconductor structure according to claim 5, characterized in that, The upper surface of the support structure facing away from the substrate is flush with the top surface of the second electrode facing away from the substrate.

7. The semiconductor structure according to claim 5, characterized in that, The support structure includes: an auxiliary conductive portion connected to the adjacent second electrode; Alternatively, the support structure may include: an auxiliary conductive portion and a support portion located above the auxiliary conductive portion; the auxiliary conductive portion is connected to the adjacent second electrode.

8. The semiconductor structure according to claim 1, characterized in that, The first electrode is located vertically above the capacitor contact structure, and in any two adjacent capacitor cells in the direction perpendicular to the capacitor contact structure, the first electrode is interconnected and connected to the capacitor contact structure. The high-K dielectric layer is disposed on the sidewall of the first electrode, and the high-K dielectric layer is interconnected in any two adjacent capacitor cells in the direction perpendicular to the capacitor contact structure. The second electrode is disposed on the sidewall of the high-k dielectric layer, and the second electrode is interconnected in any two adjacent capacitor cells in the direction perpendicular to the capacitor contact structure.

9. The semiconductor structure according to claim 8, characterized in that, A barrier layer exists between the high-K dielectric layer and the first electrode.

10. The semiconductor structure according to claim 8, characterized in that, The high-K dielectric layer in the top capacitor cell also covers the top surface of the first electrode away from the substrate, and the second electrode in the top capacitor cell also covers the top surface of the high-K dielectric layer away from the substrate; The semiconductor structure further includes a common source electrode layer covering the sidewall of the second electrode and the second electrode facing away from the top surface of the substrate.

11. The semiconductor structure according to any one of claims 8 to 10, characterized in that, The plurality of said capacitive contact structures are arranged in an array on the substrate; wherein, in any two adjacent said capacitive units in a direction parallel to the substrate, the second electrode is interconnected.

12. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate has a capacitive contact structure; Multiple capacitor units are stacked in a direction perpendicular to the capacitor contact structure to form a capacitor structure, and the capacitor structure is connected to the capacitor contact structure. The capacitor unit includes: a capacitor connection structure, a first electrode, a second electrode, and a high-k dielectric layer; The capacitor connection structure is prepared layer by layer by epitaxial growth self-alignment and electrically connected to the capacitor contact structure. Each capacitor unit adopts a structure in which a first electrode, a high-K dielectric layer and a second electrode are sequentially wrapped around the sidewall of the capacitor connection structure.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The stacking of multiple capacitor units in a direction perpendicular to the capacitor contact structure to form a capacitor structure includes: A bottom capacitor unit is formed vertically above the capacitor contact structure, including: forming a capacitor connection structure vertically above the capacitor contact structure, and sequentially forming a first electrode, a high-K dielectric layer, and a second electrode on the sidewall of the capacitor connection structure; Intermediate capacitor units are stacked layer by layer vertically above the bottom capacitor unit; wherein, forming the N+1th layer of the intermediate capacitor unit includes: forming the N+1th layer of capacitor connection structure vertically above the Nth layer of capacitor connection structure, and sequentially forming a first electrode, a high-K dielectric layer, and a second electrode on the sidewall of the N+1th layer of capacitor connection structure; wherein, N is a positive integer and 2≤N+1≤M; Stacking a top capacitor unit vertically above the intermediate capacitor unit includes: forming an M+1 layer capacitor connection structure vertically above the M layer capacitor connection structure, and sequentially forming a first electrode, a high-K dielectric layer, and a second electrode on the sidewall of the M+1 layer capacitor connection structure.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The preparation method further includes: A top dielectric material layer is formed to cover the top capacitor unit; The top dielectric material layer is patterned to form a top dielectric layer; the top dielectric layer has an opening, and the second electrode of the top capacitor unit is exposed in the opening; A common source electrode layer is formed covering the top dielectric layer, and the common source electrode layer is connected to the second electrode.

15. The method for preparing a semiconductor structure according to claim 13, characterized in that, The first electrode, a high-k dielectric layer, and a second electrode are sequentially formed on the sidewall of the capacitor connection structure, including: A first electrode is formed on the sidewall of the capacitor connection structure; A high-k dielectric material layer and a second electrode material layer are deposited sequentially; A portion of the high-K dielectric material layer and a portion of the second electrode material layer are removed to form a high-K dielectric layer located on the sidewall of the first electrode and a second electrode located on the sidewall of the high-K dielectric layer.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, Before removing a portion of the high-k dielectric material layer and a portion of the second electrode material layer to form the high-k dielectric layer located on the sidewall of the first electrode and the second electrode located on the sidewall of the high-k dielectric layer, the fabrication method further includes: Deposit an auxiliary conductive material layer covering the second electrode material layer; A portion of the auxiliary conductive material layer is removed, and an auxiliary conductive portion is formed between any two adjacent capacitor cells in a direction parallel to the substrate.

17. The method for preparing a semiconductor structure according to claim 16, characterized in that, Before removing a portion of the high-k dielectric material layer and a portion of the second electrode material layer to form the high-k dielectric layer located on the sidewall of the first electrode and the second electrode located on the sidewall of the high-k dielectric layer, the fabrication method further includes: A support material layer covering the second electrode material layer and the auxiliary conductive part is deposited; A portion of the supporting material layer is removed to form a support portion between any two adjacent capacitor cells in a direction parallel to the substrate; the support portion is located above the auxiliary conductive portion and together with the auxiliary conductive portion constitutes a support structure.

18. The method for preparing a semiconductor structure according to claim 13, characterized in that, The capacitor connection structure is formed by an epitaxial growth process.

19. The method for preparing a semiconductor structure according to claim 12, characterized in that, The stacking of multiple capacitor units in a direction perpendicular to the capacitor contact structure to form a capacitor structure includes: A bottom capacitor unit is formed vertically above the capacitor contact structure, including: forming a first electrode vertically above the capacitor contact structure, and sequentially forming a high-k dielectric layer and a second electrode on the sidewall of the first electrode; Intermediate capacitor units are stacked vertically above the bottom capacitor unit; wherein, forming the (N+1)th layer of the intermediate capacitor unit includes: forming the (N+1)th layer of the first electrode vertically above the Nth layer of the first electrode, and sequentially forming a high-K dielectric layer and a second electrode on the sidewall of the (N+1)th layer of the first electrode; wherein, N is a positive integer and 2≤N+1≤M; Stacking a top capacitor unit vertically above the intermediate capacitor unit includes: forming a first electrode of layer M+1 vertically above the first electrode of layer M, and sequentially forming a high-K dielectric layer and a second electrode at least on the sidewall of the first electrode of layer M+1.

20. The method for preparing a semiconductor structure according to claim 19, characterized in that, In the step of stacking intermediate capacitor units vertically above the bottom capacitor unit, the step of sequentially forming a high-K dielectric layer and a second electrode on the sidewall of the first electrode includes: sequentially depositing a high-K dielectric material layer and a second electrode material layer on the structure obtained by forming the first electrode; removing part of the high-K dielectric material layer and part of the second electrode material layer to form a high-K dielectric layer located on the sidewall of the first electrode and a second electrode located on the sidewall of the high-K dielectric layer. In the step of stacking the top capacitor unit vertically above the intermediate capacitor unit, the step of sequentially forming a high-K dielectric layer and a second electrode on at least the sidewall of the first electrode includes: sequentially depositing a high-K dielectric layer and a second electrode on the structure obtained by forming the first electrode; wherein the high-K dielectric layer at least covers the sidewall of the first electrode and the top surface of the first electrode facing away from the substrate, and the second electrode covers the sidewall of the high-K dielectric layer and the top surface of the high-K dielectric layer facing away from the substrate.

21. The method for preparing a semiconductor structure according to claim 20, characterized in that, Before removing a portion of the high-k dielectric material layer and a portion of the second electrode material layer to form the high-k dielectric layer located on the sidewall of the first electrode and the second electrode located on the sidewall of the high-k dielectric layer, the fabrication method further includes: Deposit an auxiliary conductive material layer covering the second electrode material layer; A portion of the auxiliary conductive material layer is removed, and an auxiliary conductive portion is formed between any two adjacent capacitor cells in a direction parallel to the substrate.

22. The method for preparing a semiconductor structure according to claim 21, characterized in that, Before removing a portion of the high-k dielectric material layer and a portion of the second electrode material layer to form the high-k dielectric layer located on the sidewall of the first electrode and the second electrode located on the sidewall of the high-k dielectric layer, the fabrication method further includes: A support material layer covering the second electrode material layer and the auxiliary conductive part is deposited; A portion of the supporting material layer is removed to form a support portion between any two adjacent capacitor cells in a direction parallel to the substrate; the support portion is located above the auxiliary conductive portion and together with the auxiliary conductive portion constitutes a support structure.

23. The method for preparing a semiconductor structure according to claim 20, characterized in that, After stacking the top capacitor unit vertically above the intermediate capacitor unit, the fabrication method further includes: forming a common source electrode layer covering the sidewall of the second electrode in the top capacitor unit and the second electrode facing away from the top surface of the substrate.

24. The method for preparing a semiconductor structure according to claim 19, characterized in that, The first electrode is formed by an epitaxial growth process.

25. The method for preparing a semiconductor structure according to claim 24, characterized in that, Before forming the high-k dielectric layer, the preparation method further includes: forming a barrier layer covering the first electrode; The formation of the high-K dielectric layer further includes: forming the high-K dielectric layer on the surface of the barrier layer opposite to the first electrode.

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