A display control method, a display control device and a smart terminal

Abstract

A display control method, a display control device and a smart terminal, the method comprising: acquiring a source video of a first refresh rate (S100); based on two logical chips, converting the refresh rate of the source video to obtain a target video of a second refresh rate (S200), wherein the first refresh rate is less than or equal to the second refresh rate; inputting the target video into a display module and displaying through the display module (S300). Based on two logical chips, the source video of a low refresh rate can be converted into a video of a higher refresh rate, so that the user can watch a more smooth and clear video picture.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of large-screen ultra-high-definition display, in particular to a display control method, a display control device and a smart terminal. BACKGROUND

[0002] In the high-end large-size display market application, the 8K high resolution plus 120Hz high refresh rate of the movie effect is excellent, which becomes one of the hotspots of consumer attention. In order to send 8K120Hz video content from a live scene or a television channel to a television display terminal and finally present it to the user, each node of the transmission chain needs to have 8K120Hz processing capability (such as program source recording, video compression, content distribution, network transmission, set-top box reception, video decompression, high-speed transmission from set-top box to television, video processing and display of television), otherwise, the final presentation of the original 8K120Hz video image content cannot be guaranteed. However, the development of the display industry is not balanced before and after the 8K120Hz ecological chain. The highest quality of the front-end program source is only 8K60Hz, while the 8K120Hz display module at the back end has been mature and mass-produced, so that the low refresh rate source video cannot be displayed in the high refresh rate display module, resulting in that the user cannot watch more smooth and clear video pictures.

[0003] Therefore, the prior art still needs to be improved and developed. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a display control method, a display control device, a refresh rate conversion method and a smart terminal, aiming at solving the problem that the low refresh rate source video cannot be displayed in the high refresh rate display module in the prior art, resulting in that the user cannot watch more smooth and clear video pictures.

[0005] The technical scheme adopted by the present application to solve the problem is as follows:

[0006] In a first aspect, the present application further provides a display control device, wherein the device comprises: two logic chips for converting a source video of a first refresh rate into a target video of a second refresh rate, wherein the first refresh rate is less than the second refresh rate;

[0007] A logic board connected with the two logic chips, for converting the target video into a low-voltage differential signal;

[0008] A display module connected with the logic board, for displaying the low-voltage differential signal.

[0009] In a second aspect, the present application provides a display control method, wherein the method comprises:

[0010] acquire a source video with a first refresh rate;

[0011] convert the source video into a target video with a second refresh rate based on two logic chips, wherein the first refresh rate is less than or equal to the second refresh rate;

[0012] input the target video into a display module and display the target video through the display module.

[0013] In an implementation manner, the two logic chips are a first logic chip and a second logic chip; each of the logic chips comprises a double data rate synchronous dynamic random access memory and a motion compensation module; and the converting the source video into the target video with the second refresh rate based on the two logic chips comprises:

[0014] inputting the source video into the first logic chip, decoding the source video through the first communication protocol, and obtaining a second decoded video;

[0015] obtaining the target video with the second refresh rate based on the first logic chip, the second logic chip and the second decoded video.

[0016] In an implementation manner, the obtaining the target video with the second refresh rate based on the first logic chip, the second logic chip and the second decoded video comprises:

[0017] obtaining a first region video according to the second decoded video and the first logic chip;

[0018] obtaining a second region video according to the second decoded video and the second logic chip;

[0019] merging the first region video and the second region video to obtain the target video with the second refresh rate.

[0020] In an implementation manner, the obtaining the first region video according to the second decoded video and the first logic chip comprises:

[0021] converting the second decoded video into a second video with the second refresh rate through the double data rate synchronous dynamic random access memory in the first logic chip;

[0022] compensating the second video through the motion compensation module in the first logic chip to obtain a second motion compensation video;

[0023] protocol-encoding the second motion compensation video to obtain the first region video.

[0024] In an implementation manner, the obtaining the second region video according to the second decoded video and the second logic chip comprises:

[0025] performing refresh rate conversion on the second decoded video through the double data rate synchronous dynamic random access memory in the second logic chip to obtain a third video of a second refresh rate;

[0026] performing motion compensation on the third video through the motion compensation module in the second logic chip to obtain a third motion compensated video;

[0027] protocol encoding the third motion compensated video to obtain the second region video.

[0028] In an implementation manner, the performing refresh rate conversion on the source video based on the two logic chips to obtain a target video of a second refresh rate comprises:

[0029] inputting the source video into each of the logic chips respectively, and decoding through the second communication protocol to obtain two third decoded videos;

[0030] obtaining two region videos according to the two third decoded videos;

[0031] merging the two region videos to obtain the target video of the second refresh rate.

[0032] In an implementation manner, the obtaining the two region videos according to the two third decoded videos comprises:

[0033] performing refresh rate conversion on each of the third decoded videos through the double data rate synchronous dynamic random access memory to obtain two fourth videos of a second refresh rate;

[0034] performing motion compensation on each of the fourth videos through the motion compensation module to obtain two fourth motion compensated videos;

[0035] protocol encoding each of the fourth motion compensated videos to obtain the two region videos.

[0036] In a third aspect, an embodiment of the present application further provides an intelligent terminal, which comprises a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors, and the one or more programs comprise programs for executing the display control method according to any one of the above.

[0037] In a fourth aspect, an embodiment of the present application further provides a non-transitory computer readable storage medium, when instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the display control method according to any one of the above aspects.

[0038] The present application has the following beneficial effects: the embodiment of the present application firstly acquires a source video with a first refresh rate; then performs refresh rate conversion on the source video based on two logic chips to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate; finally, the target video is input into a display module and displayed through the display module; it can be seen that the two logic chips can convert the source video with a low refresh rate into a video with a higher refresh rate, so that the user can watch a more smooth and clear video picture. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0040] Figure 1 The principle block diagram of the 8K120Hz display driving scheme provided by the prior art is shown.

[0041] Figure 2 The principle block diagram of the display control device provided by the embodiment of the present application is shown.

[0042] Figure 3 The flowchart of the display control method provided by the embodiment of the present application is shown.

[0043] Figure 4 The principle block diagram of the module in the two FPGAs of the 8K120Hz display driving scheme technology of one embodiment of the embodiment of the present application is shown.

[0044] Figure 5 The principle block diagram of the 8K60Hz display driving scheme (same hardware and same platform as the 8K120Hz driving scheme) of one embodiment of the embodiment of the present application is shown.

[0045] Figure 6 The 8K60Hz frame synchronization signal timing diagram of the input end of the two FPGAs of one embodiment of the embodiment of the present application is shown.

[0046] Figure 7 The 8K120Hz frame synchronization signal timing diagram of the output end of the two FPGAs of one embodiment of the embodiment of the present application is shown.

[0047] Figure 8 An image effect diagram before and after a motion compensation module provided in an embodiment of the present application.

[0048] Figure 9 An internal structure principle block diagram of the intelligent terminal provided in the embodiment of the present application. DETAILED DESCRIPTION

[0049] The present application discloses a display control method, a display control device, an intelligent terminal and a storage medium. In order to make the purpose, technical scheme and effect of the present application more clear and explicit, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0050] Those skilled in the art can understand that, unless specifically stated otherwise, the singular forms "a", "an" and "the" as used herein include plural forms. It should be further understood that the phrase "comprising" used in the specification of the present application means that the features, integers, steps, operations, elements and / or components exist, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connected" or "coupled" used herein can include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any single unit and all combinations of the associated listed items.

[0051] Those skilled in the art can understand that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as that generally understood by those skilled in the art to which the present application belongs. It should also be understood that terms such as those defined in a general dictionary should be understood to have meanings consistent with those in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as such.

[0052] Due to the prior art, with the development of large screen display, 8K ultra-high definition resolution, 120Hz high refresh rate and other technologies, the device comprising the above technology (invention point) has the following bottlenecks and defects: (1) The refresh frame rate of the output signal is only 8K60Hz at most. (2) At least 4 FPGAs are used to realize the basic functions, the data of the FPGA is more, which increases the complexity of the system design, and the more the number of FPGAs, the lower the reliability of the operation. The prior art of the existing 201610695970.7 (invention name: display control device, display control method and display device) is used as the prior art. The device comprising the technology (invention point) uses at least 4 FPGA chips (including 2 data generation chips and 2 data processing chips) as the basic architecture, supports input data left and right two-split screen, also supports input data left and right, and upper and lower four-split screen decoding and processing, and finally sends out the driving TCON to light the screen, but the technology only supports 8K60Hz.

[0053] The scheme of most of the 8K120Hz complete machines (television sets) that have been mass-produced in the market has the following defects: 1. A picture scaling IC (Scalar IC) is added to complete the amplification of 4K to 8K resolution, and the amplified image is lossy and has poor quality. 2. The picture scaling IC (Scalar IC) is complex in development technology, has a small production volume, and the technology is mastered by a few developers, so the purchase price is very expensive. Moreover, the technology does not support 8K60Hz signal source input. As shown in the scheme of most of the 8K120Hz complete machines (television sets) that have been mass-produced in the market, Figure 1 Although it can also meet the basic video effect, this scheme has the disadvantage that the image amplification process is lossy and the quality is lost.

[0054] In order to solve the problems of the prior art, the embodiment provides a display control method, which can convert a source video with a low refresh rate into a video with a higher refresh rate, so that the user can watch a more smooth and clear video picture. In specific implementation, first, a source video with a first refresh rate is acquired; then the source video is converted in refresh rate to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate; finally, the target video is input into a display module and displayed through the display module.

[0055] Exemplary device

[0056] The embodiment provides a display control device, which comprises:

[0057] two logic chips, configured to convert the source video of the first refresh rate into target video of the second refresh rate, wherein the first refresh rate is less than the second refresh rate;

[0058] a logic board connected with the two logic chips, configured to convert the target video into low-voltage differential signal;

[0059] a display module connected with the logic board, configured to display the low-voltage differential signal.

[0060] Specifically, as shown in the drawings, Figure 2 The source video signal in the present application can come from the VbyOne signal of the commercial display device (including but not limited to commercial advertising display screen) of the SoC, or from the HDMI2.1 or DP signal output by the computer (or set-top box). The first refresh rate of the source video is low, which can be converted into target video of higher refresh rate through two logic chips, and then the target video output by the two logic chips (Tcon board) is converted into low-voltage differential signal (LVDS) through the logic board, and finally the low-voltage differential signal is displayed through the display module connected with the logic board, that is, the display module is driven to light up through the logic board.

[0061] Exemplary method

[0062] The present embodiment provides a display control method, which can be applied to the intelligent terminal of large-screen ultra-high-definition display. Specifically, as shown in the drawings, Figure 3 The method comprises the following steps:

[0063] S100, obtaining source video of the first refresh rate;

[0064] Specifically, the first refresh rate is 60Hz or lower, and the resolution of the source video can be 4K or 8K. In the present embodiment, the resolution of the source video is 8K, and the refresh rate is 60Hz. First, the source video of 8K60Hz is obtained to prepare for subsequent refresh rate conversion.

[0065] After obtaining the source video, the following steps can be performed as shown in the drawings: Figure 3 S200, based on two logic chips, converting the source video to refresh rate to obtain target video of the second refresh rate; wherein the first refresh rate is less than the second refresh rate;

[0066] Specifically, the prior art converts the refresh rate by 4 logic chips, which consumes more resources, while the present application only needs to use two logic chips, which can save half of the resources. In addition, there is also a technology in the prior art to convert 60Hz to 120Hz, but it is based on a resolution below 2K, and cannot convert the refresh rate of higher resolution videos such as 4K or even 8K, which will reduce the resolution and result in low video quality. The logic chip can be an ASIC chip, an FPGA chip, etc. In this embodiment, the logic chip is an FPGA chip, that is, the conversion of the source video of the first refresh rate to the target video of the second refresh rate is completed by the FPGA chip to convert the refresh rate. In order to save resources, the present application uses 2 said logic chips, which is lower in cost than using only one large-capacity logic resource FPGA chip, because the algorithm for 8K 120Hz ultra-high-definition display requires a large amount of data processing due to its high complexity, and the logic resources required are also very high. Therefore, the FPGA chip used to realize 8K 120Hz needs to select a high-level FPGA chip with large resource quantity and many special differential high-speed transceivers (Serdes), which is very expensive. Secondly, the two medium logic resource FPGAs used in the present application have the same internal modules and the same development program, which can speed up the time consumed in engineering development.

[0067] Further, the present application can be applied according to actual needs, and can be applied to two display modules (8K 60Hz display module and 8K 120Hz display module) on the market under the same hardware and platform, as shown in Figure 3 , which increases the flexibility of market layout and further saves procurement costs. The 8K 60Hz display module is the prior art, which will not be described here.

[0068] In this embodiment, the second refresh rate is 120Hz, which is higher than the first refresh rate. Since the prior art can only generate 8K 60Hz source video, but cannot generate 8K 120Hz source video, the mature mass-produced 8K 120Hz display module cannot be widely applied, so the present application converts the 8K 60Hz source video into 8K 120Hz video, so that users can watch more smooth and clear video pictures. Compared with the existing 8K 120Hz display driving scheme (such as Figure 1 ), it has a more realistic and delicate display effect, and can reduce the problems of motion blur and motion jitter, making the motion picture more smooth and clear. This system can break the bottleneck of no 8K 120Hz source in the existing digital television broadcast network, ensure the optimal display of 8K 120Hz user end, and has high system operation reliability, low production cost, and is convenient for rapid promotion.

[0069] In addition, the input interface types include a VbyOne input interface and an HDMI2.1 / DP1.4 input interface, and the source video input through the two interfaces needs to use two logic chips, but the specific connection method of the source video and the logic chip is different, and the target video of the second refresh rate can be obtained through refresh rate conversion of the two logic chips. Therefore, the application is more widely applied, and can be applied to commercial display devices (including but not limited to commercial advertising display screens) without SoC, and can also directly use the computer (or set top box) to output the HDMI2.1 or DP signal and access the system shown in the application, as shown in the figure, that is, the commercial display device can be driven and lit. Figure 3

[0070] In an implementation manner, the two logic chips are a first logic chip and a second logic chip; each of the logic chips includes a double-rate synchronous dynamic random access memory and a motion compensation module; and step S200 includes the following steps.

[0071] S201, input the source video into the first logic chip, and decode through the first communication protocol to obtain a second decoded video;

[0072] S202, based on the first logic chip, the second logic chip and the second decoded video, obtain a target video of a second refresh rate.

[0073] Specifically, in step S201, the first logic chip and the second logic chip are both FPGA chips, the internal structures of which are the same, the first refresh rate is 60Hz, the second refresh rate is 120Hz, the video source is from a set top box / computer, and is input through an HDMI2.1 / DP1.4 interface. The HDMI2.1 / DP1.4 protocol can transmit 32 lanes, and one HDMI2.1 / DP1.4 interface can meet the minimum transmission bandwidth requirement of 8K60Hz, so all (whole picture) 8K60Hz pictures can be input into any one of the two FPGA chips (for example, only transmitted to FPGA#1 in the example in Figure 3 , the second decoded video is obtained through decoding of the HDMI2.1 / DP1.4 protocol in any one of the FPGA chips, and finally the target video of the second refresh rate can be obtained according to the second decoded video, the first logic chip and the second logic chip.

[0074] Step S202 includes the following steps.

[0075] S2021, obtain a first region video according to the second decoded video and the first logic chip;

[0076] S2022, obtain a second region video according to the second decoded video and the second logic chip; ​

[0077] S2023, merge the first area video and the second area video to obtain a target video of the second refresh rate.

[0078] Specifically, according to the second decoded video and the first logic chip, the first area video is obtained by refreshing the second decoded video through the double data rate synchronous dynamic random access memory in the first logic chip to obtain a second video of the second refresh rate, performing motion compensation on the second video through the motion compensation module in the first logic chip to obtain a second motion compensation video, and performing protocol encoding on the second motion compensation video to obtain the first area video. In practice, the internal module structures of the first logic chip and the second logic chip are the same, so the subsequent modules after obtaining the second decoded video through HDMI2.1 / DP1.4 protocol decoding in any logic chip are the same, except that they are located in the first logic chip and the second logic chip, respectively. The second decoded video is motion compensated through the motion compensation module in the first logic chip to obtain a second motion compensation video, and then protocol encoded to obtain the first area video. According to the second decoded video and the second logic chip, the second area video is obtained by refreshing the second decoded video through the double data rate synchronous dynamic random access memory in the second logic chip to obtain a third video of the second refresh rate, performing motion compensation on the third video through the motion compensation module in the second logic chip to obtain a third motion compensation video, and performing protocol encoding on the third motion compensation video to obtain the second area video. Based on the same principle, the second decoded video is motion compensated through the motion compensation module in the second logic chip to obtain a third motion compensation video, and then protocol encoded through VbyOne protocol to obtain the second area video. The first area video and the second area video can be upper and lower half-screen videos of one screen area, or left and right half-screen videos of one screen area. For example, FPGA#1 transmits the right half-screen picture of the 8K60Hz picture decoded by HDMI2.1 / DP1.4 protocol to FPGA#2 through image interconnection signals. The subsequent image data processing parts of the two FPGAs are completely the same in processing mode. In this embodiment, the first area video and the second area video are left and right half-screen videos of one screen area, respectively. Finally, the first area video and the second area video are merged to obtain a target video of the second refresh rate, and the target video is a complete screen video. The motion compensation module uses a dynamic imaging system to insert a motion compensation frame between two traditional frames of images, thereby increasing the refresh rate, so that the motion picture is clearer and smoother, which is better than the normal response effect.

[0079] In another implementation, since the internal structures of the two logical chips are completely the same. The method for converting the refresh rate of the source video to obtain the target video of the second refresh rate based on the two logical chips comprises the following steps: inputting the source video into each of the logical chips respectively, decoding through the second communication protocol to obtain two third decoded videos; converting the refresh rate of each of the third decoded videos through the double data rate synchronous dynamic random access memory to obtain two fourth videos of the second refresh rate; performing motion compensation on each of the fourth videos through the motion compensation module to obtain two fourth motion compensation videos; performing protocol encoding on each of the fourth motion compensation videos to obtain two region videos; and merging the two region videos to obtain the target video of the second refresh rate.

[0080] In the embodiment, the first refresh rate is 60 Hz, and the second refresh rate is 120 Hz. At this time, the video signal source output by the front-end 8K SoC is an 8K60Hz picture, which is sent to the receiving end of the FPGA through the VbyOne protocol. 32 lane differential signals (each lane rate is 2.97 Gbps) are required to meet the minimum transmission bandwidth requirement of 8K60Hz (note: the transmission bandwidth of 8K60Hz is about 90Gbps, and at least 32 lane VbyOne signals are required to meet the transmission requirement. The VbyOne protocol can only transmit 16 lanes, so the source video of 8K60Hz of 16 lanes is distributed into each logic chip, decoded through the VbyOne protocol, and the third decoded video corresponding to each logic chip is obtained. The first 16 lanes transmit the left half screen picture of the 8K60Hz video, and the last 16 lanes transmit the right half screen picture of the 8K60Hz video. Then each third decoded video is converted in refresh rate through the double rate synchronous dynamic random access memory to obtain the fourth video corresponding to each logic chip. In this way, there are two fourth videos, each fourth video is motion compensated through the motion compensation module to obtain the fourth motion compensated video corresponding to each logic chip, and then each fourth motion compensated video is protocol encoded through the VbyOne protocol to obtain the region video corresponding to each logic chip. In practice, the transmission bandwidth of 8K120Hz is about 180Gbps, and at least 64 lane VbyOne signals are required to meet the transmission requirement.

[0081] In another implementation, when the first refresh rate is equal to the second refresh rate, the refresh rate of the source video is unchanged, and the refresh rate is unchanged before and after the refresh rate conversion, at this time, a logic chip is used. In this embodiment, the video source is 8K60Hz, when the display module is also 8K60Hz, the modules in the FPGA chip are consistent with the FPGA#1 part (or the FPGA#2 part) in the 8K60Hz display module Figure 4 . At this time, only one FPGA can realize all functions, and the same hardware circuit, the same FPGA chip, and the same module in the FPGA chip are used as the 8K120Hz architecture diagram (such as Figure 4 ). The difference is that only one FPGA (such as FPGA#1 in Figure 5 ) is used, and the modules in the FPGA are pre-set differently.

[0082] When the first refresh rate is equal to the second refresh rate, the first decoded video is obtained by decoding through the first communication protocol; the first video of the second refresh rate is obtained by refreshing the first decoded video through the double data rate synchronous dynamic random access memory; the first motion compensation video is obtained by performing motion compensation on the first video through the motion compensation module; and the target video of the second refresh rate is obtained by performing protocol encoding on the first motion compensation video.

[0083] Specifically, the first communication protocol is HDMI2.1 / DP1.4, at this time, the video source comes from a set-top box / computer, and is input through the HDMI2.1 / DP1.4 interface, when the first refresh rate is equal to the second refresh rate, for example, the source video of 8K60Hz is input, and the target video is 8K60Hz, the source video of 8K60Hz is first decoded through the HDMI2.1 / DP1.4 protocol to obtain the first decoded video. Then the first decoded video is refreshed through the double data rate synchronous dynamic random access memory to obtain the first video of the second refresh rate; at this time, in order to keep the FPGA chip internal module structure of 8K60Hz and the FPGA chip internal module structure of 8K120Hz same, the FPGA chip still includes the double data rate synchronous dynamic random access memory, but does not do interpolation, so that the data rate of the output and the input is the same, in this way, the refresh rate of the obtained first video and the first decoded video is the same. Then the first video is motion compensated through the motion compensation module to obtain the first motion compensation video; in this way, the first motion compensation video presents a more real and delicate display effect, and can reduce the problems of motion blur and motion jitter, so that the motion picture is more smooth and clear. Finally, the first motion compensation video is encoded through the HDMI2.1 / DP1.4 protocol to obtain the target video of the second refresh rate.

[0084] Further, the two FPGAs are not constrained and can be arbitrarily exchanged, and the implementation mode of the internal module in the application is as follows:

[0085] The internal module part of the two FPGAs is as shown in the figure. Figure 4 The total amount of data processed by FPGA #1 and FPGA #2 and the functions implemented are the same (the difference is that FPGA #1 processes left half screen image data and FPGA #2 processes right half screen image data), so the internal modules of FPGA #1 and FPGA #2 are consistent.

[0086] In FPGA #1, the VbyOne protocol decoding module or the HDMI2.1 / DP1.4 protocol decoding module decodes and outputs the image data of the left half screen, which will be cached in an asynchronous FiFo (the capacity of the FiFo is small, for example, 8K resolution half row 3840 pixel storage space), then under the constraint of the input end frame synchronization control module in FPGA #1 and FPGA #2, the left half screen image data in FPGA #1 and the right half screen image data in FPGA #2 are time-synchronously aligned and output to the back-end DDR read-write control module and the back-end dual-port RAM1 module (the cache capacity of the dual-port RAM1 is about 5 rows, each row has 7680 pixels, which is used for interpolation calculation of the motion compensation module).

[0087] The input end frame synchronization control module is responsible for constraining the left and right half screen image data received by the two FPGAs, and the timing is as shown in the figure. Figure 6 The figure shows the digital signal timing diagram of the image in a frame of time, wherein one frame has M rows and each row has N pixels (i.e. 8K screen M=4320; N=7680). At this time, the input frame synchronization signals that FPGA #1 needs to transmit to FPGA #2 include: (1) Pixel CLK1: left half screen image pixel clock, frequency about 75MHz, the clock is generated by the PLL in FPGA #1; (2) input DE1: left half screen image data valid signal, the signal is generated by the front-end VbyOne protocol decoding module or HDMI2.1 / DP1.4 protocol decoding module, when the signal is high, it indicates that the pixel data is valid at this time. Similarly, the input frame synchronization signals that FPGA #2 needs to transmit to FPGA #1 include Pixel CLK2: right half screen image pixel clock, frequency about 75MHz, the clock is generated by the PLL in FPGA #2; (3) input DE2: right half screen image data valid signal, the signal is generated by the front-end VbyOne protocol decoding module or HDMI2.1 / DP1.4 protocol decoding module, when the signal is high, it indicates that the pixel data is valid at this time. After the above signal mutual transmission, FPGA #1 will calculate the time difference of the pixel data in FPGA #2 (as shown in the figure). Figure 6The input pixel data of FPGA#1 (left half screen) is 2 clock cycles faster than the input pixel data of FPGA#2 (right half screen). Similarly, FPGA#2 also calculates the time difference of the internal pixel data of FPGA#1 (i.e., the input pixel data of FPGA#2 (right half screen) is 2 clock cycles slower than FPGA#1). Then the frame synchronization can be triggered at a preset position (such as Figure 6 The example position is that the input first pixel data of the first row of FPGA#2 triggers the frame synchronization. In actual application, the triggering position can be selected according to the capacity of the asynchronous FiFo. The buffered image data is continuously read out from the asynchronous FiFo starting from the triggering position. Through the above steps, the left and right half screen image data input by the two FPGAs are guaranteed to be synchronous and aligned in time, avoiding the tearing problem of the left and right half screen input image. The input end is 8K60Hz frame synchronization, and the output end is 8K120Hz frame synchronization. The asynchronous FiFo (small capacity) is used as the image input end buffer.

[0088] The DDR read-write control module is responsible for writing the image data sent out by the previous module (asynchronous FiFo) into the DDR storage unit in real time. At the same time, the image data of the previous frame is continuously read from the DDR storage unit under the constraint of the output end frame synchronization control module, and is sent to the dual-port RAM2 module (the buffer capacity of the dual-port RAM2 is about 5 rows, and each row has 7680 pixels, which is used for interpolation calculation of the motion compensation module). The dual-port RAM (large capacity) is used as the image output end buffer, which is convenient for interpolation calculation of the motion compensation module.

[0089] The output end frame synchronization control module is used to autonomously generate the total timing of 8K120Hz pixel scanning of the image. Two FPGAs are connected through the output frame synchronization signal, which guarantees that the 8K120Hz scanning timing of the two chips is synchronous and aligned every frame. One of the FPGAs can be preset to autonomously generate the DE signal of 8K120Hz pixel scanning (such as Figure 7 The example in the figure is that FPGA#1 autonomously generates and outputs DE1 signal), which is then transmitted to the other FPGA (such as Figure 7 The example in the figure is FPGA#2). The other FPGA chip samples the signal, but because sampling takes 1 clock cycle, the DE1 signal received by FPGA#2 from FPGA#1 is delayed by 1 clock.

[0090] Therefore, the output end frame synchronization module needs to transmit only one synchronization signal between FPGA#1 and FPGA#2: the DE signal of 8K120Hz pixel scanning. FPGA#1 can be preset to transmit to FPGA#2, or FPGA#2 can be preset to transmit to FPGA#1 (such as Figure 7An example in the middle is FPGA #1 transmitting to FPGA #2.

[0091] In the output end frame synchronization module, the trigger frame synchronization position can be preset (such as Figure 7 An example in the middle is FPGA #1 transmitting to FPGA #2. Figure 7 As shown in the figure, the self-generated output DE1 after synchronization in the output end frame synchronization module inside the FPGA #1 chip will be synchronized with the self-generated output DE2 after synchronization in the output end frame synchronization module inside the FPGA #2 chip.

[0092] In the [output end frame synchronization module] inside the FPGA #1 chip, the self-generated output DE1 signal after synchronization will control the [DDR read-write control module] to read the pixel image data (left half screen) of the previous frame from the DDR storage unit.

[0093] Similarly, in the [output end frame synchronization module] inside the FPGA #2 chip, the self-generated output DE2 signal after synchronization will control the [DDR read-write control module] to read the pixel image data (right half screen) of the previous frame from the DDR storage unit.

[0094] The continuous reading of the previous frame image data from the DDR storage unit will be cached in the dual-port RAM2. The motion compensation module will receive the current frame (Kth frame) image data of the dual-port RAM1 and the previous frame (K-1th frame) image data in the dual-port RAM2, and the motion compensation module will analyze and calculate the 8K60Hz image data of the two frames and output the 8K120Hz image with motion compensation effect, as shown in the figure. Figure 8 The output 8K120Hz image with motion compensation has motion enhancement effect, which can reduce picture trailing and jitter problems, making the motion scene more smooth and clear.

[0095] FPGA #1 will finally encode the 8K120Hz image (left half screen) with motion compensation into a 32lane VbyOne signal using the VbyOne protocol and send it to the backend Tcon board to drive the left half screen to light up. FPGA #2 will finally encode the 8K120Hz image (right half screen) with motion compensation into a 32lane VbyOne signal using the VbyOne protocol and send it to the backend Tcon board to drive the right half screen to light up.

[0096] After obtaining the target video of the second refresh rate, the method can be executed as shown in the figure. Figure 3The steps are shown as follows: S300, inputting the target video into a display module, and displaying through the display module.

[0097] In the embodiment, the display module is a Tcon plate. After inputting the target video into the rear-end Tcon plate, the display module is driven to light up.

[0098] Based on the above embodiment, the application further provides an intelligent terminal, a principle diagram of which can be shown as follows. Figure 9 The intelligent terminal includes a processor, a memory, a network interface, a display screen, and a temperature sensor connected through a system bus. The processor of the intelligent terminal is used to provide calculation and control capabilities. The memory of the intelligent terminal includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The network interface of the intelligent terminal is used to communicate with external terminals through network connection. The computer program is executed by the processor to implement a display control method. The display screen of the intelligent terminal can be a liquid crystal display screen or an electronic ink display screen. The temperature sensor of the intelligent terminal is pre-set in the intelligent terminal and is used to detect the running temperature of internal devices.

[0099] Those skilled in the art can understand that Figure 9 the principle diagram in the above embodiment is only a block diagram of part of structures related to the application scheme and does not constitute a limitation on the intelligent terminal to which the application scheme is applied. The specific intelligent terminal can include more or fewer components than those shown in the diagram, or combine certain components, or have a different component arrangement.

[0100] In one embodiment, an intelligent terminal is provided, including a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors, and the one or more programs contain instructions for performing the following operations:

[0101] obtaining a source video with a first refresh rate;

[0102] performing refresh rate conversion on the source video to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate;

[0103] inputting the target video into a display module, and displaying through the display module.

[0104] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of each method can be included. Any reference to memory, storage, database or other medium used in each embodiment provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0105] In summary, the present application discloses a display control method, a display control device, a smart terminal and a storage medium, the method comprising: obtaining a source video with a first refresh rate; converting the refresh rate of the source video to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate; inputting the target video into a display module and displaying through the display module. The present application can convert the source video with a low refresh rate into a video with a higher refresh rate, so that the user can watch a more smooth and clear video picture.

[0106] The detailed effect description is:

[0107] The present application provides an 8K120Hz display control system and a display device, which supports converting the refresh rate of an 8K60Hz input source to 120Hz output and driving a display module (including but not limited to LCD, LED 8K120Hz display large screen). Compared with the existing 8K120Hz display driving scheme (such as Figure 1 ), it has a more realistic and delicate display effect, can reduce the problems of motion blur and motion jitter, and makes the motion picture more smooth and clear. This system can break the bottleneck of no 8K120Hz source in the existing digital television broadcast network, ensure the optimal display of 8K120Hz user end, and has high system operation reliability, low production cost and is convenient for rapid promotion.

[0108] The application can realize all functions by using two FPGA chips with medium logic resources, and the cost is lower than using one FPGA chip with large capacity logic resources (reason: if the algorithm of 8K 120Hz ultra-high definition display is realized by one FPGA chip, the logic resources required are very high due to the high complexity and large data processing amount of the ultra-high definition algorithm, so the FPGA chip used for realizing 8K 120Hz needs to be a high-level FPGA chip with large resource quantity and many special differential high-speed transceivers (Serdes), and the cost is very expensive). Secondly, the two FPGA chips with medium logic resources used in the application have the same internal modules and the same development program, which can speed up the time consumed in engineering development.

[0109] The application can be applied according to actual needs, and can be applied to two display modules (8K 60Hz display module and 8K 120Hz display module) on the market under the same hardware and platform to increase the layout market flexibility and further save the procurement cost.

[0110] The application is more widely applied, and can be applied to commercial display equipment (including but not limited to commercial advertising display screens) without SoC, and the commercial display equipment can be directly driven and lightened by using a computer (or a set-top box) to output an HDMI2.1 or DP signal and accessing the system (such as Figure 3 ) shown in the application.

[0111] Based on the above embodiment, a display control method is disclosed, and it should be understood that the application of the application is not limited to the above examples, and those skilled in the art can improve or change the application according to the above description, and all these improvements and changes should belong to the protection scope of the claims attached to the application.

Claims

1. A display control device, characterized in that, The device includes: Two logic chips are used to convert a source video with a first refresh rate into a target video with a second refresh rate, wherein the first refresh rate is less than the second refresh rate; A logic board, connected to the two logic chips, is used to convert the target video into a low-voltage differential signal; The display module, connected to the logic board, is used to display the low-voltage differential signal; The two logic chips used to convert the source video at the first refresh rate into the target video at the second refresh rate include: The source video is input into each of the logic chips respectively, and decoded through the second communication protocol to obtain two third decoded videos; Based on the two third-decoded videos, two regional videos are obtained; The two regional videos are merged to obtain the target video at the second refresh rate.

2. A display control method, characterized in that, The method includes: Get the source video at the first refresh rate; Based on two logic chips, the source video is converted to a second refresh rate to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate. The target video is input into the display module and displayed through the display module; The step of converting the source video to a second refresh rate based on two logic chips includes: The source video is input into each of the logic chips respectively, and decoded through the second communication protocol to obtain two third decoded videos; Based on the two third-decoded videos, two regional videos are obtained; The two regional videos are merged to obtain the target video with the second refresh rate.

3. The display control method according to claim 2, characterized in that, The two logic chips are a first logic chip and a second logic chip; each logic chip includes a double-rate synchronous dynamic random access memory and a motion compensation module; the step of converting the refresh rate of the source video based on the two logic chips to obtain a target video with a second refresh rate includes: The source video is input into the first logic chip and decoded using the first communication protocol to obtain the second decoded video; Based on the first logic chip, the second logic chip, and the second decoded video, a target video with a second refresh rate is obtained.

4. The display control method according to claim 3, characterized in that, The process of obtaining the target video with the second refresh rate based on the first logic chip, the second logic chip, and the second decoded video includes: Based on the second decoded video and the first logic chip, the first region video is obtained; Based on the second decoded video and the second logic chip, the second region video is obtained; The first and second region videos are merged to obtain the target video with the second refresh rate.

5. The display control method according to claim 4, characterized in that, The step of obtaining the first region video based on the second decoded video and the first logic chip includes: The second decoded video is converted to a second refresh rate through the double-rate synchronous dynamic random access memory in the first logic chip to obtain a second video with a second refresh rate. The motion compensation module in the first logic chip performs motion compensation on the second video to obtain a second motion-compensated video. The second motion-compensated video is encoded using a protocol to obtain the first region video.

6. The display control method according to claim 4, characterized in that, The step of obtaining the second region video based on the second decoded video and the second logic chip includes: The second decoded video is converted to a higher refresh rate using the double-rate synchronous dynamic random access memory in the second logic chip to obtain a third video with a second refresh rate. The motion compensation module in the second logic chip performs motion compensation on the third video to obtain a third motion-compensated video. The third motion-compensated video is encoded using a protocol to obtain the second region video.

7. The display control method according to claim 2, characterized in that, Each of the aforementioned logic chips includes a double-rate synchronous dynamic random access memory and a motion compensation module; obtaining the two region videos based on the two third decoded videos includes: Each of the third decoded videos is refreshed using the double-rate synchronous dynamic random access memory to obtain two fourth videos with a second refresh rate. The motion compensation module performs motion compensation on each of the fourth videos to obtain two fourth motion-compensated videos. Each fourth motion-compensated video is encoded using a protocol to obtain two region videos.

8. A smart terminal, characterized in that, The system includes a memory and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by one or more processors to perform a display control method, the method comprising the steps of: Get the source video at the first refresh rate; Based on two logic chips, the source video is converted to a second refresh rate to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate. The target video is input into the display module and displayed through the display module; The step of converting the source video to a second refresh rate based on two logic chips includes: The source video is input into each of the logic chips respectively, and decoded through the second communication protocol to obtain two third decoded videos; Based on the two third-decoded videos, two regional videos are obtained; The two regional videos are merged to obtain the target video with the second refresh rate.

9. The smart terminal according to claim 8, characterized in that, The two logic chips are a first logic chip and a second logic chip; each logic chip includes a double-rate synchronous dynamic random access memory and a motion compensation module; the step of converting the refresh rate of the source video based on the two logic chips to obtain a target video with a second refresh rate includes: The source video is input into the first logic chip and decoded using the first communication protocol to obtain the second decoded video; Based on the first logic chip, the second logic chip, and the second decoded video, a target video with a second refresh rate is obtained.

10. The smart terminal according to claim 9, characterized in that, The process of obtaining the target video with the second refresh rate based on the first logic chip, the second logic chip, and the second decoded video includes: Based on the second decoded video and the first logic chip, the first region video is obtained; Based on the second decoded video and the second logic chip, the second region video is obtained; The first and second region videos are merged to obtain the target video with the second refresh rate.

11. The smart terminal according to claim 10, characterized in that, The step of obtaining the first region video based on the second decoded video and the first logic chip includes: The second decoded video is converted to a second refresh rate through the double-rate synchronous dynamic random access memory in the first logic chip to obtain a second video with a second refresh rate. The motion compensation module in the first logic chip performs motion compensation on the second video to obtain a second motion-compensated video. The second motion-compensated video is encoded using a protocol to obtain the first region video.

12. The smart terminal according to claim 10, characterized in that, The step of obtaining the second region video based on the second decoded video and the second logic chip includes: The second decoded video is converted to a higher refresh rate using the double-rate synchronous dynamic random access memory in the second logic chip to obtain a third video with a second refresh rate. The motion compensation module in the second logic chip performs motion compensation on the third video to obtain a third motion-compensated video. The third motion-compensated video is encoded using a protocol to obtain the second region video.

13. The smart terminal according to claim 8, characterized in that, Each of the aforementioned logic chips includes a double-rate synchronous dynamic random access memory and a motion compensation module; obtaining the two region videos based on the two third decoded videos includes: Each of the third decoded videos is refreshed using the double-rate synchronous dynamic random access memory to obtain two fourth videos with a second refresh rate. The motion compensation module performs motion compensation on each of the fourth videos to obtain two fourth motion-compensated videos. Each fourth motion-compensated video is encoded using a protocol to obtain two region videos.

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