Display panel

Abstract

This invention discloses a display panel having an active area and a peripheral area, and comprising a substrate, multiple pixels, multiple gate lines, gate connection lines, a common line, and a compensation electrode. The multiple pixels are disposed on the substrate and located in the active area. The gate lines are disposed on the substrate and configured to receive multiple scan signals. Each gate line is coupled to one or more of the multiple pixels, wherein the number of pixels coupled to a first gate line is less than the number of pixels coupled to a second gate line, and the first gate line spans the active area and the peripheral area. The gate connection lines are located in the peripheral area and electrically connected to the first gate lines. The common line and the compensation electrode are both located in the peripheral area and respectively disposed below and above the gate connection lines, and are both configured to receive a common voltage signal. The common line, gate connection lines, and compensation electrode overlap in the normal direction of the display panel. This invention provides a gate line impedance compensation function, which can improve problems such as poor grayscale display.

Description

Technical Field

[0001] This invention relates to a display panel, and more particularly to a display panel having a free-shaped active area. Background Technology

[0002] With the evolution of display panel manufacturing technology, high-resolution display panels are now applicable to wearable and handheld electronic products, such as smartwatches and fitness trackers. On the other hand, consumers' aesthetic demands for electronic products are also increasing, leading to the use of display panels with unique designs in various electronic products. These display panels typically have non-rectangular shapes, such as circles or other irregular shapes. However, for this type of display panel, the number of pixels in each pixel row within the active area is inconsistent, resulting in different impedances for each pixel row. This can cause significant differences in brightness across different areas of the active area, leading to problems such as poor grayscale display. Summary of the Invention

[0003] The purpose of this invention is to provide a display panel that has a free-shaped active area and includes impedance compensation function for gate lines, so as to improve problems such as poor grayscale display.

[0004] To achieve the above objectives, the present invention provides a display panel having an active region and a peripheral region, and comprising a substrate, a plurality of pixels, a plurality of gate lines, gate connection lines, a common line, and a compensation electrode. The plurality of pixels are disposed on the substrate and located in the active region. The gate lines are disposed on the substrate and configured to receive a plurality of scan signals, each of the plurality of gate lines being coupled to one or more of the plurality of pixels, wherein the number of pixels coupled to a first gate line is less than the number of pixels coupled to a second gate line, and the first gate line spans the active region and the peripheral region. The gate connection lines are located in the peripheral region and electrically connected to the first gate lines. The common line is located in the peripheral region and disposed below the gate connection lines, and is configured to receive a common voltage signal. The compensation electrode is located in the peripheral region and disposed above the gate connection lines, and is configured to receive the common voltage signal. The common line, the gate connection lines, and the compensation electrode overlap in the normal direction of the display panel.

[0005] According to one embodiment of the present invention, the display panel further includes a bridging structure located in the peripheral area and directly connected to the first gate line and the gate connection line.

[0006] According to another embodiment of the present invention, each of the plurality of pixels includes a pixel electrode and a common electrode, wherein the common electrode is located above the pixel electrode, and the common electrode, the bridging structure and the compensation electrode belong to the same transparent conductive layer.

[0007] According to another embodiment of the present invention, the display panel further includes a compensation trace located in the peripheral region and disposed above the compensation electrode, and configured to receive the same scan signal as the first gate line. The common line, the gate connection line, the compensation electrode, and the compensation trace overlap in the normal direction of the display panel.

[0008] According to another embodiment of the present invention, the compensation trace is directly connected to the bridging structure and the gate connection line.

[0009] According to another embodiment of the present invention, each of the plurality of pixels includes a pixel electrode and a common electrode, the common electrode being located below the pixel electrode, and the common electrode and the compensation electrode belonging to the same transparent conductive layer.

[0010] According to another embodiment of the present invention, the width of the common line is greater than the width of the gate connection line.

[0011] According to another embodiment of the present invention, the active region is irregularly shaped and has a first sub-region and a second sub-region, wherein the first sub-region and the second sub-region are opposite to each other and have a gap between them, and the common line and the gate connection line are disposed in this gap.

[0012] To achieve the above objectives, the present invention further provides a display panel having an active region and a peripheral region, and comprising a substrate, a plurality of pixels, a plurality of gate lines, a common line, a compensation trace, and a compensation electrode. The plurality of pixels are disposed on the substrate and located in the active region. The gate lines are disposed on the substrate and configured to receive a plurality of scan signals, each of the plurality of gate lines being coupled to one or more of the plurality of pixels, wherein the number of pixels coupled to a first gate line is less than the number of pixels coupled to a second gate line, and the first gate line spans the active region and the peripheral region. The common line is disposed above the first gate line and located in the peripheral region, and is configured to receive a common voltage signal. The compensation trace is located above the common line and is configured to receive the same scan signal as the first gate line. The compensation electrode is located above the compensation trace and is configured to receive the common voltage signal. The first gate line, the common line, the compensation trace, and the compensation electrode overlap in the normal direction of the display panel.

[0013] According to one embodiment of the present invention, the display panel further includes a bridging structure located in the peripheral area and directly connected to the first gate line and the compensation trace.

[0014] According to another embodiment of the present invention, each of the plurality of pixels includes a pixel electrode and a common electrode, wherein the common electrode is located below the pixel electrode, and the pixel electrode, the bridging structure and the compensation electrode belong to the same transparent conductive layer.

[0015] The beneficial effects of this invention are at least in providing gate line impedance compensation, which can improve problems such as poor grayscale display. Attached Figure Description

[0016] To gain a more complete understanding of the embodiments and their advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein:

[0017] Figure 1 This is a schematic diagram of the display panel;

[0018] Figure 2 for Figure 1 An enlarged view of the upper side of the display panel shown;

[0019] Figure 3A and Figure 3B For each example Figure 2 A cross-sectional view of the pixels shown;

[0020] Figure 4A According to the first embodiment of the present invention Figure 2 A partial layout diagram of the display panel is shown;

[0021] Figure 4B for Figure 4A A sectional view along section line B-B' in the layout area shown;

[0022] Figure 5A This is a partial layout diagram of a display panel according to a second embodiment of the present invention;

[0023] Figure 5B for Figure 5A A sectional view along section line B-B' in the layout area shown;

[0024] Figure 6A This is a partial layout diagram of a display panel according to a third embodiment of the present invention;

[0025] Figure 6B for Figure 6A A sectional view along section line B-B' in the layout area shown;

[0026] Figure 7A This is a partial layout diagram of a display panel according to the fourth embodiment of the present invention;

[0027] Figure 7B for Figure 7A A sectional view along section line B-B' in the layout area shown;

[0028] Figure 8 This is a comparison chart of the gate line impedance differences between the embodiments and comparative examples of the present invention. Detailed Implementation

[0029] The embodiments disclosed herein are discussed in detail below. However, it will be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific situations. The discussed and disclosed embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the claims. Unless otherwise limited, the singular forms of “a” or “described” may also be used to denote the plural forms.

[0031] It is understood that although terms such as "first," "second," etc., may be used in this document to describe various features, these terms should not limit these features. These terms are only used to distinguish one feature from another.

[0032] The use of spatial relativity is intended to describe the different orientations of a component during use or operation, and is not limited to the orientation shown in the accompanying drawings. Components may also be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relativity descriptions used herein can be interpreted in the same way.

[0033] For the sake of simplicity and clarity, element symbols and / or letters may be repeated in various embodiments herein, but this does not imply a causal relationship between the various embodiments and / or configurations discussed.

[0034] Furthermore, for the sake of simplifying the accompanying drawings, some conventional structures and components in the art will be shown in a simple schematic manner in the drawings, or will not appear in the drawings at all, and the actual size and scale of each component in this document are not limited to the content shown in the accompanying drawings.

[0035] Figure 1 This is a schematic diagram of the display panel 100. The display panel 100 may be, for example, a twisted nematic (TN) type, an in-plane switching (IPS) type, a fringe-field switching (FFS) type, a vertical alignment (VA) type, a reflective type, or a transflective type liquid crystal display panel, but is not limited to these.

[0036] The display panel 100 includes a substrate 102 and has an active region 110 and a peripheral region 120 surrounding the active region, and a plurality of pixels ( Figure 1 (Not shown) Pixels are disposed on substrate 102 and located in active region 110, and arranged in mutually perpendicular directions X and Y to form a pixel array. Display panel 100 is a free-shaped display panel. For example... Figure 1As shown, the edge 100E of the display panel 100 is irregularly shaped, and the top of the display panel 100 has a recess 100N; the edge 110E of the active area 110 is also irregularly shaped, and the top of the active area 110 also has a corresponding recess 110N. The active area 110 includes a regular area 110L (e.g., a rectangular area) and an irregular area 110U. If all pixels in the active area 110 are substantially the same size, then in the regular area 110L of the active area 110, the number of pixels in each pixel row is the same, while in the irregular area 110U of the active area 110, the irregular area 110U includes sub-areas 110U1 and 110U2, which are opposite each other and located at the upper left and upper right of the active area 110 respectively, and are separated by a gap 110S.

[0037] Figure 2 for Figure 1 An enlarged view of the upper side of the display panel 100 shown. (As shown) Figure 2 As shown, a pixel PX, gate lines SL1, SL2, and a data line DL are provided on the substrate 102. Each pixel PX has a thin-film transistor electrically connected to one of the gate lines (gate line SL1 or gate line SL2) and the data line DL to receive scan signals and data signals to display the corresponding grayscale. For ease of explanation, Figure 2 Only a portion of the pixels PX, gate lines SL1, SL2, and data line DL are shown. Pixels PX located in the same pixel row and respectively in sub-regions 110U1 and 110U2 are electrically connected to the same gate line SL1, and each gate line SL1 spans 110U1, gap 110S, and sub-region 110U2. Figure 2 It can be seen that since there are no pixels PX in the gap 110S, the number of pixels coupled to the gate line SL1 is less than the number of pixels coupled to the gate line SL2.

[0038] Figure 3A Based on an example Figure 2 The cross-sectional view of pixel PX shown. Figure 3A As shown, pixel PX has a thin-film transistor (TFT), a first transparent electrode TE1, and a second transparent electrode TE2. The TFT has a gate G, a semiconductor layer SE, a source S, and a drain D, and the second transparent electrode TE2 is located above the first transparent electrode TE1. The gate G is part of a first metal layer ML1, the source S and drain D are part of a second metal layer ML2, and a gate insulating layer INS is located between the first metal layer ML1 and the second metal layer ML2. The first transparent electrode TE1 is electrically connected to the drain D, and a passivation layer PV is located between the first transparent electrode TE1 and the second transparent electrode TE2. The first transparent electrode TE1 and the second transparent electrode TE2 are the pixel electrode and the common electrode, respectively. Figure 3AThe structure shown is a top common electrode structure, meaning the common electrode is located above the pixel electrode.

[0039] Figure 3B For example Figure 2 The cross-sectional view of pixel PX shown. Figure 3B As shown, pixel PX has a thin-film transistor (TFT), a first transparent electrode TE1, and a second transparent electrode TE2. The TFT has a gate G, a semiconductor layer SE, a source S, and a drain D, and the second transparent electrode TE2 is located above the first transparent electrode TE1. The gate G is part of a first metal layer ML1, the source S and drain D are part of a second metal layer ML2, and a gate insulating layer INS is located between the first metal layer ML1 and the second metal layer ML2. A passivation layer PV1 is located between the second metal layer ML2 and the first transparent electrode TE1, and a passivation layer PV2 is located between the first transparent electrode TE1 and the second transparent electrode TE2. The second transparent electrode TE2 passes through passivation layers PV1 and PV2 and is electrically connected to the drain D. The first transparent electrode TE1 and the second transparent electrode TE2 are the common electrode and the pixel electrode, respectively. Figure 3B The structure shown is a top pixel structure, meaning the common electrode is located below the pixel electrode.

[0040] However, for the display panel 100 with an irregularly shaped active area 110, due to the different number of pixels coupled to gate lines SL1 and SL2, if compensation is not made for gate line SL1 which couples to fewer pixels PX, the resistive-capacitive load of gate line SL1 will differ from that of gate line SL2. This results in a significant difference between the display brightness of sub-regions 110U1 and 110U2 and the display brightness of the regular region 110L, causing poor grayscale display. The following description presents several embodiments to compensate for the resistive-capacitive load of gate line SL1, making the resistive-capacitive loads of gate line SL1 and gate line SL2 more consistent, thereby improving the problem of poor grayscale display.

[0041] Figure 4A According to the first embodiment of the present invention Figure 2 A partial layout diagram of the display panel 100 shown. Figure 4A The layout area shown can be Figure 2Region A. A potential line VL may be located in the boundary region between the active region 110 and the peripheral region 120, and it is used to provide a common voltage signal to the common electrode of each pixel PX. A gate line SL1 spans the active region 110 and the peripheral region 120, and a bridging structure BR directly connects the gate line SL1 and the gate connection line SLC located in the peripheral region 120, such that the gate line SL1 is electrically connected to the gate connection line SLC via the bridging structure BR. A common line CL is located in the peripheral region 120 and is electrically connected to the potential line VL via a connection structure CS1, such that the potential line VL provides a common voltage signal to the common line CL via the connection structure CS1. A compensation electrode CE is located in the peripheral region 120 and is electrically insulated from the gate line SL1 and the gate connection line SLC, and is electrically connected to the potential line VL via a connection structure CS2, such that the potential line VL provides a common voltage signal to the compensation electrode CE via the connection structure CS2.

[0042] Figure 4B for Figure 4A A sectional view along section line B-B' in the layout area shown. Figure 4B The sectional view shown corresponds to Figure 3A Please refer to the pixel structure shown below. Figure 3A and Figure 4B The common line CL and the compensation electrode CE are located below and above the gate connection line SLC, respectively. The gate G, gate line SL1, and common line CL all belong to the first metal layer ML1. The source S, drain D, and gate connection line SLC all belong to the second metal layer ML2. The second transparent electrode TE2, the bridging structure BR, and the compensation electrode CE all belong to the second transparent conductive layer TC2. The material of the second transparent conductive layer TC2 can be indium tin oxide (ITO), indium zinc oxide (IZO), or other suitable transparent conductive materials. The common line CL and the gate connection line SLC are disposed in the gap 110S.

[0043] The common line CL, gate connection line SLC, and compensation electrode CE overlap in the normal direction of the display panel 100, resulting in parasitic capacitance between the gate connection line SLC and the common line CL, and also between the gate connection line SLC and the compensation electrode CE. This increases the capacitive load of gate line SL1, making the capacitive loads of gate line SL1 and gate line SL2 nearly identical. Furthermore, as... Figure 4A and Figure 4B As shown, the width of the common line CL can be greater than the width of the gate connection line SLC to avoid the overlap area between the common line CL and the gate connection line SLC being inconsistent due to process variations in the first metal layer ML1 and the second metal layer ML2, thereby preventing the parasitic capacitance value between the gate connection line SLC and the common line CL from fluctuating.

[0044] Figure 5A According to the second embodiment of the present invention Figure 2 A partial layout diagram of the display panel 100 shown. Figure 5A The layout area shown can be Figure 2 Region A in the middle. Because Figure 5A The partial layout diagram shown is consistent with Figure 4A The content shown is largely the same, so please refer to the previous explanation for related details. Figure 4A The explanation will not be repeated here.

[0045] Figure 5B for Figure 5A A sectional view along section line B-B' in the layout area shown. Figure 5B The sectional view shown corresponds to Figure 3B Please refer to the pixel structure shown below. Figure 3B and Figure 5B The common line CL and the compensation electrode CE are located below and above the gate connection line SLC, respectively. The gate G, gate line SL1, and common line CL all belong to the first metal layer ML1. The source S, drain D, and gate connection line SLC all belong to the second metal layer ML2. The first transparent electrode TE1 and the compensation electrode CE both belong to the first transparent conductive layer TC1, and the second transparent electrode TE2 and the bridging structure BR both belong to the second transparent conductive layer TC2. The material of the second transparent conductive layer TC2 can be indium tin oxide, indium zinc oxide, or other suitable transparent conductive materials. The common line CL and the gate connection line SLC are disposed in the gap 110S.

[0046] Similar to the first embodiment, in the second embodiment, the common line CL, the gate connection line SLC, and the compensation electrode CE overlap in the normal direction of the display panel 100, and the width of the common line CL can be greater than the width of the gate connection line SLC. Similarly, the width of the compensation electrode CE can be greater than the width of the gate connection line SLC to avoid the overlap area between the gate connection line SLC and the compensation electrode CE being inconsistent due to process variations in the second metal layer ML2 and the first transparent conductive layer TC1, thereby preventing fluctuations in the parasitic capacitance value between the gate connection line SLC and the compensation electrode CE.

[0047] Figure 6A According to the third embodiment of the present invention Figure 2 A partial layout diagram of the display panel 100 shown. Figure 6A The layout area shown can be Figure 2 Region A in the middle. Figure 6A The partial layout diagram shown is consistent with Figure 4A The difference shown is that the bridging structure BR directly connects the gate line SL1 and the compensation trace CPL located in the peripheral region 120, so that the gate line SL1 is electrically connected to the compensation trace CPL via the bridging structure BR. Furthermore, as... Figure 6AAs shown, the gate line SL1 and the compensation trace CPL extend together along the X direction. The compensation electrode CE is located in the peripheral region 120 and is electrically insulated from the gate line SL1 and the compensation trace CPL. It is electrically connected to the potential line VL via the connection structure CS, so that the potential line VL provides a common voltage signal to the compensation electrode CE via the connection structure CS. The remaining part is... Figure 4A The content shown is largely the same, so please refer to the previous explanation for related details. Figure 4A The explanation will not be repeated here.

[0048] Figure 6B for Figure 6A A sectional view along section line B-B' in the layout area shown. Figure 6B The sectional view shown corresponds to Figure 3B Please refer to the pixel structure shown below. Figure 3B and Figure 6B The common line CL and the compensation electrode CE are located below and above the compensation line CPL, respectively. The gate G and gate line SL1 both belong to the first metal layer ML1. The source S, drain D, and common line CL all belong to the second metal layer ML2. The first transparent electrode TE1 and compensation line CPL both belong to the first transparent conductive layer TC1, and the second transparent electrode TE2, the bridging structure BR, and compensation electrode CE all belong to the second transparent conductive layer TC2. The common line CL and compensation line CPL are located in the gap 110S.

[0049] Gate line SL1, common line CL, compensation line CPL, and compensation electrode CE overlap in the normal direction of display panel 100, resulting in parasitic capacitance between gate line SL1 and common line CL, parasitic capacitance between common line CL and compensation line CPL, and parasitic capacitance between compensation line CPL and compensation electrode CE. This increases the capacitive load of gate line SL1, making the capacitive loads of gate line SL1 and gate line SL2 nearly identical. Furthermore, as... Figure 6A and Figure 6B As shown, the width of the common line CL can be greater than the width of the gate line SL1 and the width of the compensation line CPL, so as to avoid the overlapping area of ​​the gate line SL1, the common line CL and the compensation line CPL being inconsistent due to process variations of the first metal layer ML1, the second metal layer ML2 and the first transparent conductive layer TC1, thereby avoiding the fluctuation of the parasitic capacitance values ​​between the gate line SL1 and the common line CL and between the common line CL and the compensation line CPL.

[0050] Figure 7A According to the fourth embodiment of the present invention Figure 2 A partial layout diagram of the display panel 100 shown. Figure 7A The partial layout diagram shown is consistent with Figure 4AThe difference shown is that the bridging structure BR is part of the compensation trace CPL located in the peripheral area 120. Furthermore, as... Figure 7A As shown, the compensation electrode CE is located in the peripheral region 120 and is electrically insulated from the gate connection line SLC and the compensation trace CPL. It is electrically connected to the potential line VL via the connection structure CS2, so that the potential line VL provides a common voltage signal to the compensation electrode CE via the connection structure CS2.

[0051] Figure 7B for Figure 7A A sectional view along section line B-B' in the layout area shown. Figure 7B The sectional view shown corresponds to Figure 3B Please refer to the pixel structure shown below. Figure 3B and Figure 7B The common line CL and the compensation electrode CE are located below and above the gate connection line SLC, respectively. The compensation trace CPL is located above the compensation electrode CE. The gate G, gate line SL1, and common line CL all belong to the first metal layer ML1. The source S, drain D, and gate connection line SLC all belong to the second metal layer ML2. The first transparent electrode TE1 and the compensation electrode CE both belong to the first transparent conductive layer TC1, and the second transparent electrode TE2, the bridging structure BR, and the compensation trace CPL all belong to the second transparent conductive layer TC2. The common line CL, gate connection line SLC, and compensation trace CPL are disposed in the gap 110S.

[0052] The common line CL, gate connection line SLC, compensation electrode CE, and compensation trace CPL overlap in the normal direction of the display panel 100, causing parasitic capacitance to be generated between the gate connection line SLC and the common line CL, between the gate connection line SLC and the compensation electrode CE, and between the compensation electrode CE and the compensation trace CPL. This increases the capacitive load of gate line SL1, making the capacitive loads of gate line SL1 and gate line SL2 nearly identical. Furthermore, as... Figure 7A and Figure 7B As shown, the width of the common line CL can be greater than the width of the gate connection line SLC to avoid the overlap area between the common line CL and the gate connection line SLC being inconsistent due to process variations in the first metal layer ML1 and the second metal layer ML2, thereby preventing the parasitic capacitance value between the gate connection line SLC and the common line CL from fluctuating.

[0053] Figure 8 This is a comparison chart of gate line impedance differences between embodiments and comparative examples of the present invention. The broken line in the embodiments represents the resistance-capacitance impedance difference between irregular and regular region gate lines with the compensation structure design of the present invention, while the broken line in the comparative examples represents the resistance-capacitance impedance difference between irregular and regular region gate lines without the compensation structure design of the present invention. Based on... Figure 8 As shown, in the comparative example, the resistance-capacitance difference between the irregular and regular gate lines decreases sequentially (the topmost gate line is the first irregular gate line, and the gate line numbers increase from top to bottom). However, the resistance-capacitance difference between the last irregular gate line and the regular gate line is still higher than 55%. In contrast, in the embodiment of the present invention, the resistance-capacitance difference between all irregular and regular gate lines is less than 5%. Therefore, the compensation structure design proposed in this invention can significantly reduce the resistance-capacitance difference between irregular and regular gate lines, making their resistance-capacitance nearly identical, thereby improving the problem of poor grayscale display.

[0054] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A display panel, characterized in that, The display panel has an active area and a peripheral area, and the display panel includes: One substrate; Multiple pixels are disposed on the substrate and located in the active region; A plurality of gate lines are disposed on the substrate and configured to receive a plurality of scan signals. Each of the plurality of gate lines is coupled to one or more of the plurality of pixels. The number of pixels coupled to a first gate line of the plurality of gate lines is less than the number of pixels coupled to a second gate line of the plurality of gate lines. The first gate line spans the active region and the peripheral region. A gate connection line is located in the peripheral region and electrically connected to the first gate line; A common line is located in the peripheral region and disposed below the gate connection line, the common line being configured to receive a common voltage signal; A compensation electrode is located in the peripheral region and disposed above the gate connection line, the compensation electrode being configured to receive the common voltage signal; as well as A compensation trace is located in the peripheral region and disposed above the compensation electrode, and the compensation trace is configured to receive the same scan signal as the first gate line; The common line, the gate connection line, the compensation electrode, and the compensation trace overlap in the normal direction of the display panel.

2. The display panel as described in claim 1, characterized in that, Also includes: A bridging structure is located in the peripheral region and directly connects the first gate line and the gate connection line.

3. The display panel as described in claim 2, characterized in that, The compensation trace directly connects the bridging structure and the gate connection line.

4. The display panel as described in claim 1, characterized in that, Each of the plurality of pixels includes a pixel electrode and a common electrode, the common electrode being located below the pixel electrode, and the common electrode and the compensation electrode belonging to the same transparent conductive layer.

5. The display panel as described in claim 1, characterized in that, The width of the common line is greater than the width of the gate connection line.

6. The display panel as described in claim 1, characterized in that, The active region is irregularly shaped and has a first sub-region and a second sub-region. The first sub-region and the second sub-region are opposite to each other and have a gap between them. The common line and the gate connection line are disposed in the gap.

7. A display panel, characterized in that, The display panel has an active area and a peripheral area, and the display panel includes: One substrate; Multiple pixels are disposed on the substrate and located in the active region; A plurality of gate lines are disposed on the substrate and configured to receive a plurality of scan signals. Each of the plurality of gate lines is coupled to one or more of the plurality of pixels. The number of pixels coupled to a first gate line of the plurality of gate lines is less than the number of pixels coupled to a second gate line of the plurality of gate lines. The first gate line spans the active region and the peripheral region. A common line is disposed above the first gate line and located in the peripheral region, and the common line is configured to receive a common voltage signal; A compensation trace, located above the common line, is configured to receive the same scan signal as the first gate line; and A compensation electrode is located above the compensation trace, and the compensation electrode is configured to receive the common voltage signal; The first gate line, the common line, the compensation trace, and the compensation electrode overlap in the normal direction of the display panel.

8. The display panel as described in claim 7, characterized in that, Also includes: A bridging structure is located in the peripheral region and directly connects the first gate line and the compensation trace.

9. The display panel as described in claim 8, characterized in that, Each of the plurality of pixels includes a pixel electrode and a common electrode, the common electrode being located below the pixel electrode, and the pixel electrode, the bridging structure, and the compensation electrode belonging to the same transparent conductive layer.

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