A holding output circuit for analog signals and an air conditioner

Abstract

The application discloses a holding output circuit for analog signals and an air conditioner, which comprises a delay output module connected with the conversion module, an output selection module connected with the conversion module and the delay output module, and an amplification module connected with the output selection module. When the first voltage signal output by the conversion module is not within the preset voltage signal range, the output selection module is disconnected with the conversion module, the output selection module is communicated with the delay output module, the first voltage signal is delayed by the delay setting of the delay output module, and then a second voltage signal within the preset voltage signal range is output to the output selection module, so that the upper computer system can receive and identify the second voltage signal, and the upper computer system can stably operate and prevent the upper computer system from running collapse.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more particularly to a hold output circuit for analog signals and an air conditioner. Background Technology

[0002] With the rapid development of modern measurement technology, automatic control, and artificial intelligence, sensors, as core components in the technological field, are playing an increasingly important role, and the stability of sensor data transmission is becoming increasingly crucial. When a sensor device directly transmits electrical signals to a host computer system without processing, the host computer system will be unable to recognize the signal if the transmitted signal is outside the sensor's operating signal range. This can lead to errors in the signal and, in severe cases, even cause the host computer system to crash. Summary of the Invention

[0003] In view of this, the present invention provides a hold output circuit and an air conditioner for analog signals, which solves the problem in the prior art that when the electrical signal transmitted by the sensor to the host computer system is not within the preset voltage signal range, the host computer system will not be able to recognize the electrical signal, resulting in errors in the electrical signal, and in severe cases, even causing the host computer system to crash.

[0004] To achieve one, some, or all of the above objectives, or other objectives, the technical solution of the present invention is to provide a hold output circuit for analog signals, comprising:

[0005] The conversion module is used to convert the input current signal into a first voltage signal and output it externally.

[0006] A delay output module, which is connected to the conversion module, is used to output a second voltage signal within the preset voltage signal range after a delay setting by the delay output module when the first voltage signal output by the conversion module is not within the preset voltage signal range.

[0007] An output selection module, which is connected to the conversion module and the delay output module, is used to disconnect from the conversion module and connect to the delay output module when the first voltage signal output by the conversion module is not within the preset voltage signal range;

[0008] An amplification module, connected to the output selection module, is used to amplify and output the input voltage signal.

[0009] Furthermore, the conversion module includes: operational amplifier U1, resistor R1, resistor R2, resistor R3, feedback resistor R4, and resistor R5;

[0010] The first ends of resistor R1 and resistor R2 are simultaneously connected to a first terminal, which serves as the positive terminal of the current signal; the second ends of resistor R1 and resistor R3 are simultaneously connected to a second terminal, which serves as the negative terminal of the current signal.

[0011] The second end of resistor R2 and the first end of feedback resistor R4 are both connected to the inverting input of operational amplifier U1;

[0012] The second end of resistor R3 and the first end of resistor R5 are both connected to the non-inverting input of operational amplifier U1, and the second end of resistor R5 is grounded.

[0013] The output terminal of the operational amplifier U1 is simultaneously connected to the second terminal of the feedback resistor R4, the input terminal of the delay output module, and the first input terminal of the output selection module.

[0014] Furthermore, the resistance values ​​of resistor R2 and resistor R3 are the same; the resistance values ​​of feedback resistor R4 and resistor R5 are the same.

[0015] Furthermore, the formula for calculating the voltage V1 at the output terminal of the operational amplifier U1 is as follows:

[0016] V1 = -u1 * (R4 / R2);

[0017] Where u1 is the voltage difference generated by resistor R1, R4 is the resistance value of feedback resistor R4, and R2 is the resistance value of resistor R2.

[0018] Furthermore, the delayed output module includes: operational amplifier U2, feedback resistor R6, resistor R7, resistor R8, resistor R9, capacitor C1, capacitor C2, and diode D1;

[0019] The first end of the resistor R9 is connected to the output terminal of the operational amplifier U1, the second end of the resistor R9 is connected to the first end of the capacitor C1, the second end of the capacitor C1, the first end of the capacitor C2, the first end of the resistor R8 and the positive terminal of the diode D1 are all connected to the inverting terminal of the operational amplifier U2, and the second end of the capacitor C2 is grounded.

[0020] The second end of resistor R8, the cathode of diode D1, the second end of feedback resistor R6, and the second input end of output selection module are all connected to the output end of operational amplifier U2. The first end of feedback resistor R6 and the first end of resistor R7 are all connected to the non-inverting input of operational amplifier U2. The second end of resistor R7 is grounded.

[0021] The power supply terminal of the operational amplifier U2 is connected to the VCC pin, and the ground terminal of the operational amplifier U2 is grounded.

[0022] Furthermore, the output selection module includes: selection switch S1 and selection switch S2;

[0023] The rotating end of the selection switch S1 is connected to the output end of the operational amplifier U2. The first connection end of the selection switch S1 is grounded. The second connection end of the selection switch S1 is connected to the second connection end of the selection switch S2. The first connection end of the selection switch S2 is connected to the output end of the operational amplifier U1. The rotating end of the selection switch S2 is connected to the input end of the amplification module.

[0024] Furthermore, the amplification module includes: operational amplifier U3, resistor R10, resistor R11, and feedback resistor Rf;

[0025] The first end of the resistor R10 is connected to the rotating end of the selector switch S2. The second end of the resistor R10 and the first end of the feedback resistor Rf are simultaneously connected to the inverting end of the operational amplifier U3. The output end of the operational amplifier U3 and the second end of the feedback resistor Rf are simultaneously connected to the output end of the amplification module. The non-inverting end of the operational amplifier U3 is connected to the first end of the resistor R11. The second end of the resistor R11 is grounded.

[0026] Furthermore, the formula for calculating the voltage V3 at the output terminal of the operational amplifier U3 is as follows:

[0027] V3 = -Vi * (Rf / R10);

[0028] Where Vi is the input voltage at the inverting input of operational amplifier U3, Rf is the resistance value of feedback resistor Rf, and R10 is the resistance value of resistor R10.

[0029] Furthermore, the preset voltage signal range is the operating signal range of the sensor.

[0030] An air conditioner includes the hold output circuit for analog signals as described in any one of the preceding claims.

[0031] Compared with the prior art, the present invention has at least the following beneficial effects:

[0032] This invention includes a conversion module, a delay output module, an output selection module, and an amplification module. When the first voltage signal output by the conversion module is not within the preset voltage signal range, the output selection module disconnects from the conversion module and connects to the delay output module. This allows the first voltage signal to undergo a delay set by the delay output module before outputting a second voltage signal within the preset voltage signal range to the output selection module. This enables the host computer system to receive and recognize the second voltage signal, ensuring stable operation of the host computer system and preventing system crashes. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a circuit diagram of the analog signal hold output circuit of the present invention;

[0035] Figure 2 This is a connection block diagram of the analog signal hold output circuit of the present invention;

[0036] Figure 3 This is a circuit diagram showing the first operating condition of the analog signal holding output circuit of the present invention;

[0037] Figure 4 This is a circuit diagram illustrating the second operating condition of the analog signal holding output circuit of the present invention.

[0038] Figure label:

[0039] 10. Conversion module; 20. Delay output module; 30. Output selection module; 40. Amplification module. Detailed Implementation

[0040] To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Therefore, a feature pointed out in this specification is used to illustrate one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0041] The principles and structure of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0042] To enable the host computer system to recognize the received voltage signal, this invention designs a hold-output circuit for analog signals, including a conversion module 10, a delay output module 20, an output selection module 30, and an amplification module 40. When the first voltage signal output by the conversion module 10 is not within the preset voltage signal range, the output selection module 30 is disconnected from the conversion module 10 and connected to the delay output module 20. This allows the first voltage signal to be delayed by the delay output module 20 and then output to the output selection module 30 as a second voltage signal within the preset voltage signal range. This enables the host computer system to receive and recognize the second voltage signal, preventing the host computer system from crashing.

[0043] As one embodiment, refer to the appendix Figure 1-4 This invention proposes a hold-output circuit for analog signals, comprising: a conversion module 10, which converts an input current signal into a first voltage signal and outputs it; a delay output module 20, connected to the conversion module 10, which outputs a second voltage signal within the preset voltage signal range after a delay set by the delay output module 20 when the first voltage signal output by the conversion module 10 is outside the preset voltage signal range; an output selection module 30, connected to the conversion module 10 and the delay output module 20, which disconnects from the conversion module 10 and connects to the delay output module 20 when the first voltage signal output by the conversion module 10 is outside the preset voltage signal range; and an amplification module 40, connected to the output selection module 30, which amplifies the input voltage signal and outputs it.

[0044] Specifically, the preset voltage signal range is preferably the operating signal range of the sensor.

[0045] Specifically, the hold output circuit for analog signals of the present invention has two forms:

[0046] See attached document Figure 3 First, when the first voltage signal output by the conversion module 10 is within the preset voltage signal range, the output selection module 30 is connected to the conversion module 10, and the output selection module 30 is disconnected from the delay output module 20 (at this time, the delay output module 20 can be regarded as not working). The first voltage signal is directly output to the host computer system through the output selection module 30 and the amplification module 40.

[0047] See attached document Figure 4Secondly, when the first voltage signal output by the conversion module 10 is not within the preset voltage signal range, the output selection module 30 is disconnected from the conversion module 10 and connected to the delay output module 20. At this time, the first voltage signal that is not within the preset voltage signal range will be delayed by the delay output module 20, and then the delay output module 20 will output a second voltage signal within the preset voltage signal range to the output selection module 30 so that the host computer system can receive and identify the second voltage signal, ensuring that the second voltage signal is not distorted and that the host computer system can operate stably without crashing.

[0048] For details, please refer to the appendix. Figure 1 The conversion module 10 includes: operational amplifier U1, resistors R1, R2, R3, feedback resistor R4, and R5; the delay output module 20 includes: operational amplifier U2, feedback resistors R6, R7, R8, and R9, capacitors C1 and C2, and diode D1; the output selection module 30 includes: selection switch S1 and selection switch S2; the amplification module 40 includes: operational amplifier U3, resistors R10 and R11, and feedback resistor Rf.

[0049] Among them, the operational amplifiers U1, U2 and U3 are any one of LM1458, LM2904, LM308, LM358 and F318 respectively, and of course, other operational amplifiers that can perform the corresponding functions are also included; resistor R1 is the sampling resistor.

[0050] The first end of resistor R1 and the first end of resistor R2 are both connected to a first terminal, which serves as the positive terminal of the current signal; the second end of resistor R1 and the first end of resistor R3 are both connected to a second terminal, which serves as the negative terminal of the current signal.

[0051] The second end of resistor R2 and the first end of feedback resistor R4 are simultaneously connected to the inverting input of operational amplifier U1; the second end of resistor R3 and the first end of resistor R5 are simultaneously connected to the non-inverting input of operational amplifier U1, and the second end of resistor R5 is grounded; the output terminal of operational amplifier U1 is simultaneously connected to the second end of feedback resistor R4, the first end of resistor R9 and the first selection terminal of selection switch S2.

[0052] The second end of the resistor R9 is connected to the first end of the capacitor C1. The second end of the capacitor C1, the first end of the capacitor C2, the first end of the resistor R8, and the positive terminal of the diode D1 are all connected to the inverting input of the operational amplifier U2. The second end of the capacitor C2 is grounded.

[0053] The second end of resistor R8, the cathode of diode D1, the second end of feedback resistor R6, and the first connection terminal of selector switch S1 are all connected to the output terminal of operational amplifier U2; the first end of feedback resistor R6 and the first end of resistor R7 are all connected to the non-inverting input of operational amplifier U2, and the second end of resistor R7 is grounded; the power supply terminal of operational amplifier U2 is connected to the VCC pin, and the ground terminal of operational amplifier U2 is grounded; wherein the power supply voltage of the VCC pin is 5V.

[0054] The first connection terminal of the selector switch S1 is grounded, the second connection terminal of the selector switch S1 is connected to the second connection terminal of the selector switch S2, the rotating end of the selector switch S2 is connected to the first terminal of the resistor R10, the second terminal of the resistor R10 and the first terminal of the feedback resistor Rf are simultaneously connected to the inverting terminal of the operational amplifier U3, the output terminal of the operational amplifier U3 and the second terminal of the feedback resistor Rf are simultaneously connected to the output terminal of the amplification module 40, the non-inverting terminal of the operational amplifier U3 is connected to the first terminal of the resistor R11, and the second terminal of the resistor R11 is grounded.

[0055] For details, please refer to the appendix. Figure 1 The present invention provides two types of hold output circuits for analog signals:

[0056] See attached document Figure 3 Firstly, when the first voltage signal output from the output terminal of operational amplifier U1 is within the preset voltage signal range, the rotating end of selector switch S2 is connected to the first connection terminal of selector switch S2, and the rotating end of selector switch S1 is connected to the first connection terminal of selector switch S1 (that is, output selection module 30 is connected to conversion module 10, and output selection module 30 is disconnected from delay output module 20). The output terminal of operational amplifier U2 remains at a low level and is grounded. The first voltage signal flows directly from operational amplifier U1 to operational amplifier U3, and is then amplified and output.

[0057] See attached document Figure 4Secondly, when the first voltage signal output from the output terminal of operational amplifier U1 is outside the preset voltage signal range, the rotating terminal of selector switch S2 is connected to the second connection terminal of selector switch S2, and the rotating terminal of selector switch S1 is connected to the second connection terminal of selector switch S1 (i.e., output selection module 30 is disconnected from conversion module 10, and output selection module 30 is connected to delay output module 20). At this time, the first voltage signal (also called a negative pulse) outside the preset voltage signal range will be input to the inverting terminal of operational amplifier U2 through resistor R9 and capacitor C1, causing the potential of the inverting terminal of operational amplifier U2 to be lower than the potential of the non-inverting terminal of operational amplifier U2. Then, the output terminal of operational amplifier U2 will flip from low level to high level. The high level of the output terminal of operational amplifier U2 is then divided by resistors R6 and R7 and input to the non-inverting terminal of operational amplifier U2, making the potential of the non-inverting terminal of operational amplifier U2 higher than the potential of the inverting terminal of operational amplifier U2, thereby keeping the output terminal of operational amplifier U2 at a high level.

[0058] The delay setting logic of the delayed output module 20 is as follows: the high level at the output of operational amplifier U2 charges capacitor C2 through resistor R8. When the voltage of capacitor C2 is charged to the point that the potential of the inverting input of operational amplifier U2 is higher than the potential of the non-inverting input, the output of operational amplifier U2 flips to a low level. At this time, the potential of the non-inverting input of operational amplifier U2 is approximately zero, while the voltage of capacitor C2 discharges rapidly to the output of operational amplifier U2 through diode D1, accelerating the circuit's return to the initial state (the initial state is that the output of operational amplifier U2 is low). After the circuit stabilizes, the potential of the inverting input of operational amplifier U2 remains higher than the potential of the non-inverting input, thus maintaining the low level of the output of operational amplifier U2.

[0059] Therefore, the first voltage signal, which is outside the preset voltage signal range, flows to the operational amplifier U2 to generate a second voltage signal within the preset voltage signal range. This second voltage signal then flows to the operational amplifier U3, is amplified, and outputs outward so that the host computer system can receive and recognize the second voltage signal, ensuring that the data in the second voltage signal is not distorted and that the host computer system can operate stably without crashing.

[0060] For details, please refer to the appendix. Figure 1 The resistance values ​​of resistor R2 and R3 are the same; the resistance values ​​of feedback resistor R4 and R5 are the same. From the virtual open circuit, we can conclude that the current flowing through resistors R2 and R4 is equal, and the current flowing through resistors R3 and R5 is equal. From the virtual short circuit, we can conclude that the voltage at the non-inverting input of operational amplifier U1 is equal to the voltage at the inverting input of operational amplifier U1.

[0061] Therefore, the formula for calculating the voltage V1 at the output terminal of operational amplifier U1 is:

[0062] V1 = -u1 * (R4 / R2);

[0063] Where u1 is the voltage difference generated by sampling resistor R1, R4 is the resistance value of feedback resistor R4, and R2 is the resistance value of resistor R2.

[0064] For details, please refer to the appendix. Figure 1 The first or second voltage signal flowing into the amplification module 40 is applied to the inverting input of the operational amplifier U3 via resistor R10. The voltage at the output of the operational amplifier U3 is fed back to the inverting input of the operational amplifier U3 via feedback resistor Rf, forming a voltage parallel negative feedback amplification circuit. Furthermore, based on the virtual open circuit, the current flowing through resistor R10 and feedback resistor Rf is equal.

[0065] Therefore, the formula for calculating the voltage V3 at the output terminal of operational amplifier U3 is:

[0066] V3 = -Vi * (Rf / R10);

[0067] Where Vi is the input voltage at the inverting input of operational amplifier U3, Rf is the resistance value of feedback resistor Rf, and R10 is the resistance value of resistor R10.

[0068] The principle of virtual short circuit: When analyzing an operational amplifier in a linear state, the inverting and non-inverting inputs can be considered to be at the same potential. This characteristic is called a virtual short circuit, or simply virtual short.

[0069] Virtual Short Circuit Principle: When analyzing an operational amplifier in a linear state, the inverting and non-inverting inputs can be considered as equivalent open circuits. This characteristic is called a virtual open circuit, or simply virtual short circuit.

[0070] Specifically, if the first voltage signal is not within the preset voltage signal range during the first operation of the analog signal holding output circuit of the present invention, the delay output module 20 will not work properly, which will cause the analog signal holding output circuit of the present invention to malfunction.

[0071] The present invention also proposes an air conditioner, including the analog signal holding output circuit described in any one of the above claims. The air conditioner contains a corresponding sensor, and the current signal output by the sensor first passes through the analog signal holding output circuit of the present invention before being transmitted to the host computer system, ensuring that the electrical signal received by the host computer system is within the sensor's operating signal range. Preferably, the host computer system is an air conditioner group control system.

[0072] Working principle of the invention:

[0073] First, the input current signal passes through the sampling resistor R1 of the conversion module 10, generating a voltage difference u1 across resistor R1. Since R3=R2 and R4=R5, based on circuit knowledge such as virtual short and virtual open, the voltage V1 at the output terminal of the operational amplifier U1 is -u1*(R4 / R2).

[0074] Then, the voltage signal output from the output terminal of operational amplifier U1 has two possibilities:

[0075] First, if the first voltage signal output by operational amplifier U1 is within the preset voltage signal range, then the first voltage signal will not pass through operational amplifier U2 and will be directly input to operational amplifier U3. Then, operational amplifier U3 will amplify the first voltage signal and input it to the host computer system.

[0076] Second, if the first voltage signal output by the operational amplifier U1 is not within the preset voltage signal range, then the first voltage signal that is not within the preset voltage signal range will not be directly input to the operational amplifier U3. Instead, it will first be delayed by the delay output module 20 to generate a second voltage signal within the preset voltage signal range. Then, the operational amplifier U2 will input the second voltage signal to the operational amplifier U3. Finally, the operational amplifier U3 will amplify the second voltage signal and input it to the host computer system.

[0077] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A hold output circuit for analog signals, characterized in that: include: The conversion module is used to convert the input current signal into a first voltage signal and output it externally. A delay output module, which is connected to the conversion module, is used to output a second voltage signal within the preset voltage signal range after a delay setting by the delay output module when the first voltage signal output by the conversion module is not within the preset voltage signal range. An output selection module, which is connected to the conversion module and the delay output module, is used to disconnect from the conversion module and connect to the delay output module when the first voltage signal output by the conversion module is not within the preset voltage signal range; An amplification module, connected to the output selection module, is used to amplify and output the input voltage signal; The delay output module contains a capacitor, and the delay setting is generated by charging and discharging the capacitor, which is used to convert a first voltage signal that is not within the preset voltage signal range into a second voltage signal within the preset voltage signal range.

2. The hold output circuit for analog signals according to claim 1, characterized in that: The conversion module includes: operational amplifier U1, resistor R1, resistor R2, resistor R3, feedback resistor R4, and resistor R5; The first ends of resistor R1 and resistor R2 are simultaneously connected to a first terminal, which serves as the positive terminal of the current signal; the second ends of resistor R1 and resistor R3 are simultaneously connected to a second terminal, which serves as the negative terminal of the current signal. The second end of resistor R2 and the first end of feedback resistor R4 are simultaneously connected to the inverting input of operational amplifier U1; the second end of resistor R3 and the first end of resistor R5 are simultaneously connected to the non-inverting input of operational amplifier U1, and the second end of resistor R5 is grounded; the output terminal of operational amplifier U1 is simultaneously connected to the second end of feedback resistor R4, the input terminal of delay output module, and the first input terminal of output selection module.

3. The hold output circuit for analog signals according to claim 2, characterized in that: The resistance value of resistor R2 is the same as that of resistor R3; the resistance value of feedback resistor R4 is the same as that of resistor R5.

4. The hold output circuit for analog signals according to claim 3, characterized in that: The formula for calculating the voltage V1 at the output terminal of the operational amplifier U1 is as follows: V1 = -u1 * (R4 / R2); Where u1 is the voltage difference generated by resistor R1, R4 is the resistance value of feedback resistor R4, and R2 is the resistance value of resistor R2.

5. The hold output circuit for analog signals according to claim 2, characterized in that: The delayed output module includes: operational amplifier U2, feedback resistor R6, resistor R7, resistor R8, resistor R9, capacitor C1, capacitor C2, and diode D1; The first end of resistor R9 is connected to the output terminal of operational amplifier U1, and the second end of resistor R9 is connected to the first end of capacitor C1. The second end of capacitor C1, the first end of capacitor C2, the first end of resistor R8, and the positive terminal of diode D1 are all connected to the inverting input of operational amplifier U2. The second end of capacitor C2 is grounded. The second end of resistor R8, the negative terminal of diode D1, the second end of feedback resistor R6, and the second input terminal of output selection module are all connected to the output terminal of operational amplifier U2. The first end of feedback resistor R6 and the first end of resistor R7 are all connected to the non-inverting input of operational amplifier U2. The second end of resistor R7 is grounded. The power supply terminal of operational amplifier U2 is connected to the VCC pin, and the ground terminal of operational amplifier U2 is grounded.

6. The hold output circuit for analog signals according to claim 5, characterized in that: The output selection module includes: selection switch S1 and selection switch S2; The rotating end of the selection switch S1 is connected to the output end of the operational amplifier U2. The first connection end of the selection switch S1 is grounded. The second connection end of the selection switch S1 is connected to the second connection end of the selection switch S2. The first connection end of the selection switch S2 is connected to the output end of the operational amplifier U1. The rotating end of the selection switch S2 is connected to the input end of the amplification module.

7. The hold output circuit for analog signals according to claim 6, characterized in that: The amplification module includes: operational amplifier U3, resistor R10, resistor R11, and feedback resistor Rf; The first end of the resistor R10 is connected to the rotating end of the selector switch S2. The second end of the resistor R10 and the first end of the feedback resistor Rf are simultaneously connected to the inverting end of the operational amplifier U3. The output end of the operational amplifier U3 and the second end of the feedback resistor Rf are simultaneously connected to the output end of the amplification module. The non-inverting end of the operational amplifier U3 is connected to the first end of the resistor R11. The second end of the resistor R11 is grounded.

8. The hold output circuit for analog signals according to claim 7, characterized in that: The formula for calculating the voltage V3 at the output terminal of the operational amplifier U3 is as follows: V3 = -Vi * (Rf / R10); Where Vi is the input voltage at the inverting input of operational amplifier U3, Rf is the resistance value of feedback resistor Rf, and R10 is the resistance value of resistor R10.

9. The hold output circuit for analog signals according to claim 1, characterized in that: The preset voltage signal range is the operating signal range of the sensor.

10. An air conditioner, characterized in that: Includes the hold output circuit for analog signals as described in any one of claims 1-9.

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