Pixel circuit and driving method thereof, and display panel

Abstract

The present invention provides a pixel circuit, a driving method thereof, and a display panel. The pixel circuit includes an initialization module, a light-emitting element, a first light-emitting control module, and a driving transistor; the initialization module includes first, second, and third initialization modules; the first initialization module resets the potential of the first end of the light-emitting element and the control end of the driving transistor with a reference voltage; the second initialization module resets the potential of the first and second ends of the driving transistor with a reference voltage; the third initialization module resets the potential of the control end of the driving transistor with a first power supply voltage or a voltage of a second light-emitting control signal; the first light-emitting control module resets the potential of the first and second ends of the driving transistor with a first power supply voltage; wherein the reference voltage is less than the voltage of the first power supply voltage or the second light-emitting control signal. The present invention improves the display ghosting problem of the display panel caused by the hysteresis of the driving transistor by resetting the three-terminal potential of the driving transistor alternately with high and low potentials.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display panel. Background Art

[0002] Organic Light Emitting Display (OLED) devices have many advantages, such as being fully solid-state, self-luminous, wide viewing angle, wide color gamut, fast response speed, high luminous efficiency, high brightness, high contrast, ultra-thin, ultra-light, low power consumption, wide operating temperature range, the ability to produce large-size and flexible panels, and simple manufacturing process. They can achieve truly flexible displays and have received increasing attention and attention in the market in recent years.

[0003] In organic light-emitting display devices, OLEDs are driven to emit light through pixel circuits, which include multiple transistors. Due to the hysteresis effect of transistors, when low grayscale (especially black screen) and high grayscale (especially 255 grayscale) are switched to medium grayscale at the same time, there is a current difference, which will cause afterimages and reduce display quality. In addition, the hysteresis effect of the transistors makes the brightness of the first frame when switching from low grayscale to high grayscale fail to meet expectations, which will cause a smearing phenomenon and also affect the display quality of the display device. To address the impact of the hysteresis effect of the driving transistor on display quality, most current methods use process improvements, but the process fluctuates greatly and has not yet achieved a good and stable improvement effect. Summary of the Invention

[0004] In view of the problems in the prior art, the present invention aims to provide a pixel circuit and a driving method thereof, as well as a display panel, to improve the influence of the hysteresis effect of the driving transistor on the display effect.

[0005] An embodiment of the present invention provides a pixel circuit, comprising an initialization module, a light-emitting element, a first light-emitting control module, and a driving transistor;

[0006] The initialization module includes a first initialization module, a second initialization module, and a third initialization module; a control end of the first initialization module is electrically connected to the first scan signal line, a first end of the first initialization module is electrically connected to the reference voltage signal line, and a second end of the first initialization module is electrically connected to the first end of the light-emitting element and the control end of the driving transistor; the first initialization module initializes the potential of the first end of the light-emitting element and the potential of the control end of the driving transistor with a reference voltage in response to the first scan signal;

[0007] The control end of the second initialization module is electrically connected to the second scan signal line, the first end of the second initialization module is electrically connected to the reference voltage signal line, and the second end of the second initialization module is electrically connected to the first end or the second end of the driving transistor; the second initialization module initializes the potentials of the first end and the second end of the driving transistor with the reference voltage in response to the second scan signal;

[0008] The control end of the third initialization module is electrically connected to the third scan signal line, the first end of the third initialization module is electrically connected to the first power supply voltage signal line or the second light-emitting control signal line, and the second end of the third initialization module is electrically connected to the control end of the driving transistor; the third initialization module initializes the potential of the control end of the driving transistor with the first power supply voltage or the second light-emitting control signal in response to the third scan signal;

[0009] The control terminal of the first light-emitting control module is electrically connected to the first light-emitting control signal line, the first terminal of the first light-emitting control module is electrically connected to the first power supply voltage signal line, and the second terminal of the first light-emitting control module is electrically connected to the first terminal of the driving transistor; the first light-emitting control module initializes the potentials of the first terminal and the second terminal of the driving transistor with the first power supply voltage in response to the first light-emitting control signal;

[0010] The reference voltage is smaller than the first power supply voltage or the voltage of the second light-emitting control signal.

[0011] An embodiment of the present invention further provides a method for driving a pixel circuit, for driving the pixel circuit as described above, comprising an initialization phase during a write frame display, wherein the initialization phase comprises a first initialization phase and a second initialization phase that are repeated alternately, and the last initialization phase is a third initialization phase;

[0012] In the first initialization stage, the first scanning signal is at an operating level, and the first initialization module resets the first end of the light-emitting element and the control end of the driving transistor with the reference voltage; the second scanning signal is at an operating level, and the second initialization module resets the first end and the second end of the driving transistor with the reference voltage;

[0013] In the second initialization stage: the third scanning signal is at an operating level, and the third initialization module resets the control terminal of the driving transistor with the first power supply voltage or the voltage of the second light-emitting control signal; the first light-emitting control signal is at an operating level, and the first light-emitting control module resets the control terminal of the driving transistor with the first power supply voltage;

[0014] In the third initialization stage: the first scanning signal is at a working level, and the first initialization module resets the first end of the light-emitting element and the control end of the driving transistor with the reference voltage.

[0015] An embodiment of the present invention also provides a display panel, comprising a substrate, comprising a display area and a non-display area surrounding the display area; the display area comprises the pixel circuit array as described above; the non-display area comprises a gate drive circuit, a light emitting control drive circuit, a data drive circuit, and a reference voltage signal line, which are respectively electrically connected to the pixel circuit array to control the pixel units in the display area to display row by row.

[0016] The pixel circuit, driving method thereof, and display panel provided by the present invention have the following advantages:

[0017] The present invention uses a first initialization module and a second initialization module to reset the three-terminal potential of the driving transistor with a low-potential reference voltage, and uses a third initialization module and a first light-emitting control module to reset the three-terminal potential of the driving transistor with a high-potential first power supply voltage or the voltage of the second light-emitting control signal, that is, the three terminals of the driving transistor are reset by alternating high and low potentials, thereby improving the threshold voltage drift caused by the driving transistor under the same bias voltage and improving the display ghosting problem caused by the hysteresis effect of the driving transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0019] Figure 1 is a schematic structural diagram of a pixel circuit according to embodiment 1 of the present invention;

[0020] Figure 2 1 is a driving timing diagram of the pixel circuit of embodiment 1 of the present invention when writing a frame;

[0021] Figure 3 1 is a driving timing diagram of the pixel circuit of Example 1 of the present invention when maintaining a frame;

[0022] Figure 4 yes Figure 3 Driving timing diagram of the middle bias stage t4;

[0023] Figure 5 is a specific circuit diagram of a pixel circuit according to embodiment 1 of the present invention;

[0024] Figure 6 is a schematic structural diagram of a pixel circuit according to embodiment 2 of the present invention;

[0025] Figure 7is a specific circuit diagram of a pixel circuit according to embodiment 2 of the present invention;

[0026] Figure 8 is a schematic structural diagram of a pixel circuit according to embodiment 3 of the present invention;

[0027] Figure 9 is a specific circuit diagram of a pixel circuit according to embodiment 3 of the present invention;

[0028] Figure 10 is a schematic structural diagram of a pixel circuit according to embodiment 4 of the present invention;

[0029] Figure 11 is a specific circuit diagram of a pixel circuit according to embodiment 4 of the present invention;

[0030] Figure 12 is a schematic diagram of a display panel according to embodiment 5 of the present invention. DETAILED DESCRIPTION

[0031] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. In the figures, identical reference numerals denote identical or similar structures, and thus repetitive descriptions thereof will be omitted. The use of "or" and "either" in this specification may mean "and" or "or."

[0032] In the description of this application, reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this application. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and integrate different embodiments or examples described in this application, as well as features of different embodiments or examples, unless otherwise contradictory.

[0033] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include at least one such feature. In the context of this application, "plurality" means two or more, unless otherwise specifically defined.

[0034] To improve the image sticking problem caused by the hysteresis of the driving transistor in the prior art, the present invention provides a pixel circuit, a driving method thereof, and a display panel. The pixel circuit, a driving method thereof, and a display panel provided by the present invention will be explained in detail below with reference to specific embodiments.

[0035] Example 1

[0036] Figure 1 This is a schematic diagram of the structure of a pixel circuit provided by Example 1 of the present invention. Figure 1 As shown, the pixel circuit includes an initialization module, a light emitting element 20, a first light emitting control module 41 and a driving transistor 30; wherein,

[0037] The initialization module includes a first initialization module 11, a second initialization module 12, and a third initialization module 13. The control terminal of the first initialization module 11 is electrically connected to the first scan signal line, the first terminal of the first initialization module 11 is electrically connected to the reference voltage signal line, and the second terminal of the first initialization module 11 is electrically connected to the first terminal of the light-emitting element 20 and the control terminal of the driving transistor 30. In response to the first scan signal Scan1 transmitted by the first scan signal line, the first initialization module 11 initializes the potential of the first terminal of the light-emitting element 20 and the potential of the control terminal of the driving transistor 30 using the reference voltage Vref provided by the reference voltage signal line, thereby resetting the first terminal of the light-emitting element 20 and the control terminal of the driving transistor 30. The light-emitting element in this embodiment of the present invention is an OLED light-emitting element, but is not limited to this.

[0038] The control end of the second initialization module 12 is electrically connected to the second scan signal line, and the first end of the second initialization module 12 is electrically connected to the reference voltage signal line; the second initialization module 12 responds to the second scan signal Scan2 transmitted by the second scan signal line to initialize the potential of the first end and the second end of the driving transistor 30.

[0039] The control terminal of the third initialization module 13 is electrically connected to the third scan signal line, the first terminal of the third initialization module 13 is electrically connected to the first power supply voltage signal line, the second terminal of the third initialization module 13 is electrically connected to the control terminal of the driving transistor 30, and the second terminal of the third initialization module 13 is electrically connected to the control terminal of the driving transistor 30. The third initialization module 13 is configured to initialize the potential of the control terminal of the driving transistor 30 with the first power supply voltage VDD transmitted by the first power supply voltage signal line in response to the third scan signal Scan3 transmitted by the third scan signal line.

[0040] The control end of the first light-emitting control module 41 is electrically connected to the first light-emitting control signal line, the first end of the first light-emitting control module 41 is electrically connected to the first power supply voltage signal line, and the second end of the first light-emitting control module 41 is electrically connected to the first end of the driving transistor 30. The first light-emitting control module 41 responds to the first light-emitting control signal EM1 transmitted by the first light-emitting control signal line, and initializes the potential of the first end and the second end of the driving transistor 30 with the first power supply voltage VDD.

[0041] The reference voltage Vref is greater than the first power supply voltage VDD. It should be noted that the reference voltage Vref is a negative voltage, while the first power supply voltage VDD is a positive voltage. Therefore, the first initialization module 11 and the second initialization module 12 initialize the three-terminal potentials of the driving transistor 30 at a low potential, while the third initialization module 13 and the first light-emitting control module 41 initialize the three-terminal potentials of the driving transistor 30 at a high potential.

[0042] Please continue reading Figure 1 The pixel circuit further includes a storage capacitor 50, a compensation module 60, a data writing module 70 and a second light emitting control module 42, wherein:

[0043] A first end of the storage capacitor 50 is electrically connected to the first power supply voltage line, a second end of the storage capacitor 50 is electrically connected to the second end of the compensation module 60 and the control end of the driving transistor 30; the control end of the compensation module 60 is electrically connected to the fourth scan signal line, and a first end of the compensation module 40 is electrically connected to the second end of the driving transistor 30;

[0044] The control end of the data writing module 70 is electrically connected to the fifth scanning signal line, the first end of the data writing module 70 is electrically connected to the data line, and the second end of the data writing module 70 is electrically connected to the first end of the driving transistor 30;

[0045] A control terminal of the second light-emitting control module 42 is electrically connected to a second light-emitting control signal line. A first terminal of the second light-emitting control module 42 is electrically connected to a second terminal of the driving transistor 30. A second terminal of the second light-emitting control module 42 is electrically connected to a first terminal of the light-emitting element 20. A second terminal of the light-emitting element 20 is electrically connected to a second power supply voltage signal line. The second power supply voltage signal line provides a negative power supply voltage VSS.

[0046] Furthermore, the pixel circuit includes a potential stabilization module 80, the two ends of which are electrically connected to the first and second ends of the driving transistor 30, respectively. The potential stabilization module 80 can stabilize the potential difference between the first and second ends of the driving transistor 30, so that the voltage difference between the two ends of the driving transistor 30 is stable and does not undergo sudden changes during the light-emitting phase. This ensures that the light-emitting element 20 emits light stably, and the brightness of the light-emitting element 20 does not show obvious flickering that can be observed by humans.

[0047] Figure 2 1 is a driving timing diagram of the pixel circuit of embodiment 1, which is used to drive the pixel circuit as described above. Figure 1 and Figure 2 The display of a written frame includes an initialization phase t1, a data writing phase, a compensation phase t2, and a light-emitting phase t3. The initialization phase t1 includes a first initialization phase t11 and a second initialization phase t12, which are repeated alternately, and a third initialization phase t13, which is the final initialization phase. The driving method of the pixel circuit of Example 1 is described by taking the example of each module in the pixel circuit being turned on by a low-level signal input to its control terminal.

[0048] In the first initialization phase t11:

[0049] The first scanning signal Scan1 is at a working level, the first initialization module 11 is turned on, and the first initialization module 11 resets the first end of the light emitting element 20 and the control end of the driving transistor 30 with the reference voltage Vref;

[0050] The second scanning signal Scan2 is at an operating level, the second initialization module 12 is turned on, and the first and second terminals of the driving transistor 30 are reset with the reference voltage Vref by the second initialization module 12. It should be noted that since the reference voltage Vref is a negative voltage, when the reference voltage Vref is written to the control terminal of the driving transistor 30, the driving transistor 30 is turned on, and the potential of the second terminal of the driving transistor 30 is pulled down to a level close to the reference voltage Vref of the first terminal, that is, the first and second terminals of the driving transistor 30 are reset with the reference voltage Vref.

[0051] In the second initialization phase t12:

[0052] The third scanning signal Scan3 is at the working level, the third initialization module 13 is turned on, the first power supply voltage VDD is transmitted to the control terminal of the driving transistor 30 through the third initialization module 13, and the control terminal of the driving transistor 30 is reset by the third initialization module 13 with the first power supply voltage VDD;

[0053] The first light-emitting control signal EM1 is at an operating level, the first light-emitting control module 41 is turned on, and the first power supply voltage VDD is transmitted to the first terminal of the driving transistor 30 via the first light-emitting control module 41. The first terminal and the second terminal of the driving transistor 30 are reset by the first power supply voltage VDD. It should be noted that in the second initialization stage t12, the three terminals of the driving transistor 30 are reset by the high potential VDD.

[0054] The first initialization phase t11 and the second initialization phase t12 are alternately repeated twice according to actual needs. The timing diagram herein illustrates an example in which the first initialization phase t11 and the second initialization phase t12 are alternately repeated twice, but the present invention is not limited thereto. Alternating high and low potentials to reset the three terminals of the driving transistor 30 can improve the threshold drift caused by biasing the driving transistor 30 at the same potential, thereby improving the hysteresis effect of the driving transistor.

[0055] The last initialization is the third initialization phase t13. In the third initialization phase t13:

[0056] The first scanning signal Scan1 is at a working level, the first initialization module 11 is turned on, and the first initialization module 71 resets the first end of the light emitting element 20 and the control end of the driving transistor 30 with the reference voltage Vref.

[0057] During the first initialization phase, the first initialization module 11 performs a low-voltage reset on the control terminal of the driving transistor 30, and the second initialization module 12 performs a low-voltage reset on the first and second terminals of the driving transistor 30. During the second initialization phase, the third initialization module 13 performs a high-voltage reset on the control terminal of the driving transistor 30, and the first light control module 41 performs a high-voltage reset on the first and second terminals of the driving transistor 30. The first and second initialization phases alternate multiple times, i.e., multiple low-voltage and high-voltage resets are performed on the control terminal, first terminal, and second terminal of the driving transistor 30. The final initialization phase is the third initialization phase, in which the first initialization module 11 performs a low-voltage reset only on the control terminal of the driving transistor 30. Multiple high- and low-voltage resets prevent the threshold voltage Vth from drifting due to the continuous application of a certain voltage to the driving transistor 30, and prevent the influence of the same voltage bias on the driving transistor 30, allowing the driving transistor 30 to return to its initial state without bias. Preferably, the reference voltage Vref during the third initialization phase is lower than the reference voltage Vref during the first phase. This reduces the difference between the data voltage and the reset voltage during the data writing phase, improves the data voltage writing and compensation rate, and further improves image sticking.

[0058] Please continue reading Figure 2 When writing a frame display, the writing frame display also includes a data writing stage, a compensation stage t2, and a light emitting stage t3, including the following steps:

[0059] In the data writing stage and the compensation stage t2: the fourth scanning signal Scan4 and the fifth scanning signal Scan5 are at the working level, and the data writing module 70 and the compensation module 60 store the data voltage Data and the threshold voltage of the driving transistor 30 in the storage capacitor 50;

[0060] In the light emitting stage t3 , the first light emitting control signal EM1 and the second light emitting control signal EM2 are at working levels, driving the light emitting element 20 to emit light; the potential stabilizing module 80 stabilizes the potential difference between the first terminal and the second terminal of the driving transistor 30 .

[0061] When the display panel displays at low frequency, such as Figure 3 and Figure 4 As shown, a holding frame (i.e., no new data voltage Data is written) is included between the two writing frames. In the holding frame, the initialization module and the compensation module 60 do not work. The writing frame display includes a bias phase and a light-emitting phase. The bias phase includes a first sub-bias phase t41 and a second sub-bias phase t42 that are alternately repeated, and includes the following steps:

[0062] In the first sub-bias phase t41, the fifth scan signal Scan5 is at the working level.

[0063] Resetting the potentials of the first terminal and the second terminal of the driving transistor 30 with the data voltage Data;

[0064] In the second sub-bias stage t42, the first light-emitting control signal EM1 is at the working level, and the potentials of the first and second terminals of the driving transistor 30 are reset with the first power supply voltage VDD. It should be noted that, under the action of the storage capacitor 50, the driving transistor 30 is in the on state at this moment. In the bias stage of the holding frame, only the bias states of the first and second terminals of the driving transistor 30 are reset.

[0065] In the light-emitting stage t5: the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at the working level, driving the light-emitting element 20 to emit light; when there is a potential stabilization module 80 in the pixel circuit, under the action of the potential stabilization module 80, the potential of the first end and the second end of the driving transistor 30 changes stably without sudden changes, so that the light-emitting brightness of the light-emitting element 20 changes stably.

[0066] like Figure 5 As shown, a specific circuit diagram of a pixel circuit provided by Embodiment 1 of the present invention is shown, wherein the first initialization module 11 includes a first transistor T1 and a second transistor T2, wherein a first end of the first transistor T1 is electrically connected to a reference voltage signal line, and a second end of the first transistor T1 is connected to a first end of the light-emitting element 20;

[0067] The driving transistor 30 is a ninth transistor T9, the control terminal of the second transistor T2 is electrically connected to the first scan signal line, the first terminal of the second transistor T2 is electrically connected to the reference voltage signal line, and the second terminal of the second transistor T2 is electrically connected to the control terminal of the ninth transistor T9;

[0068] The second initialization module 12 includes a third transistor T3, and the potential stabilization module 80 includes a first capacitor C1. The control end of the third transistor T3 is electrically connected to the second scan signal line, the first end of the third transistor T3 is electrically connected to the reference signal line, and the second end of the third transistor T3 is electrically connected to the first end of the ninth transistor T9. The two ends of the first capacitor C1 are electrically connected to the first end and the second end of the ninth transistor T9, respectively.

[0069] The third initialization module 13 includes a fourth transistor T4, a control terminal of the fourth transistor T4 is electrically connected to the third scan signal line, a first terminal of the fourth transistor T4 is electrically connected to the first power supply voltage signal line, and a second terminal of the fourth transistor T4 is electrically connected to the control terminal of the ninth transistor T9;

[0070] The data writing module 70 includes a fifth transistor T5, a control end of the fifth transistor T5 is electrically connected to the fifth scan signal line, a first end of the fifth transistor T5 is electrically connected to the data line, and a second end of the fifth transistor T5 is electrically connected to the first end of the ninth transistor T9;

[0071] The compensation module 60 includes a sixth transistor T6, a storage capacitor is a second capacitor C2, a control end of the sixth transistor T6 is electrically connected to the fourth scan signal line, a first end of the sixth transistor T6 is electrically connected to the second end of the second capacitor C2, and a second end of the sixth transistor T6 is electrically connected to the second end of the ninth transistor T9;

[0072] The first light emitting control module 41 includes a seventh transistor T7, a control end of the seventh transistor T7 is electrically connected to the first light emitting control signal line, a first end of the seventh transistor T7 is electrically connected to the first power supply voltage signal line, and a second end of the seventh transistor T7 is electrically connected to the first end of the ninth transistor T9;

[0073] The second light-emitting control module 42 includes an eighth transistor T8, a control end of the eighth transistor T8 is electrically connected to the second light-emitting control signal line, a first end of the eighth transistor T8 is electrically connected to the second end of the ninth transistor T9, and a second end of the eighth transistor T8 is electrically connected to the first end of the light-emitting element 20.

[0074] Each of the above-mentioned transistors has a first terminal, a second terminal, and a control terminal. The first terminal is one of the source or drain, the second terminal is the other of the source or drain, and the control terminal is the gate. The transistors in the pixel circuits of all embodiments of the present invention are P-type thin-film transistors. P-type thin-film transistors are turned on when the control terminal is at a low level and turned off when the control terminal is at a high level. The first terminal of each transistor is the source, and the second terminal is the drain. In other embodiments, the above-mentioned transistors can also be replaced with N-type transistors.

[0075] Combine Figures 2 to 4 ,right Figure 5The working principle of the pixel circuit shown is explained in detail.

[0076] When high-frequency display is used, the display only includes a writing frame, which includes an initialization phase t1, a data writing and compensation phase t2, and a light-emitting phase t3. The initialization phase t1 includes two alternating repetitions of a first initialization phase t11 and a second initialization phase t12, and the last initialization is a third initialization phase t13:

[0077] In the first initialization phase t11: the first scan signal Scan1 is at a low level, the first transistor T1 and the second transistor T2 are turned on, and the reference voltage Vref is transmitted to the first terminal of the light-emitting element 20 through the first transistor T1 to improve the bias state of the light-emitting element 20. Here, the first terminal of the light-emitting element 20 is the anode. The reference voltage Vref is transmitted to the control terminal of the ninth transistor T9 through the second transistor T2 to initialize the potential of the control terminal of the ninth transistor T9 and improve the bias state of the control terminal of the ninth transistor T9. Here, the reference voltage Vref is a negative voltage.

[0078] The second scan signal Scan2 is at a low level, the third transistor T3 is turned on, and the reference voltage Vref is transmitted to the first end of the ninth transistor T9 through the third transistor T3. Since the control end of the ninth transistor T9 is initialized with the reference voltage Vref in the first initialization phase, the ninth transistor T9 remains in the on state, and the reference voltage Vref is transmitted to the first end and the second end of the ninth transistor T9, respectively, to initialize the first end and the second end of the ninth transistor T9.

[0079] In the second initialization stage t12: the third scan signal Scan3 is at a low level, the fourth transistor T4 is turned on, the first power supply voltage VDD is transmitted to the control end of the ninth transistor T9 through the fourth transistor T4, and the control end of the ninth transistor T9 is reset with the first power supply voltage VDD; the first light-emitting control signal EM1 is at a low level, the seventh transistor T7 is turned on, the first power supply voltage VDD is transmitted to the first end of the ninth transistor T9 through the seventh transistor T7, and when the ninth transistor is not turned off, the first power supply voltage VDD resets the first end and the second end of the ninth transistor T9.

[0080] Repeat the first initialization phase t11 and the second initialization phase t12 twice;

[0081] In the third initialization stage t13: the first scan signal Scan1 is at a low level, the first transistor T1 and the second transistor T2 are turned on, and the reference voltage Vref is transmitted to the first end of the light-emitting element 20 through the first transistor T1 to improve the bias state of the OLED; the reference voltage Vref is transmitted to the control end of the ninth transistor T9 through the second transistor T2 to initialize the control end potential of the ninth transistor T9 and improve the bias state of the ninth transistor T9. The reference voltage Vref in the third initialization stage can be slightly increased, for example, to -3V. The reference voltage Vref in the first initialization stage can be -4V. The slight increase in potential in the last initialization stage can reduce the difference between the Data voltage written in the data writing stage and the reset voltage, increase the writing rate of the data voltage Data and the compensation voltage, and improve the afterimage during display. By repeatedly resetting the high and low potentials, the threshold voltage drift caused by the continuous application of a certain voltage to the driving transistor is avoided, and the screen afterimage caused by the hysteresis of the driving transistor is reduced.

[0082] In the data writing phase and the compensation phase t2: the fourth scanning signal Scan4 and the fifth scanning signal Scan5 are at a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, and the data voltage Data and the threshold voltage of the ninth transistor T9 are stored in the second capacitor C2;

[0083] In the light-emitting stage t3: the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a low level, the seventh transistor T7 and the eighth transistor T8 are turned on, and under the action of the second capacitor C2, the ninth transistor T9 is turned on to drive the light-emitting element 20 to emit light; under the action of the first capacitor C1, the potential difference between the first end and the second end of the ninth transistor T9 changes stably, maintaining the stable operation of the ninth transistor T9.

[0084] When the display panel is displayed at a low frequency (for example, at a refresh rate of less than 30 Hz), a hold frame is further included between two writing frames. The hold frame display includes a bias phase t4 and a light-emitting phase t5. The bias phase t4 includes a first sub-bias phase t41 and a second sub-bias phase t42 that are alternately repeated, and includes the following steps:

[0085] In the first sub-bias phase t41, the fifth scan signal Scan5 is at the working level, and the potentials of the first terminal and the second terminal of the ninth transistor T9 are reset by the data voltage Data;

[0086] In the second bias sub-phase t42, the first light-emitting control signal EM1 is at the working level, and the potentials of the first terminal and the second terminal of the ninth transistor T9 are reset by the first power supply voltage VDD;

[0087] The first sub-bias phase t41 and the second sub-bias phase t42 are repeated alternately once more;

[0088] During the bias phase of the holding frame, only the bias states of the first and second ends of the ninth transistor T9 are reset, thereby improving the influence of the hysteresis effect of the ninth transistor T9 and making the ninth transistor T9 work stably during the holding frame phase.

[0089] In the light-emitting stage t5: the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at the operating level, the seventh transistor T7 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned on under the action of the second capacitor C2, driving the light-emitting element 20 to emit light; the first capacitor C1 stabilizes the potential difference between the first end and the second end of the ninth transistor T9, so that the ninth transistor T9 operates stably in the light-emitting stage, and the light-emitting element 20 emits light stably.

[0090] Example 2

[0091] Figure 6 and Figure 7 The structural diagram of the pixel circuit provided in Example 2 and the specific circuit diagram of the pixel circuit are shown respectively. Figure 6 As shown, the difference from embodiment 1 is that the first end of the third initialization module 13 is electrically connected to the second light-emitting control signal line; Figure 7 As shown, the difference from embodiment 1 is that the first end of the fourth transistor T4 is electrically connected to the second light emitting control signal line.

[0092] The second light-emission control signal line provides the voltage of the second light-emission control signal EM2. During the initialization phase, the voltage of the second light-emission control signal EM2 is at a high level. Specifically, during the second initialization phase t12, the third scan signal Scan3 is at an operating level, the third initialization module 13 is turned on, and the first power supply voltage VDD is transmitted to the control terminal of the driving transistor 30 via the third initialization module 13. The control terminal of the driving transistor 30 is then reset by the third initialization module 13 using the voltage of the second light-emission control signal EM2.

[0093] The electrical connection arrangement and driving methods of the remaining modules in Example 2 are the same as those of the modules in Example 1. For details, please refer to the description in Example 1 and will not be repeated here.

[0094] Example 3

[0095] Figure 8 and 9 FIG1 shows a schematic diagram of the structure of the pixel circuit provided by embodiment 3 of the present invention, and a specific circuit diagram of the pixel circuit. Figure 8 As shown, the difference from embodiment 2 is that the second end of the second initialization module 12 is electrically connected to the second end of the driving transistor 30; Figure 9As shown, the second end of the third transistor T3 is electrically connected to the second end of the ninth transistor T9. In the driving method of the pixel circuit provided in this embodiment, when the first and second ends of the driving transistor 30 are performing a low potential initialization operation, the reference voltage Vref is first written to the second end of the driving transistor 30. Since the driving transistor 30 is in the on state at this time, the potential of its first end is slowly pulled down to a level close to the reference voltage of the second end, thereby resetting the first and second ends of the driving transistor 30.

[0096] The electrical connection arrangement and driving method of the remaining modules in Example 2 are the same as those of the modules in Example 2. For details, please refer to the description in Example 1 and Example 2, which will not be repeated here.

[0097] Example 4

[0098] Figure 10 and Figure 11 FIG1 shows a schematic diagram of the structure and a specific circuit diagram of a pixel circuit provided by embodiment 4 of the present invention. Figure 10 As shown, the difference from Example 2 is that the reference voltage signal line includes a first reference voltage signal line and a second reference voltage signal line. The first reference voltage signal line provides a first reference voltage Vref1, and the second reference voltage signal line provides a second reference voltage Vref2. The first initialization module 11 includes a first sub-initialization module 111 and a second sub-initialization module 112. The first end of the first sub-initialization module 111 is electrically connected to the second reference voltage signal line, and the second end of the first sub-initialization module 111 is electrically connected to the first end of the light-emitting element 20. The first end of the second sub-initialization module 112 is electrically connected to the first reference voltage signal line, and the second end of the second sub-initialization module 112 is electrically connected to the control end of the driving transistor 30. The first end of the second initialization module 12 is electrically connected to the first reference voltage signal line. In response to the first scan signal Scan1, the first sub-initialization module 111 resets the first end of the light-emitting element 20 with the second reference voltage Vref2. In response to the first scan signal Scan1, the second sub-initialization module 112 resets the control end of the light-emitting element 20 with the first reference voltage Vref1. It should be noted that the first reference voltage Vref1 and the second reference voltage Vref2 are different. Resetting the control terminal of the driving transistor 30 using two reference voltages can improve the reset efficiency of the pixel circuit and increase the refresh rate of the display.

[0099] The pixel circuit further includes a fourth initialization module 14 and a fifth initialization module 15, wherein:

[0100] The control end of the fourth initialization module 14 is electrically connected to the second scan signal line, the first end of the fourth initialization module 14 is electrically connected to the first reference voltage signal line, and the second end of the fourth initialization module 14 is electrically connected to the second end of the driving transistor 30;

[0101] The control end of the fifth initialization module 15 is electrically connected to the third scan signal line, the first end of the fifth initialization module 15 is electrically connected to the second light emitting control signal line, and the second end of the fifth initialization module 15 is electrically connected to the second end of the driving transistor 30 .

[0102] The fourth initialization module 14, in response to the second scan signal Scan2, resets the second terminal of the driving transistor 30 with the first reference voltage Vref1. The fifth initialization module 15, in response to the third scan signal Scan3, resets the second terminal of the driving transistor 30 with the voltage of the second emission control signal EM2. By providing the initialization module directly at the second terminal of the driving transistor 30, the three terminals of the driving transistor 30 can be initialized to high and low voltages simultaneously, improving the efficiency of returning the driving transistor 30 to its initial state before the bias state, reducing the hysteresis of the driving transistor, and alleviating the image sticking problem caused by the hysteresis on the display panel.

[0103] like Figure 11 As shown, the specific circuit layout is different from that in Example 2 in that the first end of the first transistor T1 is electrically connected to the second reference voltage signal line, and the first end of the second transistor T2 is electrically connected to the first reference voltage signal line. The fourth initialization module 14 includes a tenth transistor T10, the control end of the tenth transistor T10 is electrically connected to the second scan line, the first end of the tenth transistor T10 is electrically connected to the first reference voltage signal line, and the second end of the tenth transistor T10 is electrically connected to the second end of the driving transistor 30. The fifth initialization module 15 includes an eleventh transistor T11, the control end of the eleventh transistor T11 is electrically connected to the third scan signal line, the first end of the eleventh transistor T11 is electrically connected to the second light-emitting control signal line, and the second end of the tenth transistor T11 is electrically connected to the second end of the driving transistor 30.

[0104] Accordingly, the driving method of the pixel circuit provided in Example 4 includes an initialization phase when displaying a written frame. The initialization phase includes a first initialization phase t11 and a second initialization phase t12 which are repeated alternately, and a third initialization phase t13 which is the last phase. The method includes the following steps:

[0105] In the first initialization stage, the first scan signal Scan1 is at an operating level, the first sub-initialization module 111 resets the first terminal of the light-emitting element 20 with the second reference voltage Vref2, and the second sub-initialization module 112 resets the control terminal of the driving transistor 30 with the first reference voltage Vref1; the second scan signal Scan2 is at an operating level, and the second initialization module 12 and the fourth initialization module 14 reset the first terminal and the second terminal of the driving transistor 30 with the first reference voltage;

[0106] In the second initialization phase t12, the third scanning signal Scan3 is at an operating level, the third initialization module 13 resets the control terminal of the driving transistor 30 with the voltage of the second light-emitting control signal EM2, and the fifth initialization module 15 resets the first terminal and the second terminal of the driving transistor 30 with the voltage of the second light-emitting control signal EM2; the first light-emitting control signal EM1 is at an operating level, and the first light-emitting control module resets the first terminal and the second terminal of the driving transistor 30 with the first power supply voltage VDD;

[0107] In the third initialization stage t13 , the first scan signal Scan1 is at the working level, the first sub-initialization module 111 resets the first end of the light emitting element 20 with the second reference voltage Vref2 , and the second sub-initialization module 112 resets the control end of the driving transistor 30 with the first reference voltage Vref1 .

[0108] The electrical connection method of other modules in Example 4 is the same as the electrical connection method in Example 2, and the other stages of the driving method of the pixel circuit are the same as the driving method in Example 1. For details, please refer to the description of Example 2 and will not be repeated here.

[0109] Example 5

[0110] Accordingly, an embodiment of the present invention further provides a display panel, comprising the pixel circuit as described above. Figure 12 As shown, the display panel includes:

[0111] a substrate comprising a display area and a non-display area surrounding the display area;

[0112] The display area includes a pixel circuit array as described above;

[0113] The non-display area includes a gate drive circuit, a light-emitting control drive circuit, a data drive circuit, and a reference voltage signal line, which are electrically connected to the pixel circuit array respectively to control the pixel units in the display area to display row by row. The gate drive circuit includes an S1 drive circuit, an S2 drive circuit, an S3 drive circuit, an S4 drive circuit, and an S5 drive circuit to provide scan signals Scan1 to Scan5 to the pixel circuit. The light-emitting control drive circuit includes an EM1 drive circuit and an EM2 drive circuit to provide light-emitting control signals EM1 and EM2 to the pixel circuit. In an embodiment of the present invention, the reference voltage signal line includes a Vref1 signal line and a Vref2 signal line. In other embodiments, there may be only one reference signal line, which can be set according to actual needs.

[0114] The display panel includes the pixel circuit as described above, and therefore, all technical effects of the pixel circuit can be achieved, which will not be described in detail here.

[0115] In summary, the pixel circuit, driving method thereof, and display panel provided by the present invention have the following advantages:

[0116] The present invention provides an initialization module at the control end of the driving transistor, and initializes the control end, the first end, and the second end of the control module with high and low potentials during the initialization phase, thereby improving the influence of the driving transistor being under a voltage bias for a long time and improving the hysteresis effect of the driving transistor.

[0117] By setting a potential stabilization module at the first end and the second end of the driving transistor to stabilize the potential difference between the first end and the second end of the driving transistor, the potential fluctuation at both ends of the driving transistor is reduced, the stability of the pixel circuit in the light-emitting stage is maintained, the stability of the light-emitting current in the light-emitting stage is improved, and the afterimage problem of the display screen is improved.

[0118] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: It includes an initialization module, a light-emitting element, a first light-emitting control module and a driving transistor; The initialization module includes a first initialization module, a second initialization module, and a third initialization module; the control end of the first initialization module is electrically connected to the first scan signal line, the first end of the first initialization module is electrically connected to the reference voltage signal line, and the second end of the first initialization module is electrically connected to the first end of the light-emitting element and the control end of the driving transistor; The first initialization module initializes the potential of the first terminal of the light emitting element and the potential of the control terminal of the driving transistor with a reference voltage in response to the first scanning signal; The control end of the second initialization module is electrically connected to the second scan signal line, the first end of the second initialization module is electrically connected to the reference voltage signal line, and the second end of the second initialization module is electrically connected to the first end or the second end of the driving transistor; the second initialization module initializes the potentials of the first end and the second end of the driving transistor with the reference voltage in response to the second scan signal; The control end of the third initialization module is electrically connected to the third scan signal line, the first end of the third initialization module is electrically connected to the first power supply voltage signal line or the second light-emitting control signal line, and the second end of the third initialization module is electrically connected to the control end of the driving transistor; The third initialization module initializes the potential of the control terminal of the driving transistor with the first power supply voltage or the voltage of the second light emitting control signal in response to the third scanning signal; The control terminal of the first light-emitting control module is electrically connected to the first light-emitting control signal line, the first terminal of the first light-emitting control module is electrically connected to the first power supply voltage signal line, and the second terminal of the first light-emitting control module is electrically connected to the first terminal of the driving transistor; the first light-emitting control module initializes the potentials of the first terminal and the second terminal of the driving transistor with the first power supply voltage in response to the first light-emitting control signal; The reference voltage is smaller than the first power supply voltage or the voltage of the second light-emitting control signal.

2. The pixel circuit according to claim 1, wherein: The reference voltage signal line includes a first reference voltage signal line and a second reference voltage signal line; The first initialization module includes a first sub-initialization module and a second sub-initialization module, a first end of the first sub-initialization module is electrically connected to the second reference voltage signal line, and a second end of the first sub-initialization module is electrically connected to the first end of the light-emitting element; A first end of the second sub-initialization module is electrically connected to the first reference voltage signal line, and a second end of the second sub-initialization module is electrically connected to the control end of the driving transistor.

3. The pixel circuit according to claim 2, wherein: It also includes a fourth initialization module and a fifth initialization module, wherein: The control end of the fourth initialization module is electrically connected to the second scan signal line, the first end of the fourth initialization module is electrically connected to the first reference voltage signal line, and the second end of the fourth initialization module is electrically connected to the second end of the driving transistor; The control end of the fifth initialization module is electrically connected to the third scan signal line, the first end of the fifth initialization module is electrically connected to the second light emitting control signal line, and the second end of the fifth initialization module is electrically connected to the second end of the driving transistor.

4. The pixel circuit according to any one of claims 1 to 3, wherein: It also includes a potential stabilization module, and two ends of the potential stabilization module are electrically connected to the first end and the second end of the driving transistor respectively.

5. The pixel circuit according to claim 4, wherein: It also includes a storage capacitor, a compensation module, a data writing module and a second light emitting control module, wherein: The first end of the storage capacitor is electrically connected to the first power supply voltage line, and the second end of the storage capacitor is electrically connected to the second end of the compensation module and the control end of the driving transistor; the control end of the compensation module is electrically connected to the fourth scan signal line, and the first end of the compensation module is electrically connected to the second end of the driving transistor; The control end of the data writing module is electrically connected to the fifth scan signal line, the first end of the data writing module is electrically connected to the data line, and the second end of the data writing module is electrically connected to the first end of the driving transistor; The control end of the second light-emitting control module is electrically connected to the second light-emitting control signal line, the first end of the second light-emitting control module is electrically connected to the second end of the driving transistor, the second end of the second light-emitting control module is electrically connected to the first end of the light-emitting element; and the second end of the light-emitting element is electrically connected to the second power supply voltage signal line.

6. The pixel circuit according to claim 5, wherein: The first initialization module includes a first transistor and a second transistor, wherein the control end of the first transistor is electrically connected to the first scan signal line, the first end of the first transistor is electrically connected to the reference voltage signal line, and the second end of the first transistor is connected to the first end of the light-emitting element; The driving transistor is a ninth transistor, the control terminal of the second transistor is electrically connected to the first scan signal line, the first terminal of the second transistor is electrically connected to the reference voltage signal line, and the second terminal of the second transistor is electrically connected to the control terminal of the ninth transistor; The second initialization module includes a third transistor, a control end of the third transistor is electrically connected to the second scan signal line, a first end of the third transistor is electrically connected to the reference voltage signal line, and a second end of the third transistor is electrically connected to the first end of the ninth transistor; The potential stabilization module includes a first capacitor, wherein two ends of the first capacitor are electrically connected to a first end and a second end of the ninth transistor respectively; The third initialization module includes a fourth transistor, a control terminal of the fourth transistor is electrically connected to the third scan signal line, a first terminal of the fourth transistor is electrically connected to the first power supply voltage signal line, and a second terminal of the fourth transistor is electrically connected to the control terminal of the ninth transistor; The data writing module includes a fifth transistor, a control end of the fifth transistor is electrically connected to the fifth scan signal line, a first end of the fifth transistor is electrically connected to the data line, and a second end of the fifth transistor is electrically connected to the first end of the ninth transistor; The compensation module includes a sixth transistor, the storage capacitor is a second capacitor, the control end of the sixth transistor is electrically connected to the fourth scan signal line, the first end of the sixth transistor is electrically connected to the second end of the second capacitor, and the second end of the sixth transistor is electrically connected to the second end of the ninth transistor; the first end of the second capacitor is electrically connected to the first power supply voltage signal line; The first light emitting control module includes a seventh transistor, a control end of the seventh transistor is electrically connected to the first light emitting control signal line, a first end of the seventh transistor is electrically connected to the first power supply voltage signal line, and a second end of the seventh transistor is electrically connected to the first end of the ninth transistor; The second light-emitting control module includes an eighth transistor, the control end of the eighth transistor is electrically connected to the second light-emitting control signal line, the first end of the eighth transistor is electrically connected to the second end of the ninth transistor, and the second end of the eighth transistor is electrically connected to the first end of the light-emitting element.

7. The pixel circuit according to claim 6, wherein: The device further comprises a fourth initialization module and a fifth initialization module, wherein the reference voltage signal line comprises a first reference voltage signal line and a second reference voltage signal line, the fourth initialization module comprises a tenth transistor, and the fifth initialization module comprises an eleventh transistor; The first terminal of the first transistor is electrically connected to the second reference voltage signal line; A first terminal of the second transistor is electrically connected to the first reference voltage signal line; The first terminal of the third transistor is electrically connected to the first reference voltage signal line; The control terminal of the tenth transistor is electrically connected to the second scan signal line, the first terminal of the tenth transistor is electrically connected to the first reference voltage signal line, and the second terminal of the tenth transistor is electrically connected to the second terminal of the ninth transistor; The control end of the eleventh transistor is electrically connected to the third scan signal line, the first end of the eleventh transistor is electrically connected to the second light emitting control signal line, and the second end of the eleventh transistor is electrically connected to the second end of the ninth transistor.

8. A method for driving a pixel circuit, characterized in that: Used to drive the pixel circuit according to claim 1, comprising an initialization phase when a writing frame is displayed, wherein the initialization phase comprises a first initialization phase and a second initialization phase that are repeated alternately, and the last initialization phase is a third initialization phase; In the first initialization stage, the first scanning signal is at an operating level, and the first initialization module resets the first end of the light-emitting element and the control end of the driving transistor with the reference voltage; the second scanning signal is at an operating level, and the second initialization module resets the first end and the second end of the driving transistor with the reference voltage; In the second initialization stage: the third scanning signal is at an operating level, and the third initialization module resets the control terminal of the driving transistor with the first power supply voltage or the voltage of the second light-emitting control signal; the first light-emitting control signal is at an operating level, and the first light-emitting control module resets the control terminal of the driving transistor with the first power supply voltage; In the third initialization stage: the first scanning signal is at a working level, and the first initialization module resets the first end of the light-emitting element and the control end of the driving transistor with the reference voltage.

9. A method for driving a pixel circuit, characterized in that: The method for driving the pixel circuit according to claim 3 includes an initialization phase during a write frame display, wherein the initialization phase includes a first initialization phase and a second initialization phase that are repeated alternately, and a third initialization phase that is the last phase, and includes the following steps: In the first initialization stage, the first scanning signal is at an operating level, the first sub-initialization module resets the first terminal of the light-emitting element with a second reference voltage, and the second sub-initialization module resets the control terminal of the driving transistor with the first reference voltage; the second scanning signal is at an operating level, the second initialization module and the fourth initialization module reset the first terminal and the second terminal of the driving transistor respectively with the first reference voltage; In the second initialization stage: the third scanning signal is at a working level, and the third initialization module resets the control terminal of the driving transistor with the first power supply voltage or the voltage of the second light-emitting control signal; The fifth initialization module resets the second end of the driving transistor with the voltage of the second light emitting control signal; the first light emitting control signal is at a working level, and the first light emitting control module resets the first end of the driving transistor with the first power supply voltage; In the third initialization stage: the first scanning signal is at a working level, the first sub-initialization module resets the first end of the light-emitting element with the second reference voltage, and the second sub-initialization module resets the control end of the driving transistor with the first reference voltage.

10. The driving method of the pixel circuit according to claim 8 or 9, characterized in that: The pixel circuit further includes a storage capacitor, a data writing module, a compensation module, a potential stabilization module, and a second light emitting control module. The writing frame display further includes a data writing stage, a compensation stage, and a light emitting stage, including the following steps: In the data writing phase and the compensation phase: the fourth scanning signal and the fifth scanning signal are at a working level, and the data writing module and the compensation module store the data voltage and the threshold voltage of the driving transistor in the storage capacitor; In the light-emitting stage: the first light-emitting control signal and the second light-emitting control signal are at a working level, driving the light-emitting element to emit light; The potential stabilization module stabilizes a potential difference between a first terminal and a second terminal of the driving transistor.

11. The driving method of the pixel circuit according to claim 10, wherein: A holding frame is further included between the two writing frames, and the writing frame display includes a bias phase and the light emitting phase, wherein the bias phase includes a first sub-bias phase and a second sub-bias phase that are alternately repeated, and includes the following steps: In the first sub-bias phase: the fifth scanning signal is at a working level, and the potentials of the first terminal and the second terminal of the driving transistor are reset by the data voltage; In the second sub-bias phase, the first light-emitting control signal is at a working level, and the potentials of the first terminal and the second terminal of the driving transistor are reset by the first power supply voltage; In the light-emitting stage, the first light-emitting control signal and the second light-emitting control signal are at a working level, driving the light-emitting element to emit light; The potential stabilization module stabilizes a potential difference between a first terminal and a second terminal of the driving transistor.

12. A display panel, characterized in that: include: a substrate comprising a display area and a non-display area surrounding the display area; The display area includes a pixel circuit array according to any one of claims 1 to 5; The non-display area includes a gate driving circuit, a light emitting control driving circuit, a data driving circuit, and a reference voltage signal line, which are electrically connected to the pixel circuit array respectively to control the pixel units in the display area to display row by row.

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