A counting circuit, a delay monitoring circuit and a semiconductor memory

Abstract

The embodiment of the present disclosure provides a counting circuit, a delay monitoring circuit and a semiconductor memory. The counting circuit comprises a plurality of counting modules. The counting circuit is configured to receive a clock signal, count the clock signal through the plurality of counting modules, and obtain a counting signal. One counting module is configured to output a group of counting sub-signals. The encoding mode of the group of counting sub-signals is Gray coding. A plurality of groups of counting sub-signals are sequentially combined to form the counting signal. The encoding mode of the counting signal is Gray coding. In this way, since the group Gray coding is adopted, the counting signal involves the change of only one counting sub-signal each time, that is, the Bit Toggle involved in the counting value jump is less, the switching noise is reduced, and the counting accuracy is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and more particularly to a counting circuit, a delay monitoring circuit, and a semiconductor memory. Background Technology

[0002] In electronic devices, it is common to use counting circuits to count the oscillations of a loop oscillator in order to monitor its pulse period. Currently, the counting signal output by the counting circuit uses binary encoding, which may introduce noise into the loop oscillator and adversely affect the electronic device. Summary of the Invention

[0003] This disclosure provides a counting circuit, a delay monitoring circuit, and a semiconductor memory that can reduce switching noise and improve counting accuracy.

[0004] In a first aspect, embodiments of this disclosure provide a counting circuit, which includes a plurality of counting modules; wherein the counting circuit is configured to receive a clock signal and count the clock signal through the plurality of counting modules to obtain a counting signal; wherein one counting module is configured to output a set of counting sub-signals, and the encoding method of the set of counting sub-signals is Gray code, and the plurality of sets of counting sub-signals are sequentially combined to form a counting signal, and the encoding method of the counting signal is Gray code.

[0005] In some embodiments, the plurality of counting modules include a first counting module, a second counting module, a third counting module, and a fourth counting module; wherein, the first counting module is configured to receive a clock signal and output a first set of counting sub-signals and a first carry clock signal; the second counting module is configured to receive the first carry clock signal and output a second set of counting sub-signals and a second carry clock signal; the third counting module is configured to receive the second carry clock signal and output a third set of counting sub-signals and a third carry clock signal; and the fourth counting module is configured to receive the third carry clock signal and output a fourth set of counting sub-signals.

[0006] In some embodiments, each counting module includes a clock processing module and a counting processing module; wherein, the clock processing module is configured to receive a counting clock signal, count the counting clock signal, and output an internal clock signal and a corresponding carry clock signal; wherein, the counting clock signal refers to one of a clock signal, a first carry clock signal, a second carry clock signal, and a third carry clock signal; the counting processing module is configured to receive an internal clock signal, count the internal clock signal, and output a corresponding set of counting sub-signals.

[0007] In some embodiments, the counting module is further configured to, when the counting clock signal generates a pulse, control the carry clock signal to remain unchanged and control the internal clock signal to generate a pulse after completing one pulse cycle, so as to change the count value of a set of counting sub-signals; or, control the carry clock signal to generate a pulse after completing one pulse cycle and control the internal clock signal to remain unchanged, so as to maintain the count value of a set of counting sub-signals unchanged.

[0008] In some embodiments, the counting processing module includes a count value output module and an encoding module; wherein, the count value output module is configured to receive an internal clock signal and a set of encoded signals, sample the set of encoded signals according to the internal clock signal, and output a set of count sub-signals; the encoding module is configured to receive a set of count sub-signals, calculate and output a set of encoded signals.

[0009] In some embodiments, a set of counting sub-signals includes A-bit counting sub-signals, and a set of encoding signals includes A-bit encoding signals; the counting value output module includes A first flip-flops; wherein, the i-th first flip-flop is configured to receive an internal clock signal and the i-th bit encoding signal, and sample the i-th bit encoding signal according to the internal clock signal to output the i-th bit counting sub-signal; i and A are both positive integers, and i is less than or equal to A.

[0010] In some embodiments, the encoding module includes A encoding sub-modules, the i-th encoding sub-module being used to output the i-th bit encoded signal; the i-th encoding sub-module includes C first AND gates and one first OR gate; wherein, the first AND gate is configured to receive a portion of the counting sub-signals in a set of counting sub-signals and output a decoded signal; the first OR gate is configured to receive the decoded signals output by each of the C first AND gates and output the i-th bit encoded signal; wherein, C is a positive integer.

[0011] In some embodiments, the clock processing module includes a comparison module and a clock generation module, and the comparison module includes a judgment module and a reference module; wherein, the judgment module is configured to receive a set of encoded signals and a set of reference signals, compare the set of encoded signals and the set of reference signals, and output a switch signal; the reference module is configured to receive a counting clock signal, a switch signal and a set of counting sub-signals, and output a set of reference signals; the clock generation module is configured to receive the switch signal and the counting clock signal, and output an internal clock signal and a carry clock signal.

[0012] In some embodiments, the determining module is further configured to output a switch signal in an active state when a set of reference signals and a set of encoded signals correspond to the same state; or, when a set of reference signals and a set of encoded signals do not correspond to the same state, output a switch signal in an inactive state; the reference module is further configured to update the level state of a set of reference signals using a set of counter sub-signals when the switch signal is in an active state; and to keep a set of reference signals unchanged when the switch signal is in an inactive state.

[0013] The clock generation module is further configured to, when the counting clock signal generates a pulse after completing one pulse cycle and the switch signal is in an invalid state, control the carry clock signal to remain unchanged and control the internal clock signal to generate a pulse after completing one pulse cycle, so as to change the count value of a set of counting sub-signals; or, when the counting clock signal generates a pulse after completing one pulse cycle and the switch signal is in an active state, control the carry clock signal to generate a pulse after completing one pulse cycle and control the internal clock signal to remain unchanged, so as to maintain the count value of a set of counting sub-signals unchanged.

[0014] In some embodiments, the judgment module includes A arithmetic processing modules and a second AND gate; wherein, the i-th arithmetic processing module is configured to receive the i-th bit encoded signal and the i-th bit reference signal, and output the i-th arithmetic value; wherein, the i-th arithmetic value is used to indicate whether the i-th bit encoded signal and the i-th bit reference signal are the same; the second AND gate is used to receive the A arithmetic values ​​output by the A arithmetic processing modules and output a switch signal.

[0015] In some embodiments, a set of reference signals includes A reference signals, and the reference module includes A reference sub-modules. The i-th reference sub-module is used to output the i-th reference signal. The i-th reference sub-module includes a first transmission gate, a second transmission gate, and a second flip-flop. The first transmission gate is configured to receive a switch signal and the i-th counting sub-signal, and output the i-th counting sub-signal as an intermediate transmission signal when the switch signal is active. The second transmission gate is configured to receive the inverted signal of the switch signal and the i-th reference signal, and output the i-th reference signal as an intermediate transmission signal when the switch signal is inactive. The second flip-flop is configured to receive a counting clock signal and the intermediate transmission signal, sample the intermediate transmission signal according to the counting clock signal, and output the i-th reference signal.

[0016] In some embodiments, the clock generation module includes a transmission submodule, a sampling submodule, a first arithmetic submodule, and a second arithmetic submodule; wherein, the transmission submodule is configured to select a first logic signal and a second logic signal according to a switch signal to output a first processing signal; the sampling submodule is connected to the transmission submodule and configured to sample the first processing signal and output a target sampling signal; the first arithmetic submodule receives the target sampling signal and a counting clock signal and outputs an internal clock signal; the second arithmetic submodule is configured to receive the target sampling signal and the counting clock signal and output a carry clock signal.

[0017] In some embodiments, the transmission submodule includes a third transmission gate and a fourth transmission gate; the sampling submodule includes a third flip-flop and a fourth flip-flop; the first operation submodule includes a third AND gate, and the second operation submodule includes a third inverter and a fifth flip-flop; wherein, the third transmission gate is configured to receive a switch signal and a first standard logic signal, and output the first standard logic signal as a first processing signal when the switch signal is in an active state; the fourth transmission gate is configured to receive the inverted signal of the switch signal and the second standard logic signal, and output the second standard logic signal as the first processing signal when the switch signal is in an inactive state; the third flip-flop is configured to sample the first processing signal according to the counting clock signal and output an intermediate sampling signal; the fourth flip-flop is configured to sample the intermediate sampling signal according to the counting clock signal and output a target sampling signal; the third AND gate is configured to perform an AND operation on the counting clock signal and the target sampling signal and output an internal clock signal; the third inverter is configured to invert the target sampling signal to output an inverted target sampling signal; and the fifth flip-flop is configured to sample the inverted target sampling signal according to the counting clock signal and output a carry clock signal.

[0018] In some embodiments, in the A first flip-flops, second flip-flops, third flip-flops, fourth flip-flops, and fifth flip-flops, each flip-flop is further configured to receive a respective reset signal and perform reset processing according to the received reset signal.

[0019] Secondly, embodiments of this disclosure provide a delay monitoring circuit for monitoring whether a sampled signal experiences a delay due to a first parameter, the first parameter including at least one of the following: process parameters, operating voltage parameters, and operating temperature parameters; the delay monitoring circuit includes an oscillator circuit and a counting circuit as described in the first aspect; the oscillator circuit is configured to output a clock signal; wherein the oscillation period of the clock signal is the same as the delay value of the sampled signal; the counting circuit is configured to receive the clock signal; and count the clock signal during a first time period and a second time period respectively to obtain a first counting result and a second counting result; wherein the first time period and the second time period have the same duration; wherein if the first counting result and the second counting result are the same, it is determined that the sampled signal does not experience a delay due to process parameters; if the first counting result and the second counting result are different, it is determined that the sampled signal experiences a delay due to process parameters.

[0020] Thirdly, embodiments of this disclosure provide a semiconductor memory including the delay monitoring circuit described in the first aspect.

[0021] This disclosure provides a counting circuit, a delay monitoring circuit, and a semiconductor memory. The counting circuit uses group Gray encoding, which involves only a change in one counting sub-signal each time the counting signal changes. That is, there are fewer bit toggles involved when the count value jumps, which reduces switching noise and improves counting accuracy. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a counting circuit provided in an embodiment of the present disclosure;

[0023] Figure 2 This is a schematic diagram of another counting circuit provided in an embodiment of the present disclosure;

[0024] Figure 3 This is a schematic diagram of the structure of a counting module provided in an embodiment of the present disclosure;

[0025] Figure 4 This is a schematic diagram of the structure of a counting processing module provided in an embodiment of the present disclosure;

[0026] Figure 5 A detailed structural diagram of a counting value output module provided in an embodiment of this disclosure;

[0027] Figure 6 A detailed structural diagram of an encoding module provided in an embodiment of this disclosure;

[0028] Figure 7 This is a schematic diagram of the structure of a clock processing module provided in an embodiment of the present disclosure;

[0029] Figure 8 A detailed structural diagram of a judgment module provided in an embodiment of this disclosure;

[0030] Figure 9 A detailed structural diagram of a reference module provided for an embodiment of this disclosure;

[0031] Figure 10 A detailed structural diagram of a clock generation module provided in an embodiment of this disclosure;

[0032] Figure 11 A signal timing diagram provided in an embodiment of this disclosure;

[0033] Figure 12 This is a schematic diagram of the structure of a delay monitoring circuit provided in an embodiment of the present disclosure;

[0034] Figure 13 This is a schematic diagram of the structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0035] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely configured to explain the relevant application and not to limit the application. It should also be noted that, for ease of description, only the parts related to the relevant application are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are merely configured to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0036] The following are explanations of the technical terms used in the embodiments of this disclosure, as well as the correspondences of some terms:

[0037] Dynamic Random Access Memory (DRAM)

[0038] Synchronous Dynamic Random Access Memory (SDRAM)

[0039] Double Data Rate (DDR) SDRAM

[0040] Memory compliant with the fifth generation DDR SDRAM standard (5th DDR, DDR5)

[0041] Process, Voltage, Temperature (PVT)

[0042] The memory contains a counting circuit for counting the number of oscillations of the loop oscillator. This counting circuit generally uses binary encoding, as shown in Table 1.

[0043] Table 1

[0044]

[0045]

[0046] As shown in Table 1, the binary-encoded count value consists of multiple bits. Incrementing the count value may involve simultaneous changes in multiple bits. In other words, after the loop oscillator generates a pulse, the level states of multiple sub-signals in the counting signal may change simultaneously, meaning that the count value transition involves numerous bit toggle operations, potentially introducing noise into the loop oscillator. Furthermore, because the loop oscillator has a short pulse period and is highly sensitive to noise, it is crucial to minimize the introduction of noise into the loop oscillator.

[0047] Based on this, the present disclosure provides a counting circuit that uses group Gray coding, which involves only the change of one counting sub-signal each time the counting signal changes, thus achieving less bit toggle when the count value jumps, reducing switching noise and improving counting accuracy.

[0048] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0049] In one embodiment of this disclosure, see Figure 1 This illustrates a schematic diagram of the composition of a counting circuit 10 provided in an embodiment of this disclosure. For example... Figure 1 As shown, the counting circuit 10 includes several counting modules (e.g., Figure 1Counting modules 11, 12, 13, and 14 (in the module); where,

[0050] The counting circuit 10 is configured to receive a clock signal and count the clock signal through several counting modules to obtain a counting signal. Among them, one counting module is configured to output a set of counting sub-signals, and the encoding method of the set of counting sub-signals is Gray code. Several sets of counting sub-signals are sequentially combined to form a counting signal, and the encoding method of the counting signal is Gray code.

[0051] It should be noted that the counting circuit 10 in this embodiment is used to count the number of pulses of the clock signal, thereby obtaining an accurate value of the clock tree delay offset in the memory. Furthermore, the counting circuit 10 can also be applied to other circuit scenarios involving counting, and this embodiment does not limit its application.

[0052] It should be noted that the counting signal output by the counting circuit 10 adopts a grouped Gray code method. Specifically, the counting signal includes multiple groups of counting sub-signals, which together constitute a Gray code unit, and one group of counting sub-signals is equivalent to one element of the Gray code unit; at the same time, one group of counting sub-signals includes multiple bit counting sub-signals, which also constitute a Gray code unit, and in this case, one bit of counting sub-signal is equivalent to one element of the Gray code unit.

[0053] It should be understood that the number of counting modules and the number of counting sub-signals contained in a set of counting sub-signals need to be determined according to the actual application scenario, and this disclosure does not impose any limitations. In addition, the number of each set of counting sub-signals can be the same or different.

[0054] Taking a 16-bit counting signal as an example, such as Figure 1 As shown, the number of counting modules can be four, in which case each group of counting sub-signals includes four-bit sub-signals. Taking a 12-bit counting signal as an example, the number of counting modules can be three, and each group of counting sub-signals includes four-bit sub-signals, but this does not constitute a limitation.

[0055] For ease of explanation, the counting circuit 10 will be explained using a 16-bit counting signal in the following explanations.

[0056] It should be noted that, according to the Gray coding rules, any two adjacent count values ​​differ by only one bit. See Table 2 for an example of the intra-group coding rules for a set of counting sub-signals. See Table 3 for an example of the overall coding rules for a counting signal comprising four sets of counting sub-signals.

[0057] Table 2

[0058]

[0059]

[0060] Table 3

[0061]

[0062] In Tables 2 and 3, adjacent rows represent the corresponding decimal values ​​being incremented by one in sequence. Thus, combining Tables 2 and 3, it can be seen that when the count value increases by one, only one bit of the counting sub-signal changes. The bit toggle involved in the count value transition is reduced, thus lowering switching noise and improving counting accuracy.

[0063] In a specific example, such as Figure 2 As shown, the counting modules may include a first counting module 101, a second counting module 102, a third counting module 103 and a fourth counting module 104, and each group of counting sub-signals includes 4-bit counting sub-signals.

[0064] The first counting module 101 is configured to receive the clock signal clk and output the first set of counting sub-signals cnt[3:0]_1 and the first carry clock signal clk_nxt_1; the second counting module 102 is configured to receive the first carry clock signal clk_nxt_1 and output the second set of counting sub-signals cnt[3:0]_2 and the second carry clock signal clk_nxt_2; the third counting module 103 is configured to receive the second carry clock signal clk_nxt_1 and output the third set of counting sub-signals cnt[3:0]_3 and the third carry clock signal clk_nxt_3; the fourth counting module 104 is configured to receive the third carry clock signal clk_nxt_3 and output the fourth set of counting sub-signals cnt[3:0]_4.

[0065] It should be noted that the first counting module 101, the second counting module 102, the third counting module 103 and the fourth counting module 104 have similar structures, and they can all count based on the number of pulses of the received signal.

[0066] Specifically, the first counting module 101 counts the pulses of the clock signal clk and outputs the first set of counting sub-signals cnt[3:0]_1 and the first carry clock signal clk_nxt_1; the second counting module 102 counts the pulses of the first carry clock signal clk_nxt_1 and outputs the second set of counting sub-signals cnt[3:0]_2 and the second carry clock signal clk_nxt_2; the third counting module 103 counts the pulses of the second carry clock signal clk_nxt_2 and outputs the third set of counting sub-signals cnt[3:0]_3 and the third carry clock signal clk_nxt_3; the fourth counting module 104 counts the pulses of the third carry clock signal clk_nxt_3 and outputs the fourth set of counting sub-signals cnt[3:0]_4.

[0067] Thus, the first set of counting sub-signals cnt[3:0]_1, the second set of counting sub-signals cnt[3:0]_2, the third set of counting sub-signals cnt[3:0]_3, and the fourth set of counting sub-signals cnt[3:0]_4 together constitute the counting signal, which can be represented as cnt[15:0]. That is to say, the first set of counting sub-signals cnt[3:0]_1 can be regarded as the 3rd to 0th bits of the counting signal, i.e., cnt[3:0]; the second set of counting sub-signals cnt[3:0]_2 can be regarded as the 7th to 4th bits of the counting signal, i.e., cnt[7:4]; the third set of counting sub-signals cnt[3:0]_3 can be regarded as the 11th to 8th bits of the counting signal, i.e., cnt[11:8]; and the third set of counting sub-signals cnt[3:0]_4 can be regarded as the 15th to 12th bits of the counting signal, i.e., cnt[15:12].

[0068] It should also be noted that, according to the rules of Gray coding, adjacent count values ​​differ by only one digit. Therefore, for the first counting module 101, when the clock signal clk generates a pulse, it may control a change in one bit of the first set of counting sub-signals cnt[3:0]_1, while keeping the first carry clock signal clk_nxt_1 unchanged, thereby changing the count value. In addition, if a carry occurs relative to the first counting module 101, then the first set of counting sub-signals cnt[3:0]_1 remains unchanged, while the first carry clock signal clk_nxt_1 changes, so that the count value can be changed by subsequent counting modules. The changes in other counting modules are similar.

[0069] It should be understood that the fourth counting module 104 is structurally similar to the first counting module 101, the second counting module 102, and the third counting module 103. That is to say, the fourth counting module 104 can also output a fourth carry signal clk_nxt_4, but as the last counting module, the corresponding carry clock signal does not have any practical function, so it can be left unextracted.

[0070] In addition, such as Figure 2 As shown, each counting module (e.g., the first counting module 101, the second counting module 102, the third counting module 103, and the fourth counting module 104) is also configured to receive a reset signal rst and perform a reset operation based on the reset signal rst. Furthermore, the reset signal rst received by each counting module can be a different signal.

[0071] In this way, by using grouped Gray coding, a wide-bit counting signal can be implemented using multiple structurally similar modules, reducing the complexity of the circuit.

[0072] The internal structure of each counting module is described in detail below.

[0073] like Figure 3 As shown, in some embodiments, each counting module includes a clock processing module 21 and a counting processing module 22; wherein,

[0074] The clock processing module 21 is configured to receive a counting clock signal, count the counting clock signal, and output an internal clock signal and a corresponding carry clock signal; wherein, the counting clock signal refers to one of the clock signal, the first carry clock signal, the second carry clock signal, and the third carry clock signal;

[0075] The counting processing module 22 is configured to receive the internal clock signal, count the internal clock signal, and output a set of corresponding counting sub-signals.

[0076] It should be noted that, in combination Figure 2 and Figure 3As shown, for the first counting module 101, the counting clock signal is the clock signal clk, the corresponding carry clock signal is the first carry clock signal clk_nxt_1, and the corresponding set of counting sub-signals is the first set of counting sub-signals cnt[3:0]_1; for the second counting module 102, the counting clock signal is the first carry clock signal clk_nxt_1, the corresponding carry clock signal is the second carry clock signal clk_nxt_2, and the corresponding set of counting sub-signals is the second set of counting sub-signals cnt[3:0]_2; for the third counting module 103 .... The counting clock signal is the second carry clock signal clk_nxt_2, the corresponding carry clock signal is the third carry clock signal clk_nxt_3, and the corresponding set of counting sub-signals is the third set of counting sub-signals cnt[3:0]_3; for the fourth counting module 13, the counting clock signal is the third carry clock signal clk_nxt_3, the corresponding carry clock signal is the fourth carry clock signal clk_nxt_4 (which may not be brought out when the counting signal is 16 bits), and the corresponding set of counting sub-signals is the fourth set of counting sub-signals cnt[3:0]_4.

[0077] In one configuration, the counting module is further configured to, upon the generation of a pulse by the counting clock signal, maintain a constant carry clock signal and generate a pulse by the internal clock signal to change the count value of a set of counting sub-signals. In this case, the change in the set of counting sub-signals output by the counting module will cause a change in the overall count value of the counting signal cnt[15:0].

[0078] In another scenario, when the counting clock signal generates a pulse, the carry clock signal is controlled to generate a pulse, while the internal clock signal remains unchanged to maintain the count value of a set of counting sub-signals. At this time, because the carry clock signal changes, a set of counting sub-signals in a subsequent counting module will change, thus causing a change in the overall count value of the counting signal cnt[15:0].

[0079] like Figure 4 As shown, in some embodiments, the counting processing module 22 includes a count value output module 221 and an encoding module 222; wherein, the count value output module 221 is configured to receive the internal clock signal and a set of encoded signals, sample the set of encoded signals according to the internal clock signal, and output the set of count sub-signals; the encoding module 222 is configured to receive a set of count sub-signals, calculate and output a set of encoded signals.

[0080] It should be noted that a set of coded signals essentially represents the theoretical value of a set of counter sub-signals after the next count value transition. In other words, without involving carry, if the internal clock signal generates a new pulse, the count value output module 221 will output a set of coded signals as a set of counter sub-signals.

[0081] In some embodiments, a set of counting sub-signals includes A-bit counting sub-signals, and a set of encoding signals includes A-bit encoding signals; the counting value output module includes A first flip-flops; wherein, the i-th first flip-flop is configured to receive an internal clock signal and the i-th bit encoding signal, and sample the i-th bit encoding signal according to the internal clock signal to output the i-th bit counting sub-signal; i and A are both positive integers, and i is less than or equal to A.

[0082] In some embodiments, the encoding module 222 includes A encoding sub-modules, the i-th encoding sub-module being used to output the i-th bit encoded signal; the i-th encoding sub-module includes C first AND gates and one first OR gate; wherein, the first AND gate is configured to receive a portion of the counting sub-signals in the set of counting sub-signals and output a decoded signal; the first OR gate is configured to receive the decoded signals output by each of the C first AND gates and output the i-th bit encoded signal; wherein, C is a positive integer.

[0083] Thus, after the internal clock signal generates a pulse, the counting value output module 221 samples and outputs a set of coded signals to obtain a set of counting sub-signals; at the same time, the encoding module 222 updates a set of coded signals according to the latest set of counting sub-signals to prepare for the next counting.

[0084] Specifically, in some embodiments, the counting value output module can simultaneously output a set of counting sub-signals and their inverted signals, so that the encoding module can calculate and output a set of encoded signals based on the set of counting sub-signals and their inverted signals. Therefore, the counting value output module may also include A first inverters, with the input terminal of the i-th first inverter connected to the output terminal of the i-th first flip-flop, and the output terminal of the i-th first inverter used to output the inverted signal of the i-th counting sub-signal; alternatively, the counting value output module may also exclude the first inverters and directly output the inverted signal of the i-th counting sub-signal through the inverted output terminal of the i-th first flip-flop.

[0085] For example, taking A=4 as an example, see Figure 5 This illustrates a schematic diagram of the specific structure of a counting value output module 221 provided in an embodiment of this disclosure. Figure 5In this code, a set of counting sub-signals are represented as cnt[3], cnt[2], cnt[1], and cnt[0], a set of encoded signals are represented as c3, c2, c1, and c0, a set of inverted counting sub-signals are represented as ~cnt[3], ~cnt[2], ~cnt[1], and ~cnt[0], and the internal clock signal is represented as gclk. Figure 5 As shown, the counting value output module 221 includes a first flip-flop 301, a first flip-flop 302, a first flip-flop 303, a first flip-flop 304, a first inverter 305, a first inverter 306, a first inverter 307, and a first inverter 308. The input terminal (D) of the first flip-flop 301 is used to receive the encoded signal c0, the clock terminal of the first flip-flop 301 is used to receive the internal clock signal gclk, and the output terminal (Q) of the first flip-flop 301 is used to output the counting sub-signal cnt[0]. The input terminal of the first inverter 305 is connected to the output terminal of the first flip-flop 301 and is used to receive the counting sub-signal cnt[0]. The output terminal of the first inverter 305 is used to output the inverted signal ~cnt[0] of the counting sub-signal. The other first flip-flops and first inverters can be understood by analogy. In addition, each of the first flip-flops 301, 302, 303, and 304 also has a reset terminal for receiving a reset signal rst, so that a reset process can be performed according to the reset signal rst.

[0086] Accordingly, see Figure 6 This illustrates a schematic diagram of the specific structure of an encoding module 222 provided in an embodiment of this disclosure. For example... Figure 6 As shown, encoding module 222 includes four different encoding sub-modules. The first encoding sub-module outputs encoded signal c3, the second encoding sub-module outputs encoded signal c2, the third encoding sub-module outputs encoded signal c1, and the fourth encoding sub-module outputs encoded signal c0. Taking C=4 as an example, each encoding sub-module consists of four first AND gates and one first OR gate. The input of the first AND gate receives a set of counting sub-signals and a portion of their inverted signals. The outputs of all first AND gates are connected to the inputs of the first OR gate, and the output of the first OR gate outputs the corresponding encoded signal. It should be understood that the specific structure of the encoding sub-modules and the specific signals received by each encoding sub-module need to be determined according to specific decoding rules. Figure 6 This is for illustrative purposes only and does not constitute a limitation.

[0087] Thus, as Figure 5 and Figure 6As shown, the counting output module 221 can determine a set of counting sub-signals cnt[3:0] and a set of inverted counting sub-signals ~cnt[3:0] when the internal clock signal gclk generates a pulse; the encoding module 222 can update a set of encoded signals in order to perform the next counting.

[0088] In some embodiments, such as Figure 7 As shown, the clock processing module 21 includes a comparison module 211 and a clock generation module 212. The comparison module 211 includes a judgment module 2111 and a reference module 2112. The judgment module 2111 is configured to receive a set of encoded signals and a set of reference signals, compare the set of encoded signals and the set of reference signals, and output a switch signal. The reference module 2112 is configured to receive a counting clock signal, a switch signal, and a set of counting sub-signals, and output a set of reference signals. The clock generation module 212 is configured to receive a switch signal and a counting clock signal, and output an internal clock signal and a carry clock signal.

[0089] It should be noted that, according to the foregoing, the counting process of each counting module can be divided into two cases: (1) When the counting clock signal generates a pulse, the carry clock signal of the counting module does not have a pulse (no carry occurs), and the set of counting sub-signals it outputs changes. For example, referring to Table 3 above, when the count value (G0 G0 G0 G14) is incremented by one, the next count value is (G0 G0 G0 G15). At this time, the set of counting sub-signals output by the fourth counting module changes from G14 to G15, and the output carry clock signal does not generate a pulse; (2) When the counting clock signal generates a pulse, and the carry clock signal generated by the counting module has a pulse (carry occurs), the set of counting sub-signals it outputs remains unchanged. Referring to Table 3 above, when the count value (G0 G0 G0 G15) is incremented, the next count value is (G0 G0 G1 G15). At this time, the set of counting sub-signals output by the fourth counting module remains unchanged at G15, and the output carry clock signal generates a pulse, causing the set of counting sub-signals output by the third counting module to change from G0 to G1. It is worth noting that the set of counting sub-signals that remain unchanged is different depending on the timing of the carry. For example, when the count value (G0 G0 G1 G14) is incremented, the next count value is (G0 G0 G2 G14), and the set of counting sub-signals output by the fourth counting module remains unchanged at G14.

[0090] The clock processing module 21 is configured to implement the aforementioned mechanism. Specifically, the reference module 2112 determines the values ​​of a set of counting sub-signals corresponding to the next carry opportunity, i.e., a set of reference signals. The judgment module 2111 compares the real-time generated set of counting sub-signals with the set of reference signals in real time. If the comparison results are the same, it indicates that a carry is needed. The clock generation module 212 then outputs an internal clock signal without pulses and a carry clock signal with pulses. The internal clock signal without pulses ensures that the set of counting sub-signals remains unchanged during the current counting process, while the carry clock signal with pulses controls subsequent counting modules. Conversely, if the comparison results are different, it indicates that a carry is not needed. The clock module 212 then outputs an internal clock signal with pulses and a carry clock signal without pulses. The internal clock signal with pulses ensures that the set of counting sub-signals changes during the current counting process to achieve counting, while the carry clock signal without pulses does not cause the next counting module to start counting.

[0091] Therefore, in some embodiments, the determination module 2111 is further configured to output a switch signal in an effective state when a set of reference signals and a set of encoded signals correspond to the same value; or, when a set of reference signals and a set of encoded signals do not correspond to the same value, output a switch signal in an invalid state.

[0092] Reference module 2112 is further configured to update the level state of a set of reference signals using a set of counter sub-signals when the switch signal is in an active state; and to keep a set of reference signals unchanged when the switch signal is in an inactive state.

[0093] The clock generation module 212 is further configured to, when the counting clock signal generates a pulse and the switch signal is in an invalid state, control the carry clock signal to remain unchanged and control the internal clock signal to generate a pulse to change the count value of a set of counting sub-signals; or, when the counting clock signal generates a pulse and the switch signal is in an active state, control the carry clock signal to generate a pulse and control the internal clock signal to remain unchanged to maintain the count value of a set of counting sub-signals unchanged.

[0094] In some embodiments, the judgment module 2111 includes A arithmetic processing modules and a second AND gate; wherein, the i-th arithmetic processing module is configured to receive the i-th bit encoded signal and the i-th bit reference signal, and output the i-th arithmetic value; wherein, the i-th arithmetic value is used to indicate whether the i-th bit encoded signal and the i-th bit reference signal are the same; the second AND gate is used to receive the A arithmetic values ​​output by the A arithmetic processing modules and output a switch signal.

[0095] It should be noted that the arithmetic processing module can be composed of a combination of XOR gates and NOT gates, or other XOR gate structures.

[0096] For example, taking A=4 as an example, a set of reference signals are represented as reference signal change_point[0], reference signal change_point[1], reference signal change_point[2], and reference signal change_point[3]. Figure 8 As shown, the judgment module 2111 includes XOR gate 309, XOR gate 310, XOR gate 311, XOR gate 312, second inverter 313, second inverter 314, second inverter 315, second inverter 316, and AND gate 317. XOR gate 309 is used to receive the encoded signal c0 and the reference signal change_point[0]. The output terminal of XOR gate 309 is connected to the input terminal of the second inverter 313, that is, XOR gate 309 and the second inverter 313 together constitute an arithmetic processing module. If the encoded signal c0 and the reference signal change_point[0] are the same, the second inverter 313 outputs a high-level signal; if the encoded signal c0 and the reference signal change_point[0] are different, the second inverter 313 outputs a low-level signal. The working principles of the other XOR gates and the second inverter can be understood by referring to this.

[0097] Finally, AND gate 317 receives the output signals of the second inverter 313, the second inverter 314, the second inverter 315, and the second inverter 316 to obtain the switch signal flag_match. Here, if a set of encoded signals and a set of reference signals are the same, the switch signal flag_match is active high, indicating that a carry is needed for the next count; conversely, if a set of encoded signals and a set of reference signals are different, the switch signal flag_match is inactive low, indicating that no carry is needed for the next count.

[0098] In some implementations, a set of reference signals includes A reference signals, and the reference module includes A reference sub-modules. The i-th reference sub-module is used to output the i-th reference signal. The i-th reference sub-module includes a first transmission gate, a second transmission gate, and a second flip-flop. The first transmission gate is configured to receive a switch signal and the i-th counting sub-signal, and output the i-th counting sub-signal as an intermediate transmission signal when the switch signal is active. The second transmission gate is configured to receive the inverted signal of the switch signal and the i-th reference signal, and output the i-th reference signal as an intermediate transmission signal when the switch signal is inactive. The second flip-flop is configured to receive a counting clock signal and the intermediate transmission signal, sample the intermediate transmission signal according to the counting clock signal, and output the i-th reference signal.

[0099] It should be noted that, see Figure 9 This illustrates a schematic diagram of a reference submodule. It should be understood that, with A=4, reference module 2112 can include four such submodules. Figure 9 The structure shown.

[0100] like Figure 9 As shown, the reference submodule may include a first transmission gate 318, a second transmission gate 319, and a second flip-flop 320. The input of the first transmission gate 318 is connected to the output of the first flip-flop to receive a one-bit counting sub-signal cnt[i]. The control terminal of the first transmission gate 318 is connected to the switch signal flag_match. The input of the second transmission gate 319 is connected to the output of the second flip-flop 320 to receive a one-bit reference signal change_point[i]. The control terminal of the second transmission gate 319 is connected to the inverted signal ~flag_match of the switch signal. The input of the second flip-flop 320 is simultaneously connected to the outputs of both the first transmission gate 318 and the second transmission gate 319. The clock terminal of the second flip-flop 320 is connected to the counting clock signal clk, thereby outputting a one-bit reference signal change_point[i]. The value of i ranges from 0, 1, 2, and 3.

[0101] In other words, when the switch signal flag_match is valid, the first transmission gate 318 outputs the counter sub-signal cnt[i]. If the counting clock signal clk generates a pulse, the second flip-flop 320 samples the counter sub-signal cnt[i] as the reference signal change_point[i], thus updating the reference signal change_point[i]. That is, a carry occurs during this counting process, and the reference signal change_point[i] needs to indicate the next carry opportunity. For example, referring to Table 3 above, after each carry, a set of reference signals will be updated to a set of counter sub-signals corresponding to (current count value - 1). That is, after a carry in G15, the next carry opportunity is G14. In addition, after a carry in G0, the next carry opportunity can be G15.

[0102] When the switch signal flag_match is invalid, the second transmission gate 319 outputs a reference signal change_point[i]. If the counting clock signal clk generates a pulse, the second flip-flop 320 samples the reference signal change_point[i] as the reference signal change_point[i], keeping the reference signal change_point[i] unchanged. That is, no carry occurred in this counting process, and the reference signal change_point[i] remains unchanged.

[0103] In some embodiments, such as Figure 10 As shown, the clock generation module 212 may include a transmission submodule, a sampling submodule, a first arithmetic submodule, and a second arithmetic submodule. The transmission submodule is configured to select between a first logic signal 1'b0 and a second logic signal 1'b1 based on the switch signal flag_match to output a first processed signal. The sampling submodule, connected to the transmission submodule, is configured to sample the first processed signal and output a target sampling signal g. The first arithmetic submodule receives the target sampling signal g and a counting clock signal clk, and outputs an internal clock signal gclk. The second arithmetic submodule is configured to receive the target sampling signal g and the counting clock signal clk, and output a carry clock signal clk_nxt.

[0104] For example, the first logic signal 1'b0 refers to a standard level signal, such as logic 0; the second logic signal 1'b1 refers to a standard level signal, such as logic 1. That is, the first logic signal and the second logic signal are different.

[0105] In some embodiments, such as Figure 10As shown, the transmission submodule may include a third transmission gate 321 and a fourth transmission gate 322; the sampling submodule may include a third flip-flop 323 and a fourth flip-flop 324; the first operation submodule may include a third AND gate 325, and the second operation submodule may include a third inverter 326 and a fifth flip-flop 327; wherein, the third transmission gate 321 is configured to receive the switch signal flag_match and the first standard logic signal 1'b0, and output the first standard logic signal 1'b0 as a first processing signal when the switch signal is in an active state; the fourth transmission gate 322 is configured to receive the inverted signal ~flag_match of the switch signal and the second standard logic signal 1'b1, and output the first standard logic signal 1'b0 as a first processing signal when the switch signal flag_match is in an active state; In the effective state, the second standard logic signal 1'b1 is output as the first processing signal; the third flip-flop 323 is configured to sample the first processing signal according to the counting clock signal clk and output an intermediate sampling signal; the fourth flip-flop 324 is configured to sample the intermediate sampling signal gg according to the counting clock signal clk and output the target sampling signal g; the third AND gate 325 is configured to perform an AND operation on the counting clock signal clk and the target sampling signal g and output an internal clock signal gclk; the third inverter 326 is configured to invert the target sampling signal to output an inverted target sampling signal; the fifth flip-flop 327 is configured to sample the inverted target sampling signal according to the counting clock signal clk and output a carry clock signal clk_nxt.

[0106] In other words, when the switch signal flag_match is valid (meeting the carry timing), a carry is required in this counting process. The transmission submodule outputs the first logic signal 1'b0, and the sampling submodule generates a target sampling signal g that remains low based on the first logic signal 1'b0 and the counting clock signal clk. Consequently, the first arithmetic submodule outputs the internal clock signal gclk that remains low (logic 0). Figure 5 The counting output module 221 does not perform sampling processing, which is equivalent to shielding this pulse, and its output set of counting sub-signals remains unchanged. In addition, the second operation sub-module generates a carry clock signal clk_nxt based on the target sampling signal g, which will jump to logic 1, thereby generating a pulse.

[0107] If the switch signal flag_match is invalid (does not meet the carry timing), no carry is needed in this counting process. The transmission submodule outputs the second logic signal 1'b1, and the sampling submodule generates a target sampling signal g that is continuously high based on the second logic signal 1'b1 and the counting clock signal clk. This causes the first arithmetic submodule to output an internal clock signal gclk containing pulses, so that... Figure 5The counting value output module 221 outputs a new set of counting sub-signals based on gclk; in addition, the second operation sub-module generates a carry clock signal clk_nxt without pulses based on the target sampling signal g.

[0108] Due to the diversity of circuit components, Figure 5 , Figure 6 , Figure 8 , Figure 9 and Figure 10 The circuit structure shown is not the only one and can be adapted to achieve similar circuit functions.

[0109] In addition, each of the A first flip-flops, second flip-flops, third flip-flops, fourth flip-flops, and fifth flip-flops is also configured to receive its own reset signal and perform reset processing according to the received reset signal.

[0110] It should be understood that, Figure 5 , Figure 6 , Figure 8 , Figure 9 and Figure 10 In this diagram, the reset signal for each flip-flop is denoted by rst. However, the reset signals for different flip-flops can be different signals or the same signal. That is, the reset signals for different flip-flops can have the same waveform or different waveforms, depending on the specific situation. Apart from the reset signal rst, other signals can be considered to have the same waveform if they use the same name.

[0111] This disclosure also describes embodiments of... Figure 5 , Figure 6 , Figure 8 , Figure 9 and Figure 10 The constructed counting circuit was simulated and verified, see [link / reference] Figure 11 It shows a signal timing diagram provided in an embodiment of the present disclosure.

[0112] exist Figure 11 Part (a) provides waveform diagrams of the clock signal clk, the first set of counter sub-signals cnt[3:0]_1, and the first carry clock signal clk_nxt_1. Specifically, when the clock signal clk generates a pulse, if the first carry clock signal clk_nxt_1 does not have a pulse, one data bit in the first set of counter sub-signals cnt[3:0]_1 changes; conversely, when the counter clock signal clk generates a pulse, if the first carry clock signal clk_nxt_1 has a pulse, the first set of counter sub-signals cnt[3:0]_1 remains unchanged. The output signals of other counting modules can be understood by referring to this diagram.

[0113] exist Figure 11 Part (b) provides waveform diagrams for the first set of counting sub-signals cnt[3:0]_1, the second set of counting sub-signals cnt[3:0]_2, the third set of counting sub-signals cnt[3:0]_3, the fourth set of counting sub-signals cnt[3:0]_4, and the counting signal cnt[15:0]. Specifically, for the counting signal cnt[15:0], only the encoding form after the highest non-zero bit is shown; that is, the complete encoding of 1-1000 is: 0000 0000 0001 1000. Specifically, when the counting signal cnt[15:0] changes, only one set of counting sub-signals cnt[3:0]_1 changes, and only one bit of this set of counting sub-signals cnt[3:0]_1 changes.

[0114] In summary, the present disclosure provides a counting circuit that employs a block Gray coding scheme, where only one data bit changes each time the count value changes. This offers at least the following advantages: Firstly, it reduces noise, as only one data bit changes state when the count value changes, minimizing simultaneous switching noise (SSN). Secondly, it reduces the error rate: assuming the error rate when the counting circuit samples one data bit is F, then the success rate of the counting circuit = (1-F). n Where n is the number of data bits that change, i.e., n=1 in this embodiment of the present disclosure, the counting circuit can achieve the best success rate; on the other hand, it reduces the impact of setup and hold timing violations; furthermore, the counting circuit using Gray encoding is more robust and has a higher yield; furthermore, the area of ​​the counting circuit in this embodiment of the present disclosure is basically the same as that of the counting circuit using ordinary binary encoding, without adding extra circuit burden; furthermore, this embodiment of the present disclosure reduces the implementation complexity of multi-bit (e.g., 16-bit) Gray encoding by implementing Gray encoding through grouping.

[0115] In another embodiment of this disclosure, the counting circuit 10 based on the foregoing embodiment is described below. Figure 12 This illustrates a detailed structural diagram of a delay monitoring circuit 40 provided in an embodiment of the present disclosure. Figure 12 As shown, the delay monitoring circuit 40 is used to monitor whether there is a delay in the sampling signal due to a first parameter, the first parameter including at least one of the following: process parameters, operating voltage parameters, and operating temperature parameters; the delay monitoring circuit 40 includes an oscillator circuit 401 and a counting circuit 10 as described in any of the preceding items;

[0116] Oscillator circuit 401 is used to output a clock signal; wherein the oscillation period of the clock signal is the same as the delay value of the sampled signal;

[0117] The counting circuit 10 is configured to receive a clock signal; and to count the clock signal in a first time period and a second time period respectively, to obtain a first counting result and a second counting result; wherein the first time period and the second time period have the same duration.

[0118] Specifically, if the first counting result and the second counting result are the same, it is determined that the sampling signal does not have a delay caused by process condition parameters; if the first counting result and the second counting result are different, it is determined that the sampling signal has a delay caused by process condition parameters.

[0119] It should be noted that, taking DDR5 as an example, the delay monitoring circuit 40 can be applied to the DQS IntervalOscillator module. This module is mainly used to monitor the DQS clock tree delay offset caused by PVT, ensuring the stability of the relative sampling positions of the data signal DQ and the data control signal DQS. In other words, the sampling signal refers to the data control signal DQS.

[0120] Therefore, the delay monitoring circuit 40 includes two main modules: an oscillator circuit 401 simulating the DQS clock tree delay and a counting circuit 10. The oscillator circuit 401 has the same period as the DQS Tree Delay, meaning the oscillation period of the clock signal is the same as the delay value of the sampled signal. The counting circuit 10 counts the number of clock signal pulses at fixed intervals (first time interval / second time interval) to determine whether the first parameter (e.g., PVT) affects the clock tree delay, and simultaneously determines the delay value of the sampled signal. Here, the first time interval and the second time interval have the same length.

[0121] For example, suppose that the count value of the counting signal is 5 in the first time period (10 nanoseconds); if the count value of the counting signal is still 5 in the second time period (10 nanoseconds), it means that PVT has no effect on the clock tree delay; conversely, if the count value of the counting signal is 4 in the second time period (10 nanoseconds), it means that PVT has an effect on the clock tree delay, and the single delay period has become 2.5 nanoseconds.

[0122] It should be understood that, since the oscillator circuit 401 is relatively sensitive to noise, when using the counting rules of conventional binary encoding (see Table 1), the count value transitions involve a large number of bit toggle operations, which may introduce noise into the oscillator, causing a deviation between the oscillation period of the clock signal and the delay value of the sampled signal. In this embodiment of the present disclosure, since the counting circuit 10 uses group Gray encoding for counting, low bit toggle operations are achieved during count value transitions, minimizing the impact on the oscillator circuit 401.

[0123] This disclosure provides a delay monitoring circuit in which the counting circuit uses grouped Gray coding, which involves only the change of one counting sub-signal each time the counting signal changes, achieving low bit toggle, avoiding the introduction of noise into the oscillator circuit 401, thereby improving the performance of the semiconductor memory.

[0124] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 13 This illustrates a schematic diagram of the structural composition of a semiconductor memory 50 provided in an embodiment of this disclosure. For example... Figure 13 As shown, the semiconductor memory 50 may include the delay monitoring circuit 40 of any of the foregoing embodiments.

[0125] Thus, in this embodiment of the disclosure, the semiconductor memory 50 includes a delay monitoring circuit 40, which involves only a change in one counting sub-signal each time the counting signal changes. That is, the bit toggle involved when the count value jumps is less, avoiding the introduction of noise into the oscillator circuit 401, thereby improving the performance of the semiconductor memory.

[0126] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A delay monitoring circuit, characterized in that, The delay monitoring circuit is used to monitor whether there is a delay in the sampling signal due to a first parameter, the first parameter including at least one of the following: process parameters, operating voltage parameters, and operating temperature parameters; The delay monitoring circuit includes an oscillator circuit and a counting circuit; The oscillator circuit is used to output a clock signal; wherein the oscillation period of the clock signal is the same as the delay value of the sampled signal; The counting circuit is configured to receive the clock signal; and to count the clock signal in a first time period and a second time period respectively, to obtain a first counting result and a second counting result; wherein the first time period and the second time period have the same duration. Wherein, if the first counting result and the second counting result are the same, it is determined that the sampling signal does not have a delay caused by process condition parameters; if the first counting result and the second counting result are different, it is determined that the sampling signal has a delay caused by process condition parameters. The counting circuit includes several counting modules, configured to count the clock signal through the several counting modules to obtain a counting signal; One of the counting modules is configured to output a set of counting sub-signals, and the encoding method of the set of counting sub-signals is Gray code. Several sets of counting sub-signals are sequentially combined to form the counting signal, and the encoding method of the counting signal is Gray code.

2. The delay monitoring circuit according to claim 1, characterized in that, The plurality of counting modules includes a first counting module, a second counting module, a third counting module, and a fourth counting module; wherein, The first counting module is configured to receive the clock signal and output a first set of counting sub-signals and a first carry clock signal; The second counting module is configured to receive the first carry clock signal and output a second set of counting sub-signals and a second carry clock signal; The third counting module is configured to receive the second carry clock signal and output a third set of counting sub-signals and a third carry clock signal; The fourth counting module is configured to receive the third carry clock signal and output the fourth set of counting sub-signals.

3. The delay monitoring circuit according to claim 2, characterized in that, Each of the aforementioned counting modules includes a clock processing module and a counting processing module; wherein, The clock processing module is configured to receive a counting clock signal, count the counting clock signal, and output an internal clock signal and a corresponding carry clock signal; wherein, the counting clock signal refers to one of the clock signal, the first carry clock signal, the second carry clock signal, and the third carry clock signal; The counting processing module is configured to receive the internal clock signal, count the internal clock signal, and output a corresponding set of counting sub-signals.

4. The delay monitoring circuit according to claim 3, characterized in that, The counting module is further configured to, when the counting clock signal generates a pulse, control the carry clock signal to remain unchanged and control the internal clock signal to generate a pulse to change the count value of the set of counting sub-signals; or, control the carry clock signal to generate a pulse and control the internal clock signal to remain unchanged to maintain the count value of the set of counting sub-signals unchanged.

5. The delay monitoring circuit according to claim 4, characterized in that, The counting processing module includes a count value output module and an encoding module; wherein... The counting value output module is configured to receive the internal clock signal and a set of encoded signals, sample the set of encoded signals according to the internal clock signal, and output the set of counting sub-signals; The encoding module is configured to receive the set of counting sub-signals and output the set of encoded signals.

6. The delay monitoring circuit according to claim 5, characterized in that, The set of counting sub-signals includes A-bit counting sub-signals, and the set of encoded signals includes A-bit encoded signals; The count value output module includes A first flip-flops; wherein... The i-th first flip-flop is configured to receive the internal clock signal and the i-th bit encoded signal, sample the i-th bit encoded signal according to the internal clock signal, and output the i-th bit counter sub-signal; i and A are both positive integers, and i is less than or equal to A.

7. The delay monitoring circuit according to claim 6, characterized in that, The encoding module includes A encoding sub-modules, and the i-th encoding sub-module is used to output the i-th bit encoded signal; The i-th encoding submodule includes C first AND gates and one first OR gate; wherein... The first AND gate is configured to receive a portion of the counting sub-signals from the set of counting sub-signals and to output a decoded signal; The first OR gate is configured to receive the decoded signals output by C first AND gates respectively, and output the i-th bit encoded signal; where C is a positive integer.

8. The delay monitoring circuit according to claim 5, characterized in that, The clock processing module includes a comparison module and a clock generation module, and the comparison module includes a judgment module and a reference module; wherein, The judgment module is configured to receive the set of encoded signals and the set of reference signals, compare the set of encoded signals and the set of reference signals, and output a switch signal; The reference module is configured to receive the counting clock signal, the switching signal, and the set of counting sub-signals, and output the set of reference signals. The clock generation module is configured to receive the switch signal and the counting clock signal, and output the internal clock signal and the carry clock signal.

9. The delay monitoring circuit according to claim 8, characterized in that, The judgment module is further configured to output the switch signal in an effective state when the set of reference signals and the set of encoded signals correspond to the same value; or to output the switch signal in an invalid state when the set of reference signals and the set of encoded signals do not correspond to the same value. The reference module is further configured to update the level state of the set of reference signals using the set of counter sub-signals when the switch signal is in an active state. When the switch signal is in an invalid state, the set of reference signals remains unchanged; The clock generation module is further configured to, when the counting clock signal generates a pulse and the switch signal is in an invalid state, control the carry clock signal to remain unchanged and control the internal clock signal to generate a pulse to change the count value of the set of counting sub-signals; or, when the counting clock signal generates a pulse and the switch signal is in an active state, control the carry clock signal to generate a pulse and control the internal clock signal to remain unchanged to maintain the count value of the set of counting sub-signals unchanged.

10. The delay monitoring circuit according to claim 9, characterized in that, The judgment module includes A arithmetic processing modules and a second AND gate; wherein... The i-th processing module is configured to receive the i-th encoded signal and the i-th reference signal, and output the i-th operation value; wherein the i-th operation value is used to indicate whether the i-th encoded signal and the i-th reference signal are the same; The second AND gate is used to receive A operation values ​​output by the A operation processing modules, and to output the switch signal.

11. The delay monitoring circuit according to claim 9, characterized in that, The set of reference signals includes A reference signals, and the reference module includes A reference sub-modules, wherein the i-th reference sub-module is used to output the i-th reference signal; wherein... The i-th reference submodule includes a first transmission gate, a second transmission gate, and a second flip-flop; wherein... The first transmission gate is configured to receive the switch signal and the i-th bit counter sub-signal, and output the i-th bit counter sub-signal as an intermediate transmission signal when the switch signal is in an active state; The second transmission gate is configured to receive the inverted signal of the switch signal and the i-th reference signal, and output the i-th reference signal as the intermediate transmission signal when the switch signal is in an invalid state; The second trigger is configured to receive the counting clock signal and the intermediate transmission signal, sample the intermediate transmission signal according to the counting clock signal, and output the i-th reference signal.

12. The delay monitoring circuit according to claim 9, characterized in that, The clock generation module includes a transmission submodule, a sampling submodule, a first calculation submodule, and a second calculation submodule; wherein... The transmission submodule is configured to select a first logic signal and a second logic signal based on the switch signal to output a first processing signal; The sampling submodule is connected to the transmission submodule and is configured to sample the first processed signal and output the target sampled signal; The first arithmetic submodule receives the target sampling signal and the counting clock signal, and outputs the internal clock signal; The second operation submodule is configured to receive the target sampling signal and the counting clock signal, and output the carry clock signal.

13. The delay monitoring circuit according to claim 12, characterized in that, The transmission submodule includes a third transmission gate and a fourth transmission gate; the sampling submodule includes a third flip-flop and a fourth flip-flop; the first arithmetic submodule includes a third AND gate, and the second arithmetic submodule includes a third inverter and a fifth flip-flop; wherein... The third transmission gate is configured to receive the switch signal and the first standard logic signal, and output the first standard logic signal as the first processing signal when the switch signal is in an active state. The fourth transmission gate is configured to receive the inverted signal of the switch signal and the second standard logic signal, and output the second standard logic signal as the first processing signal when the switch signal is in an invalid state. The third trigger is configured to sample the first processing signal according to the counting clock signal and output an intermediate sampling signal; The fourth flip-flop is configured to sample the intermediate sampling signal according to the counting clock signal and output the target sampling signal; The third AND gate is configured to perform an AND operation on the counting clock signal and the target sampling signal to output the internal clock signal; The third inverter is configured to invert the target sampling signal to output an inverted target sampling signal; The fifth flip-flop is configured to sample the inverted target sampling signal according to the counting clock signal and output the carry clock signal.

14. The delay monitoring circuit according to any one of claims 6, 11, and 13, characterized in that, In the A first flip-flop, second flip-flop, third flip-flop, fourth flip-flop and fifth flip-flop, each flip-flop is also configured to receive its own reset signal and perform reset processing according to the received reset signal.

15. A semiconductor memory, characterized in that, The semiconductor memory includes at least the delay monitoring circuit as described in claim 1.

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