Semiconductor device and integrated circuit

Abstract

A semiconductor device includes: a first semiconductor relay and a second semiconductor relay connected in parallel with each other; an input switching circuit that switches a path of a signal input to the first and second semiconductor relays; an output switching circuit that switches a path of a signal output from the first and second semiconductor relays; and a monitoring section that performs abnormality detection and warning of the first and second semiconductor relays. Also, either of a redundant mode and a non-redundant mode is executed in correspondence with a first setting signal from the outside, in the redundant mode, the input switching circuit is controlled in a manner that inputs of the first and second semiconductor relays are shared, and the output switching circuit is controlled in a manner that only one of the first and second semiconductor relays is output, in the non-redundant mode, the input switching circuit and the output switching circuit are controlled in a manner that inputs and outputs of the first and second semiconductor relays are different, respectively.

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a semiconductor relay and an integrated circuit having a semiconductor relay, wherein the semiconductor relay is used to control two points to one of an electrically conductive state and an electrically inductive state. Background Technology

[0002] Currently, the electronic and electrical architecture of motor vehicles is undergoing a period of transformation. For example, companies are exploring a shift from the existing flat, hierarchical architecture, which merges ECUs (Engine Control Units) by function, to a zone architecture, which merges ECUs by region within the vehicle. Furthermore, within this trend of ECU consolidation, research is underway to modify component configurations, particularly regarding the replacement of mechanical relays and fuses with semiconductor relays.

[0003] Patent Document 1 discloses a relay circuit that can suppress the increase in manufacturing costs when using expensive semiconductor relays with large breaking currents. The relay circuit described in Patent Document 1 includes a circuit-breaking section and a control section for controlling the operation of the circuit-breaking section. The circuit-breaking section has a first relay (mechanical relay) and a second relay (semiconductor relay) connected to each other. When the current path is cut off, the control section moves the first relay from off to on, then moves the second relay from on to off, and then moves the first relay from on to off. Furthermore, when the current path is cut off, if the control section determines, based on the temperature of the semiconductor relay or the current flowing in the semiconductor relay, that it is unnecessary to turn on the mechanical relay, it keeps the mechanical relay off while turning the semiconductor relay off.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2017-46564 Summary of the Invention

[0007] The technical problem that the invention aims to solve

[0008] However, existing fuses, including the relay circuit shown in Patent Document 1, are so-called fail-safe devices that stop functioning due to overcurrent. However, it is foreseeable that in the future, at Level 3 and above of autonomous driving, certain functions will require continued operation even in the event of an anomaly—a so-called fail-operation. Therefore, when replacing fuses with semiconductor relays, it is necessary to support not only fail-safe operation but also fail-operation.

[0009] The purpose of this invention is to provide a semiconductor device and integrated circuit that can switch to a replacement semiconductor relay without interrupting the function when the main system malfunctions.

[0010] Technical means to solve the problem

[0011] To solve the above problems, for example, the structure described in the technical solution to be protected by the invention may be adopted.

[0012] This application includes multiple solutions to the above-mentioned problems. For example, the semiconductor device of the present invention includes: a first semiconductor relay and a second semiconductor relay connected in parallel; an input switching circuit that switches the path of signals input to the first semiconductor relay and the second semiconductor relay; an output switching circuit that switches the path of signals output from the first semiconductor relay and the second semiconductor relay; a monitoring unit that performs abnormality detection and warning for the first semiconductor relay and the second semiconductor relay; and a control circuit that executes either a redundant mode or a non-redundant mode in response to a first setting signal from the outside. In the redundant mode, the input switching circuit is controlled to share the inputs of the first semiconductor relay and the second semiconductor relay, and the output switching circuit is controlled to output only one of the first semiconductor relay and the second semiconductor relay. In the non-redundant mode, the input switching circuit and the output switching circuit are controlled in such a way that the inputs and outputs of the first semiconductor relay and the second semiconductor relay are different.

[0013] Invention Effects

[0014] This invention provides a semiconductor device that constitutes a redundant system and can switch to a replacement semiconductor relay without interrupting the function in the event of a main system failure. This enables its application in vehicle systems for functions requiring fault operation. Furthermore, the same semiconductor device can also be used as a non-redundant dual-channel (2ch) semiconductor relay structure, allowing for application in systems with different requirements by using the same component selectively, thus enabling its application in a wide range of systems.

[0015] Other issues, features, and effects not described above will become clear through the following examples of implementation. Attached Figure Description

[0016] Figure 1 This is a block diagram illustrating one example of the structure of a semiconductor device according to the first embodiment of the present invention.

[0017] Figure 2 This is a diagram illustrating one example of the structure of the input switching circuit 10 in the first embodiment.

[0018] Figure 3 This is a diagram illustrating one example of the structure of the output switching circuit 20 in the first embodiment.

[0019] Figure 4 It is a structural diagram of a table that records the control contents of the control circuit 30 in the first embodiment on the input switching circuit 10 and the output switching circuit 20.

[0020] Figure 5 This is a diagram illustrating one example of the structure of the semiconductor relay 1 in the first embodiment.

[0021] Figure 6 This is a flowchart illustrating the diagnostic process performed by the diagnostic unit 70 in the first embodiment.

[0022] Figure 7 This is a diagram illustrating a modified example of the structure of the semiconductor device 100 in the first embodiment.

[0023] Figure 8 This is a timing diagram of overcurrent diagnosis performed in the first embodiment.

[0024] Figure 9 This is a block diagram illustrating one example of the structure of a semiconductor device 100 according to a second embodiment of the present invention.

[0025] Figure 10 This is a block diagram illustrating one example of the structure of a semiconductor device 100 according to a third embodiment of the present invention.

[0026] Figure 11 This is a timing diagram for overcurrent diagnosis in the third embodiment.

[0027] Figure 12 This is a block diagram of a semiconductor integrated circuit 150 according to the fourth embodiment of the present invention.

[0028] Figure 13 This is a block diagram illustrating a modified example of a semiconductor integrated circuit 151 in the fourth embodiment of the present invention. Detailed Implementation

[0029] Hereinafter, as an example of an embodiment of the semiconductor device of the present invention, a semiconductor device having a semiconductor relay that constitutes a redundant system and can switch to a replacement system without interrupting the function when the main system fails.

[0030] By providing the semiconductor device of the present invention, it is possible to apply it to functions requiring fault operation in vehicle systems. Furthermore, the same semiconductor device can also be used as a non-redundant dual-channel (2ch) semiconductor relay structure, thereby enabling its application to systems with different requirements by using the same component selectively.

[0031] <First Embodiment Example of the Invention>

[0032] In the first embodiment of the present invention (hereinafter referred to as "this example"), when the operating mode of the semiconductor device 100 is set to the redundant mode, when the semiconductor relay of the main system malfunctions, it is possible to switch to the alternative system without interrupting the relay function. The operation during this switching will be described below.

[0033] The redundant mode in this invention employs the following operating mode: among the two semiconductor relays that are part of the semiconductor device 100, semiconductor relay 1 acts as the main system and is responsible for implementing the relay function of controlling the conduction or non-conduction state between the two points. Semiconductor relay 2 acts as a replacement system for semiconductor relay 1 and is in a functional standby state in case of main system failure.

[0034] That is, for the sake of simplicity, the semiconductor device 100 in this example assumes that semiconductor relay 1 is the main system and semiconductor relay 2 is the substitute system, but it is not problematic to have semiconductor relay 2 as the main system and semiconductor relay 1 as the substitute system. In addition, the signals used for setting and control in the description of semiconductor device 100 in this example are assumed to be binary logic, and are described as being valid when the level is high (hereinafter referred to as H level or H) and invalid when the level is low (hereinafter referred to as L level or L).

[0035] <Overall Structure and Function of Semiconductor Device 100>

[0036] Figure 1 This is a block diagram illustrating one example of the structure of the semiconductor device 100 in this example. For example... Figure 1 As shown, the semiconductor device 100 includes two semiconductor relays 1 and 2, an input switching circuit 10, an output switching circuit 20, and a control circuit 30.

[0037] As signals for connecting the semiconductor device 100 to its external environment, there are semiconductor relay control signals IN1 and IN2, and two output signal pairs OUT1 and OUT2. Additionally, there is a redundancy mode setting signal 30a for setting whether semiconductor relays 1 and 2 operate in a redundant mode consisting of a main system and a substitute system, and emergency stop signals 91a and 92a for emergency stopping semiconductor relays 1 and 2 from outside the semiconductor device 100. That is, the redundancy mode setting signal 30a can be considered as a signal that determines whether semiconductor relays 1 and 2 operate in redundant mode or in the non-redundancy mode described later.

[0038] Additionally, there is an input / output commonality setting signal 30b, which is used to set whether the semiconductor relay control signals IN1 and IN2 are used as common input signals in the semiconductor device 100 operating in redundant mode, and whether the output signal pairs OUT1 and OUT2 are used as common output signal pairs. Specifically, the output signal pair OUT1 consists of two output signals OUT1U and OUT1L, and the output signal pair OUT2 consists of two signals OUT2U and OUT2L. That is, the input / output commonality setting signal 30b controls the input switching circuit 10 and the output switching circuit 20 to make the input and output of semiconductor relay 1 and semiconductor relay 2 a dual system (i.e., two sets). Here, as a higher-level concept, the redundancy mode setting signal 30a is referred to as the first setting signal, and the input / output commonality setting signal 30b is referred to as the second setting signal.

[0039] The input switching circuit 10 takes semiconductor relay control signals IN1 and IN2 and input control signal 31 from the control circuit 30 as inputs, and outputs drive signals 11 and 12 for indicating drive to semiconductor relays 1 and 2. For example, the input switching circuit 10... Figure 2 The structure shown employs switches S1, S2, and S3. The control of the on / off state of each switch in the input switching circuit 10 is based on the control signal 31 from the input section of the control circuit 30.

[0040] The output switching circuit 20 takes semiconductor relay outputs 41a and 41b from semiconductor relay 1 and semiconductor relay outputs 42a and 42b from semiconductor relay 2 as inputs, and outputs output signals OUT1 and OUT2.

[0041] In this example, the output switching circuit 20 in the semiconductor device 100 is, for example... Figure 3The circuit shown employs a structure with switches SU11-SU22, SU3, SL11-SL22, and SL3. The on / off state of each switch in the output switching circuit 20 is controlled based on the control signal 32 from the output unit of the control circuit 30.

[0042] A redundancy mode setting signal 30a and an input / output commonality setting signal 30b are input to the control circuit 30, and an abnormality warning signal 71b is input from the semiconductor relay 1. The control circuit 30 outputs an input control signal 31 and an output control signal 32 accordingly based on the combination of these three input signals. As a result, the control circuit 30 controls the input switching circuit 10 and the output switching circuit 20 to their respective configurations, as described later. Figure 4 The state shown.

[0043] Figure 4 This is a structural diagram showing the control content of the control circuit 30 when it controls the on / off states of the switches included in the input switching circuit 10 and the output switching circuit 20. In this example, the input switching circuit 10 and the output switching circuit 20 of the semiconductor device 100 are selected according to the combination of the redundancy mode setting signal 30a, the input / output commonality setting signal 30b, and the abnormal warning signal 71b. Figure 4 The switches shown are set to No.1 to No.5.

[0044] <Structure and Function of Semiconductor Relays>

[0045] Figure 5 This diagram illustrates an example structure of the semiconductor relay 1 used in the semiconductor device 100 of this example. The semiconductor relay 1 includes a switching element 40, a temperature sensor 50, a current sensor 60, a diagnostic unit 70, and a drive circuit 80. Here, the temperature sensor 50 constitutes a temperature detection unit, and the current sensor 60 constitutes a current detection unit. Furthermore, the temperature sensor 50, the current sensor 60, and the diagnostic unit 70 together form a monitoring unit that performs abnormality detection and warnings for both the first semiconductor relay 1 and the second semiconductor relay 2.

[0046] The two semiconductor relays, 1 and 2, have identical components, but their signal lines and control lines are labeled with different numbers for clarity in the description. However, all components other than the signal lines and control lines are labeled with the same number.

[0047] The following describes the components of semiconductor relay 1. As for the components of semiconductor relay 2, since only the signal lines and control lines are labeled differently from those of semiconductor relay 1, the description is omitted.

[0048] The switching element 40 is turned on or off based on the switching element control signal 81 output by the drive circuit 80, controlling the two points 41a and 41b of the semiconductor relay to be in a conducting or non-conducting state. When the switching element 40 is on, the two points 41a and 41b of the semiconductor relay are controlled to be in a conducting state; when the switching element 40 is off, the two points 41a and 41b of the semiconductor relay are controlled to be in a non-conducting state. Furthermore, in this example, the semiconductor device 100 uses, for example, a switching element 40, such as... Figure 2 The N-channel MOSFET shown.

[0049] Temperature sensor 50 detects the temperature of switching element 40 and provides temperature detection result 51 to diagnostic unit 70. Additionally, current sensor 60 detects the current flowing in switching element 40 and provides current detection result 61 to diagnostic unit 70.

[0050] Based on the temperature detection results 51 and current detection results 61 supplied from the temperature sensor 50 and the current sensor 60, the diagnostic unit 70 compares the temperature and current of the switching element 40 with predetermined thresholds, and outputs a drive stop signal and / or an abnormal warning signal 71b based on the abnormal diagnostic result 71a.

[0051] The diagnostic unit 70 uses overheat warning threshold 51a, overheat diagnostic threshold 51b, overcurrent warning threshold 61a, and overcurrent diagnostic threshold 61b as comparison thresholds. Here, overheat diagnostic threshold 51b is a value larger than overheat warning threshold 51a, and overcurrent diagnostic threshold 61b is a value larger than overcurrent warning threshold 61a.

[0052] Specifically, the diagnostic unit 70 compares the temperature detection result 51 with the overheat diagnosis threshold 51b. If the temperature detection result 51 is higher than the overheat diagnosis threshold 51b, the switching element 40 is diagnosed as being in an overheated state.

[0053] In addition, the diagnostic unit 70 compares the current detection result 61 with the overcurrent diagnostic threshold 61b. If the current detection result 61 is greater than or equal to the overcurrent diagnostic threshold 61b, the switching element 40 is diagnosed as being in an overcurrent state.

[0054] When the diagnostic unit 70 diagnoses the switching element 40 as being in an overheated and / or overcurrent state, it outputs an abnormal diagnosis result 71a and an abnormal warning signal 71b as diagnostic information. Here, the abnormal diagnosis result 71a is output to the drive circuit 80. Based on this abnormal diagnosis result 71a, the drive circuit 80 controls the switching element 40 to a non-conducting state. Additionally, the abnormal warning signal 71b is supplied to… Figure 1The control circuit 30 is used to control the cutting off of the input switching circuit 10 and the output switching circuit 20.

[0055] The overheat warning threshold 51a, overheat diagnostic threshold 51b, overcurrent warning threshold 61a, and overcurrent diagnostic threshold 61b can all be generated by circuitry installed inside the diagnostic unit 70, or they can be generated externally and input to the diagnostic unit 70. Furthermore, these thresholds can be configured as analog voltage values ​​or digital values ​​consisting of multiple bits.

[0056] The drive circuit 80 receives a drive signal 11, an abnormal diagnosis result 71a, and an emergency stop signal 91a as inputs, and outputs a switching element control signal 81. Here, the emergency stop signal 91a is a high-level signal supplied from the load circuit side when an abnormality occurs in the load circuit, which is the target of the semiconductor relay 1, preventing the load circuit from automatically disconnecting.

[0057] When both the abnormal diagnosis result 71a and the emergency stop signal 91a are at the L level, the drive circuit 80 directly supplies the indication of the drive signal 11 as the control signal 81 to the switch element 40 to control the switching element 40 to turn on and off.

[0058] Furthermore, when at least one of the abnormal diagnosis result 71a and the emergency stop signal 91a is at a high level, the drive circuit 80 outputs a switching element control signal 81 that turns off the switching element 40, regardless of the state of the drive signal 11. That is, the abnormal diagnosis result 71a and the emergency stop signal 91a have the function of forcibly turning off the switching element 40.

[0059] <Diagnostic Processing Flow in the Diagnostic Unit 70 of Semiconductor Relays>

[0060] Figure 6 This is a flowchart illustrating the diagnostic process performed by the diagnostic unit 70 of the semiconductor relay 1 in the semiconductor device 100 of this example.

[0061] First, the diagnostic unit 70 of the semiconductor relay 1 diagnoses whether the temperature detection result 51 in the switching element 40 of the semiconductor relay 1 exceeds the overheat diagnostic threshold 51b, or whether the current detection result 61 exceeds the overcurrent diagnostic threshold 61b (ST1). If the diagnostic unit 70 diagnoses that the relay is in an overheat or overcurrent state (ST1 "Yes"), the diagnostic unit 70 outputs an H level as both an abnormal diagnostic result 71a and an abnormal warning signal 71b (ST10).

[0062] If neither overheating nor overcurrent occurs in step ST1 (ST1 is "No"), the diagnostic unit 70 then diagnoses whether the temperature detection result 51 is above the overheat warning threshold 51a or whether the current detection result 61 is above the overcurrent warning threshold 61a (ST2).

[0063] If the diagnostic unit 70 determines in step ST2 that it is in an overheat warning or overcurrent warning state (ST2 "Yes"), the diagnostic unit 70 outputs an H level as an abnormal warning signal 71b. Alternatively, if it is not in an overheat or overcurrent state, the diagnostic unit 70 outputs an L level as an abnormal diagnosis result 71a (ST11).

[0064] If, in step ST2, the diagnostic unit 70 diagnoses that both temperature and current are normal (ST2 "No"), the diagnostic unit 70 outputs an L level as both an abnormal diagnosis result 71a and an abnormal warning signal 71b (ST12). Once the diagnosis of each state in ST10 to ST12 is determined, the diagnostic processing flow of the diagnostic unit 70 ends.

[0065] In this example of semiconductor device 100, when the main system's semiconductor relay 1 reaches an overheat warning or overcurrent warning state, the substitute system's semiconductor relay 2 is also turned on. Thus, both semiconductor relay 1 and semiconductor relay 2 temporarily perform relay functions. When semiconductor relay 1 is eventually forcibly turned off due to an overheat or overcurrent diagnosis, semiconductor relay 2 can be used to maintain the operation of semiconductor device 100 without interruption in time.

[0066] The following uses Figure 7 The structural diagram of the semiconductor device 100 shown in this example and Figure 8 The timing diagram shown illustrates the structure and function.

[0067] Figure 7 This is a block diagram illustrating a modified structure of the semiconductor device 100 in this example. Figure 1 The difference is that in semiconductor device 100, one of the relay outputs of the main system, OUT1U, is connected to the battery voltage VB, and the other output, OUT1L, is connected to the ground potential GND via load 90.

[0068] For simplicity, it is assumed that OUT1U of OUT1U and OUT1L is at a relatively high potential. Furthermore, it is assumed that the first setting signal (redundancy mode setting signal 30a) and the second setting signal (input / output commonality setting signal 30b) are respectively connected to the power supply and have fixed potentials. This prevents unexpected mode changes during the operation of the semiconductor device 100.

[0069] In the semiconductor device 100 of this example, the redundancy mode setting signal 30a is connected to and fixed with the battery voltage VB, and the input / output commonality setting signal 30b is connected to and fixed with the ground potential GND.

[0070] Figure 8 This is a timing diagram that represents the current of semiconductor relay 1, a component of semiconductor device 100, as I1, and the current of semiconductor relay 2 as I2. The horizontal axis represents time, indicating any given time. The vertical axis represents the current value. Figure 8 (a) represents the current I1. Figure 8 (b) represents the current I2. Figure 8 (c) represents the total current (I1+I2) of currents I1 and I2. Additionally, in Figure 8 (a) and Figure 8 In (b), the overcurrent warning thresholds 61a and 62a, and the overcurrent diagnosis thresholds 61b and 62b are marked respectively.

[0071] Figure 8 In this example, the semiconductor device 100 is set to redundant mode, the semiconductor relay 1 acts as the main system responsible for relay operation, and the timing diagram begins from the state where the switching element 40 is turned on. Furthermore, the input / output commonality setting signal 30b is not directly related to this operation description, so it is at low level here.

[0072] At the beginning of the timing diagram, the settings of each switch included in the input switching circuit 10 and the output switching circuit 20 conform to... Figure 4 The switch setting is No. 1.

[0073] and Figure 3 By referring to the structural diagram and focusing on the output switching circuit 20, it can be seen that the outputs 41a and 41b of the main system, i.e., semiconductor relay 1, are connected to the outputs OUT1U and OUT1L because switches SU11, SU12, SL11, and SL12 are turned on. On the other hand, the outputs 42a and 42b of the alternative system, i.e., semiconductor relay 2, are electrically insulated from OUT1U and OUT1L because switches SU21, SU3, SL21, and SL3 are turned off.

[0074] Under the above premises, refer to Figure 8 The timing diagram assumes that at time t1, the current value of semiconductor relay 1 begins to increase due to aging or other reasons. The current 11 of semiconductor relay 1 continues to increase, reaching the overcurrent warning threshold 61a at time t2. Thus, at time t2, the diagnostic unit 70... Figure 6 The diagnostic process shown indicates that semiconductor relay 1 is in an overcurrent warning state, causing the abnormal warning signal 71b to change from L level to H level (ST1→ST2→ST11).

[0075] Due to the change in the output level of the abnormal warning signal 71b, the switching setting of the output switching circuit 20 changes from... Figure 4 In the table, No. 1 is moved to No. 2. Under switch setting No. 2, switches SU21, SU3, SL21, and SL3 are further turned on compared to switch setting No. 1. As a result, the outputs 42a and 42b of the substitute system, i.e., semiconductor relay 2, are connected to the outputs OUT1U and OUT1L of semiconductor device 100. That is, at time t2, the outputs 41a and 41b of semiconductor relay 1 and the outputs 42a and 42b of semiconductor relay 2 are both connected to the outputs OUT1U and OUT1L of semiconductor device 100, thus creating a state where the load 90 is driven by both the main system, i.e., semiconductor relay 1, and the substitute system, i.e., semiconductor relay 2.

[0076] The current in semiconductor relay 1 continues to increase after time t2, reaching the overcurrent diagnosis threshold 61b at time t3. At this time, the diagnostic unit 70... Figure 6 The diagnostic process described herein diagnoses that semiconductor relay 1 is in an overcurrent state, causing the abnormal diagnostic result 71a to change from L level to H level (ST1→S10). Thus, since the abnormal diagnostic result 71a becomes H level, the switching element 40 of semiconductor relay 1 is forcibly turned off, switching to drive the load 90 using only semiconductor relay 2.

[0077] Here, we focus on Figure 8 As shown in (c), the total current (I1+I2) of currents I1 and I2 will not cause current interruption due to the above operation, and the load 90 can be continuously driven on the time axis. As explained above, even if the semiconductor relay of the main system malfunctions, it is possible to switch to the alternative system without interrupting the relay function.

[0078] <Second Embodiment Example of the Invention>

[0079] Next, refer to Figure 9 The structure and function of the semiconductor device 100 according to the second embodiment of the present invention will be described.

[0080] exist Figure 9 In the second embodiment of the present invention shown, a case where the semiconductor relay of the main system malfunctions when the operating mode of the semiconductor device 100 is set to redundant mode is described. That is, in this embodiment, in the operation of switching to the alternative system without interrupting the relay function in time, a structure is adopted to further improve reliability by configuring the inputs of the semiconductor device 100, namely the semiconductor relay control signals IN1 and IN2, and the outputs of the semiconductor device 100, namely the output signals OUT1 and OUT2, as a dual system (two sets).

[0081] In the second embodiment, the operation mode adopted by the redundancy mode is the same as that in the first embodiment. Among the two semiconductor relays that are part of the semiconductor device 100, semiconductor relay 1 is the main system responsible for realizing the relay function of controlling the conduction or non-conduction state between the two points. Semiconductor relay 2 is the replacement system for semiconductor relay 1 and is in a functional standby state in order to prevent the main system from malfunctioning.

[0082] exist Figure 9 In the second embodiment shown, for the sake of simplicity, semiconductor relay 1 is assumed to be the main system and semiconductor relay 2 is the alternative system, and appropriate omissions are made. Figure 1 The description of the first embodiment shown is repeated.

[0083] The semiconductor device 100 differs from the one in the first embodiment in the following three structural aspects. First, instead of connecting the input / output common setting signal 30b to ground potential GND, it is connected to the battery voltage VB, thus fixing the potential. Second, in order to configure the input of the semiconductor device 100 as a dual system (i.e., two sets), signals IN1 and IN2 are interconnected externally to the semiconductor device 100. Third, in order to configure the output of the semiconductor device 100 as a dual system similarly to the input, output signals OUT1 and OUT2 are interconnected, such that OUT1 and OUT2 are connected in parallel as viewed from the load 90.

[0084] and Figure 1 Similar to the first embodiment shown, in this embodiment, when the semiconductor relay 1 in the main system reaches an overheat warning or overcurrent warning state, the semiconductor device 100 also switches on the system's semiconductor relay 2, thereby temporarily allowing both semiconductor relay 1 and semiconductor relay 2 to perform relay functions. Furthermore, according to the semiconductor device 100 of this embodiment, when semiconductor relay 1 is eventually forcibly turned off due to an overheat or overcurrent diagnosis, semiconductor relay 2 can be used to ensure uninterrupted relay function over time. Moreover, the detailed operation can be explained in the same way as in the first embodiment, so the description of this embodiment can be directly referred to in the description of the first embodiment. Figures 2-6 and Figure 8 .

[0085] and Figure 1 The difference in the first embodiment shown is that, since the input / output commonality setting signal 30b is at level H, the switching settings of the input switching circuit 10 and the output switching circuit 20 are set to... Figure 4The examples shown are No. 3 (normal condition) and No. 4 (main system relay malfunction). Furthermore, as described above, in the first embodiment example... Figure 4 The switches shown are set to No.1 (normal operation) and No.2 (when the main system relay malfunctions). Therefore, in addition to the dualization (dual redundancy) of the relay function described in the first embodiment, a dual system (redundant system) is further constructed in the input / output section of the semiconductor device 100, so that the operation of the semiconductor device 100 can continue even if the input or output of one of the dual systems is disconnected.

[0086] As explained above, the second embodiment is characterized by a structure in which, in the event of an abnormality in the semiconductor relay of the main system, in addition to switching to the operation of the system without interrupting the relay function, the inputs of the semiconductor device 100, namely the semiconductor relay control signals IN1 and IN2, and the outputs of the semiconductor device 100, namely the output signals OUT1 and OUT2, are also dualized, thereby improving reliability.

[0087] <Third Embodiment Example of the Invention>

[0088] In the third embodiment of the present invention, reference is made to... Figure 10 The operation of the semiconductor device 100 when its operating mode is set to non-redundant mode will be explained.

[0089] The non-redundant mode in the third embodiment employs an operating mode in which two semiconductor relays 1 and 2, which are components of the semiconductor device 100, are each individually responsible for implementing the relay function of controlling the conduction or non-conduction state between the two points. This operating mode corresponds to the case where an L level is applied as a redundancy mode setting signal 30a.

[0090] In non-redundant mode, both semiconductor relays 1 and 2 are primary systems, and there is no substitute system. Therefore, in cases where an abnormality is diagnosed due to overheating or overcurrent, the relay function is cut off and operation ceases, thus enabling systems with fault protection requirements that use semiconductor devices 100 with the same structure as other implementation examples.

[0091] Figure 10 This is a block diagram illustrating one example of the structure of the semiconductor device 100 according to the third embodiment of the present invention. The structure differs from that of the semiconductor device 100 in the first embodiment in that the redundancy mode setting signal 30a is connected to GND, and loads 91 and 92 are respectively provided in the output section for the independent use of semiconductor relay 1 and semiconductor relay 2.

[0092] Because the redundancy mode setting signal 30a is at L level, therefore... Figure 4 According to the switch setting table, the switch setting of the input switching circuit 10 and the output switching circuit 20 of the semiconductor device 100 in this embodiment is No. 5. That is, switches S3, SU3 and SL3 are in the off state. As a result, the input of semiconductor relay 1 is IN1 and the output is OUT1 (the pair of OUT1U and OUT1L), and the input of semiconductor relay 2 is IN2 and the output is OUT2 (the pair of OUT2U and OUT2L).

[0093] Next, the action of immediately stopping the relay function in the event of an abnormality in the semiconductor relay will be explained in this embodiment. In this embodiment, semiconductor relay 1 and semiconductor relay 2 operate independently, and the action stopping process in case of abnormality is also an independent action.

[0094] In addition, the diagnostics of each semiconductor relay 1 and 2 are performed according to... Figure 6 The diagnostic procedure shown is performed. Here, since semiconductor relays 1 and 2 operate independently, an example of a malfunction in semiconductor relay 1 is used for illustration.

[0095] Figure 11 This is a timing diagram in which the current of semiconductor relay 1 in this embodiment is denoted as I1 and the current of semiconductor relay 2 is denoted as I2. Figure 11 (a) is plotted with current I1 as the vertical axis. Figure 11 (b) With current I2 as the vertical axis, in Figure 11 (a) and Figure 11 In (b), the overcurrent warning thresholds 61a and 62a and the overcurrent diagnosis thresholds 61b and 62b are marked respectively.

[0096] Assuming in Figure 11 At time t11 in the timing diagram, the current value of semiconductor relay 1 begins to increase due to aging and other factors. The current of semiconductor relay 1 continues to increase, reaching the overcurrent warning threshold 61a at time t12. At this time t12, the diagnostic unit 70... Figure 6 The diagnostic process shown indicates that semiconductor relay 1 is in an overcurrent warning state, causing the abnormal warning signal 71b to change from L level to H level (ST1→ST2→ST11).

[0097] However, in Figure 4 In the switch setting table, because it is in non-redundant mode (redundant mode setting signal 30a is at L level), the abnormal warning signal 71a is unrelated to switch control, and the semiconductor relay 1 remains in the ON state.

[0098] After time t12, the current 11 of semiconductor relay 1 continues to increase, reaching the overcurrent diagnosis threshold 61b at time t13. At this time, the diagnostic unit 70 proceeds according to... Figure 6 The diagnostic process diagnoses semiconductor relay 1 as being in an overcurrent state, causing the abnormal diagnostic result 71a to change from L level to H level (ST1→S10). Therefore, because the abnormal diagnostic result 71a becomes H level, the switching element 40 of semiconductor relay 1 is forcibly turned off, and the drive of load 91 stops. Regarding semiconductor relay 2, it continues to operate in non-redundant mode regardless of whether semiconductor relay 1 experiences an abnormality.

[0099] As described above, even in non-redundant mode, if a semiconductor relay malfunctions, it can immediately stop the relay function.

[0100] <Fourth Embodiment Example of the Invention>

[0101] In the fourth embodiment of the present invention, reference is made to... Figure 12 The semiconductor integrated circuit integrating the semiconductor devices 100 described in the first to third embodiments will be described. When the functions of the redundant structure formed by the main system and the alternative system are integrated into the circuit, electrical damage, cracking, and combustion that may lead to common cause failure may become a problem. Here, technical means to avoid such problems will be specifically described.

[0102] Figure 12 This example illustrates a semiconductor integrated circuit 150 according to a fourth embodiment of the present invention. The semiconductor integrated circuit 150 of this embodiment includes an SOI (Silicon On Insulator) substrate 110, on which semiconductor relay 1, semiconductor relay 2, input switching circuit 10, output switching circuit 20, and control circuit 30 are integrated. Furthermore, the constituent elements mounted on the SOI substrate are electrically isolated from each other by element isolation films 200 formed of silicon dioxide (SiO2) as insulators.

[0103] like Figure 12 As shown, each component mounted on the SOI substrate 110 is formed on a silicon surface electrically isolated by the component isolation film 200. Here, it is conceivable that the semiconductor relay 1 may suffer electrical damage, such as a short circuit, due to electrical stress from outside the integrated circuit 150, causing electrical failure of the semiconductor relay 1. However, even in such a case, because each component is electrically isolated by the component isolation film 200, electrical damage to one component can be prevented from affecting other components on the SOI substrate 110. Therefore, common-cause failure of other components can be avoided.

[0104] In addition, as a common cause failure avoidance measure in the fourth embodiment, it is also possible to consider Figure 13The semiconductor integrated circuit 151 shown is an example of another embodiment as a variation. In Figure 13 In the semiconductor integrated circuit 151 of the modified fourth embodiment shown, semiconductor relay 1 is formed as a semiconductor relay chip 101 integrated on a silicon substrate, and semiconductor relay 2 is formed as a semiconductor relay chip 102 integrated on a different silicon substrate than semiconductor relay 1. Furthermore, a peripheral circuit chip 103 is provided, on a different silicon substrate than semiconductor relay chips 101 and 102, integrating an input switching circuit 10, an output switching circuit 20, and a control circuit 30. Thus, the modified fourth embodiment is characterized by employing a System-in-Package (SIP) structure that seals chips 101 to 103 within the same resin package.

[0105] In the SIP structure, each chip 101 to 103 is mounted in a different position within the resin package, thus achieving both physical and electrical isolation through the different mounting positions.

[0106] For example, in the event of electrical damage to the semiconductor relay chip 101 due to electrical stress, the electrical fault can be prevented from propagating to other chips. Furthermore, in the event of a fault such as cracking or burning of the semiconductor relay chip 101 due to rapid heating or high current, physical distance can prevent other isolated chips from malfunctioning.

[0107] As explained above, the semiconductor device according to this embodiment can avoid common-cause failures that start with the failure of a certain component, which can be problematic when the functions of the redundant structure formed by the main system and the alternative system are integrated into the circuit.

[0108] Furthermore, in the accompanying drawings, only the necessary parts of the control lines and information lines are marked, and not all control lines and information lines on the product are necessarily marked. Also, this invention is not limited to the above-described embodiments; various applications and modifications are included as long as they do not depart from the technical solution to be protected by the invention.

[0109] For example, the above-described embodiments are detailed to aid in understanding the present invention and are not intended to limit the implementation to all of the described structures. Furthermore, a portion of the structure of one embodiment can be replaced with the structure of another embodiment, or the structure of another embodiment can be added to the structure of one embodiment. Additionally, for a portion of the structure of each embodiment, other structures can be added, deleted, or replaced.

[0110] Explanation of reference numerals in the attached figures

[0111] 100… Semiconductor device; 101, 102… Semiconductor relay chip; 103… Peripheral circuit chip; 110… SOI substrate; 150, 151… Semiconductor integrated circuit; 200… Component isolation film

[0112] 1, 2... Semiconductor relays; 10... Input switching circuit; 11, 12... Drive signals; 20... Output switching circuit; 30... Control circuit; 30a... Redundancy mode setting signal; 30b... Input / output commonality setting signal; 31... Input control signal; 32... Output control signal; 40... Switching element; 41a, 41b, 42a, 42b... Semiconductor relay outputs; 50... Temperature sensor; 51, 52... Temperature detection results; 51a... Overheat warning threshold; 51b... Overheat diagnostic threshold Values: 60... Current sensor; 61, 62... Current detection results; 61a, 62a... Overcurrent warning threshold; 61b, 62b... Overcurrent diagnostic threshold; 70... Diagnostic unit; 71a, 72a... Abnormal diagnostic results; 71b, 72b... Abnormal warning signals; 80... Drive circuit; 81, 82... Switching element control signals; 90, 91, 92... Load circuit; 91a, 92a... Emergency stop signals; IN1, IN2... Semiconductor relay control signals; OUT1, OUT2... Output signal pairs

[0113] S1, S2, S3, SU11, SU12, SU21, SU22, SU3, SU11, SU12, SU21, SU22, SU3... switches.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor relay and a second semiconductor relay connected in parallel to each other; An input switching circuit that switches the path of the signal input to the first semiconductor relay and the second semiconductor relay; An output switching circuit that switches the path of the signal output from the first semiconductor relay and the second semiconductor relay; The monitoring unit performs anomaly detection and warnings for the first and second semiconductor relays; and A control circuit that executes either a redundancy mode or a non-redundancy mode in response to a first setting signal from an external source. In the redundancy mode, the input switching circuit is controlled by sharing the inputs of the first and second semiconductor relays, and the output switching circuit is controlled by outputting only one of the first and second semiconductor relays. In the non-redundancy mode, the input switching circuit and the output switching circuit are controlled with the inputs and outputs of the first and second semiconductor relays being different, respectively.

2. The semiconductor device as described in claim 1, characterized in that: In the redundant mode, the output switching circuit is controlled by the control circuit to share the outputs of both the first semiconductor relay and the second semiconductor relay, corresponding to the warning from the monitoring unit.

3. The semiconductor device as described in claim 1, characterized in that: The first semiconductor relay and the second semiconductor relay include: Switching elements; A drive circuit that drives the switching element; and The monitoring unit, wherein The switching element is turned off using the drive circuit in accordance with the output of the monitoring unit.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The monitoring unit includes: The temperature detection unit detects the temperature of the switching elements of the first semiconductor relay and the second semiconductor relay. A current detection unit that detects the current flowing in the switching element; and The diagnostic unit detects overheating and / or overcurrent as abnormalities of the switching element based on the temperature information obtained by the temperature detection unit and / or the current information obtained by the current detection unit, and issues an overheating and / or overcurrent warning before the switching element reaches an abnormality based on the temperature information obtained by the temperature detection unit and / or the current information obtained by the current detection unit.

5. The semiconductor device as described in claim 4, characterized in that: The control circuit further controls the input switching circuit and the output switching circuit in a redundant mode in accordance with a second setting signal from the outside, so that the inputs and outputs of the first semiconductor relay and the second semiconductor relay become a dual system.

6. An integrated circuit, characterized in that: The integrated circuit includes semiconductor devices. The semiconductor device includes: A first semiconductor relay and a second semiconductor relay connected in parallel to each other; An input switching circuit that switches the path of the signal input to the first semiconductor relay and the second semiconductor relay; An output switching circuit that switches the path of the signal output from the first semiconductor relay and the second semiconductor relay; The monitoring unit performs anomaly detection and warnings for the first and second semiconductor relays; and A control circuit that executes either a redundancy mode or a non-redundancy mode in response to a first setting signal from an external source. In the redundancy mode, the input switching circuit is controlled by sharing the inputs of the first and second semiconductor relays, and the output switching circuit is controlled by outputting only one of the first and second semiconductor relays. In the non-redundancy mode, the input switching circuit and the output switching circuit are controlled with the inputs and outputs of the first and second semiconductor relays being different, respectively. In the integrated circuit, the first semiconductor relay, the second semiconductor relay, the input switching circuit, the output switching circuit, and the control circuit are integrated on a single SOI substrate, and... The integrated components are electrically isolated from each other on the SOI substrate by a component isolation film formed of silicon dioxide.

7. An integrated circuit, characterized in that: The integrated circuit includes semiconductor devices. The semiconductor device includes: A first semiconductor relay and a second semiconductor relay connected in parallel to each other; An input switching circuit that switches the path of the signal input to the first semiconductor relay and the second semiconductor relay; An output switching circuit that switches the path of the signal output from the first semiconductor relay and the second semiconductor relay; The monitoring unit performs anomaly detection and warnings for the first and second semiconductor relays; and A control circuit that executes either a redundancy mode or a non-redundancy mode in response to a first setting signal from an external source. In the redundancy mode, the input switching circuit is controlled by sharing the inputs of the first and second semiconductor relays, and the output switching circuit is controlled by outputting only one of the first and second semiconductor relays. In the non-redundancy mode, the input switching circuit and the output switching circuit are controlled with the inputs and outputs of the first and second semiconductor relays being different, respectively. In the integrated circuit, the first semiconductor relay chip, the second semiconductor relay chip, and the peripheral circuit chip are sealed in the same package. The first semiconductor relay chip integrates the first semiconductor relay, the second semiconductor relay chip integrates the second semiconductor relay, and the peripheral circuit chip integrates the input switching circuit, the output switching circuit, and the control circuit.

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