Monolithic integrated circuit and method for manufacturing the same

Abstract

The present application discloses a monolithic integrated circuit and a method for manufacturing the same. The method for manufacturing the monolithic integrated circuit includes providing a substrate; forming a resonator on the substrate; forming a capacitor on the substrate; and / or forming an inductor on the substrate; and manufacturing metal interconnects on the substrate to connect the capacitor and / or the inductor to the resonator. The present application integrates the resonator and the LC circuit on the same chip to form a MEMS monolithic integrated circuit, forming a multifunctional integrated device, and improving performance and integration.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment, and in particular to a monolithic integrated circuit and a manufacturing method thereof. Background Art

[0002] MEMS devices are micro-electro-mechanical systems (Micro-Electro-Mechanical System), which are small devices or structural systems that may include integrated mechanical devices and electronic devices to sense immediate or local environmental changes. Or when there is a corresponding signal input, it will perform some physical interaction with the immediate or local environment.

[0003] The rapid development of modern electronic information technology has greatly promoted the development of electronic products towards multi-function, high performance, reliability, miniaturization, portability and low cost required by popularization. The product based on this patent integrates the MEMS resonator and the LC circuit on the same chip to form a MEMS monolithic integrated circuit and a multifunctional integrated chip, so as to achieve the requirements of improving product integration, high performance, miniaturization and low cost. Summary of the invention

[0004] The purpose of the present application is to provide a monolithic integrated circuit with good performance and high integration and a method for manufacturing the same.

[0005] The present application discloses a method for manufacturing a monolithic integrated circuit, which comprises:

[0006] S1: providing a substrate;

[0007] S2: forming a resonator on the substrate;

[0008] S3: forming a capacitor on the substrate; and / or forming an inductor on the substrate;

[0009] S4: Fabricate metal interconnection lines on the substrate to connect the capacitor and / or the inductor to the resonator.

[0010] Optionally, step S2 is performed before step S3, or step S2 is performed after step S3, or step S2 and step S3 are performed simultaneously. Optionally, the substrate is a wafer.

[0011] Optionally, step S3 includes:

[0012] T1: defining the morphology of the inductor on the substrate by photolithography technology;

[0013] T2: depositing a polymer film in the grooves formed by photolithography;

[0014] T3: etching the polymer film along a first direction;

[0015] T4: etching the substrate along the first direction;

[0016] Repeating the step T2, the step T3 and the step T4 multiple times to achieve deep silicon etching;

[0017] T5: forming a seed layer in the groove formed by deep silicon etching;

[0018] T6: Filling the groove formed by deep silicon etching with metal to form the inductor.

[0019] Optionally, step S2 includes:

[0020] forming a piezoelectric film on one side of the substrate;

[0021] forming a second electrode on a side of the piezoelectric film away from the substrate;

[0022] Etching is performed on a side of the substrate away from the piezoelectric film to form a cavity, the projection of the cavity in the first direction falls within the projection of the piezoelectric film in the first direction, and the cavity connects the piezoelectric film and the side of the substrate away from the piezoelectric film;

[0023] A first electrode is formed in the cavity. The first electrode is located on a side of the piezoelectric film away from the second electrode and is attached to the piezoelectric film.

[0024] Optionally, the step S2 further includes:

[0025] A metal layer is formed in the cavity, and the metal layer realizes electrical connection between the first electrode and a side of the substrate facing away from the piezoelectric film.

[0026] Optionally, step S4 further includes:

[0027] Bonding the side of the substrate close to the resonator to a carrier;

[0028] A thinning process is performed on a side of the substrate away from the resonator to reduce the thickness of the substrate to 50 μm-150 μm.

[0029] Optionally, step S4 further includes:

[0030] Positioning a plurality of back holes and defining the opening sizes of the back holes on a side of the substrate away from the resonator by a photolithography process, wherein the projection of the back holes in a first direction has an overlapping area with a metal electrode of the resonator or the capacitor or the inductor;

[0031] Performing deep silicon etching on the positions of the located back holes to form the back holes, wherein the back holes connect the metal electrodes of the resonator or the capacitor or the inductor with a side of the substrate away from the resonator;

[0032] A back metal structure is formed on a side of the substrate away from the resonator and in the back hole, and the metal layer is connected to metal electrodes of the resonator and / or the capacitor and / or the inductor.

[0033] Optionally, step S2 includes:

[0034] forming a piezoelectric layer on one side of the substrate;

[0035] An IDT and a reflection grating are formed on a side of the piezoelectric layer away from the substrate. The reflection grating is distributed on two opposite sides of the IDT to reflect energy back to the IDT.

[0036] Optionally, step S2 includes:

[0037] forming a Bragg reflection layer on one side of the substrate;

[0038] forming a first electrode on a side of the Bragg reflection layer away from the substrate;

[0039] forming a piezoelectric film on a side of the first electrode away from the Bragg reflection layer;

[0040] A second electrode is formed on a side of the piezoelectric film away from the first electrode.

[0041] Optionally, step S2 includes:

[0042] forming a sacrificial layer on one side of the substrate;

[0043] forming a seed layer on a side of the substrate where the sacrificial layer is formed, wherein the seed layer covers the sacrificial layer;

[0044] forming a first electrode on a side of the seed layer away from the sacrificial layer;

[0045] forming a piezoelectric film on a side of the first electrode away from the seed layer;

[0046] forming a second electrode on a side of the piezoelectric film away from the first electrode;

[0047] The sacrificial layer is removed to form a cavity between the seed layer and the substrate.

[0048] Optionally, the inductor has a square winding shape.

[0049] The present application also discloses a monolithic integrated circuit, which is manufactured using the monolithic integrated circuit manufacturing method as described above.

[0050] Compared with the related art, the present application integrates the MEMS resonator and the LC circuit on the same chip to form a MEMS monolithic integrated circuit, forming a multifunctional integrated chip, thereby improving performance and integration.

[0051] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0053] Figure 1 Schematic diagram of the structure of the filter in the related art.

[0054] Figure 2 This is a schematic diagram of the manufacturing process of the monolithic integrated circuit manufacturing method of the present application.

[0055] Figure 3 This is a schematic diagram of the circuit structure of an embodiment of the monolithic integrated circuit of the present application.

[0056] Figure 4 This is a schematic diagram of the circuit structure of another embodiment of the monolithic integrated circuit of the present application.

[0057] Figure 5 This is a schematic diagram of the circuit structure of another embodiment of the monolithic integrated circuit of the present application.

[0058] Figure 6 This is a schematic top view of a surface acoustic wave resonator in a monolithic integrated circuit of the present application.

[0059] Figure 7 This is a schematic diagram of the structure of the surface acoustic wave resonator in the monolithic integrated circuit of the present application.

[0060] Figure 8 It is a schematic structural diagram of a bulk acoustic wave resonator in an embodiment of a monolithic integrated circuit of the present application.

[0061] Fig. 9 It is a schematic structural diagram of a bulk acoustic wave resonator in another embodiment of the monolithic integrated circuit of the present application.

[0062] Fig.10 It is a schematic structural diagram of a bulk acoustic wave resonator in another embodiment of the monolithic integrated circuit of the present application.

[0063] Fig.11It is a schematic diagram of the structure of an inductor in an embodiment of a monolithic integrated circuit of the present application.

[0064] Fig.12 FIG. 1 is a schematic top view of an inductor in an embodiment of a monolithic integrated circuit of the present application.

[0065] Figures 13 to 16 This is a schematic structural diagram of each stage in the inductor manufacturing process in another embodiment of the monolithic integrated circuit of the present application.

[0066] Figures 17 to 20 This is a schematic diagram of the structure of each stage in the capacitor manufacturing process of the monolithic integrated circuit of this application.

[0067] Fig.21 This is a schematic diagram of the structure of a monolithic integrated circuit in an embodiment of the present application.

[0068] Explanation of reference numerals: substrate, 10; input terminal, 101; ground terminal, 102; first node, 103; second node, 104; output terminal, 105; back hole, 11; back metal structure, 12; resonator, 20; surface acoustic wave resonator, 21; piezoelectric layer, 211; interdigital transducer, 212; reflection grating, 213; first bulk acoustic wave resonator, 22; first lower electrode, 221; first piezoelectric film, 222; first upper electrode, 223; Bragg reflection layer, 224; first impedance layer, 2241; second impedance layer, 2242; second bulk acoustic wave resonator, 23; second lower electrode, 231; second piezoelectric film, 232; second upper electrode, 233; sacrificial layer, 234 ; seed layer, 235; third bulk acoustic wave resonator, 24; third lower electrode, 241; third piezoelectric film, 242; third upper electrode, 243; cavity, 244; metal layer, 245; inductor, 30; first inductor, 31; groove, 311; first inductor dielectric layer, 312; second inductor, 32; second inductor dielectric layer, 321; second inductor metal layer, 322; photoresist, 323; capacitor, 40; first capacitor metal layer, 41; dielectric layer, 42; capacitor metal inter-layer, 43; second capacitor metal layer, 44; first through hole, 45; second through hole, 46; first metal connection, 47; second metal connection, 48; insulating dielectric layer, 49; metal interconnection line, 50. DETAILED DESCRIPTION

[0069] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this specification. Instead, they are merely examples of devices and methods consistent with some aspects of this specification as detailed in the appended claims.

[0070] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in this specification should be understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar words used in this specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantitative limit, but indicate the existence of one. "Multiple" or "several" means two or more. Unless otherwise specified, words such as "front", "rear", "lower" and / or "upper" are only for the convenience of explanation and are not limited to one position or one spatial orientation. Words such as "include" or "comprise" mean that the elements or objects appearing in front of "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect.

[0071] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. The singular forms of "a", "the" and "the" used in this specification and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0072] like Figure 1 As shown, in the related art, a plurality of resonators 20 with different frequencies are generally connected in series and parallel to form a filter circuit. The construction of such a filter circuit has extremely strict requirements on the thickness and uniformity of the film, resulting in a complex manufacturing process, low product yield and high manufacturing cost.

[0073] like Figure 2 To solve the above problems, the present application provides a method for manufacturing a monolithic integrated circuit, which comprises:

[0074] S1: providing a substrate 10;

[0075] S2: forming a resonator 20 on the substrate 10;

[0076] S3: forming a capacitor 40 on the substrate 10; and / or forming an inductor 30 on the substrate 10;

[0077] S4: Fabricate metal interconnection lines 50 on the substrate 10 to connect the capacitor 40 and / or the inductor 30 to the resonator 20.

[0078] In order to solve the above technical problems, the present application further provides a monolithic integrated circuit, which is manufactured using the above monolithic integrated circuit manufacturing method.

[0079] The present application integrates the resonator and the LC circuit on the same chip to form a MEMS monolithic integrated circuit, forming a multifunctional integrated chip, thereby improving performance and integration.

[0080] The following will describe in detail various embodiments of the present application that are consistent with the above-mentioned creative concepts.

[0081] like Figure 3 As shown, in an optional embodiment, the monolithic integrated circuit of the present application includes an input terminal 101, a ground terminal 102, a first node 103, a second node 104, and an output terminal 105. An inductor 30 and a capacitor 40 are arranged in parallel between the first node 103 and the ground terminal 102. A resonator 20 and an inductor 30 are arranged in parallel between the first node 103 and the second node 104. An inductor 30 and a capacitor 40 are arranged in parallel between the second node 104 and the ground terminal 102.

[0082] like Figure 4 As shown, in an optional embodiment, the monolithic integrated circuit of the present application includes an input terminal 101, a ground terminal 102, a first node 103, a second node 104 and an output terminal 105. An inductor 30 and a capacitor 40 are arranged in parallel between the first node 103 and the ground terminal 102. A resonator 20 and an inductor 30 are arranged in parallel between the first node 103 and the second node 104. An inductor 30 and a capacitor 40 are arranged in parallel between the second node 104 and the ground terminal 102. A capacitor 40 is arranged between the input terminal 101 and the first node 103. A capacitor 40 is arranged between the second node 104 and the output terminal 105.

[0083] like Figure 5 As shown, in an optional embodiment, the monolithic integrated circuit of the present application includes an input terminal 101, a ground terminal 102, a first node 103, a second node 104 and an output terminal 105. An inductor 30 and a capacitor 40 are arranged in parallel between the first node 103 and the ground terminal 102. A resonator 20 and an inductor 30 are arranged in parallel between the first node 103 and the second node 104. An inductor 30 and a capacitor 40 are arranged in parallel between the second node 104 and the ground terminal 102. An inductor 30 is arranged between the input terminal 101 and the first node 103. An inductor 30 is arranged between the second node 104 and the output terminal 105.

[0084] The monolithic integrated circuits of the above three embodiments have a bandpass filter function, which is used to provide the required filter bandwidth to meet the requirements of 5G and future communications for large bandwidth and high transmission speed. The resonator 20 in the above three embodiments can be a bulk acoustic wave resonator, a surface acoustic wave resonator or a Lamb wave resonator, etc. The circuits shown in the figure are just three examples, not any restrictions on circuit design. Regardless of how the circuit design changes, the manufacturing process is the same and is within the scope of protection of this application. The number and position of the resonators, capacitors and inductors in the above embodiments do not constitute a limitation on this application. The number and position of the resonators, capacitors and inductors in the circuit can be freely set in a reasonable manner.

[0085] The substrate 10 provided in step S1 may be a silicon substrate, a silicon carbide substrate, a sapphire substrate or a glass substrate, etc. The size of the substrate 10 is 2-6 inches. For a silicon substrate, including an insulator silicon (SOI) substrate, the substrate 10 may be 4-12 inches. In an optional embodiment, the substrate 10 of the present application is a large-sized silicon wafer. Using a silicon wafer as a substrate can facilitate compatibility with CMOS (Complementary Metal Oxide Semiconductor) processes and manufacturing technologies.

[0086] Step S2 may form a MEMS resonator 20 , and the formed resonator may be a bulk acoustic wave resonator, a surface acoustic wave resonator, or a Lamb wave resonator.

[0087] like Figure 6 and Figure 7 As shown, in an optional embodiment, step S2 includes forming a surface acoustic wave resonator 21. It includes first forming a piezoelectric layer 211 on the surface of the substrate 10, and the piezoelectric layer 211 can be polycrystalline or single crystal, and can be doped or undoped. An interdigital transducer 212 is formed on the side of the piezoelectric layer 211 away from the substrate 10, and the interdigital transducer 212 can realize the conversion between mechanical energy and electrical energy. A reflection grating 213 is provided along the direction of propagation of the sound wave in the interdigital transducer 212, and a pair of reflection gratings 213 are distributed on opposite sides of the interdigital transducer 212. The reflection grating 213 can reflect energy back to the interdigital transducer 212, which can effectively reduce energy loss.

[0088] like Figure 8As shown, in an optional embodiment, step S2 includes forming a first bulk acoustic wave resonator 22. It includes first forming a Bragg reflection layer 224 on the surface of the substrate 10. The Bragg reflection layer 224 includes a plurality of first impedance layers 2241 and second impedance layers 2242 arranged at intervals. The thickness of the first impedance layer 2241 and the second impedance layer 2242 is 1 / 4 of the wavelength of the sound wave, so that most of the reflected waves will be superimposed on the original waves, thereby improving the reflection effect of the reflection layer. The first impedance layer 2241 and the second impedance layer 2242 have different impedances to the sound wave. Optionally, the first impedance layer 2241 has a larger acoustic wave impedance, and the second impedance layer 2242 has a smaller acoustic wave impedance, or the first impedance layer 2241 has a smaller acoustic wave impedance, and the second impedance layer 2242 has a larger acoustic wave impedance. Then, a first lower electrode 221 is formed on the side of the Bragg reflection layer 224 away from the substrate 10. Then, a first piezoelectric film 222 is formed on the side of the first lower electrode 221 away from the Bragg reflection layer 224. Finally, a first upper electrode 223 is formed on a side of the first piezoelectric film 222 away from the first lower electrode 221. The Bragg reflection layer 224 can reflect the sound waves into the first piezoelectric film 222, and the sound waves form standing waves in the first piezoelectric film 222, which can effectively reduce the loss and improve the effect.

[0089] like Fig. 9 As shown, in an optional embodiment, step S2 includes forming a second bulk acoustic wave resonator 23. It includes first forming a sacrificial layer 234 on the surface of the substrate 10, and then forming a seed layer 235 on the side of the sacrificial layer 234 away from the substrate 10. Then, a second lower electrode 231 is formed on the side of the seed layer 235 away from the sacrificial layer 234. After that, a second piezoelectric film 232 is formed on the side of the second lower electrode 231 away from the seed layer 235. Then, a second upper electrode 233 is formed on the side of the second piezoelectric film 232 away from the second lower electrode 231. Finally, the sacrificial layer 234 is removed, and a cavity is formed between the seed layer 235 and the substrate. The outer sides of the two electrodes of the second bulk acoustic wave resonator 23 are cavity structures. The acoustic wave impedance of the air in the cavity structure is much lower than the acoustic wave impedance of the second piezoelectric film 232. Most of the sound waves will bounce back to the second piezoelectric film 232, effectively reducing energy loss.

[0090] like Fig.10As shown, in an optional embodiment, step S2 includes forming a third bulk acoustic wave resonator 24. It includes first forming a third piezoelectric film 242 on the surface of the substrate 10. Then, a third upper electrode 243 is formed on the side of the third piezoelectric film 242 away from the substrate 10. Then, the side of the substrate 10 away from the third piezoelectric film 242 is etched until the third piezoelectric film 242 is etched to form a cavity 244. The projection of the cavity 244 in the first direction falls within the projection of the third piezoelectric film 242 in the first direction. The first direction in this embodiment refers to the direction perpendicular to the plane of the substrate 10. The cavity 244 connects the side of the third piezoelectric film 242 close to the substrate 10 and the side of the substrate 10 away from the third piezoelectric film 242. A third lower electrode 241 is formed in the cavity 244. The third lower electrode 241 is located on the side of the third piezoelectric film 242 away from the third upper electrode 243 and is in contact with the third piezoelectric film 242. The outer sides of the two electrodes of the third BAW resonator 24 are cavity structures. The acoustic impedance of the air in the cavity structure is much lower than the acoustic impedance of the third piezoelectric film 242 . Most of the sound waves will bounce back to the third piezoelectric film 242 , effectively reducing energy loss.

[0091] Optionally, a metal layer 245 is formed in the cavity 244 , and the metal layer 245 realizes electrical connection between the third lower electrode 241 and a side of the substrate 10 facing away from the third piezoelectric film 242 .

[0092] like Fig.11 and Fig.12 As shown, in an optional embodiment, step S3 includes forming a first inductor 31. It includes:

[0093] T1: defining the topography of the first inductor 31 on the substrate 10 by photolithography technology.

[0094] The design shape of the first inductor 31 can be a square winding shape, a circular winding shape, or other winding shapes designed according to requirements. The material of the first inductor 31 can be gold, aluminum, copper, iron, nickel, or other alloy materials. The thickness, width, number of turns, and spacing between turns of the first inductor 31 are determined by design and application.

[0095] T2: depositing a polymer film 314 in the groove 311 formed by the photolithography technology.

[0096] The polymer film 314 is used as a passivation film in the silicon etching step to prevent the sidewalls of the groove 311 from being etched. 4 F 8 Gas is used as deposition gas. C 4 F 8It is a cyclic molecule. In plasma, its ring breaks into short-chain molecules. The active part of the short-chain molecule combines with other molecules, the chain length increases, and it is attached to the silicon substrate to form a polymer film 314. Other methods can also be used to form the polymer film 314 according to actual needs.

[0097] T3: etching the polymer film 314 along the first direction.

[0098] The polymer film 314 at the bottom of the groove 311 is selectively etched. Optionally, the etching gas is SF 6 Gas, or other gases that can be used for etching. During etching, a certain bias voltage is applied to complete the etching of the bottom film.

[0099] T4: etching the substrate 10 along the first direction.

[0100] Since the sidewall of the groove 311 is protected by the polymer film 314, only the silicon substrate at the bottom of the groove 311 is etched during the etching process of the substrate 10, and the substrate 10 is etched along the first direction.

[0101] During the etching process, the step T2, the step T3 and the step T4 need to be repeated multiple times to achieve directional deep silicon etching.

[0102] T5: forming a seed layer in the groove 311 formed by deep silicon etching.

[0103] Prepare a titanium copper target, mix titanium and copper in appropriate proportions as required, and prepare it into a target form. Sputtering deposition, place the titanium copper target in a sputtering device, add appropriate process gas, and sputter under high vacuum conditions. Use arc discharge, magnetron sputtering and other methods to release the titanium copper material on the surface of the target and deposit it into the groove 311 to form a titanium copper seed layer. The thickness of titanium is 50A-200A, and the thickness of copper is 300A-5000A.

[0104] T6: Filling the groove 311 formed by deep silicon etching with metal to form the inductor.

[0105] Metal is filled into the groove 311 by an electroplating process, and optionally, the electroplated metal is copper. Then, the surface of the substrate 10 is flattened by a CMP (Chemical Mechanical Polishing) process to remove excess metal. A first inductor dielectric layer 312 is formed on the substrate 10, and the first inductor dielectric layer 312 covers the inductor 30 and exposes two electrodes of the inductor 30.

[0106] like Figures 12 to 16 As shown, in an optional embodiment, step S3 includes forming a second inductor 32 .

[0107] The design shape of the second inductor 32 can be a square winding shape, or a circular winding shape, or other winding shapes designed according to requirements. The material of the second inductor 32 can be gold, aluminum, copper, iron, nickel, or other alloy materials. The thickness, width, number of turns, and spacing between turns of the second inductor 32 are determined by design and application.

[0108] The second inductor 32 is formed by first forming a second inductor dielectric layer 321 on one side of the substrate 10. Then forming a second inductor metal layer 322 on the side of the second inductor dielectric layer 321 away from the substrate 10. The second inductor metal layer 322 can be formed by vacuum evaporation or sputtering deposition. Then, a photoresist 323 is coated on the side of the second inductor metal layer 322 away from the second inductor dielectric layer 321. Then, the photoresist 323 is exposed and developed to form a preset morphology of the second inductor 32. Then, the second inductor metal layer 322 is etched to make the second inductor metal layer 322 into an inductor with a specific morphology. Finally, the photoresist 323 is removed and cleaned to obtain the second inductor 32.

[0109] like Figures 17 to 20 As shown, in an optional embodiment, step S3 includes forming a capacitor 40 .

[0110] The method includes first forming an insulating dielectric layer 49 on one side of a substrate 10, and forming a first capacitor metal layer 41 on a side of the insulating dielectric layer 49 away from the substrate 10. Then, a dielectric layer 42 is formed on a side of the insulating dielectric layer 49 close to the first capacitor metal layer 41 and a side of the first capacitor metal layer 41 away from the insulating dielectric layer 49. The dielectric layer 42 is provided with a first through hole 45. The projection of the first through hole 45 in the first direction falls into the first capacitor metal layer 41, and the first through hole 45 connects the first capacitor metal layer 41 with a side of the dielectric layer 42 away from the first capacitor metal layer 41.

[0111] A capacitor metal interlayer dielectric layer 43 is formed on a side of the dielectric layer 42 away from the first capacitor metal layer 41. The capacitor metal interlayer dielectric layer 43 continues the first through hole 45 structure of the dielectric layer 42. The capacitor metal interlayer dielectric layer 43 is provided with a second through hole 46. The projection of the second through hole 46 in the first direction falls into the first capacitor metal layer 41, and the projection of the second through hole 46 in the first direction has no overlapping area with the projection of the first through hole 45 in the first direction. The second through hole 46 connects the dielectric layer 42 with the side of the capacitor metal interlayer dielectric layer 43 away from the dielectric layer 42.

[0112] A second capacitor metal layer 44 is formed in the second through hole 46, and the second capacitor metal layer 44 covers the second through hole 46. A first metal connection 47 and a second metal connection 48 are made. The first metal connection 47 is electrically connected to the first capacitor metal layer 41 through the first through hole 45 and the second through hole 46, and the second metal connection 48 is connected to the second capacitor metal layer 44 through the second through hole 46.

[0113] The capacitor 40 can be a square capacitor, or a rectangular or other shaped capacitor, and the size of the capacitor 40 can be designed according to actual needs. The material of the metal layer can be metal materials such as gold, aluminum, copper, or other alloy materials. The metal layer can be made by etching or metal stripping. The material of the dielectric layer 42 can be silicon nitride, silicon oxide, or other dielectric materials, such as hafnium silicate, zirconium silicate, hafnium dioxide or zirconium dioxide with high dielectric constant. The use of materials with high dielectric constant can further improve the capacitance density and reduce the area of ​​the capacitor. The material of the capacitor metal interlayer 43 can be polyimide resin or benzocyclobutene material, or it can be materials such as silicon nitride or silicon oxide. The thickness of the dielectric layer and the metal layer is determined by the specific application and design.

[0114] Step S2 may be performed before step S3, or after step S3, or simultaneously with step S3. For example, the dielectric layer or metal layer in the manufacturing process of the resonator 20, the inductor 30, and the capacitor 40 may be manufactured simultaneously or successively.

[0115] like Fig.21 As shown, in an optional embodiment, step S4 further includes performing a thinning process and a backside process on the substrate 10 .

[0116] It includes a bonding process: bonding the substrate 10 of the front process devices such as the resonator 20, the inductor 30 and the capacitor 40 to a carrier, and the carrier can be a sapphire carrier or a carrier of other materials. Apply bonding glue on the surface of the device wafer or the surface of the sapphire carrier. After the bonding glue is applied, the wafer or the carrier is placed in a baking oven for baking. After the bonding glue is cured, the substrate 10 and the carrier are bonded. Bonding can be achieved in different ways, and can be achieved by hot pressing bonding or ultrasonic bonding.

[0117] Thinning process: A thinning process is performed on a side of the substrate 10 away from the resonator to reduce the thickness of the substrate 10 to 50 μm-150 μm.

[0118] Photolithography process: The positions of a plurality of back holes 11 are located and the opening sizes of the back holes 11 are defined on a side of the substrate 10 away from the resonator 20 through the photolithography process. The projection of the back holes 11 in the first direction has an overlapping area with the metal electrode of the resonator 20 or the capacitor 40 or the inductor 30.

[0119] Back hole etching process: deep silicon etching is performed on the positions of the located back holes 11 to form the back holes 11 , and the back holes 11 connect the metal electrodes of the resonator 20 or the capacitor 40 or the inductor 30 with the side of the substrate 10 away from the resonator 20 .

[0120] Back metallization: a back metal structure 12 is formed on a side of the substrate 10 away from the resonator 20 and in the back hole 11 . The back metal structure 12 is connected to metal electrodes of the resonator 20 and / or the capacitor 40 and / or the inductor 30 .

[0121] Scribe groove etching: The metal at the scribe groove position is removed through steps such as photolithography, etching, degumming and cleaning to facilitate subsequent steps such as wafer cutting.

[0122] Debonding: Separate the substrate 10 from the carrier and clean the substrate 10 to remove the bonding glue and other residues.

[0123] This application integrates the MEMS resonator and the LC circuit composed of inductors and capacitors on the same chip to improve device integration, communication bandwidth, and system efficiency. At the same time, the chip area is reduced and the cost is reduced. In the process of manufacturing the MEMS device monolithic integrated circuit, the deep silicon etching and metallization process are used to improve the Q value of the inductor. At the same time, the back hole etching and back metallization process are used to improve the performance of the integrated circuit. The product of this application can use large-sized silicon wafers, which is conducive to large-scale production and reduces costs.

[0124] Those skilled in the art will readily appreciate other embodiments of the specification after considering the specification and practicing the invention claimed herein. The specification is intended to cover any variations, uses or adaptations of the specification that follow the general principles of the specification and include common knowledge or customary techniques in the art that are not claimed in the specification. The specification and examples are to be considered exemplary only, and the true scope and spirit of the specification are indicated by the following claims.

[0125] It should be understood that the present description is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.

[0126] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A method for manufacturing a monolithic integrated circuit, characterized in that: include: S1: providing a substrate; S2: forming a resonator on the substrate; S3: forming a capacitor on the substrate; and / or forming an inductor on the substrate; S4: manufacturing metal interconnection lines on the substrate to connect the capacitor and / or the inductor to the resonator; The step S2 comprises: forming a piezoelectric film on one side of the substrate; forming a second electrode on a side of the piezoelectric film away from the substrate; Etching is performed on a side of the substrate away from the piezoelectric film to form a cavity, the projection of the cavity in the first direction falls within the projection of the piezoelectric film in the first direction, and the cavity connects the piezoelectric film and the side of the substrate away from the piezoelectric film; forming a first electrode in the cavity, wherein the first electrode is located on a side of the piezoelectric film away from the second electrode and is bonded to the piezoelectric film; forming a metal layer in the cavity, wherein the metal layer realizes electrical connection between the first electrode and a side of the substrate facing away from the piezoelectric film; The step S4 further comprises: Positioning a plurality of back holes and defining the opening sizes of the back holes on a side of the substrate away from the resonator by a photolithography process, wherein the projection of the back holes in a first direction has an overlapping area with a metal electrode of the resonator or the capacitor or the inductor; Performing deep silicon etching on the positions of the located back holes to form the back holes, wherein the back holes connect the metal electrodes of the resonator or the capacitor or the inductor with a side of the substrate away from the resonator; A back metal structure is formed on a side of the substrate away from the resonator and in the back hole, and the back metal structure is connected to metal electrodes of the resonator and / or the capacitor and / or the inductor.

2. The method for manufacturing a monolithic integrated circuit according to claim 1, characterized in that: The step S2 is performed before the step S3, or the step S2 is performed after the step S3, or the step S2 and the step S3 are performed simultaneously.

3. The method for manufacturing a monolithic integrated circuit according to claim 1, characterized in that: The substrate is a wafer.

4. The method for manufacturing a monolithic integrated circuit according to claim 3, characterized in that: The step S3 comprises: T1: defining the morphology of the inductor on the substrate by photolithography technology; T2: Deposition of polymer film in the grooves formed by photolithography; T3: etching the polymer film along a first direction; T4: etching the substrate along the first direction; Repeating the step T2, the step T3 and the step T4 multiple times to achieve deep silicon etching; T5: forming a seed layer in the groove formed by deep silicon etching; T6: Filling the groove formed by deep silicon etching with metal to form the inductor.

5. The method for manufacturing a monolithic integrated circuit according to claim 3, characterized in that: The step S4 further comprises: Bonding the side of the substrate close to the resonator to a carrier; A thinning process is performed on a side of the substrate away from the resonator to reduce the thickness of the substrate to 50 μm-150 μm.

6. The method for manufacturing a monolithic integrated circuit according to claim 4, characterized in that: The inductor has a square winding shape.

7. A monolithic integrated circuit, characterized in that: The monolithic integrated circuit is manufactured using the method for manufacturing a monolithic integrated circuit as described in any one of claims 1-6.

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