Transistor configuration for vertical memory array

Abstract

This application is directed to transistor configurations for vertical memory arrays. A memory device can implement a multi-transistor architecture, such as a dual transistor architecture, which can operate to couple a pillar with a bit line. For example, a memory device can include a conductive pillar that extends through a hierarchy of layers of a memory array. The pillar can be coupled with a first bit line via a first transistor and a second bit line via a second transistor. To access a memory cell coupled with the pillar, the memory device can bias a word line coupled with the memory cell to a first access voltage, bias one of the bit lines to a second access voltage, activate one of the transistors to couple the pillar with the one of the bit lines, and deactivate the other transistor to isolate the pillar from the other of the bit lines.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 823,371, filed August 30, 2022, entitled "Transistor Configurations for Vertical Memory Arrays," and U.S. Provisional Patent Application No. 63 / 365,683, filed June 1, 2022, entitled "Transistor Configurations for Vertical Memory Arrays," each of which is assigned to the assignee, and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] This technical field relates to transistor configurations for vertical memory arrays. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, typically indicated by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any one of which can be stored. To access the stored information, components can read (e.g., sense, detect, retrieve, identify, determine, evaluate) the stored states in the memory device. To store information, components can write (e.g., program, set, assign) states into the memory device.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, chalcogenide memory technology, etc. Memory cells can be described in terms of volatile or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain their stored logic state for a long period of time even without an external power supply. Memory cells configured in a volatile configuration lose their stored state when disconnected from an external power supply. Summary of the Invention

[0006] An apparatus is described. The apparatus may include: a conductive pillar extending through multiple layers of a memory array, wherein at each of the multiple layers, one or more memory cells of the memory array are coupled between the conductive pillar and a corresponding word line; a first transistor operable to couple the conductive pillar to a first bit line at least partially based on a first voltage at the gate of the first transistor; and a second transistor operable to couple the conductive pillar to a second bit line at least partially based on a second voltage at the gate of the second transistor.

[0007] A method is described. The method may include: accessing a memory cell coupled between a conductive pillar of a memory die and a word line of the memory die, accessing the memory cell including: coupling the conductive pillar to the first bit line at least partially based on activating a first transistor between the conductive pillar and the first bit line; isolating the conductive pillar from a second bit line at least partially based on deactivating a second transistor between the conductive pillar and the second bit line; biasing the word line with a first access voltage; and biasing the first bit line with a second access voltage.

[0008] A device is described. The device may include: a conductive pillar; a word line; a memory cell coupled between the conductive pillar and the word line; a first transistor having a first channel portion coupled between the conductive pillar and the first bit line; a second transistor having a second channel portion coupled between the conductive pillar and the second bit line; and a controller for performing an access operation on the memory cell, the controller being operable to cause the device to: couple the conductive pillar to the first bit line at least partially based on activating the first channel portion; isolate the conductive pillar from the second bit line at least partially based on deactivating the second channel portion; bias the word line with a first access voltage; and bias the first bit line with a second access voltage. Attached Figure Description

[0009] Figure 1 Examples of memory arrays supporting transistor configurations for vertical memory arrays are shown, based on examples disclosed herein.

[0010] Figure 2 A top view is shown of an example of a memory array that supports a transistor configuration for a vertical memory array, according to examples disclosed herein.

[0011] Figure 3A and 3B A side view of an example of a memory array that supports a transistor configuration for a vertical memory array, according to examples disclosed herein.

[0012] Figure 4 ,5 Figures 6 and 7 illustrate examples of layouts supporting transistor configurations for vertical memory arrays, based on examples disclosed herein.

[0013] Figure 7 A block diagram is shown of a memory system supporting transistor configurations for vertical memory arrays, based on examples disclosed herein.

[0014] Figure 8 Flowcharts illustrating one or more methods for supporting transistor configurations for vertical memory arrays, based on examples disclosed herein. Detailed Implementation

[0015] In some memory architectures, a memory device may include a memory array arranged in a vertical architecture, such as a three-dimensional architecture, comprising memory cells arranged according to different levels (e.g., layers, stacks, planes, hierarchies). In some such architectures, memory cells may be coupled to word lines and conductive pillars extending through the levels of the memory array (e.g., physically coupled between them, electrically coupled between them, or both). To access a memory cell, the memory device may include circuitry configured to bias the word lines and conductive pillars to corresponding voltages such that a bias is applied across the memory cell. Logic state may be written to a memory cell based on current (e.g., current magnitude, current direction) driven through the memory cell due to the bias applied across the memory cell. Logic state may be read from a memory cell based on or in response to current (e.g., current presence, current absence, current magnitude) flowing through the memory cell based on the bias applied across the memory cell.

[0016] To bias conductive pillars according to access operations of selected memory cells, a memory device can be configured to couple conductive pillars (e.g., a first conductive pillar, a pillar coupled to the selected memory cell) to a bit line while isolating other conductive pillars (e.g., one or more second conductive pillars) from the bit line. This prevents or reduces biasing across unselected memory cells. For example, the memory device can activate a first transistor between the first conductive pillar and the bit line to couple the conductive pillar to the bit line, thereby biasing the conductive pillar with the voltage of the bit line. The memory device can deactivate a second transistor between the second conductive pillar and the bit line to decouple the second conductive pillar from the bit line. In some cases, the memory device can deactivate the second transistor by biasing its gate to a negative voltage, which can result in a relatively large voltage difference across the second transistor (e.g., gate-to-source differential, drain-to-source differential). For example, if the bit line is biased to a positive voltage +V according to an access operation and the gate of the second transistor is biased to a negative voltage -V, a voltage difference of 2V can be generated across the second transistor. In some cases, such a voltage difference can be associated with leakage at the second transistor (e.g., charge leakage, current leakage, leakage between circuit elements intended to be isolated from each other), which can interrupt the access operation (e.g., change the voltage of the bit line or the current along the bit line, which can increase the delay of the access operation or cause the access operation to fail), increase power consumption, or both.

[0017] According to examples disclosed herein, memory devices can implement multi-transistor architectures, such as dual-transistor architectures, operable to couple a given conductive pillar to a set (e.g., a pair, one, or more) bit lines. This reduces voltage differentials across the respective transistors, thereby reducing leakage. For example, a memory device may include conductive pillars that are coupled to a first bit line via a first transistor and to a second bit line via a second transistor. In some examples, to bias the conductive pillars with a positive voltage (e.g., +V), the memory device may be configured to bias the first bit line to +V, activate the first transistor to couple the conductive pillar to the first bit line, and deactivate the second transistor to isolate the conductive pillar from the second bit line. In some examples, to bias the conductive pillars with a negative voltage (e.g., -V), the memory device may be configured to bias the second bit line to -V, activate the second transistor to couple the conductive pillar to the second bit line, and deactivate the first transistor to isolate the conductive pillar from the first bit line. By using different bit lines to positively and negatively bias the conductive pillars, the voltage difference across the deactivated transistor can be reduced, thereby reducing leakage associated with the deactivated transistor. For example, the bit lines and the corresponding gates of the deactivated transistor can be biased such that, during access operations, the corresponding voltage difference across the deactivated transistor can have a value between 0 and V (e.g., a potential value of 2V that could occur in a single-transistor implementation). Therefore, by implementing a multi-transistor architecture, such as a dual-transistor architecture, to bias the conductive pillars of the memory device according to the examples disclosed herein, the memory device can be implemented with reduced leakage from the deactivated transistor, which can support reduced power consumption, increased access operation accuracy, or any combination thereof, and other benefits.

[0018] Firstly, in reference Figure 1 , 2 Features of this disclosure are described in the context of memory devices and arrays of types 3A and 3B. (See references...) Figure 4-6 The features of this disclosure are described in the context of the example layout. References refer to, for example, references to, [references to, and] Figure 7 and 8 The device diagrams and flowcharts describing the transistor configuration for vertical memory arrays further illustrate and describe these and other features of this disclosure.

[0019] Figure 1Examples of memory devices 100 supporting transistor configurations for vertical memory arrays, as disclosed herein, are shown. In some examples, memory device 100 may be referred to as or comprise a memory die, memory chip, or electronic memory device. Memory device 100 may be operable to provide a location for storing information (e.g., a physical memory address) that is available for use by a system (e.g., for a host device coupled to memory device 100 to write or read information).

[0020] The memory device 100 may include one or more memory cells 105, each of which may be programmable to store different logical states (e.g., programmed to be one of a set of two or more possible states). For example, the memory cell 105 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, the memory cell 105 (e.g., a multi-level memory cell 105) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, the memory cells 105 may be arranged in an array.

[0021] Memory cell 105 may use configurable materials to store logical states. These configurable materials may be referred to as memory elements, storage elements, memory storage elements, material elements, material memory elements, material portions, or material portions with write polarity, etc. The configurable material of memory cell 105 may refer to chalcogenide-based storage components. For example, chalcogenide storage elements may be used in phase-change memory cells, threshold processing memory cells, or self-selecting memory cells, as well as other architectures.

[0022] In some instances, the material of memory cell 105 may comprise chalcogenide materials or other alloys, including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some instances, chalcogenide materials primarily comprising selenium (Se), arsenic (As), and germanium (Ge) may be referred to as SAG alloys. In some instances, SAG alloys may also comprise silicon (Si), and such chalcogenide materials may be referred to as SiSAG alloys. In some instances, SAG alloys may comprise silicon (Si) or indium (In), or combinations thereof, and such chalcogenide materials may be accordingly referred to as SiSAG alloys or InSAG alloys, or combinations thereof. In some instances, the chalcogenide material may comprise additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

[0023] In some instances, memory cell 105 may be an example of a phase-change memory cell. In such instances, the material used in memory cell 105 may be based on an alloy (e.g., the alloys listed above) and operable to change to a different physical state (e.g., undergo a phase transition) during normal operation of memory cell 105. For example, phase-change memory cell 105 may be associated with a relatively disordered atomic configuration (e.g., a relatively amorphous state) and a relatively ordered atomic configuration (e.g., a relatively crystalline state). The relatively disordered atomic configuration may correspond to a first logic state (e.g., a reset state, logic 0), and the relatively ordered atomic configuration may correspond to a second logic state (e.g., a logic state different from the first logic state, a set state, logic 1).

[0024] In some instances (e.g., for threshold processing memory cell 105, for auto-select memory cell 105), some or all of the set of logic states supported by memory cell 105 may be associated with a relatively disordered atomic configuration of a chalcogenide material (e.g., amorphous materials may be operable to store different logic states). In some instances, the storage elements of memory cell 105 may be instances of auto-select memory elements. In such instances, the material used in memory cell 105 may be based on an alloy (e.g., alloys listed above) and operable to undergo changes in different physical states during normal operation of memory cell 105. For example, auto-select or threshold processing memory cell 105 may have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state may correspond to a first logic state (e.g., a reset state, logic 0), and the low threshold voltage state may correspond to a second logic state (e.g., a logic state different from the first logic state, a set state, logic 1).

[0025] During a write operation (e.g., a programming operation) of the self-selected or threshold-processed memory cell 105, the polarity of the write operation can affect (e.g., determine, set, program) the behavior or characteristics of the material of the memory cell 105, such as the threshold processing characteristics of the material (e.g., threshold voltage). For different logic states stored by the material of the memory cell 105, the differences between the threshold processing characteristics of the material of the memory cell 105 (e.g., the difference between the threshold voltages when the material is storing logic state '0' versus logic state '1') can correspond to the read window of the memory cell 105.

[0026] Memory device 100 may include access lines arranged in a pattern such as a grid pattern (e.g., row lines 115 each extending along an illustrative x-direction, and column lines 125 each extending along an illustrative y-direction). The access lines may be formed of one or more conductive materials. In some instances, a row line 115 or a portion thereof may be referred to as a word line. In some instances, a column line 125 or a portion thereof may be referred to as a number line or bit line. References to access lines or the like may be interchanged without loss of understanding. Memory cells 105 may be located at the intersection of access lines, such as row lines 115 and column lines 125. In some instances, memory cells 105 may also be arranged (e.g., addressed) along an illustrative z-direction, for example in embodiments where the collection of memory cells 105 is located at different levels (e.g., layers, stacks, planes, hierarchies) along the illustrative z-direction. In some instances, the memory device 100, which includes memory cells 105 at different levels, may be supported by access lines, decoders, and other supporting circuitry systems with different configurations than those shown.

[0027] Operations, such as read and write operations, can be performed on memory cell 105 by activating access lines (e.g., one or more of row lines 115 or column lines 125) and other access lines associated with alternative configurations. For example, memory cell 105 can be accessed based on its intersection by activating row lines 115 and column lines 125 (e.g., applying voltage to row lines 115 or column lines 125). The intersection of row lines 115 and column lines 125 and other access lines in various two-dimensional or three-dimensional configurations may be referred to as the address of memory cell 105. In some instances, access lines may be conductive lines coupled to memory cell 105 and can be used to perform access operations on memory cell 105. In some instances, memory device 100 may perform operations in response to commands, which may be issued by a host device coupled to memory device 100 or generated by memory device 100 (e.g., by local memory controller 150).

[0028] The access memory unit 105 can be controlled by one or more decoders, such as row decoder 110 or column decoder 120, and other examples. For instance, row decoder 110 can receive row addresses from local memory controller 150 and activate row line 115 based on the received row addresses. Column decoder 120 can receive column addresses from local memory controller 150 and activate column line 125 based on the received column addresses.

[0029] Sensing component 130 may be operable to detect the state of memory cell 105 (e.g., material state, resistance state, threshold state) and determine the logic state of memory cell 105 based on the detected state. Sensing component 130 may include one or more sensing amplifiers to convert (e.g., amplify) signals generated by accessing memory cell 105 (e.g., signals from column line 125 or other access lines). Sensing component 130 may compare the signals detected from memory cell 105 with reference 135 (e.g., reference voltage, reference charge, reference current). The detected logic state of memory cell 105 may be provided as an output of sensing component 130 (e.g., to input / output component 140) and may indicate the detected logic state to another component of memory device 100 or to a host device coupled to memory device 100.

[0030] The local memory controller 150 can control access to memory cells 105 through various components (e.g., row decoder 110, column decoder 120, sensing component 130, and other components). In some instances, one or more of the row decoder 110, column decoder 120, and sensing component 130 may co-address with the local memory controller 150. The local memory controller 150 may be operable to receive information (e.g., commands, data) from one or more different controllers (e.g., an external memory controller associated with a host device, another controller associated with memory device 100), translate the information into signaling usable by memory device 100, perform one or more operations on memory cells 105, and transmit data from memory device 100 to a host device based on the performance of one or more operations. The local memory controller 150 may generate row address signals and column address signals to activate access lines, such as target row line 115 and target column line 125. The local memory controller 150 may also generate and control various signals (e.g., voltage, current) used during operation of the memory device 100. Generally, the amplitude, shape, or duration of the applied signals discussed herein may vary and may differ for the various operations discussed when operating the memory device 100.

[0031] The local memory controller 150 may be operable to perform one or more access operations on one or more memory cells 105 of the memory device 100. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed by the local memory controller 150 in response to an access command (e.g., from a host device) or otherwise coordinated. The local memory controller 150 may be operable to perform other access operations not listed herein or other operations related to the operation of the memory device 100 but not directly related to accessing the memory cells 105.

[0032] In some instances of the memory device 100, memory cells 105 may be arranged in a three-dimensional architecture according to different levels (e.g., along the illustrative z-direction). In some such architectures, memory cells 105 may be coupled between access lines and conductive pillars extending through the hierarchy of memory cells 105. For accessing memory cells 105, circuitry (e.g., row decoder 110, column decoder 120, or another type of decoder) may be configured to bias the access lines and conductive pillars to corresponding voltages, such that a bias is applied across memory cells 105. Logic states may be written to memory cells 105 based on currents (e.g., current magnitude, current direction) driven through memory cells 105 due to the bias applied across memory cells 105. Logic states may be read from memory cells 105 based on or in response to currents (e.g., current presence, current absence, current magnitude) flowing through memory cells 105 based on the bias applied across memory cells 105.

[0033] According to examples disclosed herein, memory device 100 may implement a multi-transistor architecture, such as a dual-transistor architecture, to couple conductive pillars to corresponding access lines (e.g., each access line is associated with a different voltage polarity), which reduces voltage differences across the transistors associated with leakage. For example, memory device 100 may include conductive pillars coupled to a first access line (e.g., associated with a positive voltage) via a first transistor and to a second access line (e.g., associated with a negative voltage) via a second transistor. By using different access lines to positively and negatively bias the conductive pillars via different transistors, voltage differences across the deactivated transistors can be reduced, thereby reducing leakage (e.g., associated with the deactivated transistors). Therefore, by implementing a multi-transistor architecture, such as a dual-transistor architecture, to bias the conductive pillars of memory device 100 according to examples disclosed herein, memory device 100 may support reduced power consumption, increased access operation accuracy, or any combination thereof, and other benefits compared to some single-transistor architectures.

[0034] Memory device 100 may include any number of non-transitory computer-readable media supporting transistor configurations for a vertical memory array. For example, local memory controller 150, row decoder 110, column decoder 120, sensing component 130, or input / output component 140, or any combination thereof, may include or access one or more non-transitory computer-readable media containing storage instructions (e.g., firmware) for performing the functions attributed herein to memory device 100. For example, if executed by memory device 100, such instructions may cause memory device 100 to perform one or more associated functions as described herein.

[0035] Figure 2 , 3A Figures 3B and 3B illustrate an example of a memory array 200 supporting a transistor configuration for a vertical memory array, according to examples disclosed herein. The memory array 200 may be included in a memory device 100, and an example of a three-dimensional arrangement of memory cells 105 accessible by various conductive structures (e.g., access lines) is shown. Figure 2 The memory array 200 is shown relative to, for example Figure 3A and 3B The top section view of the cutting plane AA shown in the figure (e.g., section AA). Figure 3A The memory array 200 is shown relative to, for example Figure 2 The side section view of the cutting plane BB shown in the figure (e.g., section BB). Figure 3B The memory array 200 is shown relative to, for example Figure 2 The image shows a side cross-sectional view of the cutting plane CC (e.g., section CC). A cross-sectional view may be an example of a cross-sectional view of the memory array 200, where some aspects (e.g., dielectric structures) are omitted for clarity. The elements of the memory array 200 may be described relative to the x, y, and z directions, as shown... Figure 2 , 3A And each of 3B is shown. Although included Figure 2 , 3A Some elements in 3B are labeled with numerical indicators, while other corresponding elements are not labeled, but they are the same or will be understood to be similar, in order to increase the visibility and clarity of the depicted features. Furthermore, although a certain number of repeating elements are shown in the illustrative example of memory array 200, the techniques described herein are applicable to any number of such elements, or the ratio of one repeating element to another.

[0036] In an example of memory array 200, memory cells 105 and word lines 205 can be configured according to hierarchy 230 (e.g., stacks, layers, planes, such as...). Figure 3A and 3B The memory array 200 (shown in the diagram) is distributed along the z-direction. In some instances, the z-direction may be orthogonal to the substrate (not shown) of the memory array 200, which may be below the structure shown along the z-direction. While the illustrative example of the memory array 200 includes four levels 230, the memory array 200 according to the examples disclosed herein may include any number of one or more levels 230 along the z-direction (e.g., 64 levels, 128 levels).

[0037] Each word line 205 may be an example of a portion of an access line formed of one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As shown, the word line 205 may be formed in a comb-like structure, including portions (e.g., protrusions, teeth) extending along the y-direction through gaps (e.g., alternating gaps) between the pillars 220. For example, as shown, the memory array 200 may include two word lines 205 per level 230 (e.g., odd-number lines 205-a-n1 and even-number lines 205-a-n2 for a given level n), wherein such word lines 205 of the same level 230 may be described as interleaved (e.g., wherein portions of the odd-number lines 205-a-n1 protrude along the y-direction between portions of the even-number lines 205-a-n2, and vice versa). In some instances, (e.g., level 230) odd-number lines 205 may be associated with a first memory cell 105 on a first side of a given pillar 220 (e.g., along the x-direction), and (e.g., level 230) even-number lines may be associated with a second memory cell 105 on a second side of a given pillar 220 (e.g., along the x-direction, opposite the first memory cell 105). Therefore, in some instances, a memory cell 105 of a given level 230 may be addressed (e.g., selected, activated) according to either even-number lines 205 or odd-number lines 205.

[0038] Each pillar 220 may be an example of a portion (e.g., a conductive pillar portion) of an access line formed from one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As shown, the pillars 220 may be arranged in a two-dimensional array (e.g., in an xy plane) having a first number of pillars 220 along a first direction (e.g., eight pillars along the x-direction, i.e., eight rows of pillars) and a second number of pillars 220 along a second direction (e.g., five pillars along the y-direction, i.e., five columns of pillars). While the illustrative example of memory array 200 includes a two-dimensional arrangement of eight pillars 220 along the x-direction and five pillars 220 along the y-direction, memory array 200 according to the examples disclosed herein may include any number of pillars 220 along the x-direction and any number of pillars 220 along the y-direction. Furthermore, as shown, each pillar 220 may be coupled to a corresponding set of memory cells 105 (e.g., one or more memory cells 105 per level 230 along the z-direction). The support 220 may have a cross-sectional area extending along the z-direction in the xy-plane. Although shown as a circular cross-sectional area in the xy-plane, the support 220 may be formed in different shapes, such as having an elliptical, square, rectangular, polygonal, or other cross-sectional area in the xy-plane.

[0039] Each memory cell 105 may contain a chalcogenide material. In some instances, memory cells 105 may be instances of threshold-processed memory cells. Each memory cell 105 may be accessed (e.g., addressed) based on the intersection between word line 205 (e.g., a hierarchy selection, which may include even or odd selections within hierarchy 230) and pillar 220. For example, as shown, the selected memory cell 105-a of hierarchy 230-a-3 may be accessed based on the intersection between pillar 220-a-43 and word line 205-a-32.

[0040] Access bias (e.g., access voltage V) can be applied across memory cell 105. 存取 The access bias can be a positive or negative voltage (which can be used to access, for example, write to, or read from) memory cell 105. In some instances, the access bias can be achieved by using a first voltage (e.g., V). 存取 / 2) Bias the selected word line 205 and pass it through a second voltage (e.g., -V) 存取 / 2) An access bias is applied by biasing the selected pillar 220, the second voltage having the opposite sign to the first voltage. With respect to the selected memory cell 105-a, a corresponding access bias (e.g., the first voltage) may be applied to word lines 205-a-32, while other unselected word lines 205 may be grounded (e.g., biased to 0V). In some instances, the word line bias may be provided by word line drivers (not shown) coupled to one or more of the word lines 205.

[0041] To apply a corresponding access bias (e.g., a second voltage) to pillar 220, pillar 220 may be configured to selectively couple to bit line 215 (e.g., a digital line, column line, or access line extending along the y-direction) via a corresponding transistor 225 coupled (e.g., physically or electrically) between pillar 220 and bit line 215. In some instances, transistor 225 may be a vertical transistor (e.g., a transistor with a channel along the z-direction, a transistor with a semiconductor junction along the z-direction), which may be formed over the substrate of memory array 200 using various techniques (e.g., thin-film technology). In some instances, selected pillar 220, selected bit line 215, or a combination thereof may serve as a reference. Figure 1 The example of selected column line 125 described.

[0042] Transistor 225 (e.g., the channel portion of transistor 225) may be activated by gate line 210 (e.g., an activation line, select line, row line, or access line extending along the x-direction), said gate line being gate-coupled to a corresponding gate of a set of transistors 225 (e.g., a set along the x-direction). In other words, each of the pillars 220 may have a first end (e.g., a bottom end facing the negative z-direction) configured for coupling with an access line (e.g., bit line 215). In some instances, gate line 210, transistor 225, or both may be considered as components of row decoder 110 (e.g., as a pillar decoder component). In some instances, the selection (e.g., bias) of pillar 220 or bit line 215, or various combinations thereof, may be supported by column decoder 120 or sensing component 130, or both.

[0043] To adjust the corresponding access bias (e.g., -V) 存取 / 2) An access bias is applied to pillar 220-a-43, bit line 215-a-4 can be biased with an access bias, and gate line 210-a-3 can be grounded (e.g., biased to 0V) or otherwise biased with an activation voltage. In an example where transistor 225 is an n-type transistor, biasing gate line 210-a-3 with a relatively higher voltage than bit line 215-a-4 can activate transistor 225-a (e.g., make transistor 225-a operate in a conductive state), thereby coupling pillar 220-a-43 to bit line 215-a-4 and biasing pillar 220-a-43 with an associated access bias. In the example where transistor 225 is a p-type transistor, biasing gate line 210-a-3 with a relatively lower voltage than bit line 215-a-4 activates transistor 225-a, thereby coupling pillar 220-a-43 to bit line 215-a-4 and biasing pillar 220-a-43 with an associated access bias. However, transistor 225 may contain different channel types or may operate according to different bias schemes to support various access operations.

[0044] In some instances, unselected pillars 220 in memory array 200 may be electrically floated when transistor 225-a is activated, or may be coupled to another voltage source (e.g., grounded, via a high-resistance path, via a leakage path) to prevent voltage drift of pillar 220. For example, applying a ground voltage to gate line 210-a-3 may not activate other transistors 225 coupled to gate line 210-a-3 because the ground voltage of gate line 210-a-3 may not be greater than the voltage of other bit lines 215 (e.g., they may be biased with a ground voltage or floatable). Furthermore, other unselected gate lines 210, including those such as... Figure 3A The gate line 210-a-5 shown in the diagram can be used with an access bias equal to or similar to (e.g., -V) 存取The voltage is biased by a voltage (or some other negative bias or bias relatively close to the access bias voltage) such that transistor 225 along the unselected gate line 210 is not activated. Therefore, transistor 225-b coupled to gate line 210-a-5 can be deactivated (e.g., operated in a non-conductive state), thereby isolating the voltage of bit line 215-a-4 from pillars 220-a-45 and the other pillars 220.

[0045] In a write operation, a write bias can be applied across memory cell 105 (e.g., where V 存取 =V 写入 A write bias (which can be a positive or negative voltage) is applied to write to memory cell 105. In some instances, the polarity of the write bias can affect (e.g., determine, set, program) the behavior or characteristics of the material of memory cell 105, such as the threshold voltage of the material. For example, applying a write bias with a first polarity can set the material of memory cell 105 to have a first threshold voltage that can be associated with storing logic 0. Furthermore, applying a write bias with a second polarity (e.g., opposite to the first polarity) can set the material of memory cell 105 to have a second threshold voltage that can be associated with storing logic 1. For different logic states stored by the material of memory cell 105, the difference between the threshold voltages of the material of memory cell 105 (e.g., the difference between the threshold voltages when the material is positively storing logic state '0' versus logic state '1') can correspond to the read window of memory cell 105.

[0046] In a read operation, a read bias can be applied across memory cell 105 (e.g., where V 存取 =V read (which can be a positive or negative voltage) is used to read memory cell 105. In some instances, the logic state of memory cell 105 can be evaluated based on whether memory cell 105 is thresholded in the presence of an applied read bias. For example, such a read bias may cause memory cell 105 storing a first logic state (e.g., logic 0) to reach a threshold (e.g., allow current flow, allow current above a threshold current) and may not cause memory cell 105 storing a second logic state (e.g., logic 1) to reach a threshold (e.g., do not allow current flow, allow current below a threshold current), wherein such current can be detected via active word line 205 or active bit line 215.

[0047] In some instances, the deactivated transistor 225 along bit line 215-a-4, and other transistors 225, may allow leakage during operation when bit line 215-a-4 is biased with an access bias. For example, unselected gate line 210 (e.g., gate line 210-a-5) may be used with a negative voltage (e.g., having a value equal to or similar to the bit line bias) having a value similar to the bit line bias.存取 A negative voltage of a magnitude of 2 is applied to deactivate transistor 225 (e.g., transistor 225-b) coupled to bit line 215-a-4 and the unselected gate line. Consequently, the corresponding gate of the deactivated transistor 225 can be biased to a negative voltage. Some access operations can result in a relatively large voltage difference across the deactivated transistor 225. For example, if bit line 215-a-4 is biased with a positive access bias (e.g., where -V...), the gate of the deactivated transistor 225 can be deactivated. 存取 / 2 is a positive voltage), then the voltage difference across the deactivated transistor 225 can correspond to a negative voltage and a positive access bias (e.g., V). 存取 The difference between ) and. In some cases, leakage associated with transistor 225 may increase as the voltage difference across transistor 225 increases. In some cases, increased leakage may be associated with increased power consumption, interrupted access operations (e.g., access operations that fail or are slowed down due to leakage altering the current or charge along bit line 215-a-4) or both.

[0048] According to the examples disclosed herein, memory array 200 may implement a multi-transistor architecture, such as a dual-transistor architecture, wherein pillar 220 may be coupled to two bit lines 215 using two transistors 225. For example, pillar 220 may be coupled to a first bit line 215 via a first transistor 225 and to a second bit line 215 via a second transistor 225. The first bit line 215 may be associated with biasing pillar 220 with a positive voltage (e.g., for -V). 存取 / 2 is the case of a positive voltage), and the second bit line 215 can be associated with biasing the pillar 220 with a negative voltage (e.g., for -V). 存取 (The case where / 2 is a negative voltage). For example, to bias the pillar 220 with a positive voltage, the memory array 200 can be configured to bias the first bit line 215 with a positive voltage (e.g., using a bit line driver, column decoder 120), activate the first transistor 225 to couple the pillar 220 to the first bit line 215, and deactivate the second transistor 225 to isolate the pillar 220 from the second bit line 215 (e.g., during this period, the second bit line can be floated, grounded, or biased with a negative voltage). To bias the pillar 220 with a negative voltage, the memory array 200 can be configured to bias the second bit line 215 with a negative voltage (e.g., using a bit line driver, column decoder 120), activate the second transistor 225 to couple the pillar 220 to the second bit line 215, and deactivate the first transistor 225 to isolate the pillar 220 from the first bit line 215 (e.g., during this period, the first bit line can be floated, grounded, or biased with a positive voltage).

[0049] By using different bit lines 215 to positively or negatively bias the pillar 220, the voltage difference across the deactivated transistor 225 can be reduced, thereby reducing the leakage current associated with the deactivated transistor 225. For example, bit line 215 and unselected gate line 210 can be biased such that during access operations, the corresponding voltage difference across the deactivated transistor 225 is approximately half the access voltage (e.g., having a voltage less than or equal to V). 存取 (a value of / 2). Therefore, by implementing a multi-transistor architecture, such as a dual-transistor architecture, to bias the pillars 220 of the memory array 200 according to the examples disclosed herein, the memory array 200 can be implemented with reduced leakage via the deactivated transistor 225, which can support reduced power consumption, increased access operation accuracy or any combination thereof, and other benefits.

[0050] Figure 4 An example of layout 400 supporting a transistor configuration for a vertical memory array, according to examples disclosed herein, is shown. Layout 400 may be used for implementing reference... Figure 2 , 3A Examples of aspects of the memory array 200 described in 3B are given, and aspects of layout 400 may be described with reference to the x-direction (e.g., row direction), y-direction (e.g., column direction), and z-direction (e.g., hierarchy direction). For example, layout 400 may include an arrangement of pillars 220-b, which may be referenced... Figure 2 , 3A The example of pillar 220 described in 3B. Layout 400 may also include various arrangements of word lines 205 (e.g., arranged in a comb-like structure) and memory cells 105 (e.g., a three-dimensional array of memory cells 105), the word lines and the memory cells also being referenced. Figure 2 , 3A Instances of the corresponding components described in 3B, although for the sake of illustrative clarity, are shown below. Figure 4 Such components have been omitted.

[0051] Each of the pillars 220-b may extend through one or more levels (e.g., level 230) of the memory cell 105 and may be coupled to one or more memory cells 105 (e.g., two memory cells 105) at each level 230. For example, at each level, one or more memory cells 105 may be coupled to the pillar 220-b and the corresponding word line 205 (e.g., physically coupled between them, electrically coupled between them, or both). While the illustrative example of layout 400 includes a circuit system associated with two pillars 220-b (e.g., a column of elements) along the x-direction, the elements of layout 400 according to the examples disclosed herein may be repeated for any number of pillars 220-b (e.g., any number of rows and columns of elements in the xy plane) along the x and y directions.

[0052] Layout 400 illustrates an example of a multi-transistor architecture, such as a dual-transistor architecture, which can be implemented to facilitate the biasing of pillar 220 (e.g., via bit line 215-b extending along the x-direction). For example, pillar 220-b-11 may be coupled to bit line 215-b-1a via transistor 225-c-11a and to bit line 215-b-1b via transistor 225-c-11b, and pillar 220-b-12 may be coupled to bit line 215-b-1a via transistor 225-c-12a and to bit line 215-b-1b via transistor 225-c-12b. Such an arrangement can be used with bit line 215 and transistor 225 that divide such pairs of elements (e.g., as referenced). Figure 2 , 3A This is related to the functionality described in 3B. For example, biasing of pillars 220-b-11 and 220-b-12 with a first voltage polarity can be supported via bit line 215-b-1a, and biasing of pillars 220-b-11 and 220-b-12 with a second voltage polarity (e.g., opposite to the first voltage polarity) can be supported via bit line 215-b-1b.

[0053] To support certain access operations, one of bit lines 215-b-1a and 215-b-1b can be activated (e.g., coupled to an access voltage source or coupled to sensing component 130), while the other of bit lines 215-b-1a and 215-b-1b can be deactivated (e.g., floating, coupled to an idle voltage source, or isolated from sensing component 130). For example, bit line 215-b-1a can be used to bias one or both of pillars 220-b-11 and 220-b-12 with a positive access voltage (e.g., during which pillars 220-b-11 and 220-b-12 can be isolated from bit line 215-b-1b), and bit line 215-b-1b can be used to bias one or both of pillars 220-b-11 and 220-b-12 with a negative voltage (e.g., during which pillars 220-b-11 and 220-b-12 can be isolated from bit line 215-b-1a).

[0054] Transistor 225-c may be operable to couple pillar 220-b to corresponding bit line 215-b in part based on the voltage at the respective gate of transistor 225-c. For example, layout 400 may include a gate line 210-b extending along the y-direction, coupled to the gate of transistor 225-c (e.g., of a row of transistors 225-c along the y-direction) and operable to bias the gate of transistor 225-c with various voltages. For example, layout 400 may include gate line 210-b-1a coupled to the gate of transistor 225-c-11a (e.g., and other transistors 225-c along the y-direction), gate line 210-b-1b coupled to the gate of transistor 225-c-11b, gate line 210-b-2a coupled to the gate of transistor 225-c-12a, and gate line 210-b-2b coupled to the gate of transistor 225-c-12b. Each of the gate lines 210-b can be driven independently (e.g., by a gate line driver) to bias the corresponding gate with the corresponding voltage.

[0055] In an example of layout 400, each transistor 225-c may be coupled to the ends of bit line 215-b and pillar 220-b (e.g., physically or electrically coupled between them). For example, transistor 225-c-11a may be coupled between bit line 215-b-1a and the first end of pillar 220-b-11 (e.g., the end in a relatively positive position along the z-direction, the top end), transistor 225-c-11b may be coupled between bit line 215-b-1b and the second end of pillar 220-b-11 (e.g., the end in a relatively negative position along the z-direction, the bottom end, the bottom end), and so on. Here, bit line 215-b-1a and transistor 225-c-1na may be located above pillar 220-b (e.g., relative to the substrate), and bit line 215-b-1b and transistor 225-c-1nb may be located below pillar 220-b (e.g., between pillar 220-b and the substrate). However, layout 400 may be implemented such that bit line 215-b-1a and transistor 225-c-1na may be located below pillar 220-b, and bit line 215-b-1b and transistor 225-c-1nb may be located above pillar 220-b.

[0056] In some instances, the transistor 225-c or bit line 215-b located above the pillar 220-b may be formed in part based on a laser annealing process. For example, in some cases, the relatively high heat from other annealing processes associated with the formation of transistor 225-c and bit line 215 may damage the memory cell 105 if it is exposed to high heat. Compared to other annealing processes, the laser annealing process can be associated with reduced heat. Therefore, by performing a laser annealing process after the formation of the memory cell 105, the heat exposure of the memory cell 105 can be reduced, thereby reducing the likelihood of damage to the memory cell 105.

[0057] In some instances, the channel type of each transistor 225-c may be implemented based on whether the transistor 225-c is operable to couple the pillar 220-b to a positive voltage (e.g., a positively biased bit line 215-b, such as bit line 215-b-1a) or to a negative voltage (e.g., a negatively biased bit line 215-b, such as bit line 215-b-1b). For example, transistor 225-c-1na (e.g., associated with a positive bias supporting the pillar 220-b) may be a first type of transistor (e.g., associated with a first channel type), and transistor 225-c-1nb (e.g., associated with a negative bias supporting the pillar 220-b) may be a second type of transistor (e.g., associated with a second channel type). In some instances, transistor 225-c-1na may be a p-type transistor, and transistor 225-c-1nb may be an n-type transistor. For example, a p-type transistor can be activated in response to biasing its gate line 210-b with a voltage relatively lower than that of bit line 215-b, and an n-type transistor can be activated in response to biasing its gate line 210-b with a voltage relatively higher than that of bit line 215-b. Therefore, biasing bit line 215-b-1a with a positive voltage and biasing the gate of transistor 225-c-1na with a ground voltage can activate transistor 225-c-1na based on the fact that transistor 225-c-1na is a p-type transistor. Similarly, biasing bit line 215-b-1b with a negative voltage and biasing the gate of transistor 225-c-1nb with a ground voltage can activate transistor 225-c-1nb based on the fact that transistor 225-c-1nb is an n-type transistor. Therefore, in some instances, each pillar 220-b can be coupled to an n-type / p-type transistor pair to support negative and positive bias of the pillar 220-b via a corresponding bit line 215-b.

[0058] Layout 400 can support access to memory cell 105 based on biasing the pillar 220-b coupled to memory cell 105 using bit line 215-b-1a or bit line 215-b-1b (e.g., reading the logic state of memory cell 105, writing the logic state to memory cell 105, and other access operations). For example, when performing an access to memory cell 105 coupled to pillar 220-b-12, the memory device 100 including layout 400 can be configured to bias pillar 220-b-12 using one of bit line 215-b-1a or bit line 215-b-1b, and isolate pillar 220-b-11 from the other of bit line 215-b-1a or bit line 215-b-1b. Based on which bit line 215-b is used to bias pillar 220-b-12 (e.g., based on whether pillar 220-b-12 is biased to a positive or negative voltage), memory device 100 can be configured to isolate unselected bit line 215-b from pillar 220-b-12.

[0059] Table 1 below depicts example voltages associated with the following: "idle" conditions (e.g., associated with the idle state of memory device 100, associated with pillars 220-b-11 and 220-b-12 not being selected for a given access operation), "positive" conditions (e.g., associated with an access operation performed on memory cell 105 coupled to pillar 220-b-12 with a positive cell bias via bit line 215-b-1a), and "negative" conditions (e.g., associated with an access operation performed on memory cell coupled to pillar 220-b-12 with a negative cell bias via bit line 215-b-1b). As shown in layout 400, voltage V_GLP1 may correspond to the voltage of gate line 210-b-1a, voltage V_GLN1 may correspond to the voltage of gate line 210-b-1b, voltage V_GLP2 may correspond to the voltage of gate line 210-b-2a, voltage V_GLN2 may correspond to the voltage of gate line 210-b-2b, voltage V_BLP may correspond to the voltage of bit line 215-b-1a, voltage V_BLN may correspond to the voltage of bit line 215-b-1b, voltage V_P1 may correspond to the voltage of pillar 220-b-11, voltage V_P2 may correspond to the voltage of pillar 220-b-12, and voltage V_WL may correspond to the voltage of word line 205 (e.g., a selected or otherwise representative word line 205). The voltages included in Table 1 are example values ​​for illustrative purposes, and other voltage values ​​may be used to support access operations as described herein.

[0060]

[0061] Table 1 - Access Voltages Associated with Operation Layout 400

[0062] In the "idle" condition, bit line 215-b and gate line 210-b can be biased such that each of the transistors 225-c is deactivated. For example, the voltage of gate line 210-b-na can be greater than the voltage of bit line 215-b-1a, and the voltage of gate line 210-b-nb can be less than the voltage of bit line 215-b-1b. Therefore, each of the transistors 225-c can be deactivated such that pillars 220-b-11 and 220-b-12 are isolated from bit line 215-b (e.g., and may be referred to as unselected pillar 220-b).

[0063] In some instances, the voltage of pillar 220-b can be biased to approximately 0V during isolation from bit line 215-b. For example, each of pillars 220-b can be coupled to a voltage source via coupler 405-a (e.g., resistive coupler, drain layer, drain device layer). Coupler 405 may contain material that provides charge dissipation, such as couplers with relatively high resistance or impedance to a ground node or other voltage source (e.g., to support passive balancing to reduce or prevent floating conditions). For example, coupler 405 may have a resistance greater than that associated with each of memory cells 105, which can provide charge dissipation with relatively low power consumption (e.g., compared to relatively low resistance dissipation couplers). In some instances, coupler 405 can be excluded from layout 400, allowing pillar 220-b to be in an electrically floating condition while isolated from bit line 215-b.

[0064] In some instances, coupler 405-a may be located between two levels of memory cell 105 in layout 400. For example, level 230 of an array that may additionally contain memory cells 105 may be replaced by coupler 405-a, such that pillar 220-b may be weakly coupled to a voltage source (e.g., weakly coupled to ground). Here, pillar 220-b may extend through coupler 405-a and may be coupled to coupler 405-a at a level within the memory array. In various instances, coupler 405 may be implemented in place of the bottom level of memory cell 105, in place of the top level of memory cell 105, or may be implemented on multiple levels, among other instances.

[0065] In a "positive" condition (e.g., when memory cell 105 is accessed with a positive cell bias via pillar 220-b-12), bit line 215-b and gate line 210-b can be biased such that pillar 220-b-12 is coupled to bit line 215-b-1a and isolated from bit line 215-b-1b. For example, when accessing memory cell 105 via pillar 220-b-12, a bit line driver (e.g., column decoder 120) can bias bit line 215-b-1a with a first access voltage (e.g., 3.5V) and bit line 215-b-1b with a ground voltage (e.g., 0V). Additionally, gate line 210-b-2a can be biased with a first voltage to activate transistor 225-c-12a, and gate line 210-b-2b can be biased with a second voltage to deactivate transistor 225-c-12b. In some instances, each of gate lines 210-b-2a and 210-b-2b can be biased with the same voltage, such as ground (e.g., 0V), and transistors 225-c-12a and 225-c-12b can be activated or deactivated based on the bias of the respective bit line 215-b. For example, V_BLP can be greater than V_GLP2 (e.g., 3.5V > 0V), which can activate transistor 225-c-12a and couple pillar 220-b-12 to bit line 215-b-1a, and V_BLN can be equal to V_GLN2 (e.g., both are biased to 0V), which can deactivate transistor 225-c-12b and isolate pillar 220-b-12 from bit line 215-b-1b.

[0066] Based on the coupling of pillar 220-b-12 to bit line 215-b-1a, pillar 220-b-12 can be biased with a first access voltage (e.g., 3.5V), which can correspond to a reference voltage. Figure 2 , 3A The voltage -V described in 3B 存取 / 2. For example, coupling pillar 220-b-12 to bit line 215-b-1a allows a first access voltage to be applied to pillar 220-b-12 such that V_P2 equals V_BLP. For the "positive" condition, an access bias (e.g., V_P2 = V_BLP) can be applied across memory cell 105 in conjunction with the bias of word line 205 coupled to memory cell 105. 存取 For example, the word line driver can bias word line 205 with a second access voltage (e.g., V_WL = -3.5V), which can correspond to a reference voltage. Figure 2 , 3A The voltage V described in 3B 存取 / 2. A logic state can be read from or written to memory cell 105 based on an access bias. For example, a logic state can be read based on whether memory cell 105 performs threshold processing in response to an access bias. In some instances, applying an access bias associated with a "positive" condition can configure the selected memory cell 105 to have a first characteristic (e.g., a first threshold voltage) associated with storing a first logic state (e.g., logic 0).

[0067] In a negative condition (e.g., when memory cell 105 is accessed with a negative cell bias via pillar 220-b-12), bit line 215-b and gate line 210-b can be biased such that pillar 220-b-12 is coupled to bit line 215-b-1b and isolated from bit line 215-b-1a. For example, when accessing memory cell 105 via pillar 220-b-12, the bit line driver can bias bit line 215-b-1b with a third access voltage (e.g., -3.5V) and bit line 215-b-1a with a ground voltage (e.g., 0V). Additionally, gate line 210-b-2b can be biased with a first voltage to activate transistor 225-c-12b, and gate line 210-b-2a can be biased with a second voltage to deactivate transistor 225-c-12a. In some instances, each of gate lines 210-b-2a and 210-b-2b can be biased with the same voltage, such as ground (e.g., 0V), and transistors 225-c-12a and 225-c-12b can be activated or deactivated based on the bias of the corresponding bit line 215-b. For example, V_BLP can be equal to V_GLP2 (e.g., both are biased to 0V), which deactivates transistor 225-c-12a and isolates the pillar 220-b-12 from bit line 215-b-1a. V_BLN can be less than V_GLN2 (e.g., -3.5V < 0V), which activates transistor 225-c-12b and couples the pillar 220-b-12 to bit line 215-b-1b.

[0068] Based on coupling the pillar 220-b-12 to the bit line 215-b-1b, the pillar 220-b-12 can be biased with a third access voltage (e.g., -3.5V) such that V_P2 equals V_BLN. For the "negative" condition, an access bias can be applied across the memory cell 105 in combination with the bias of the word line 205 coupled to the memory cell 105. For example, the word line driver can bias the word line 205 with a fourth access voltage (e.g., V_WL = 3.5V). In some instances, the logical state can be read from the memory cell 105 based on whether the memory cell 105 undergoes threshold processing in response to the access bias. In some instances, applying the access bias associated with the "negative" condition can set the selected memory cell 105 to have a second characteristic (e.g., a second threshold voltage) associated with storing a second logical state (e.g., logic 1).

[0069] When accessing the memory cell 105 via the pillar 220-b-12 (e.g., with a positive or negative cell bias), the bit line 215-b and the gate line 210-b can be biased such that the pillar 220-b-11 is isolated from both the bit line 215-b-1a and the bit line 215-b-1b. For example, when accessing the memory cell 105 via the pillar 220-b-12, two of the gate lines 210-b associated with the pillar 220-b-11 (e.g., the gate line 210-b-1a and the gate line 210-b-1b) can be biased according to an "idle" condition (e.g., V_GLP1 = 3.5V and V_GLN1 = -3.5V). Thus, both the transistor 225-c-11a and the transistor 225-c-11b can be deactivated regardless of whether the bit line 215-b-1a is biased with a first access voltage or the bit line 215-b-1b is biased with a third access voltage. For example, during positive cell bias, V_GLP1 = V_BLP and V_GLN1 < V_BLN, and during negative cell bias, V_GLP1 > V_BLP and V_GLN=V_BLN. Thus, neither the transistor 225-c-11a nor the transistor 225-c-11b can be activated during the "positive" condition or during the "negative" condition. Thus, the pillar 220-b-11 can be isolated from the bit line 215-b during an access operation via the pillar 220-b-12.

[0070] In some instances, when isolated from the bit line 215-b, the pillar 220-b-11 can be biased to ~0V based on being coupled to the coupler 405-a, which can, for example, reduce (e.g., dissipate) the voltage of the pillar 220-b-11 to ground. In some instances, the pillar 220-b-11 can be electrically floating based on being isolated from the bit line 215-b (e.g., if the coupler 405 is excluded from the layout 400).

[0071] In some instances, the biases of gate line 210-b and bit line 215-b can return to idle biases after an access operation. Coupler 405-a can reduce the voltage difference between pillar 220-b and a voltage source (e.g., a ground node), or otherwise dissipate or prevent charge accumulation on pillar 220-b. For example, after an access operation, pillar 220-b-12 can be isolated from bit line 215-b, and pillar 220-b-12 can still be at least partially biased to the access voltage (e.g., a first access voltage, a third access voltage). To dissipate such bias, coupler 405-a can support charge flow to or out of pillar 220-b-12 based on the voltage difference between pillar 220-b-12 and a voltage source (e.g., a ground voltage source). In some instances, coupler 405-a can allow at least some charge to or out of pillar 220-b-12 during an access operation. However, such charge flow can be slow enough that coupling with bit line 215-b-1a or bit line 215-b-1b can maintain the bias of pillar 220-b-12 at the access voltage during access operation.

[0072] By implementing a multi-transistor architecture, such as a dual-transistor architecture, for biasing pillar 220-b, layout 400 illustrates an example for reducing leakage through unselected transistor 225-c. For example, leakage through deactivated transistor 225-c can be related to (e.g., proportional to) the magnitude of the voltage difference across deactivated transistor 225-c. In the described example of a multi-transistor architecture, such as a dual-transistor architecture, the highest voltage difference across deactivated transistor 225-c when pillar 220-b is biased can be the magnitude of the access voltage of bit line 215-b, which can correspond to a reference... Figure 2 , 3A The V described in 3B 存取 The value of / 2 (e.g., compared to V in some single-transistor architectures) 存取 (Compared to the magnitude of the value). Therefore, by implementing a multi-transistor architecture, such as a dual-transistor architecture, according to layout 400, the voltage difference across the deactivated transistor 225-c can be smaller than that of a configuration that implements a single-transistor architecture to bias the pillar 220, which reduces the corresponding leakage.

[0073] In various instances, reducing leakage can support reduced power consumption, improved access operation accuracy, or a combination thereof, and other benefits. For example, such leakage can be associated with the power consumption used to maintain the required access voltage (e.g., a voltage source), regardless of the flow of unwanted charge. In some instances, such leakage can lead to errors in read operations. For example, leakage current can superimpose on the read current through memory cell 105, which can lead to inaccurate assessments of the resistance state stored by memory cell 105, or inaccurate assessments of whether memory cell 105 has been thresholded, and other inaccuracies. Therefore, by reducing leakage (e.g., associated with deactivated transistors), a multi-transistor architecture, such as a dual-transistor architecture, used to bias pillar 220-b can improve the performance of memory device 100 implementing layout 400.

[0074] Figure 5 An example of layout 500 supporting a transistor configuration for a vertical memory array, according to examples disclosed herein, is shown. Layout 500 may be used for implementing reference... Figure 2 , 3A This is another example of an aspect of the memory array 200 described in 3B, and aspects of layout 500 may be described with reference to the x-direction (e.g., row direction), y-direction (e.g., column direction), and z-direction (e.g., hierarchy direction). For example, layout 500 may include an arrangement of pillars 220-c, which may be referenced... Figure 2 , 3A The example of pillar 220 described in 3B. Layout 500 may also include various arrangements of word lines 205 and memory cells 105, which may also be referenced. Figure 2 , 3A Instances of the corresponding components described in 3B, although for the sake of illustrative clarity, are shown below. Figure 5 Such components have been omitted.

[0075] Layout 500 illustrates another example of a multi-transistor architecture, such as a dual-transistor architecture, which can be implemented to facilitate the biasing of pillar 220. This layout can (e.g., electrically, operatively) resemble layout 400, but may implement different physical arrangements of the elements. For example, pillar 220-c-11 may be coupled to bit line 215-c-1a via transistor 225-d-11a (e.g., based on the voltage of gate line 210-c-1a) and to bit line 215-c-1b via transistor 225-d-11b (e.g., based on the voltage of gate line 210-c-1b), and pillar 220-d-12 may be coupled to bit line 215-c-1a via transistor 225-d-12a (e.g., based on the voltage of gate line 210-c-2a) and to bit line 215-c-1b via transistor 225-d-12b (e.g., based on the voltage of gate line 210-c-2b). In some instances, such elements may operate similarly to the corresponding elements described in reference layout 400 (e.g., bit line 215-c-1a may support biasing pillar 220-c with a positive voltage, and bit line 215-c-1b may support biasing pillar 220-c with a negative voltage).

[0076] In an example of layout 500, each transistor 225-d may be coupled to the end of bit line 215-c and pillar 220-c between memory cell 105 (e.g., layer 230) and substrate. For example, features of layout 500 may be formed on or above the substrate, and each transistor 225-d may be formed between bit line 215-c and the end (e.g., bottom) of pillar 220-c along the z-direction (e.g., the end of pillar 220-c in a relatively negative position along the z-direction). In some examples, each of gate line 210-c, bit line 215-c, and transistor 225-d may be located below pillar 220-c in the z-direction (e.g., below the end of pillar 220-c between memory cell 105 and substrate).

[0077] Layout 500 may also include coupling element 405-b, which may be referenced. Figure 4 An example of the described coupling element 405. The coupling element 405-b may be a material providing dissipative coupling to a ground node or other voltage source. As shown, the coupling element 405-b may be associated with a corresponding coupling portion 505 of each of the pillars 220-c, said coupling portion may be a resistive impedance, a capacitive impedance, or a combination thereof (e.g., an RC impedance). In an example of layout 500, the coupling element 405-b may be located above the pillars 220-c (e.g., above the substrate-opposite end of the pillar 220-c). In some other examples (not shown), layout 500 may implement the coupling element 405 at or between layers 230 (e.g., as shown in reference). Figure 4 (As described).

[0078] In some instances of layout 500, the relative positions of the elements shown along the z-direction are reversible, such that gate line 210-c, bit line 215-c, and transistor 225-d can be located above pillar 220-c (e.g., opposite to the substrate). In some instances, gate line 210-c, bit line 215-c, and transistor 225-d can be formed on or above pillar 220-c in part based on a laser annealing process (e.g., when such features are formed after memory cell 105 has been formed).

[0079] Figure 6 An example of layout 600 supporting a transistor configuration for a vertical memory array, according to examples disclosed herein, is shown. Layout 600 may be used for implementing reference... Figure 2 , 3A Examples of aspects of the memory array 200 described in 3B. For example, layout 600 may show the memory array 200 relative to the cutting plane BB (e.g., as shown in the image). Figure 2 A side cross-sectional view (e.g., section BB) is shown in the figure. Layout 600 may include an arrangement of memory cells 105, word lines 205-b, gate lines 210-d, bit lines 215-d, pillars 220-d, and transistors 225-e, which may be used as a reference. Figure 2 , 3A Examples of the corresponding components described in 3B. Aspects of layout 600 can be described with reference to the x, y, and z directions.

[0080] Layout 600 illustrates an example for implementing a coupling element 405-c, which may include a leakage current material 605 and a conductor portion 610. The coupling element 405-c may extend along the x and y directions such that it is coupled to each of the pillars 220-d contained in the memory device 100 including layout 600. The coupling element 405-c may provide dissipative coupling to a ground node or other voltage source (e.g., to prevent or mitigate floating conditions of the pillars 220-d).

[0081] Coupler 405-c may be located (e.g., formed between) layers 230-b of layout 600 (e.g., between layers 230-b-1 and 230-b-2). In some instances, implementing coupler 405-c may involve replacing the layer that would otherwise contain memory cell 105. For example, elements of coupler 405-c may be implemented in place of memory cell 105 and word line 205 that would otherwise be formed along the z-direction at the layer of coupler 405-c. In some instances of layout 600 (not shown), coupler 405-c may replace the bottom layer 230-b (e.g., located below layer 230-b) or the top layer 230-b (e.g., located above layer 230-b).

[0082] Coupler 405-c may include various materials for supporting dissipative coupling. For example, coupler 405-c may include leakage current material 605 providing coupling between the support post 220-d and the conductor portion 610, wherein leakage current material 605 may support a reference... Figure 5 The described aspect of coupling portion 505. For example, leakage current material 605 may be formed in portions (e.g., discrete portions) associated with a respective impedance (e.g., relatively high resistance) between each pillar 220-d and conductor portion 610, wherein conductor portion 610 may be a conductive material coupled to a ground node or other voltage source. In some instances, the formation of leakage current material 605 and conductor portion 610 may implement aspects similar to the formation of memory cell 105 and word line 205, respectively, such as implementing similar patterning, and other operations. In some instances, the formation of conductor portion 610 may implement the same or similar conductor formation operations used for forming word line 205-b (e.g., may be the same or similar material and shape as word line 205-b), and the formation of leakage current material 605 may implement similar operations used for forming memory cell 105 but with a different (e.g., higher resistance) material.

[0083] Figure 7 A block diagram 700 is shown illustrating a memory system 720 supporting a transistor configuration for a vertical memory array, according to an example disclosed herein. The memory system 720 may be as described in the references... Figures 1 to 6 Examples of aspects of the described memory system. Memory system 720 or its various components may be examples of components for performing various aspects of transistor configurations for vertical memory arrays as described herein. For example, memory system 720 may include access component 725, coupling component 730, isolation component 735, dissipation component 740, bit line bias component 745, word line bias component 750, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0084] Access component 725 may be configured or otherwise support a component for accessing a memory cell coupled between a conductive pillar of the memory die and a word line of the memory die. In some instances, the memory cell may contain a chalcogenide memory element.

[0085] In some instances, to support access via access component 725, coupling component 730 may be configured or otherwise supported to couple the conductive pillar to the first bit line at least partially based on activating a first transistor between the conductive pillar and the first bit line. In some instances, to support access via access component 725, isolation component 735 may be configured or otherwise supported to isolate the conductive pillar from the second bit line at least partially based on deactivating a second transistor between the conductive pillar and the second bit line. In some instances, to support access via access component 725, word line biasing component 750 may be configured or otherwise supported to bias the word line with a first access voltage. In some instances, to support access via access component 725, bit line biasing component 745 may be configured or otherwise supported to bias the first bit line with a second access voltage.

[0086] In some instances, activation of the first transistor is based at least in part on biasing the gate of the first transistor with a first voltage. In some instances, deactivation of the second transistor is based at least in part on biasing the gate of the second transistor with a second voltage. In some instances, the first voltage and the second voltage are the same voltage.

[0087] In some instances, the first transistor is associated with a first channel type. In other instances, the second transistor is associated with a second channel type different from the first channel type.

[0088] In some instances, activation of the first transistor is based at least in part on biasing the first bit line with a second access voltage greater than the same voltage. In some instances, deactivation of the second transistor is based at least in part on biasing the second bit line with the same voltage.

[0089] In some instances, activation of the first transistor is based at least in part on biasing the first bit line with a second access voltage less than the same voltage. In some instances, deactivation of the second transistor is based at least in part on biasing the second bit line with the same voltage.

[0090] In some instances, the dissipative component 740 may be configured or otherwise support a component for reducing the voltage difference between the conductive pillar and the ground node after access, via a resistive coupling between the conductive pillar and the ground node, the resistive coupling having a first resistance greater than a second resistance associated with the memory cell.

[0091] In some instances, isolation component 735 may be configured or otherwise support a component that, during access, isolates the second conductive pillar from the first bit line at least in part based on deactivating a third transistor between the second conductive pillar and the first bit line. In some instances, isolation component 735 may be configured or otherwise support a component that, during access, isolates the second conductive pillar from the second bit line at least in part based on deactivating a fourth transistor between the second conductive pillar and the second bit line.

[0092] Figure 8 A flowchart illustrating a method 800 for supporting transistor configuration for a vertical memory array, according to examples disclosed herein. The operation of method 800 can be implemented by a memory system or its components as described herein. For example, it can be implemented by reference to... Figures 1 to 7 The described memory system performs the operations of method 800. In some instances, the memory system may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0093] At 805, the method may include accessing a memory cell coupled between a conductive pillar of the memory die and a word line of the memory die. The operation of 805 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 7 The described access component 725 performs aspects of the operation 805. Access to 805 can be performed according to various techniques disclosed herein, which may include operations of 810, 815, 820, or 825 or any combination thereof, as well as other operations.

[0094] In some instances, access to 805 may include (e.g., at 810) coupling the conductive pillar to the first line at least in part based on activating a first transistor between the conductive pillar and the first line. Operation of 810 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 7 The described coupling component 730 performs the operation of 810.

[0095] In some instances, access to 805 may include (e.g., at 815) at least in part isolating the conductive pillar from the second bit line by deactivating the second transistor between the conductive pillar and the second bit line. Operation of 815 may be performed according to examples disclosed herein. In some instances, it may be achieved by, as referenced... Figure 7 The described isolation component 735 performs the operation of 815.

[0096] In some instances, access to 805 may include (e.g., at 820) biasing the word line with a first access voltage. Operation of 820 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 7 The described bitline bias component 745 performs the operation of 820.

[0097] In some instances, access to the 805 may include (e.g., at the 825) biasing the first bit line with a second access voltage. Operation of the 825 may be performed according to examples disclosed herein. In some instances, it may be achieved by, as referenced... Figure 7 The described bitline bias component 745 performs the operation of 820.

[0098] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing processor-executable instructions) or any combination thereof for performing aspects of this disclosure:

[0099] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for accessing a memory cell coupled between a conductive pillar and a word line of a memory die, the accessing memory cell comprising: coupling the conductive pillar to the first bit line at least in part based on activating a first transistor between the conductive pillar and the first bit line; isolating the conductive pillar from the second bit line at least in part based on deactivating a second transistor between the conductive pillar and the second bit line; biasing the word line with a first access voltage; and biasing the first bit line with a second access voltage.

[0100] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to aspect 1, wherein activation of the first transistor is based at least in part on biasing the gate of the first transistor with a first voltage, and deactivation of the second transistor is based at least in part on biasing the gate of the second transistor with a second voltage.

[0101] Aspect 3: The method, device, or non-transitory computer-readable medium according to aspect 2, wherein the first voltage and the second voltage are the same voltage.

[0102] Aspect 4: The method, apparatus or non-transitory computer-readable medium of aspect 3, wherein the first transistor is associated with a first channel type and the second transistor is associated with a second channel type different from the first channel type.

[0103] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 3 to 4, wherein activation of the first transistor is based at least in part on biasing the first bit line when the second access voltage is greater than the same voltage, and deactivation of the second transistor is based at least in part on biasing the second bit line with the same voltage.

[0104] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 3 to 4, wherein activation of the first transistor is based at least in part on biasing the first bit line when the second access voltage is less than the same voltage, and deactivation of the second transistor is based at least in part on biasing the second bit line with the same voltage.

[0105] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 6 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for reducing the voltage difference between the conductive pillar and the ground node via a resistive coupling element having a first resistance greater than a second resistance associated with the memory cell after access.

[0106] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 7 further comprises features, circuitry, logic, components, or instructions, or any combination thereof, for: isolating the second conductive pillar from the first bit line at least in part based on deactivating a third transistor between the second conductive pillar and the first bit line during access; and isolating the second conductive pillar from the second bit line at least in part based on deactivating a fourth transistor between the second conductive pillar and the second bit line during access.

[0107] It should be noted that the methods described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0108] A device is described. An overview of aspects of the device as described herein is provided below:

[0109] Aspect 9: An apparatus comprising: a conductive pillar extending through a plurality of levels of a memory array, wherein at each of the plurality of levels, one or more memory cells of the memory array are coupled between the conductive pillar and a corresponding word line; a first transistor operable to couple the conductive pillar to a first bit line at least partially based on a first voltage at the gate of the first transistor; and a second transistor operable to couple the conductive pillar to a second bit line at least partially based on a second voltage at the gate of the second transistor.

[0110] Aspect 10: The device according to aspect 9, wherein: a first transistor is coupled between a first bit line and a first end of a conductive pillar, and a second transistor is coupled between a second bit line and a second end of a conductive pillar opposite to the first end.

[0111] Aspect 11: The device according to aspect 9, wherein: a first transistor is coupled between the ends of a first bit line and a conductive pillar between one or more memory cells and a substrate, and a second transistor is coupled between the ends of a second bit line and a conductive pillar between one or more memory cells and a substrate.

[0112] Aspect 12: The device according to aspect 9, wherein: a first transistor is coupled between a first bit line and the substrate-opposite end of a conductive pillar, and a second transistor is coupled between a second bit line and the substrate-opposite end of a conductive pillar.

[0113] Aspect 13: The apparatus according to any one of aspects 9 to 12 further comprises: a first gate line coupled to the gate of a first transistor, wherein the first transistor is operable to couple a conductive pillar to a first bit line at least partially based on the first gate line being biased to a first voltage; and a second gate line coupled to the gate of a second transistor, wherein the second transistor is operable to couple a conductive pillar to a second bit line at least partially based on the second gate line being biased to a second voltage.

[0114] Aspect 14: The device according to any one of aspects 9 to 13, wherein the conductive pillar is coupled to a voltage source via a resistive coupler having a first resistance greater than that of a second resistance associated with each of the memory cells.

[0115] Aspect 15: The device according to aspect 14, wherein at least a portion of the resistive coupling element is connected to a conductive pillar between two of the plurality of levels of the memory array.

[0116] Aspect 16: The apparatus according to any one of aspects 9 to 15, wherein the first transistor is an n-type transistor and the second transistor is a p-type transistor.

[0117] Aspect 17: The device according to aspect 16, wherein: for accessing a memory cell via a conductive pillar and a first bit line, the device is operable to bias the first bit line with a negative voltage during coupling of the conductive pillar and the first bit line; and for accessing a memory cell via a conductive pillar and a second bit line, the device is operable to bias the second bit line with a positive voltage during coupling of the conductive pillar and the second bit line.

[0118] Aspect 18: The device according to aspect 17, wherein: for accessing a memory cell via a conductive pillar and a first bit line, the device is operable to isolate the conductive pillar from the second bit line; and for accessing a memory cell via a conductive pillar and a second bit line, the device is operable to isolate the conductive pillar from the first bit line.

[0119] Aspect 19: The apparatus according to any one of aspects 9 to 18, wherein each memory cell comprises a chalcogenide memory element.

[0120] A device is described. An overview of aspects of the device as described herein is provided below:

[0121] Aspect 20: A device comprising: a conductive pillar; a word line; a memory cell coupled between the conductive pillar and the word line; a first transistor having a first channel portion coupled between the conductive pillar and the first bit line; a second transistor having a second channel portion coupled between the conductive pillar and the second bit line; and a controller for performing an access operation on the memory cell, the controller being operable to cause the device to: couple the conductive pillar to the first bit line at least partially based on activating the first channel portion; isolate the conductive pillar from the second bit line at least partially based on deactivating the second channel portion; bias the word line with a first access voltage; and bias the first bit line with a second access voltage.

[0122] Aspect 21: The apparatus according to aspect 20, wherein: to activate the first transistor, the controller is operable to bias the first gate portion of the first transistor with a first voltage; and to deactivate the second transistor, the controller is operable to bias the second gate portion of the second transistor with a second voltage.

[0123] Aspect 22: The device according to aspect 21, wherein the first voltage and the second voltage are the same voltage.

[0124] Aspect 23: The device according to aspect 22, wherein: to activate the first transistor, the controller is operable to bias the first bit line when the second access voltage is greater than the same voltage; and to deactivate the second transistor, the controller is operable to bias the second bit line with the same voltage.

[0125] Aspect 24: The device according to aspect 22, wherein: to activate the first transistor, the controller is operable to bias the first bit line when the second access voltage is less than the same voltage; and to deactivate the second transistor, the controller is operable to bias the second bit line with the same voltage.

[0126] Aspect 25: The device according to any one of aspects 20 to 24, wherein, for performing a second access operation on a memory cell, the controller is operable to cause the device to: isolate the conductive pillar from the first bit line at least partially based on deactivating the first channel portion; couple the conductive pillar to the second bit line at least partially based on activating the second channel portion; bias the word line with a third access voltage having a first polarity opposite to the second polarity of the first access voltage; and bias the second bit line with a fourth access voltage having a third polarity opposite to the fourth polarity of the second access voltage.

[0127] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, the signal may represent a bus of signals, which may have various bit widths.

[0128] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to the relationship between components that enables the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if there is any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0129] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently unable to travel between components via a conductive path, and in which a signal can travel between components via a conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0130] The term "isolation" refers to a relationship between components in which signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0131] As used herein, the term "layer" or "level" refers to a layer or sheet of geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer or level may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0132] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0133] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET accordingly can make the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0134] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all implementable instances or all instances within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to" other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0135] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0136] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations.

[0137] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions described herein: a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor may be a microprocessor, but in alternative embodiments, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0138] As used herein (included in the claims), the word "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates a list containing endpoints, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0139] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used in this article, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. This combination also includes computer-readable media.

[0140] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: A conductive pillar extends through multiple layers of a memory array, wherein at each of the multiple layers, one or more memory cells of the memory array are coupled between the conductive pillar and a corresponding word line; A first transistor, operable to couple the conductive pillar to a first bit line based at least in part on a first voltage at the gate of the first transistor; as well as The second transistor is operable to couple the conductive pillar to the second bit line based at least in part on a second voltage at the gate of the second transistor.

2. The memory device according to claim 1, wherein: The first transistor is coupled between the first bit line and the first end of the conductive pillar, and The second transistor is coupled between the second bit line and the second end of the conductive pillar opposite to the first end.

3. The memory device according to claim 1, wherein: The first transistor is coupled between the first line and the end of the conductive pillar between the one or more memory cells and the substrate, and The second transistor is coupled between the second bit line and the end of the conductive pillar between the one or more memory cells and the substrate.

4. The memory device according to claim 1, wherein: The first transistor is coupled between the first line and the end of the conductive pillar opposite to the substrate, and The second transistor is coupled between the second bit line and the end of the conductive pillar opposite the substrate.

5. The memory device according to claim 1, further comprising: A first gate line coupled to the gate of the first transistor, wherein the first transistor is operable to couple the conductive pillar to the first bit line at least in part based on the first gate line being biased to the first voltage; as well as A second gate line coupled to the gate of the second transistor, wherein the second transistor is operable to couple the conductive pillar to the second bit line at least in part based on the second gate line being biased to the second voltage.

6. The memory device of claim 1, wherein the conductive pillar is coupled to a voltage source via a resistive coupling member having a first resistance greater than a second resistance associated with each of the memory cells.

7. The memory device of claim 6, wherein at least a portion of the resistive coupling element is connected to the conductive pillar between two of the plurality of layers of the memory array.

8. The memory device of claim 1, wherein the first transistor is an n-type transistor and the second transistor is a p-type transistor.

9. The memory device according to claim 8, wherein: To access one of the memory cells via the conductive pillar and the first bit line, the device is operable to bias the first bit line with a negative voltage during the coupling between the conductive pillar and the first bit line; and To access one of the memory cells via the conductive pillar and the second bit line, the device is operable to bias the second bit line with a positive voltage during the coupling between the conductive pillar and the second bit line.

10. The memory device according to claim 9, wherein: In order to access one of the memory cells via the conductive pillar and the first bit line, the device is operable to isolate the conductive pillar from the second bit line; and In order to access one of the memory cells via the conductive pillar and the second bit line, the device is operable to isolate the conductive pillar from the first bit line.

11. The memory device of claim 1, wherein each of the memory cells comprises a chalcogenide memory element.

12. A memory device comprising: Conductive support; Word lines; A memory cell coupled between the conductive pillar and the word line; A first transistor having a first channel portion coupled between the conductive pillar and the first bit line; The second transistor has a second channel portion coupled between the conductive pillar and the second bit line; as well as A controller for performing access operations on the memory cells, the controller being operable to cause the device to: The conductive pillar is coupled to the first bit line at least in part based on activating the first channel portion; The conductive pillar is isolated from the second bit line, at least in part, based on deactivating the second channel portion; The first bit line is biased using the first access voltage; as well as The word line is biased using a second access voltage.

13. The memory device according to claim 12, wherein: To activate the first transistor, the controller is operable to cause the device to bias the first gate portion of the first transistor with a first voltage; and To deactivate the second transistor, the controller is operable to bias the second gate portion of the second transistor with a second voltage.

14. The memory device of claim 13, wherein the first voltage and the second voltage are the same voltage.

15. The memory device of claim 14, wherein: To activate the first transistor, the controller is operable to bias the first bit line when the first access voltage is greater than the same voltage; and To deactivate the second transistor, the controller can operate to bias the second bit line with the same voltage.

16. The memory device of claim 14, wherein: To activate the first transistor, the controller is operable to bias the first bit line when the first access voltage is less than the same voltage; and To deactivate the second transistor, the controller can operate to bias the second bit line with the same voltage.

17. The memory device of claim 12, wherein, for performing a second access operation on the memory cell, the controller is operable to cause the device to: The conductive pillar is isolated from the first bit line, at least in part, based on deactivating the first channel portion; The conductive pillar is coupled to the second bit line at least in part based on activating the second channel portion; The second bit line is biased with a third access voltage, the third access voltage having a first polarity opposite to the second polarity of the first access voltage; as well as The word line is biased with a fourth access voltage, which has the opposite polarity to the second access voltage.

18. A method for memory operations, comprising: Accessing a memory cell coupled between a conductive pillar of the memory die and a word line of the memory die, wherein accessing the memory cell includes: The conductive pillar is coupled to the first bit line at least in part based on activating a first transistor between the conductive pillar and the first bit line; The conductive pillar is isolated from the second bit line, at least in part, based on deactivating the second transistor between the conductive pillar and the second bit line; The first bit line is biased using a first access voltage; and The word line is biased using a second access voltage.

19. The method of claim 18, wherein: Activation of the first transistor is based at least in part on biasing the gate of the first transistor with a first voltage; and Deactivating the second transistor is based at least in part on biasing the gate of the second transistor with a second voltage.

20. The method of claim 19, wherein the first voltage and the second voltage are the same voltage.

21. The method of claim 20, wherein: The first transistor is associated with a first channel type; and The second transistor is associated with a second channel type that is different from the first channel type.

22. The method of claim 20, wherein: Activating the first transistor is based at least in part on biasing the first bit line when the first access voltage is greater than the same voltage; and Deactivating the second transistor is based at least in part on biasing the second bit line with the same voltage.

23. The method of claim 20, wherein: Activating the first transistor is based at least in part on biasing the first bit line when the first access voltage is less than the same voltage; and Deactivating the second transistor is based at least in part on biasing the second bit line with the same voltage.

24. The method of claim 18, further comprising: After the access, the voltage difference between the conductive pillar and the ground node is reduced via a resistive coupling element having a first resistance greater than the second resistance associated with the memory cell.

25. The method of claim 18, further comprising: During the access, the second conductive pillar is isolated from the first bit line at least in part based on deactivating the third transistor between the second conductive pillar and the first bit line; as well as During the access, the second conductive pillar is isolated from the second bit line at least in part based on deactivating the fourth transistor between the second conductive pillar and the second bit line.

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