Composite logic gate circuit, chip including the same, and electronic device

Abstract

A composite logic gate circuit, a chip comprising the same and an electronic device, the composite logic gate circuit comprising a driving circuit and having a signal output end and K signal input ends, a first end of the driving circuit being connected to the signal output end of the composite logic gate circuit and connected to a high-level power supply through a load circuit, and a second end of the driving circuit being connected to a low-level power supply, wherein the driving circuit comprises K first depletion-mode HEMT devices and L clamping devices, the K first depletion-mode HEMT devices are arranged into M and structures, the L clamping devices are arranged into M clamping units, each and structure corresponds to a clamping unit, M and L are positive integers, and K is an integer greater than or equal to 2. Through the embodiments of the present application, the composite logic gate circuit based on the depletion-mode field effect tube of the compound semiconductor substrate is constructed, the performance density and the function density of the high-end radio frequency system of the compound hybrid circuit can be improved, and the cost can be reduced and the reliability can be improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a composite logic gate circuit, a chip including the same, and an electronic device. Background Technology

[0002] Existing high-performance radio frequency (RF) or microwave / millimeter-wave devices and circuits mostly use compound devices as their core. For example, high-performance switches in mobile communication equipment use GaAs pHEMT technology, high-performance power amplifiers use GaAs pHEMT technology, power amplifiers and switches in 5G base stations mostly use GaN HEMT, high-end high-frequency instruments mostly use InP pHEMT devices or chips as core components, and high-performance radar systems also mainly use GaAs depletion-mode pHEMT or GaN depletion-mode HEMT as core RF devices. With the development of civilian high-frequency mobile communication, vehicle-to-everything (V2X) communication, and large satellite constellations, RF systems are developing towards higher performance density, higher functional integration, and greater flexibility.

[0003] However, in existing technologies, the driving control of compound devices or circuits (e.g., controlling the gate voltage of a field-effect transistor in a switching circuit or an amplifier) ​​typically requires additional Si-based or GeSiBiCMOS chips or circuits, which necessitates costly packaging technologies and more complex process flows. Furthermore, due to the differences in material properties between compound devices and Si or GeSi, such as their coefficients of thermal expansion and temperature-dependent behavior, it is difficult to achieve increased performance density and functional density. The high cost and system complexity associated with controlling RF circuits based on compound devices are gradually becoming bottlenecks hindering their application development.

[0004] Therefore, finding integrated drive or control functions based on high-performance RF or microwave / millimeter-wave compound devices is beneficial for solving the above problems. Summary of the Invention

[0005] This application provides a composite logic gate circuit, a chip including the same, and an electronic device.

[0006] According to one aspect, an embodiment of this application provides a composite logic gate circuit, which includes a driving circuit and has a signal output terminal and K signal input terminals. A first terminal of the driving circuit is connected to the signal output terminal of the composite logic gate circuit and connected to a high-level power supply via a load circuit. A second terminal of the driving circuit is connected to a low-level power supply. The first terminal of the load circuit is connected to both the first terminal of the driving circuit and the signal output terminal of the composite logic gate circuit, and the second terminal of the load circuit is connected to the high-level power supply. The driving circuit includes K first depletion-type HEMT devices and L clamping devices. The K first depletion-type HEMT devices are arranged on a compound semiconductor substrate and arranged in M ​​AND structures. The L clamping devices are arranged in M ​​clamping units, where each AND structure corresponds to one clamping unit. M and L are positive integers, and K is an integer greater than or equal to 2.

[0007] Each AND structure includes one or more first depletion-type HEMT devices, wherein the 1st to Mth AND structures respectively include K1, ..., K M The first depletion-type HEMT device, K1, ..., K M K1, ..., K are the same or different positive integers. M The sum equals K;

[0008] The gates of the K first depletion-type HEMT devices correspond one-to-one with the K signal input terminals of the composite logic gate circuit, and the gate of each of the K first depletion-type HEMT devices is connected to one of the corresponding K signal input terminals;

[0009] In an AND structure including multiple first depletion-type HEMT devices, the multiple first depletion-type HEMT devices in the AND structure are connected in series. The drain of the first first depletion-type HEMT device in the AND structure is connected to the first terminal of the driving circuit, the source of the last first depletion-type HEMT device in the AND structure is connected to the first terminal of a corresponding clamping unit, the drain of each other first depletion-type HEMT device in the AND structure is connected to the source of the previous first depletion-type HEMT device in the AND structure, and the source of each other first depletion-type HEMT device in the AND structure is connected to the drain of the next first depletion-type HEMT device in the AND structure. In an AND structure including a single first depletion-type HEMT device, the drain of the first depletion-type HEMT device is connected to the first terminal of the driving circuit, and the source of the first depletion-type HEMT device is connected to the first terminal of a corresponding clamping unit.

[0010] Each clamping unit includes one or more clamping devices, each clamping device having a first terminal and a second terminal, wherein the 1st to the Mth clamping units respectively include L1, ..., L...M A clamping device, L1, ..., L M For the same or different positive integers, L1, ..., L M The sum of them equals L;

[0011] In a clamping unit comprising multiple clamping devices, the multiple clamping devices in the clamping unit are connected in series, wherein the first end of the first clamping device in the clamping unit serves as the head end of the clamping unit, the second end of the last clamping device in the clamping unit serves as the tail end of the clamping unit, the first end of each other clamping device in the clamping unit is connected to the second end of the preceding clamping device in the clamping unit, and the second end of each other clamping device in the clamping unit is connected to the first end of the following clamping device in the clamping unit, wherein the tail end of the clamping unit is connected to the second end of the drive circuit; in a clamping unit comprising one clamping device, the first end of the clamping device serves as the head end of the clamping unit, the second end of the clamping device serves as the tail end of the clamping unit and is connected to the second end of the drive circuit.

[0012] According to another aspect, embodiments of this application provide a chip including the composite logic gate circuit as described in any of the above embodiments.

[0013] According to another aspect, embodiments of this application provide an electronic device including a chip as described in any of the foregoing embodiments.

[0014] This application provides a composite logic gate circuit, a chip including the same, and an electronic device. The composite logic gate circuit uses depletion-mode field-effect transistors (MOSFETs) disposed on a compound semiconductor substrate, achieving a simple structure and small size. Furthermore, by using depletion-mode field-effect transistors on a compound semiconductor substrate to construct the logic gate circuit, it is easy to integrate it with mainstream compound RF circuits or microwave / millimeter-wave circuits. This can improve the performance density and functional density of high-end RF systems using hybrid compound circuits, and also helps to reduce costs and improve reliability. Attached Figure Description

[0015] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a composite logic gate circuit according to an embodiment of this application;

[0017] Figure 2This is a schematic diagram of a composite logic gate circuit according to another embodiment of this application;

[0018] Figure 3 This is a schematic diagram of the structure of a driving circuit according to an embodiment of this application;

[0019] Figures 4A-4D This is a schematic diagram of the clamping unit according to an embodiment of this application;

[0020] Figure 5 This is a schematic diagram of a level conversion circuit according to an embodiment of this application;

[0021] Figure 6 This is a schematic diagram of the structure of a load circuit according to an embodiment of this application;

[0022] Figure 7 This is a schematic diagram of the structure of an NOR gate logic circuit provided in an embodiment of this application;

[0023] Figure 8 This is a schematic diagram of the structure of a NAND gate logic circuit provided in an embodiment of this application;

[0024] Figure 9 This is a schematic diagram of the structure of an AND, OR, NOT gate logic circuit according to an embodiment of this application;

[0025] Figure 10 This is a schematic diagram of a chip according to an embodiment of this application;

[0026] Figure 11 This is a schematic diagram of an electronic device according to an embodiment of the present application. Detailed Implementation

[0027] To make the technical problems to be solved, the technical solutions, and the beneficial effects of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely some embodiments of this application, not all embodiments, and the specific embodiments described herein are used to explain this application and are not intended to limit this application.

[0028] It should be noted that when a component is referred to as "fixed to" or "set on" another component, it can be directly on or indirectly on the other component. When a component is referred to as "connected to" another component, it can be directly connected to the other component or indirectly connected to it, for example, through a third component or a connection medium such as a cable.

[0029] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0031] Figure 1 This is a schematic diagram of a composite logic gate circuit according to an embodiment of the present application. In this embodiment, the composite logic gate circuit 100 includes a driver circuit 1 and a load circuit 2, and has a signal output terminal P. out and K signal input terminals P in-1 ... P in-K K is an integer greater than or equal to 2. The first terminal 10 of the driver circuit 1 is connected to the output terminal P. out And it is connected to the high-level power supply VH through the load circuit 2, wherein the first terminal 20 of the load circuit 2 is connected to the first terminal 10 of the drive circuit 1 and the signal output terminal P of the composite logic gate circuit 100. out The second terminal 21 of the load circuit 2 is connected to a high-level power supply VH. The second terminal 11 of the drive circuit 1 is connected to a low-level power supply, i.e. Figure 1 The low-level power supply VL is shown in the diagram. The input signal is at one of the K signal input terminals P. in-1 ... P in-K The components are connected to the drive circuit 1 via ports 12-1, ..., 12-K respectively, and connected to the output terminal P. out The output signal is displayed at the output location. The composite logic gate circuit 100 has two or more signal inputs and forms a multivariable Boolean function logic, hence it is called a composite logic gate circuit.

[0032] In some embodiments, the level of the input signal generated by the external signal source may not be suitable for the drive circuit 1 and cannot be directly input to the drive circuit 1. In this case, a level conversion circuit needs to be added between the drive circuit 1 and the K signal input terminals to convert the input signal into a suitable input logic signal. Figure 2 Such an embodiment is shown. Figure 2As shown, the composite logic gate circuit 100 also includes K level conversion circuits 3-1, ..., 3-K. These K level conversion circuits correspond one-to-one with the K signal input terminals of the composite logic gate circuit (and the K ports 12-1, ..., 12-K of the driver circuit 1). Each level conversion circuit 3-i (i = 1, 2, ..., K) is connected to the corresponding port 12-i (i = 1, 2, ..., K) of the driver circuit 1 and to the corresponding signal input terminal P. in-i (i = 1, 2, ..., K) is used to convert the signal input to the input terminal of the signal into an input logic signal suitable for the drive circuit 1.

[0033] Figure 3 A schematic diagram of a driving circuit according to an embodiment of this application is shown. Figure 3 As shown, the drive circuit 1 includes K depletion-mode HEMT devices (to distinguish them from the depletion-mode HEMTs in other modules, they are referred to as the first depletion-mode HEMT device, i.e. Figure 3 The T shown 1-1 ... T 1-K1 ... T M-1 ... T M-KM ) and L clamping devices ( Figure 3 The D shown 1-1 ... D 1-L1 ... D M-1 ... D M-LM K first depletion-type HEMT devices are arranged on a compound semiconductor substrate and are arranged as M AND structures 13-1, ..., 13-M. L clamping devices are arranged as M clamping units 14-1, ..., 14-M, where each AND structure corresponds to one clamping unit, M and L are positive integers, and K is an integer greater than or equal to 2.

[0034] The K first depletion-type HEMT devices correspond one-to-one with the K signal input terminals of the composite logic gate circuit 100. In the case of a level-shifting circuit, they also correspond to the K level-shifting circuits (such as...). Figure 2 (As shown) They correspond one-to-one. The gate of each of the K first depletion-type HEMT devices is connected to one of the corresponding K signal input terminals, or connected to the corresponding signal input terminal through a corresponding level conversion circuit. For example, each level conversion circuit is connected between the gate of the corresponding first depletion-type HEMT device and the signal input terminal corresponding to that first depletion-type HEMT device, and is used to convert the signal input to that signal input terminal into an input logic signal (i.e., a gate drive signal) suitable for that first depletion-type HEMT device.

[0035] Each AND structure 13-i (i = 1, 2, ..., M) includes one or more first depletion-type HEMT devices, wherein the 1st to the Mth AND structures respectively include K1, ..., K M The first depletion-type HEMT device, K1, ..., K M K1, ..., K are the same or different positive integers. M The sum equals K. That is, each AND structure can include a different number of depletion-type HEMT devices, or it can include the same number of depletion-type HEMT devices. Figure 3 Each AND structure is shown as including a row of depletion-type HEMT devices, but this is not an attempt to limit the physical location distribution of the depletion-type HEMT devices in each AND structure. It is understood that the depletion-type HEMT devices in each AND structure do not have to be arranged in a row, but can be distributed in any suitable location, as long as their connection relationship satisfies the following description.

[0036] When the AND structure includes multiple first depletion-type HEMT devices, these devices are connected in series. Except for the gates connected to the corresponding signal input terminals, the drains and sources of the multiple first depletion-type HEMT devices in the AND structure are connected in series sequentially. Two depletion-type HEMT devices located at the front and rear ends of this series are respectively connected to the first terminal 10 of the drive circuit 1 and the corresponding clamping unit. Here, the first depletion-type HEMT device connected to the first terminal 10 of the drive circuit 1 in the AND structure is referred to as the first first depletion-type HEMT device, and the first depletion-type HEMT device connected to the corresponding clamping unit in the AND structure is referred to as the last first depletion-type HEMT device. The direction towards the first first depletion-type HEMT device is referred to as "front," and the direction towards the last first depletion-type HEMT device is referred to as "rear." It is understood that the above definitions are for ease of explanation only, and other appropriate definitions may be used.

[0037] Specifically, the drain of the first depletion-type HEMT device in the structure is connected to the first terminal 10 of the drive circuit 1, and the source of the last depletion-type HEMT device in the structure is connected to the first terminal of a corresponding clamping unit (e.g., ...). Figure 3 As shown and described below, terminal 141-i (i = 1, 2, ..., M) is connected to the drain of each other first depletion-type HEMT device in the structure and to the source of the previous first depletion-type HEMT device in the structure, and the source of each other first depletion-type HEMT device in the structure is connected to the drain of the next first depletion-type HEMT device in the structure.

[0038] Taking structure 13-1 as an example, it includes K1 first depletion-type HEMT devices T1-1 ... T 1-K1 These K1 first depletion-type HEMT devices are connected in series. The first first depletion-type HEMT device T... 1-1 The drain of the device is connected to the first terminal 10 of the drive circuit 1, and the last first depletion-type HEMT device T 1-K1 The drain is connected to the start end 141-1 of the corresponding clamping unit 14-1. This is similar to the other first depletion-type HEMT devices in structure 13-1. Figure 3 The drain and source (not shown in the diagram) are connected in series.

[0039] When the AND structure includes a first depletion-type HEMT device, the first and last first depletion-type HEMT devices of the AND structure are both the first depletion-type HEMT device, and there are no other first depletion-type HEMT devices, then the drain of the first depletion-type HEMT device is connected to the first terminal of the drive circuit, and the source of the first depletion-type HEMT device is connected to the first terminal of a corresponding clamping unit.

[0040] In one embodiment, the K first depletion-type HET devices included in the driving circuit 1 are formed on the same compound semiconductor substrate. The compound semiconductor substrate may include at least one of GaAs, GaN, and InP.

[0041] Similar to the structure, each clamping unit also includes one or more clamping devices, each clamping device having a first end and a second end, wherein the 1st to Mth clamping units respectively include L1, ..., L... M A clamping device, L1, ..., L M For the same or different positive integers, L1, ..., L M The sum equals L. That is, each clamping unit can include a different number of clamping devices, or it can include the same number of clamping devices. Similarly, in Figure 3 Each clamping unit is shown as comprising a row of clamping devices, but this is not an attempt to limit the physical location distribution of the clamping devices in each clamping unit. It is understood that the clamping devices in each clamping unit do not necessarily have to be arranged in a row, but can be distributed in any suitable location, as long as their connection relationship satisfies the following description.

[0042] When a clamping unit includes multiple clamping devices, these clamping devices are connected in series. The first and second ends of the clamping devices in the clamping unit are connected in series sequentially, with the two clamping devices at each end of the series connected to the corresponding AND structure and the second end 11 of the drive circuit 1, respectively. Here, the clamping device connected to the corresponding AND structure is called the first clamping device of the clamping unit, the clamping device connected to the second end 11 of the drive circuit 1 is called the last clamping device of the clamping unit, the first end of the first clamping device is called the head end of the clamping unit, the second end of the last clamping device is called the tail end of the clamping unit, the direction towards the first clamping device is called "forward," and the direction towards the last clamping device is called "backward." It is understood that the above definitions are for ease of explanation only, and other appropriate definitions may be used. Figure 3 As shown, for a clamping unit including multiple clamping devices, except for the first clamping device and the last clamping device, the first end of each other clamping device in the clamping unit is connected to the second end of the previous clamping device in the clamping unit, and the second end of each other clamping device in the clamping unit is connected to the first end of the next clamping device in the clamping unit. The head end of the clamping unit is connected to the source corresponding to the last first depletion-type HEMT device in the structure, and the tail end of the clamping unit is connected to the second end 11 of the drive circuit 1.

[0043] Taking clamping unit 14-1 as an example, it includes L1 clamping devices D 1-1 ... D 1-L1 .like Figure 3 As shown, the first clamping device D 1-1 The first end serves as the head end 141-1 of the clamping unit 14-1, and is connected to the corresponding last first depletion-type HEMT device T of structure 13-1. 1-K1 The source. The last clamping device D. 1-L1 The second end is connected to the second end 11 of the drive circuit 1. Each other clamping device of clamping unit 14-1 ( Figure 3 The second end (not shown) is connected to the first end of the next clamping device in clamping unit 14-1.

[0044] In a clamping unit that includes a clamping device, the first end of the clamping device serves as the head end of the clamping unit, and the second end of the clamping device serves as the tail end of the clamping unit and is connected to the second end 11 of the drive circuit 1.

[0045] In some embodiments, the clamping device may be a compound diode, wherein the anode of the diode serves as the first end of the clamping device and the cathode of the diode serves as the second end of the clamping device. Figure 4AA clamping unit 14-i (i = 1, 2, ..., L) consisting of multiple diodes as clamping devices is shown, wherein the positive terminal of the first diode serves as the head 141-i of the clamping unit 14-i, and the negative terminal of the last diode serves as the tail 142-i of the clamping unit 14-i.

[0046] In some embodiments, the clamping device can also be a depletion-mode HEMT device (e.g., Figure 4B-4D To distinguish it from the depletion-type HEMT devices in other modules, it is called the second depletion-type HEMT device. The first end of the clamping device is the gate of the second depletion-type HEMT device, and the second end of the clamping device can be any of the following:

[0047] The drain of the second depletion-type HEMT device serves as the second terminal of the clamping device; or

[0048] The source of the second depletion-mode HEMT device serves as the second terminal of the clamping device; or

[0049] The drain and source of the second depletion-type HEMT device are shorted together as the second terminal of the clamping device.

[0050] Figure 4B An embodiment is shown in which the drain of the second depletion-type HEMT device is used as the second terminal of the clamping device, wherein the gate of each second depletion-type HEMT device in the clamping unit 14-i (i = 1, 2, ..., L) is used as the first terminal of the clamping device, the drain is used as the second terminal, and the source can be left floating.

[0051] Figure 4C An embodiment is shown in which the source of the second depletion-type HEMT device is used as the second terminal of the clamping device, wherein the gate of each second depletion-type HEMT device in the clamping unit 14-i (i = 1, 2, ..., L) is used as the first terminal of the clamping device, the source is used as the second terminal, and the drain can be left floating.

[0052] Figure 4D An embodiment is shown in which the drain and source of a second depletion-type HEMT device are shorted together as the second end of a clamping device, wherein the gate of each second depletion-type HEMT device in clamping unit 14-i (i = 1, 2, ..., L) serves as the first end of the clamping device, and the drain and source are shorted together as the second end of the clamping device.

[0053] Figure 5 A schematic diagram of a level conversion circuit 3-i (i = 1, 2, ..., K) according to an embodiment of this application is shown. (See previous reference...) Figure 2 As described above, a level shifting circuit can be provided between the signal input terminal of the composite logic gate circuit 100 and the gate of the corresponding first depletion-type HEMT device. For example... Figure 5As shown, in this embodiment, each level conversion circuit 3-i includes: N i (i = 1, 2, ..., K) level shifting elements Z1, ..., Z2 Ni First resistor R 1i The second resistor R 2i and the third resistor R 3i , where N i (i = 1, 2, ..., K) are positive integers, and N1, ..., N K These can be the same or different positive integers. That is, each level shifting circuit may include the same or different number of level shifting elements from other level shifting circuits. Additionally, different level shifting circuits may have different values ​​for the first, second, or third resistors.

[0054] N i One level shifting element is used to shift the level of the input signal, R 1i R 2i and R 3i It acts as a pressure divider. N i A level shifting element and the first resistor R 1i They are connected in series to form a series circuit, N i A level shifting element and a first resistor R 1i Each of the elements serves as a series unit in this series circuit, thus forming N. i +1 series unit. First resistor R 1i It can be connected at the beginning (i.e., as the first series unit) or the end (i.e., as the last series unit) of a series circuit, or it can be connected to N. i Between any two level shifting elements in a given set of level shifting elements. In some embodiments, the first resistor R 1i and N i The positional relationship of each level shifting element can be varied according to design requirements. Figure 5 In the illustrated embodiment, the first resistor R 1i Connected at the end of the series circuit as the last series unit, i.e., the first resistor R 1i The second terminal and the second resistor R 2i The first terminal and the third resistor R 3i The first end is connected together.

[0055] Specifically, N i +1 In the series unit, the first terminal of the first series unit is connected to the corresponding signal input terminal P among the K signal input terminals of the composite logic gate circuit 100. in-i N i The second terminal of the last series unit in the +1 series connection is connected to the second resistor R. 2i The first terminal and the third resistor R3i The first end, N i In the +1 series unit, the first end of each other series unit is connected to the second end of the previous series unit, N i +1 In the series unit, the second terminal of each other series unit is connected to the first terminal of the next series unit. The third resistor R 3i The second terminal is connected to a reference level signal Vf, and the second resistor R 2i The second terminal is connected to the gate of the corresponding first depletion-type HEMT device to input the converted gate drive signal to the first depletion-type HEMT device. The level conversion circuit 3-i divides and shifts the input signal according to the reference level signal Vf to convert it into a suitable gate drive signal.

[0056] In some embodiments, the level shifting element is a compound-based diode, with the anode of the diode serving as the first end of the series unit and the cathode of the diode serving as the second end of the series unit.

[0057] In some embodiments, the level shifting element is a depletion-mode HEMT device. To distinguish it from depletion-mode HEMT devices in other modules, it is referred to as a third depletion-mode HEMT device. The gate of the third depletion-mode HEMT device serves as the first terminal of the series unit, and the second terminal of the series unit is any of the following:

[0058] The drain of the third depletion-mode HEMT device serves as the second terminal of the series unit; or

[0059] The source of the third depletion-type HEMT device serves as the second terminal of the series unit; or

[0060] The drain and source of the third depletion-type HEMT device are shorted together to form the second end of a series unit.

[0061] In some embodiments, the multiple level conversion circuits included in the driving circuit 1 can be connected to corresponding reference level signals Vf respectively, or they can share a single reference level signal Vf. The reference level signal Vf can be a level signal that is the same as or different from the low-level power supply VL. For example, it can be a signal of ground, VL, or other negative voltage power supply.

[0062] In some embodiments, the first resistor R can be adjusted. 1i The resistance value, the second resistor R 2i The resistance value and the third resistor R 3i The resistance value is adjusted to optimize power consumption.

[0063] In specific applications, the specific structures of the multiple level-shifting circuits included in the composite logic gate circuit 100 can be designed to be the same or different depending on the application scenario or user requirements. For example, the structure of the level-shifting circuit connected to the gate of the first depletion-type HEMT device in the same structure is the same.

[0064] Figure 6 A schematic diagram of a load circuit according to an embodiment of this application is shown. (Refer to the preceding text.) Figure 2 The first terminal 10 of the driving circuit 1 can be connected to a high-level power supply VH through the load circuit 2, and the first terminal 20 of the load circuit 2 is connected to the first terminal 10 of the driving circuit 1 and the signal output terminal P of the composite logic gate circuit 100. out The second terminal 21 of the load circuit 2 is connected to a high-level power supply VH. The load circuit 2 may include a fourth depletion-type HEMT device 22 and a clamping choke resistor 23. The drain of the fourth depletion-type HEMT device 22 is connected to the second terminal 21 of the load circuit 2, the source of the fourth depletion-type HEMT device 22 is connected to the first terminal of the clamping choke resistor 23, and the gate of the fourth depletion-type HEMT device and the second terminal of the clamping choke resistor 23 are connected to the first terminal 20 of the load circuit 2.

[0065] By connecting a clamping choke resistor 23 between the fourth depletion-type HEMT device 22 and the depletion-type HEMT device of the drive circuit 1, the clamping choke resistor 23 can adjust the voltage difference between the source of the fourth depletion-type HEMT device 22 and the drain of the depletion-type HEMT device of the drive circuit 1, and reduce the source current of the fourth depletion-type HEMT device 22, thereby achieving dynamic adjustment of the impedance value of the load circuit 2.

[0066] When any of the components in the drive circuit 1 is turned on, current is generated in the clamping choke resistor 23. As the current increases, the voltage across the clamping choke resistor 23 causes the absolute value of the negative gate-source voltage of the fourth depletion-type HEMT device 22 to increase, thereby increasing the load impedance. Together with the drive circuit 1, this increases the output voltage of the RF signal at the P terminal. out The voltage of the signal output decreases as the impedance ratio of the load circuit and the drive circuit increases.

[0067] In the above embodiments, the terms "high-level power supply" and "low-level power supply" are relative. The following are examples of combinations of high-level and low-level power supplies applicable to this application:

[0068] A high-level power supply is a positive voltage, and a low-level power supply is ground; or

[0069] The high-level power supply is ground, and the low-level power supply is a negative voltage supply; or

[0070] A high-level power supply is a positive voltage supply, and a low-level power supply is a negative voltage supply.

[0071] In addition, in some embodiments, the first depletion-type HEMT device, the second depletion-type HEMT device, the third depletion-type HEMT device and the fourth depletion-type HEMT device are all depletion-type field-effect transistors based on compound semiconductor substrates.

[0072] In various embodiments of this application, composite logic gate circuits can be constructed based on depletion-type compound field-effect transistors. When M and K have different values, the composite logic gate circuits exhibit different operational logic. For example, when M = 1 and K ≥ 2, the logic gate circuits combine... Figure 1-6 The aforementioned composite logic gate circuit is called a NAND gate logic circuit, where when M≥2, K1=K2=……=K M When = 1, combine Figure 1-6 The aforementioned composite logic gate circuit is called a NOR gate logic circuit, where M≥2, K1, K2, ..., K M When any one of them is greater than or equal to 2, combine Figure 1-6 The aforementioned composite logic gates are AND, OR, NOT gates, and so on. More complex combinational and sequential logic circuits can be constructed based on these logic gates, and a simple external TTL control signal can be used to control the operating state of the compound circuit. Furthermore, these composite logic gates or combinational / sequential logic circuits can be integrated with compound RF microwave circuits onto the same chip. As an example and not a limitation, the compound semiconductor substrate may include GaAs, GaN, or InP.

[0073] Figure 7 A schematic diagram of a NOR gate logic circuit according to an embodiment of this application is shown. For Figure 3 In the driving circuit embodiment, when M≥2, K1=K2=……=K M When = 1, the drive circuit becomes Figure 7 As shown, such a drive circuit 1, together with the load circuit 2 and the level conversion circuits 3-1, ..., 3-M, constitutes a... Figure 7 In the embodiment of the OR NOT gate logic circuit, the load circuit 2 is as previously referenced. Figure 6 The level conversion circuits 3-1, ..., 3-M are as described in the previous reference. Figure 5 As described. Figure 7 As shown, the drive circuit 1 includes M depletion-type HEMT devices T 1-1 T 2-1 ... T M-1 Each of the structures 13-1, ..., 13-M includes only one depletion-type HEMT device. The drive circuit 1 also includes clamping units 14-1, ..., 14-M corresponding to structures 13-1, ..., 13-M, respectively. Figure 7The clamping units 14-1, ..., 14-M are exemplarily shown as each including only one clamping device; it is understood that they may also include multiple clamping devices.

[0074] exist Figure 7 In this embodiment, the composite logic gate is a NOR gate logic circuit, with each input terminal P... in-1 ... P in-M Each location has a corresponding input signal V in-1 ... V in-M ,according to Figure 7 The composite logic gate circuit in the embodiment performs NOR logic processing and outputs a NOT logic signal at the output terminal P. out The Boolean function that outputs the corresponding input logic signal is used as the output signal: When the input signal V in-1 ... V in-M When any one of them is high, Figure 7 The output V of the OR NOT gate logic circuit out It is low level when the input signal V in-1 ... V in-M When both are low level, Figure 7 The output V of the OR NOT gate logic circuit out It is at a high level. Its working principle will be explained below.

[0075] like Figure 7 As shown, in any level conversion circuit 3-i (i = 1, ..., M), the first resistor R 1i The second terminal, the second resistor R 2i The first terminal and the third resistor R 3i The common connection point of the first end is A. i Point, second resistor R 2i The second terminal and the common junction of the corresponding first depletion-type HEMT device are B. i Assume A i The voltage signal at point V Ai And assume any signal input terminal P in-i The input voltage signal at (i = 1, ..., M) is V in V on Let N be the on-state voltage of the level shifting element in the level conversion circuit corresponding to the signal input terminal, and N be the number of level shifting elements and be a positive integer. Then:

[0076] V Ai =(V in -N*V on -V f )*R 3i / (R 1i +R 3i )+Vf ,

[0077] Where R 1i and R 3i Let V be the resistance values ​​of the first and third resistors in the level conversion circuit, respectively. f It is the voltage value of the reference level signal Vf.

[0078] Because the current flows through the second resistor R 2i The current is relatively small, therefore point B... i Voltage V at point Bi Approximately equal to point A i Voltage V at point Ai .

[0079] When the input voltage signal V in When it is low, the voltage V Ai The first depletion-mode HEMT device is turned off when the voltage difference with VL is less than the sum of the threshold voltage of the corresponding first depletion-mode HEMT device and the threshold voltage of the clamping device. Figure 7 When all first depletion-type HEMT devices / structures are turned off (i.e., all input voltage signals are low), the signal output terminal P... out Output voltage signal V at the location out It is a high level.

[0080] When the input voltage signal V in When V increases, Ai It also increases when V Ai When the voltage difference with VL increases to a level greater than the sum of the threshold voltage of the corresponding first depletion-type HEMT device and the threshold voltage of the clamping device, the corresponding first depletion-type HEMT device and the clamping device simultaneously turn on. Figure 7 When any one or more of the first depletion-type HEMT devices and their corresponding clamping devices are turned on, the output voltage signal V out It begins to descend. With V... Ai Continue to increase, V out The voltage gradually decreases until it approaches the sum of the threshold voltage of the clamping device and the voltage value of VL.

[0081] Specifically, on the one hand, when a high-level input logic signal is connected to the gate of the first depletion-type HEMT device corresponding to any signal input terminal, the first depletion-type HEMT device is turned on, and the gate voltage of the fourth depletion-type HEMT device 22 in the load circuit 2 is a low-level voltage, that is, the output signal is low-level. The voltage difference between the gate and source of the fourth depletion-type HEMT device 22 can be adjusted by the clamping choke resistor 23 to be equal to the threshold voltage of the fourth depletion-type HEMT device 22, so as to ensure that the static current between the source of the fourth depletion-type HEMT device 22 and the drain of the first depletion-type HEMT device is small, and to prevent the fourth depletion-type HEMT device 22 from conducting, so that the gate of the fourth depletion-type HEMT device 22 outputs a low-level signal V. out .

[0082] On the other hand, when a low-level input logic signal is input to the gate of the first depletion-type HEMT device corresponding to any signal input terminal, the first depletion-type HEMT device is turned off. When all first depletion-type HEMT devices / structures are turned off, the voltage difference between the gate and source of the fourth depletion-type HEMT device 22 is 0V and greater than the threshold voltage of the fourth depletion-type HEMT device 22. At this time, the fourth depletion-type HEMT device 22 is turned on, and the gate of the fourth depletion-type HEMT device 22 outputs a high-level signal V. out .

[0083] In some embodiments, the low-level voltage can be 0V and the high-level voltage can be 3.3V.

[0084] It should be noted that the input signal in this embodiment is compatible with TTL signals, the high level of the input signal is the TTL high level, and the low level of the input signal is the TTL low level; the high and low level standards of the output signal Vout change depending on the settings of the high-level power supply VH and the low-level power supply VL.

[0085] (1) When VH is a positive voltage source with voltage VDD and VL is ground, the output signal V out The low level is the on-state voltage of the clamping device, and the high level is the positive voltage, close to VDD.

[0086] For example, the high-level power supply VH is set to 3.3V, the low-level power supply to ground, and there is one level shifting element, with a second resistor R. 2i The first resistor is 384 ohms. 1i The third resistor R is 4921 ohms. 3i The current is 9780 ohms, and the clamping choke resistor 23 is 257 ohms. When the input signal V... in When the voltage is high, such as 3.3V, point A... i voltage V Ai The voltage is 1.518V, point B.i voltage V Bi The output signal V is 1.518V. out A voltage of 1.141V is used to achieve a low-level output. When the input signal V... in When the voltage is low, such as 0V, point A i voltage V A The voltage is 0V, point B. i voltage V Bi The output signal is 0V. out It is 3.276V, achieving a high-level output.

[0087] It is worth noting that the output signal V of the OR NOT gate logic circuit out When it drops by 10%, point A i voltage V Ai The voltage is approximately 0.4V, which has a low noise margin, so N is set accordingly. i A level shifting element improves noise margin, and the first resistor R is set. 1i and the third resistor R 3i The voltage division ratio achieves the inversion point of the input signal (i.e., V). out The point at which the high and low levels reverse is adjustable.

[0088] (2) When VH is ground and VL is a negative voltage source with voltage Vss, the output signal V out The low level is the sum of the clamping device's on-state voltage and the negative voltage Vss (output signal V). out The low level is a negative voltage value), output signal V out The high level is approximately 0V.

[0089] For example, the high-level power supply VH is set to ground, the low-level power supply VL is a negative voltage source with a voltage of Vss, and the negative voltage Vss is -4V. There are four level shifting elements, and the second resistor R... 2i The first resistor is 384 ohms. 1i The third resistor R is 1464 ohms. 3i The current is 5731 ohms, and the clamping choke resistor 23 is 257 ohms. When the input signal V... in For a high level, such as 3.3V, the voltage V Ai -3.1V, the same voltage V Bi The voltage is -3.1V, and the output signal V is... out A voltage of -2.84V is used to achieve a low-level output. When the input signal V... in When it is low level, such as 0V, the voltage V Ai It is -3.9V, the same voltage V Bi The output signal V is -3.9V. out A value of -0.1V is used to achieve a high-level output.

[0090] It is worth noting that when the output signal of the first depletion-type HEMT device drops by 10%, the input signal V in Approximately 1V, voltage V Bi The voltage is approximately -3.6V, so N level shifting elements are used to adapt to the TTL signal level, and a second resistor R is set. 2i and the third resistor R 3i The inversion point of the input signal is adjustable.

[0091] (3) When VH is a positive voltage power supply and VL is a negative voltage power supply, the output signal V out The high level is VH, and the low level is VL plus about 1V.

[0092] Figure 8 A schematic diagram of a NAND gate logic circuit according to an embodiment of this application is shown. For Figure 3 In the embodiment of the driving circuit, when M=1 and K1≥2, the driving circuit becomes Figure 8 As shown, such a drive circuit 1, together with the load circuit 2 and the level conversion circuits 3-1, ..., 3-K1, constitutes... Figure 8 The NAND gate logic circuit embodiment in the example, wherein load circuit 2 is as previously referenced. Figure 6 The level conversion circuit is as described in the previous reference. Figure 5 As described. Figure 8 As shown, the drive circuit 1 includes K1 first depletion-type HEMT devices T 1-1 T 1-2 ... T 1-K1 These first depletion-type HEMT devices are connected in series to form a structure 13-1. The drive circuit 1 also includes a clamping unit 14-1 corresponding to structure 13-1. Figure 8 The clamping unit 14-1 is exemplarily shown as including only one clamping device, but it is understood that it may also include multiple clamping devices.

[0093] exist Figure 8 In the embodiment, at each input terminal P in-1 ... P in-K1 Each location has a corresponding input signal V in-1 ... V in-K1 When these input signals V in-1 ... V in-K1 When any one or more of the values ​​in the AND gate are not high, the corresponding first depletion-mode HEMT device is not turned on, and the entire AND structure 13-1 is not turned on. Therefore, in conjunction with the... Figure 7 As can be seen from the working principle description, the output signal V at this time out It is high level. When the input signal V in-1 ... Vin-K1 When all are high, all first depletion-mode HEMT devices are turned on, thus the entire interconnect structure 13-1 is turned on. Therefore, in conjunction with the... Figure 7 As can be seen from the working principle description, the output signal V at this time out It is at a low level. Therefore, it can be seen that... Figure 8 The working logic of the compound logic gate circuit is a NAND gate logic, which operates on the input terminal P. in-1 ... P in-K1 Input signal V at the location in-1 ... V in-K1 Perform AND and NOT logic processing and output P at the output terminal. out The Boolean function that outputs the corresponding input logic signal is used as the output signal:

[0094] Figure 9 A schematic diagram of an AND, OR, and NOT gate logic circuit according to an embodiment of this application is shown. For Figure 3 In the embodiment of the driving circuit, when M=2 and K1=K2=2, the driving circuit becomes Figure 9 As shown, such a drive circuit 1, together with the load circuit 2 and the level conversion circuits 3-1, ..., 3-4, constitutes... Figure 9 The AND, OR, and NOT gate logic circuit embodiment in the example, wherein the load circuit 2 is as previously referred to. Figure 6 As mentioned above, each level conversion circuit is referenced in the previous document. Figure 5 As stated above. It should be understood that, Figure 9 This is one exemplary embodiment of the AND-OR-NOT gate logic circuit according to this application, and is not the only embodiment of the AND-OR-NOT gate logic circuit. Figure 9 As shown, the drive circuit 1 includes four depletion-type HEMT devices T 1-1 T 1-2 T 2-1 T 2-2 T 1-1 and T 1-2 Connected together to form a structure 13-1, T 2-1 and T 2-2 These are connected in series to form structure 13-2. The drive circuit 1 also includes clamping units 14-1 and 14-2, which correspond to structures 13-1 and 13-2 respectively. Figure 9 The clamping units 14-1 and 14-2 are shown exemplarily as each including only one clamping device; it is understood that they may also include multiple clamping devices.

[0095] exist Figure 9 In the embodiment, at each input terminal P in-1 P in-2 P in-3 P in-4Each location has a corresponding input signal V in-1 V in-2 V in-3 V in-4 When V in-1 and V in-2 The circuit will only conduct when both voltage levels are high, and when V... in-3 and V in-4 Only when both are at high level will structure 13-2 conduct, therefore V in-1 and V in-2 For the relationship between and, V in-3 and V in-4 It is also an AND relationship. When at least one of the two AND structures 13-1 and 13-2 is active, referring to the previous reference... Figure 7 The description of the output signal V out It is at a low level. When both structures 13-1 and 13-2 are not conducting, refer to the previous reference. Figure 7 The description of the output signal V out It is at a high level. Therefore, it can be seen that... Figure 9 The working logic of the compound logic gate circuit is AND-OR-NOT gate logic, which operates on input terminal P. in-1 P in-2 P in-3 P in-4 Input signal V at the location in-1 V in-2 V in-3 V in-4 Perform AND, OR, and NOT logic processing and output P. out The Boolean function that outputs the corresponding input logic signal is used as the output signal:

[0096] The composite logic gate circuits provided in this application utilize depletion-mode field-effect transistors (MOSFETs) on compound semiconductor substrates, achieving a simple structure and small size. Furthermore, using MOSFETs on compound semiconductor substrates to construct logic gate circuits facilitates integration with mainstream compound RF circuits or microwave / millimeter-wave circuits, improving the performance density and functional density of high-end RF systems using hybrid compound circuits. Additionally, the composite logic gate circuits according to this application can be integrated with compound RF circuits or microwave / millimeter-wave circuits, allowing direct driving and control of compound circuits without the need for additional Si-based or GeSi BiCMOS chips or circuits. This reduces the cost and improves the reliability of compound RF or microwave / millimeter-wave circuits.

[0097] This application also provides a chip including the composite logic gate circuits described above, and an electronic device including such a chip. Figure 10 and Figure 11Schematic diagrams of each are shown. For example... Figure 10 As shown, chip 1000 may include a composite logic gate circuit 100, wherein the composite logic gate circuit 100 may be any embodiment of the composite logic gate circuit described above. In one example, chip 1000 may include one or more composite logic gate circuits 100.

[0098] Chips including the composite logic gate circuit embodiments of this application can be used in electronic devices. For example... Figure 11 As shown, the electronic device 1100 includes, as Figure 10 The chip 1000 is shown. The electronic device 1100 can be a wireless device or any other electronic device that can use the composite logic gate circuits according to the embodiments of this application.

[0099] Wireless devices can be user equipment (UE), mobile stations, terminals, access terminals, subscriber units, base stations, etc. Wireless devices can also be cellular phones, smartphones, tablets, wireless modems, personal digital assistants (PDAs), handheld devices, laptops, smartbooks, netbooks, cordless phones, wireless local loop (WLL) stations, Bluetooth devices, etc. Wireless devices can communicate with wireless communication systems or receive signals from broadcast stations. Wireless devices can support one or more wireless communication technologies (e.g., 5G, LTE, CDMA2000, WCDMA, TD-SCDMA, GSM, 802.11, millimeter wave, etc.).

[0100] Those skilled in the art will understand that information and signals can be represented or processed using any of a variety of different technologies and processes. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0101] It should be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0102] Unless the context otherwise indicates, throughout the specification and claims, the words “comprising,” “including,” etc., shall be interpreted broadly as inclusive rather than exclusive or exhaustive; that is, meaning “including but not limited to.” Conditional language used herein, such as “may,” “for example,” etc., unless specifically stated or otherwise understood according to the context, is generally intended to indicate that some embodiments include, while others do not, certain features, elements, and / or states. Furthermore, the words “this article,” “above,” “below,” and words of similar significance, when used in this application, should refer to the entire application and not any particular part thereof. Where the context permits, the use of singular or plural forms of words in the above detailed description may also include the plural or singular, respectively.

[0103] It should be understood that this application is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A composite logic gate circuit, characterized in that, The device includes a driving circuit with one signal output terminal and K signal input terminals. A first terminal of the driving circuit is connected to the signal output terminal of the composite logic gate circuit and connected to a high-level power supply via a load circuit. A second terminal of the driving circuit is connected to a low-level power supply. The first terminal of the load circuit is connected to both the first terminal of the driving circuit and the signal output terminal of the composite logic gate circuit. The second terminal of the load circuit is connected to the high-level power supply. The driving circuit includes K first depletion-type HEMT devices and L clamping devices. The K first depletion-type HEMT devices are arranged on a compound semiconductor substrate and configured as M AND structures. The L clamping devices are arranged as M clamping units, where each AND structure corresponds to one clamping unit. M and L are positive integers, and K is an integer greater than or equal to 2. Each AND structure includes one or more first depletion-type HEMT devices, wherein the 1st to Mth AND structures respectively include K1, ..., K M The first depletion-type HEMT device, K1, ..., K M K1, ..., K are the same or different positive integers. M The sum equals K; The gates of the K first depletion-type HEMT devices correspond one-to-one with the K signal input terminals of the composite logic gate circuit, and the gate of each of the K first depletion-type HEMT devices is connected to one of the corresponding K signal input terminals; In an AND structure including multiple first depletion-type HEMT devices, the multiple first depletion-type HEMT devices in the AND structure are connected in series. The drain of the first first depletion-type HEMT device in the AND structure is connected to the first terminal of the driving circuit, the source of the last first depletion-type HEMT device in the AND structure is connected to the first terminal of a corresponding clamping unit, the drain of each other first depletion-type HEMT device in the AND structure is connected to the source of the previous first depletion-type HEMT device in the AND structure, and the source of each other first depletion-type HEMT device in the AND structure is connected to the drain of the next first depletion-type HEMT device in the AND structure. In an AND structure including a single first depletion-type HEMT device, the drain of the first depletion-type HEMT device is connected to the first terminal of the driving circuit, and the source of the first depletion-type HEMT device is connected to the first terminal of a corresponding clamping unit. Each clamping unit includes one or more clamping devices, each clamping device having a first terminal and a second terminal, wherein the 1st to the Mth clamping units respectively include L1, ..., L... M A clamping device, L1, ..., L M For the same or different positive integers, L1, ..., L M The sum of them equals L; In a clamping unit comprising multiple clamping devices, the multiple clamping devices in the clamping unit are connected in series, wherein the first end of the first clamping device in the clamping unit serves as the head end of the clamping unit, the second end of the last clamping device in the clamping unit serves as the tail end of the clamping unit, the first end of each other clamping device in the clamping unit is connected to the second end of the preceding clamping device in the clamping unit, and the second end of each other clamping device in the clamping unit is connected to the first end of the following clamping device in the clamping unit, wherein the tail end of the clamping unit is connected to the second end of the drive circuit; in a clamping unit comprising one clamping device, the first end of the clamping device serves as the head end of the clamping unit, the second end of the clamping device serves as the tail end of the clamping unit and is connected to the second end of the drive circuit.

2. The composite logic gate circuit according to claim 1, characterized in that, The clamping device is a compound-based diode, wherein the positive terminal of the diode serves as the first end of the clamping device, and the negative terminal of the diode serves as the second end of the clamping device.

3. The composite logic gate circuit according to claim 1, characterized in that, The clamping device is a second depletion-type HEMT device, wherein the gate of the second depletion-type HEMT device serves as the first terminal of the clamping device, and wherein: The drain of the second depletion-type HEMT device serves as the second terminal of the clamping device; or The source of the second depletion-type HEMT device serves as the second terminal of the clamping device; or The drain and source of the second depletion-type HEMT device are shorted together to serve as the second terminal of the clamping device.

4. The composite logic gate circuit according to claim 1, characterized in that: The high-level power supply is a positive voltage power supply, and the low-level power supply is ground; or The high-level power supply is ground, and the low-level power supply is a negative voltage power supply; or The high-level power supply is a positive voltage power supply, and the low-level power supply is a negative voltage power supply.

5. The composite logic gate circuit according to claim 1, characterized in that, The K first depletion-type HEMT devices are formed on the same compound substrate.

6. The composite logic gate circuit according to claim 1 or 5, characterized in that, The compound substrate includes at least one of GaAs, GaN, and InP.

7. The composite logic gate circuit according to claim 1, characterized in that, It also includes K level conversion circuits, each of which corresponds one-to-one with the K first depletion-type HEMT devices. Each level conversion circuit is connected between the gate of the corresponding first depletion-type HEMT device and the signal input terminal corresponding to the first depletion-type HEMT device, and is used to convert the signal input to the signal input terminal into an input logic signal suitable for the first depletion-type HEMT device.

8. The composite logic gate circuit according to claim 7, characterized in that, The i-th level conversion circuit among the K level conversion circuits includes N i A level shifting element, and a first resistor R 1i Second resistor R 2i and the third resistor R 3i Where i = 1, ..., K, N1, ..., N K They are the same or different positive integers, where: The N i A level shifting element and the first resistor R 1i They are connected in series to form a series circuit, where the first resistor R 1i Connected to the beginning or end of the series circuit or to N i Between any two level shifting elements in the N level shifting elements i A level shifting element and a first resistor R 1i Each of them forms N as a series unit of the series circuit. i +1 serial unit, the N i +1 cascaded units, the first end of the first cascaded unit is connected to the corresponding signal input terminal among the K signal input terminals, the N i The second terminal of the last series unit in the +1 series connection is connected to the second resistor R. 2i The first terminal and the third resistor R 3i The first end, the N i In the +1 series unit, the first end of each other series unit is connected to the second end of the previous series unit, the N i In the +1 series unit, the second end of each other series unit is connected to the first end of the next series unit; The third resistor R 3i The second terminal is connected to the reference level signal, and the second resistor R 2i The second terminal is connected to the gate of the corresponding first depletion-type HEMT device to input the converted input logic signal to the first depletion-type HEMT device.

9. The composite logic gate circuit according to claim 8, characterized in that, The level shifting element is a compound-based diode, with the positive terminal of the diode serving as the first end of the series unit and the negative terminal of the diode serving as the second end of the series unit.

10. The composite logic gate circuit according to claim 8, characterized in that, The level shifting element is a third depletion-mode HEMT device, wherein the gate of the third depletion-mode HEMT device serves as the first terminal of the series unit, and wherein: The drain of the third depletion-type HEMT device serves as the second terminal of the series unit; or The source of the third depletion-type HEMT device serves as the second terminal of the series unit; or The drain and source of the third depletion-type HEMT device are shorted together to form the second terminal of the series unit.

11. The composite logic gate circuit according to claim 1, characterized in that, The load circuit includes a fourth depletion-type HEMT device and a clamping choke resistor, wherein the drain of the fourth depletion-type HEMT device is connected to the second terminal of the load circuit, the source of the fourth depletion-type HEMT device is connected to the first terminal of the clamping choke resistor, and the gate of the fourth depletion-type HEMT device and the second terminal of the clamping choke resistor are connected to the first terminal of the load circuit.

12. A chip, characterized in that, Includes the composite logic gate circuits as described in any one of claims 1-11.

13. An electronic device, characterized in that, Including the chip as described in claim 12.

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