High voltage slew rate cmti test circuit

Abstract

The application discloses a high-voltage change rate CMTI test circuit and relates to the field of CMTI detection circuits.The CMTI test circuit comprises a rising edge detection circuit and a falling edge detection circuit, and the rising edge detection circuit and the falling edge detection circuit respectively comprise a main switch circuit, a voltage acceleration change circuit and a load circuit.The voltage acceleration change circuit is connected in series between the main switch circuit and the load circuit and is used for changing the voltage change rate of a common-mode voltage.The main switch circuit is externally connected with a direct-current power supply and a modulation signal, two detection ends are respectively connected with positive and negative detection ends of a product to be tested, and a common-mode voltage pulse is controlled and output through the modulation signal.The common-mode voltage pulse is loaded to both ends of the voltage acceleration change circuit, the switching rate of the rising edge or the falling edge of the common-mode voltage pulse is improved, and the voltage acceleration change circuit is output in series with the load circuit.The scheme can effectively generate a common-mode voltage pulse with a high voltage change rate, simulate a high-stress transient interference scene, reduce circuit loss, improve test stability and equipment service life.

Description

Technical Field

[0001] This application relates to the field of CMTI detection circuits, and in particular to a high voltage change rate CMTI test circuit. Background Technology

[0002] Common-mode transient immunity (CMTI) refers to the ability of a circuit or system to resist common-mode interference signals; that is, the system's ability to maintain normal operation when faced with interference from common-mode signals. CMTI assesses the rise and fall rates of transient pulses in a critical state; exceeding these rates may lead to data loss, errors, or system failure. With the increasing integration and efficiency of motor / inverter systems, third-generation semiconductor devices such as SiC and GAN, with their advantages of higher switching frequencies, higher switching speeds, and lower heat generation, are becoming increasingly widespread. However, this also brings the challenge of understanding the relationship between voltage variation (dv / dt) and system stability.

[0003] Mainstream CMTI testing primarily relies on specialized instruments and equipment. These devices are complex, bulky, and expensive, typically costing hundreds of thousands to millions of yuan, making it difficult to meet the extensive testing needs during product development. Traditional test circuits generate common-mode voltage (VCM) pulses by adjusting the DC power supply voltage, modulation signal duty cycle, and frequency. However, due to limitations imposed by circuit parasitic parameters and device characteristics, there is a significant bottleneck in improving the voltage change rate. Specifically, factors such as inductance, switching transistor on-time, and parasitic capacitance collectively restrict the potential for increasing the voltage change rate, preventing conventional test circuits from effectively simulating transient interference scenarios under high stress conditions. Furthermore, mainstream solutions often suffer from significant circuit losses and thermal management issues when implementing high voltage change rate testing, affecting test stability and equipment lifespan. Therefore, traditional technologies urgently need improvement to address these problems. Summary of the Invention

[0004] This application provides a high voltage change rate (CMTI) test circuit that can effectively generate common-mode voltage pulses with high voltage change rate to simulate high-stress transient interference scenarios, while reducing circuit losses and improving test stability and equipment lifespan.

[0005] The test circuit includes a rising edge detection circuit and a falling edge detection circuit; the two detection terminals of the rising edge detection circuit are respectively connected to the positive and negative output terminals of the product under test when the common-mode signal is rising, and the two detection terminals of the falling edge detection circuit are respectively connected to the positive and negative output terminals of the product under test when the common-mode signal is falling.

[0006] The rising edge detection circuit and the falling edge detection circuit each include a main switching circuit, a voltage acceleration change circuit, and a load circuit; the voltage acceleration change circuit is connected in series between the main switching circuit and the load circuit to change the voltage change rate of the common-mode voltage.

[0007] The main switch circuit is connected to an external DC power supply VDC and a modulation signal, and the two detection terminals are respectively connected to the positive and negative detection terminals of the product under test. The common-mode voltage pulse is output through modulation signal regulation.

[0008] The common-mode voltage pulse is applied to both ends of the voltage acceleration circuit to increase the switching rate of the rising or falling edge of the common-mode voltage. The output of the voltage acceleration circuit is connected in series with the load circuit.

[0009] Specifically, the first voltage acceleration change circuit of the rising edge detection circuit includes a first transistor and a first current limiting circuit; the first transistor receives the common-mode voltage pulse and outputs a signal connected to the first current limiting circuit.

[0010] During rising edge detection, the first main switch circuit of the rising edge detection circuit outputs a pulse signal exceeding the withstand voltage value of the first transistor. The first transistor is in a breakdown state, and the first current limiting circuit maintains the current of the first transistor at a level not exceeding the rated avalanche withstand capacity of the product.

[0011] The second voltage acceleration change circuit of the falling edge detection circuit includes a second transistor and a second current limiting circuit connected in series; the second transistor receives the common-mode voltage pulse and its output is connected to the second current limiting circuit.

[0012] During falling edge detection, the second main switch circuit of the falling edge detection circuit outputs a pulse signal exceeding the withstand voltage of the second transistor, the second transistor is in a breakdown state, and the second current limiting circuit maintains the current of the second transistor at a level not exceeding the product's rated avalanche withstand capacity.

[0013] Specifically, the first current limiting circuit and the second current limiting circuit have the same structure, including a current limiting resistor R and a charging capacitor C connected in parallel, and the output is grounded; at the moment of transistor breakdown, the charging capacitor C charges, and a transient voltage is obtained. Rate of change, capacitor charging current Equivalent to breakdown current Charging current Over time It is expressed as follows:

[0014]

[0015] Indicates the internal resistance of the transistor. This represents the capacitor voltage.

[0016] Specifically, when the charging capacitor C is fully charged, its two ends are in an open circuit state; the first transistor or the second transistor is effectively connected in series with the current-limiting resistor R, and the voltage drop across the current-limiting resistor R is... ; It is the clamping voltage for transistor breakdown. It is the common-mode voltage output by the main switching circuit.

[0017] Specifically, the first main switching circuit includes a FET field-effect transistor Q1, an inductor L1, and a diode D2; the PWM modulation signal is connected to the gate of the field-effect transistor Q1, the drain and source of the field-effect transistor Q1 are respectively connected to the positive detection terminal and the negative detection terminal of the rising edge signal, and the source is grounded;

[0018] The DC power supply VDC is connected to the inductor L1. The output of the inductor L1 is connected to the drain of the field-effect transistor Q1 and the positive terminal of the diode D2. The output of the negative terminal of the diode D2 is connected to the load circuit and grounded. The common-mode voltage pulse is drawn out from the positive terminal of the diode D2 or the negative terminal.

[0019] Specifically, the second main switching circuit includes a FET field-effect transistor Q2, an inductor L2, and a diode D4; the PWM modulation signal is connected to the gate of the field-effect transistor Q2, the DC power supply VDC is connected to the drain of the field-effect transistor Q2, the source of the field-effect transistor Q2 is connected to the cathode of the diode D4 and one end of the inductor L2, the other end of the inductor L2 is grounded, and the anode of the diode D4 is connected to the load circuit and grounded;

[0020] The positive detection terminal of the falling edge signal is set at the negative terminal of diode D4, the negative detection terminal of the falling edge signal is set at the positive terminal of diode D4, and the common-mode voltage pulse is led out from the positive input or negative output of diode D4.

[0021] Specifically, the first transistor is one of a diode, a FET (field-effect transistor), or an insulated-gate bipolar transistor (IGBT).

[0022] Specifically, when the first transistor is a diode, the common-mode voltage pulse is input to the negative terminal of the diode, thereby increasing the VCM voltage change rate through reverse breakdown transient. ;

[0023] When the first transistor is a FET, the common-mode voltage pulse is input to the drain, and the gate and source are connected to the first current-limiting circuit. The voltage change rate of the common-mode voltage is increased through the drain-source breakdown transient. ;

[0024] When the first transistor is an IGBT, the common-mode voltage pulse is input to the collector, and the emitter and gate are connected to the first current-limiting circuit. The voltage change rate of the common-mode voltage is increased through the transient breakdown of the collector and emitter. .

[0025] Specifically, the second transistor is one of a diode, a FET (field-effect transistor), or an IGBT (insulated-gate bipolar transistor).

[0026] Specifically, when the second transistor is a diode, the common-mode voltage pulse is input to the negative terminal of the diode, thereby increasing the rate of change of the common-mode voltage through reverse breakdown transients. ;

[0027] When the second transistor is a FET, the common-mode voltage pulse is input to the drain, and the gate and source are connected to the second current-limiting circuit. The voltage change rate of the common-mode voltage is increased through the drain-source breakdown transient. ;

[0028] When the second transistor is an IGBT, the common-mode voltage pulse is input to the collector, and the emitter and gate are connected to the second current-limiting circuit. This increases the rate of change of the common-mode voltage through the transient breakdown between the collector and emitter. .

[0029] The beneficial effects of the technical solution provided in this application include at least the following: by including a rising edge detection circuit and a falling edge detection circuit, and by using the transistor breakdown principle in the voltage acceleration change circuit to change the VCM voltage change rate to improve the switching rate, it is possible to effectively generate a common-mode voltage pulse with a high voltage change rate, simulate a high-stress transient interference scenario, and at the same time reduce circuit loss, improve test stability and equipment life. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the high voltage change rate CMTI test circuit provided in the embodiments of this application;

[0031] Figure 2 This diagram illustrates the variation of a traditional VCM pulse voltage signal.

[0032] Figure 3 It is a circuit diagram that utilizes the diode breakdown effect and the rising edge detection of the VCM pulse signal drawn from the positive terminal of the diode;

[0033] Figure 4 It is a circuit diagram that utilizes the diode breakdown effect and the falling edge detection of the VCM pulse signal drawn from the positive terminal of the diode;

[0034] Figure 5 This is a circuit diagram for detecting the rising edge of the VCM pulse signal, which utilizes the breakdown effect of a field-effect transistor and the positive terminal of a diode.

[0035] Figure 6This is a circuit diagram for detecting the rising edge of the VCM pulse signal, which utilizes the IGBT breakdown effect and the positive terminal of the diode.

[0036] Figure 7 It is a circuit diagram that utilizes the diode breakdown effect and the rising edge detection of the VCM pulse signal drawn from the negative terminal of the diode;

[0037] Figure 8 It is a circuit diagram for detecting the rising edge of the VCM pulse signal by utilizing the breakdown effect of the field-effect transistor and the negative terminal of the diode;

[0038] Figure 9 This is a circuit diagram for detecting the rising edge of the VCM pulse signal, which utilizes the IGBT breakdown effect and the negative terminal of the diode.

[0039] Figure 10 This is a circuit diagram for detecting the falling edge of the VCM pulse signal, which utilizes the breakdown effect of a field-effect transistor and the positive terminal of a diode.

[0040] Figure 11 This is a circuit diagram for detecting the falling edge of the VCM pulse signal, which utilizes the IGBT breakdown effect and the positive terminal of the diode.

[0041] Figure 12 This is a circuit diagram for detecting the falling edge of the VCM pulse signal, which utilizes the diode breakdown effect and the negative terminal of the diode.

[0042] Figure 13 This is a circuit diagram for detecting the falling edge of the VCM pulse signal, which utilizes the breakdown effect of a field-effect transistor and the negative terminal of a diode.

[0043] Figure 14 This is a circuit diagram for detecting the falling edge of the VCM pulse signal, which utilizes the IGBT breakdown effect and the negative terminal of the diode. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0045] In this article, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0046] Traditional common-mode transient immunity (CMTI) testing methods primarily rely on dedicated instruments and equipment. These devices typically have complex system architectures, large physical volumes, and high acquisition costs, limiting their widespread application in extensive product development research and performance testing. Furthermore, given the challenges posed by the high voltage sag rates of highly integrated motor / inverter systems and the application of third-generation semiconductor devices, this traditional technology has limitations in providing low-cost, efficient testing solutions.

[0047] In response, this application proposes a high voltage change rate (CMTI) test circuit, such as... Figure 1 As shown, the test circuit includes a rising edge detection circuit and a falling edge detection circuit. The two detection terminals of the rising edge detection circuit are respectively connected to the positive and negative detection terminals of the product under test (VDT) when the output common-mode signal rises (i.e., VCMTIrising_V+ and VCMTIrising_V-), and the two detection terminals of the falling edge detection circuit are respectively connected to the positive and negative detection terminals of the product under test (VDT) when the output common-mode signal falls (i.e., VCMTIFalling_V+ and VCMTIFalling_V-).

[0048] The rising edge detection circuit and falling edge detection circuit each include a main switching circuit, a voltage acceleration circuit, and a load circuit; the voltage acceleration circuit is connected in series between the main switching circuit and the load circuit to change the rate of change of the common-mode voltage (VCM). Figure 1 As shown, the rising edge detection circuit can be divided into a first main switch circuit, a first voltage acceleration change circuit, and a first load circuit. The falling edge detection circuit can be divided into a second main switch circuit, a second voltage acceleration change circuit, and a second load circuit. The structures of each main switch circuit, voltage acceleration change circuit, and load circuit can be the same or different.

[0049] The main switching circuit is externally connected to a DC power supply (VDC) and a modulation signal (PWM), with its two detection terminals connected to the positive and negative detection terminals of the product under test (DUT). The common-mode voltage pulse (VCM pulse) is output through modulation of the signal. The DC power supply (VDC) provides a stable DC energy input for the entire test circuit. The PWM signal is an external control signal used to control the operating state of the main switching circuit, thereby regulating the generation and waveform characteristics of the common-mode voltage (VCM) pulse.

[0050] In one possible implementation, the main switching circuit can be a switching converter composed of power switching devices (such as MOSFETs) and energy storage elements (such as inductors or capacitors). A PWM signal is used to control the on / off state of the power switching devices, thereby generating VCM pulses with predetermined amplitude, duration, and frequency. Because the external PWM signal is used to control the VCM pulse operation of the main switching circuit and provide the VCM pulse signal required for CMTI testing, the VCM pulse low voltage can be obtained within a certain range by adjusting the VDC input voltage, PWM duty cycle, and frequency. Signal of rate of change.

[0051] A voltage acceleration circuit is connected in series between the main switching circuit and the load circuit. Its core function is to change the rate of change of the VCM voltage. For example, this acceleration circuit can be a voltage buffer with a high slew rate, used to receive the VCM pulse output from the main switching circuit and reproduce it at a faster speed; or it can be a passive network that uses a fast charge and discharge mechanism to achieve edge sharpening; or it can be a circuit that achieves transient acceleration through the characteristics of nonlinear components. In this way, the steepness of the rising or falling edge of the VCM pulse can be significantly improved.

[0052] Figure 2 A schematic diagram of the VCM pulse voltage signal in one possible state is shown. Theoretically, the rising and falling edge pulses represent a sloping voltage change curve in the timing circuit. This refers to the pulse switching slope, that is, the switching rate between the rising and falling edges. This application designs a special detection circuit to... The slope is "steeper" to achieve rapid switching. The rising edge detection circuit is specifically designed to handle rising edge signals and is designed for the "rising edge slope", while the falling edge detection circuit is specifically designed to handle falling edge signals and is designed for the "falling edge slope".

[0053] The VCM pulses from each detection circuit are applied to both ends of their respective voltage acceleration circuits to increase the switching rate of the VCM rising or falling edge. The corresponding voltage acceleration circuit outputs a series load circuit. This load circuit is typically a resistor network, used to simulate the equivalent load under the actual operating environment of the product under test, and to complete the current loop circuit, thus providing current limiting and system stabilization.

[0054] In summary, this application effectively addresses the limitations of traditional CMTI test equipment in terms of system complexity, size, and cost by integrating rising and falling edge detection functions and introducing a voltage acceleration circuit. This circuit can generate common-mode voltage pulses with high voltage change rates, enabling accurate evaluation of CMTI performance. It is particularly suitable for addressing the high voltage change rate challenges brought about by third-generation semiconductor device applications, thus providing a cost-effective, efficient, and easy-to-implement CMTI test solution.

[0055] like Figure 2 As shown, in some embodiments, the first voltage acceleration circuit of the rising edge detection circuit includes a first transistor and a first current limiting circuit; the first transistor receives a VCM pulse and its output is connected to the first current limiting circuit. Similarly, the second voltage acceleration circuit of the falling edge detection circuit includes a second transistor and a second current limiting circuit connected in series; the second transistor receives a VCM pulse and its output is connected to the second current limiting circuit.

[0056] When the rising edge is detected, the first main switch circuit of the rising edge detection circuit outputs a VCM pulse signal that exceeds the withstand voltage of the first transistor. At this time, the first transistor is in a breakdown state, and the first current limiting circuit maintains the current of the first transistor at a level that does not exceed the rated avalanche withstand capacity of the product.

[0057] Correspondingly, when the falling edge is detected, the second main switch circuit of the falling edge detection circuit outputs a VCM pulse signal that exceeds the withstand voltage of the second transistor. The second transistor is in a breakdown state, and the second current limiting circuit maintains the current of the second transistor at a level that does not exceed the rated avalanche withstand capacity of the product.

[0058] The first voltage acceleration circuit and the second voltage acceleration circuit of the falling edge detection circuit are core components specifically designed to improve the VCM voltage change rate in CMTI testing. They introduce a controllable breakdown mechanism, enabling the transient generation of extremely high voltage changes during the rising or falling edge of the VCM pulse. This allows for the simulation or testing of the immunity of the product under test under extreme common-mode transient interference. Its main function is to receive VCM pulses from the main switching circuit and convert them into signals with a high voltage change rate, while ensuring the safe and controllable breakdown process.

[0059] The first and second transistors are key semiconductor devices used to accelerate the rate of voltage change. They are selected as devices with specific breakdown voltages, capable of entering a controlled breakdown state (e.g., avalanche breakdown) when the applied voltage exceeds their breakdown voltage. In the breakdown state, the transistor's impedance drops sharply, allowing current to flow and rapidly changing the voltage across it, thus achieving [the desired effect]. The transistor can be a diode with reverse breakdown characteristics, a field-effect transistor capable of avalanche breakdown (such as MOSFET, JFET), or an insulated-gate bipolar transistor (IGBT), the choice of which depends on the required breakdown characteristics, voltage rating, and current handling capability.

[0060] The first and second current-limiting circuits are protective circuits used in conjunction with transistors. Their main function is to limit the current flowing through the transistor to a safe range, i.e., not exceeding the product's rated avalanche withstand capability, when the transistor enters a breakdown state. This is crucial for preventing transistor damage or failure due to overcurrent. Current-limiting circuits can be constructed from passive components (such as series resistors or inductors) or active components (such as constant current source circuits). For example, a purely resistive element can be used to limit the current, or a combined circuit containing capacitors and resistors can be used to provide a current path during transient breakdown and limit the steady-state current.

[0061] In some embodiments, the first current limiting circuit and the second current limiting circuit can be designed with the same circuit structure. This application uses an example including a current limiting resistor R and a charging capacitor C connected in parallel. Because a loop needs to be formed, the output of the current limiting resistor R and the charging capacitor C of each detection circuit is grounded. Figure 3 and Figure 4 Schematic diagrams of edge signal detection circuits based on the diode breakdown principle are shown. Figure 3 The components are diode D1, current-limiting resistor R1, and charging capacitor C1. Figure 4 The components are diode D3, current-limiting resistor R2, and charging capacitor C2.

[0062] At the moment of transistor breakdown, the charging capacitor C charges, and a voltage is transiently obtained. Rate of change, capacitor charging current Equivalent to breakdown current Charging current Over time It is expressed as follows:

[0063]

[0064] Indicates the internal resistance of the transistor. This represents the capacitor voltage.

[0065] This embodiment uses a diode as an example. Since the rising edge and falling edge detection acceleration circuits are structurally similar, the following derivations and calculations cover both cases. The pulsed VCM voltage signal generated by the main switching circuit is applied to... For the acceleration circuit, select a suitable diode (D1 or D2) with the appropriate voltage rating. For example, to test CMTI data under a VCM=800V condition, select a diode (D1 or D2) with a voltage rating close to 800V. (This configuration allows for the selection of one or more products, connected in series or parallel, to obtain the required voltage rating.) Adjust the VDC input voltage and the PWM signal. The main switching circuit generates a VCM pulse voltage signal higher than the diode's (D1 or D2) voltage rating, at which point the diode (D1 or D2) is in a breakdown state.

[0066] This circuit is designed as a DC circuit system (DC VDC input). At the moment diode D1 breaks down, most of the current rapidly charges capacitor C1 until it is fully charged, resulting in a large transient response. Rate of change. This process can be equivalent to a series circuit model of diode D1's internal resistance RD and C1, where the capacitor charging current... Approximate to Breakdown current, capacitor charging current .

[0067] Generally, it is considered that charging is approximately complete at t=5RC. Once the capacitor is fully charged, its terminals can be considered as an open circuit. At this point, the circuit only considers the series connection of diode D1 and resistor R1. The output voltage of the main switching circuit... D1 diode breakdown clamping voltage The voltage across the current-limiting resistor R1 Series circuit current Therefore, it can be determined that when the relative resistance is large, the circuit power consumption is low.

[0068] The above analysis shows that the operating current of diode D1 and capacitor is relatively large during charging, while the power consumption of the circuit is low in other states. Reasonable design of capacitor charging time and charging current can reduce the losses generated by the circuit.

[0069] This circuit works by utilizing the transient voltage change rate achieved during transistor breakdown. Signal, reaching CMTI The purpose of accelerating the rate of voltage change is to, through proper configuration of the current-limiting circuit with resistor R1 and capacitor C1, ensure that the device operates below its rated avalanche breakdown withstand capability, thus achieving safe and stable operation. Experiments have shown that... It can achieve a testing capability of over 200V / ns, meeting the CMTI testing requirements of most conventional products.

[0070] In the above embodiments, a first main switching circuit is proposed to output a VCM pulse signal exceeding the withstand voltage of the first transistor. However, in its implementation, a specific circuit structure is needed to achieve efficient, low-loss pulse generation and precise control of the voltage change rate. To avoid energy loss, low switching efficiency, or other issues caused by suboptimal circuit design. This addresses issues such as inaccurate control, thereby improving the reliability and stability of CMTI testing.

[0071] Therefore, this application provides a specific main switch control circuit, wherein the first main switch circuit and the second main switch circuit are structurally identical. Figure 3 and Figure 4 These are the corresponding circuit structure diagrams.

[0072] Specifically, the first main switching circuit includes a FET field-effect transistor Q1, an inductor L1, and a diode D2; the PWM modulation signal is connected to the gate of the field-effect transistor Q1, the drain and source of the field-effect transistor Q1 are connected to the positive and negative detection terminals of the rising edge signal, respectively, and the source is grounded.

[0073] The DC power supply VDC is connected to inductor L1. The output of inductor L1 is connected to the drain of MOSFET Q1 and the positive terminal of diode D2. The output of diode D2 is connected to the load circuit and grounded. The VCM pulse signal is drawn out from either the positive input or the negative output of diode D2.

[0074] by Figure 3 Taking the circuit structure as an example, the circuit calculation rules are as follows: minimize the heat generated by each component in the circuit, design the boost circuit to operate in DCM mode, and the output pulse voltage VOUT can be determined. Output It is not only related to the duty cycle D of the first / second transistor (Q1 or Q2), but also closely related to the current limiting resistor (R1 or R2), the inductor (L1 or L2) and the switching frequency f (1 / Ts).

[0075] IL is the inductor current, VDC is the input DC voltage, Ton is the on-time of transistor Q1, Coss is the parasitic capacitance between the drain and source of transistor Q1, and CD is the parasitic capacitance of the diode.

[0076] Formula 1, U=L*dt / dt, yields IL=U / L*t, IL1=VDC / L1*Ton;

[0077] Formula 2, IL=C(dv / dt), yields dVCM / dt=IL1 / C=IL1 / (Coss+CD);

[0078] The formula dVCM / dt = VDC * Ton / L1 * (Coss + CD) is derived. To improve VCM dv / dt, the input voltage VDC can be increased, the conduction time of transistor Q1 Ton can be increased, and products with small inductance L and small parasitic capacitance of transistor Q1 and diode D1 can be selected.

[0079] The FET field-effect transistor Q1 acts as the main switch, and its on / off state is precisely controlled by a PWM modulation signal, enabling flexible adjustment of the width, frequency, and voltage of the VCM pulse. This precise control is essential for achieving high performance. and low The key to pulse control is to avoid problems caused by inaccurate switching control. Distortion. Inductor L1, along with FET Q1 and diode D2, forms a boost switching circuit. When Q1 is on, inductor L1 stores energy; when Q1 is off, inductor L1 provides a high-voltage pulse to the load through diode D2. This energy conversion mechanism is efficient and low-loss, ensuring high energy utilization when generating high-voltage VCM pulses and reducing unnecessary heat generation and energy loss. The unidirectional conductivity of diode D2 ensures the correct current flow, preventing reverse current interference and damage to the circuit, thus improving circuit stability and reliability. The source-grounded design provides a stable reference potential for the product under test, reducing the introduction of common-mode noise and making the test results more accurate and reliable.

[0080] By drawing a VCM pulse from the output of inductor L1, high voltage and high efficiency are ensured. The pulse signal can be directly and with high quality input to the voltage acceleration circuit, thereby effectively improving the overall performance of the CMTI test circuit and achieving efficient, accurate, and reliable testing of the product under test. Compared to the basic solution, this specific main switch circuit structure can more effectively generate the required high voltage and high... The VCM pulse optimizes energy conversion efficiency, reduces circuit losses, and enhances the ability to... This improves the control precision, thereby significantly enhancing the reliability and stability of CMTI testing.

[0081] Similarly, the second main switch circuit includes a FET field-effect transistor Q2, an inductor L2, and a diode D4; the PWM modulation signal is connected to the gate of the field-effect transistor Q2, the DC power supply VDC is connected to the drain of the field-effect transistor Q2, the source of the field-effect transistor Q2 is connected to the cathode of the diode D4 and one end of the inductor L2, the other end of the inductor L2 is grounded, and the anode of the diode D4 is connected to the load circuit and grounded.

[0082] The positive detection terminal of the falling edge signal is set at the negative terminal of diode D4, and the negative detection terminal of the falling edge signal is set at the positive terminal of diode D3. The VCM pulse signal is output from either the positive input or the negative output of diode D4.

[0083] For the falling edge, the energy storage and filtering functions of inductor L2, combined with the freewheeling and rectification functions of diode D4, optimize the waveform quality of the VCM pulse and provide a high-quality input signal for the subsequent voltage acceleration circuit. Furthermore, the clearly defined positive and negative detection terminals for the falling edge signal and the VCM pulse output point simplify the connection and operation of the test circuit, reducing the complexity of the circuit design. This optimized second main switch circuit can stably and efficiently output the VCM pulse for falling edge detection, providing a reliable input for the subsequent voltage acceleration circuit, thereby effectively improving the accuracy and efficiency of CMTI testing and overcoming the shortcomings of existing technologies such as complex circuit design, limited test accuracy, or low efficiency.

[0084] All the above figures and embodiments are described using diodes as logic devices based on the transistor breakdown principle. In some embodiments, for the falling edge detection circuit, the first transistor is one of a diode, a FET, or an IGBT; the second transistor is one of a diode, a FET, or an IGBT.

[0085] When the first transistor is diode D1, the negative terminal of the diode receives a VCM pulse, which increases the VCM voltage change rate dv / dt through reverse breakdown transient; corresponding to Figure 3 The circuit structure diagram is shown below. At this time, D1 draws out the VCM pulse signal from the positive terminal of D2.

[0086] When the first transistor is a FET Q3, a VCM pulse is input to the drain, and the gate and source are connected to the first current-limiting circuit. This circuit improves the VCM voltage change rate dv / dt through the drain-source breakdown transient. Correspondingly... Figure 5 The circuit structure diagram shown indicates that Q3 draws out the VCM pulse signal from the positive terminal of D2.

[0087] When the first transistor is an IGBT, a VCM pulse is input to the collector of Q4, and the emitter and gate are connected to the first current-limiting circuit. This increases the VCM voltage change rate dv / dt through the collector-emitter breakdown transient. Figure 6 The circuit structure diagram shown indicates that Q4 draws out the VCM pulse signal from the negative terminal of D2.

[0088] The above three scenarios address the case where the VCM pulse is drawn from the positive terminal of D2. When the pulse is drawn from the negative terminal of D2, it can be further improved as follows: Figure 7 , Figure 8 and Figure 9 The structure is such that the corresponding transistor VCM pulse signal input terminal is set at the negative terminal of D2 for output.

[0089] For the falling edge detection circuit, when the second transistor is diode D3, the negative terminal of D3 receives the VCM pulse, which increases the VCM voltage change rate dv / dt through reverse breakdown transient; corresponding to Figure 4 The circuit structure diagram is shown.

[0090] When the second transistor is a FET Q5, a VCM pulse is input to the drain of Q5, and the gate and source are connected to a second current-limiting circuit. This circuit improves the VCM voltage change rate dv / dt through the drain-source breakdown transient. Figure 10 The circuit structure diagram is shown.

[0091] When the second transistor is an IGBT, the collector of Q6 receives a VCM pulse, and the emitter and gate are connected to the second current-limiting circuit. This improves the VCM voltage change rate dv / dt through the collector-emitter breakdown transient. Figure 11 The circuit structure diagram is shown.

[0092] The above three scenarios address the case where the VCM pulse is drawn from the positive terminal of D4. When the pulse is drawn from the negative terminal of D4, it can be further improved as follows: Figure 12 , Figure 13 and Figure 14 The structure is such that the corresponding transistor VCM pulse signal input terminal is set at the negative terminal of D4.

[0093] Whether using a rising edge detection circuit or a falling edge detection circuit, the high VCM voltage change rate (dv / dt) test can be achieved through either the positive or negative terminal of the diode. Furthermore, when D1 is connected to the positive terminal of D2, the loop is relatively shorter, the total circuit impedance is lower, and the resulting di / dt and dv / dt values ​​are relatively larger, representing the optimal operating state for the entire circuit. Diode D2 itself has certain internal impedance and parasitic capacitance parameters, which will limit the di / dt and dv / dt rates of change in the circuit to some extent after the circuit signal passes through D2. The same principle applies to other transistor structures.

[0094] Based on the circuit structure and operating principle described above, this high voltage change rate (CMTI) test circuit can achieve a CMTI testing capability of up to 200V / ns with a low cost and simple structure, meeting the high dv / dt testing requirements of next-generation semiconductor devices. Compared to dedicated test equipment costing hundreds of thousands to millions of yuan, the implementation cost of this circuit is significantly reduced, and its compact size facilitates widespread application in R&D and production environments. This modular design also makes the circuit easy to port to other similar test architectures, applicable not only to isolated circuit products but also allowing for the testing of other devices under test, circuit products, or complete systems.

[0095] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

Claims

1. A high voltage change rate (CMTI) test circuit, characterized in that, It includes a rising edge detection circuit and a falling edge detection circuit; the two detection terminals of the rising edge detection circuit are respectively connected to the positive and negative detection terminals when the common-mode signal output by the product under test is rising, and the two detection terminals of the falling edge detection circuit are respectively connected to the positive and negative detection terminals when the common-mode signal output by the product under test is falling. The rising edge detection circuit and the falling edge detection circuit each include a main switching circuit, a voltage acceleration change circuit, and a load circuit; the voltage acceleration change circuit is connected in series between the main switching circuit and the load circuit to change the voltage change rate of the common-mode voltage. The main switch circuit is connected to an external DC power supply VDC and a modulation signal, and the two detection terminals are respectively connected to the positive and negative detection terminals of the product under test. The common-mode voltage pulse is output through modulation signal regulation. The common-mode voltage pulse is applied to both ends of the voltage acceleration circuit to increase the switching rate of the rising or falling edge of the common-mode voltage. The output of the voltage acceleration circuit is connected in series with the load circuit. The first voltage acceleration change circuit of the rising edge detection circuit includes a first transistor and a first current limiting circuit; the first transistor receives the common-mode voltage pulse and outputs the pulse connected to the first current limiting circuit; during rising edge detection, the first main switch circuit of the rising edge detection circuit outputs a pulse signal exceeding the withstand voltage value of the first transistor, the first transistor is in a breakdown state, and the first current limiting circuit maintains the current of the first transistor at a level not exceeding the rated avalanche withstand capacity of the product. The second voltage acceleration change circuit of the falling edge detection circuit includes a second transistor and a second current limiting circuit connected in series; the second transistor receives the common-mode voltage pulse and outputs a signal connected to the second current limiting circuit; during falling edge detection, the second main switch circuit of the falling edge detection circuit outputs a pulse signal exceeding the withstand voltage value of the second transistor, the second transistor is in a breakdown state, and the second current limiting circuit maintains the current of the second transistor at a level not exceeding the rated avalanche withstand capacity of the product.

2. The high voltage change rate CMTI test circuit according to claim 1, characterized in that, The first current limiting circuit and the second current limiting circuit have the same structure, including a current limiting resistor R and a charging capacitor C connected in parallel, and the output is grounded; at the moment of transistor breakdown, the charging capacitor C charges, and a transient voltage is obtained. Rate of change, capacitor charging current Equivalent to breakdown current Charging current Over time It is expressed as follows: Indicates the internal resistance of the transistor. This represents the capacitor voltage.

3. The high voltage change rate CMTI test circuit according to claim 2, characterized in that, When the charging capacitor C is fully charged, its terminals are open-circuited; the first or second transistor is effectively connected in series with the current-limiting resistor R, and the voltage drop across the current-limiting resistor R is... ; It is the clamping voltage for transistor breakdown. It is the common-mode voltage output by the main switching circuit.

4. The high voltage change rate CMTI test circuit according to claim 1, characterized in that, The first main switching circuit includes a FET field-effect transistor Q1, an inductor L1, and a diode D2; the PWM modulation signal is connected to the gate of the field-effect transistor Q1, the drain and source of the field-effect transistor Q1 are respectively connected to the positive detection terminal and the negative detection terminal of the rising edge signal, and the source is grounded; The DC power supply VDC is connected to the inductor L1. The output of the inductor L1 is connected to the drain of the field-effect transistor Q1 and the positive terminal of the diode D2. The output of the negative terminal of the diode D2 is connected to the load circuit and grounded. The common-mode voltage pulse is drawn out from the positive terminal of the diode D2 or the negative terminal.

5. The high voltage change rate CMTI test circuit according to claim 1, characterized in that, The second main switching circuit includes a FET field-effect transistor Q2, an inductor L2, and a diode D4; the PWM modulation signal is connected to the gate of the FET Q2, the DC power supply VDC is connected to the drain of the FET Q2, the source of the FET Q2 is connected to the cathode of the diode D4 and one end of the inductor L2, the other end of the inductor L2 is grounded, and the anode of the diode D4 is connected to the load circuit and grounded. The positive detection terminal of the falling edge signal is set at the negative terminal of diode D4, the negative detection terminal of the falling edge signal is set at the positive terminal of diode D4, and the common-mode voltage pulse is led out from the positive input or negative output of diode D4.

6. The high voltage change rate CMTI test circuit according to claim 4, characterized in that, The first transistor is one of a diode, a FET, or an IGBT.

7. The high voltage change rate CMTI test circuit according to claim 6, characterized in that, When the first transistor is a diode, the common-mode voltage pulse is input to the cathode of the diode, which increases the VCM voltage change rate through reverse breakdown transient. ; When the first transistor is a FET, the common-mode voltage pulse is input to the drain, and the gate and source are connected to the first current-limiting circuit. The voltage change rate of the common-mode voltage is increased through the drain-source breakdown transient. ; When the first transistor is an IGBT, the common-mode voltage pulse is input to the collector, and the emitter and gate are connected to the first current-limiting circuit. The voltage change rate of the common-mode voltage is increased through the transient breakdown of the collector and emitter. .

8. The high voltage change rate CMTI test circuit according to claim 1, characterized in that, The second transistor is one of a diode, a FET, or an IGBT.

9. The high voltage change rate CMTI test circuit according to claim 8, characterized in that, When the second transistor is a diode, the common-mode voltage pulse is input to the negative terminal of the diode, which increases the rate of change of the common-mode voltage through reverse breakdown transients. ; When the second transistor is a FET, the common-mode voltage pulse is input to the drain, and the gate and source are connected to the second current-limiting circuit. The voltage change rate of the common-mode voltage is increased through the drain-source breakdown transient. ; When the second transistor is an IGBT, the common-mode voltage pulse is input to the collector, and the emitter and gate are connected to the second current-limiting circuit. This increases the rate of change of the common-mode voltage through the transient breakdown between the collector and emitter. .

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