Phase-locked loop of time-interleaved multiple reference clocks, system on chip, and electronic device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-08
- Publication Date
- 2026-08-11
AI Technical Summary
[0005]而在压控振荡器设计中，噪声与功耗是互换的，为实现更低的噪声，需要更多功耗
[0052] Essentially, this involves aligning multiple reference clocks with the multi-phase feedback clock of the frequency divider, achieving noise averaging of the reference clocks in the time domain, thereby reducing the noise of the equivalent reference clock in the phase-locked loop (PLL). Since the output load of the multi-phase frequency divider is distributed across multiple time-interleaved branches, the multiple reference clocks do not flip simultaneously but rather their edges are delayed sequentially, alternating—a process known as "time interleaving." This reduces the disturbance to the power supply and ground network during the phase detector's operation and also reduces the noise of the multi-phase frequency divider's output clock link. This further optimizes the overall noise of the reference clock path, allowing for the design of lower-noise voltage-controlled oscillators (VCOs), ultimately reducing the overall noise of the PLL and demonstrating high practicality.
Smart Images
Figure CN117155381B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a phase-locked loop with time-interleaved multi-reference clocks, a system-on-a-chip, and electronic devices. Background Technology
[0002] As people continue to pursue higher performance in portable electronic devices, more and more circuit modules are being integrated into System-on-Chip (SoC). Providing high-quality clock signals to different modules is a key issue in SoC.
[0003] In current SoC systems, the ever-advancing wireless communication technologies place higher demands on the phase noise of the frequency sources used (noise in the following text refers to phase noise). Lower noise often requires higher power consumption, and the trade-off between noise and power consumption has become an increasingly important issue in phase-locked loop design.
[0004] The noise of a phase-locked loop (PLL) can be broadly divided into in-band and out-of-band components. Out-of-band noise is mainly determined by the voltage-controlled oscillator (VCO), while in-band noise is primarily determined by the reference clock. To minimize the overall PLL noise, the strategy is to adjust the PLL bandwidth to balance the contribution ratio of in-band and out-of-band noise. The optimization result is generally that the contribution ratios of in-band and out-of-band noise to the total noise are roughly equal. To reduce the overall PLL noise, a smaller bandwidth needs to be designed to reduce the in-band noise contributed by the reference clock. This necessitates designing a lower-noise VCO to avoid excessive out-of-band noise.
[0005] In voltage-controlled oscillator (VCO) design, noise and power consumption are interchangeable; lower noise requires higher power consumption. In conclusion, due to the noise of the reference clock, the overall noise and power consumption of the phase-locked loop (PLL) are difficult to further optimize.
[0006] Therefore, how to reduce the noise of the equivalent reference clock of the phase-locked loop (PLL) and design a lower-noise voltage-controlled oscillator (VCO) to reduce the overall noise of the PLL is an urgent problem to be solved. Summary of the Invention
[0007] In view of the above problems, the present invention proposes a phase-locked loop with time-interleaved multi-reference clocks, a system-on-a-chip, and an electronic device.
[0008] This invention provides a phase-locked loop with time-interleaved multi-reference clocks. The phase-locked loop is characterized by comprising: a main loop, multiple synchronization loops, a multi-phase divider, and a voltage-controlled oscillator.
[0009] The main loop includes: a main crystal oscillator and a main phase detector;
[0010] Each of the plurality of synchronization loops includes: a slave crystal oscillator and a slave phase detector;
[0011] The multi-phase divider is connected to the master phase detector and all slave phase detectors respectively;
[0012] The master crystal oscillator is connected to the master phase detector, and the slave crystal oscillator in each synchronization loop is connected to the slave phase detector.
[0013] The outputs of all phase detectors are connected to the input of the voltage-controlled oscillator after passing through a filter, and the output of the voltage-controlled oscillator is connected to the multi-phase frequency divider.
[0014] The main crystal oscillator and multiple slave crystal oscillators generate reference clocks with different phases and output them to their respective connected phase detectors;
[0015] The multi-phase divider generates sequentially delayed feedback clocks, which are then output to all phase detectors respectively.
[0016] The main phase detector compares the phase difference between the reference clock generated by the main crystal oscillator and any feedback clock transmitted from the multi-phase divider, aligns the two clocks, and outputs the aligned clock.
[0017] Each phase detector compares the phase difference between the reference clock generated from the crystal oscillator and the feedback clock transmitted from the multi-phase divider, which has a different phase from the feedback clock received by other phase detectors, and aligns the two clocks and outputs the aligned clock.
[0018] The aligned clock output from the main phase detector is averaged with all aligned clocks output from the phase detectors, filtered by the filter, and then output to the voltage-controlled oscillator.
[0019] Optionally, in each synchronization loop, the aligned clock output from the phase detector participates in the averaging operation and is also output to the slave crystal oscillator connected to it.
[0020] Optionally, the main loop further includes a main buffer; each synchronization loop further includes a slave buffer;
[0021] The multi-phase frequency divider is connected to the main phase detector through the main buffer;
[0022] The multi-phase divider is connected to the slave phase detector in each synchronization loop through the slave buffer in that loop.
[0023] Optionally, the multi-phase frequency divider includes: a multi-mode frequency divider, an accumulator carry unit, and a multi-phase editor;
[0024] The multi-mode frequency divider is connected to the accumulator and the multi-phase editor, respectively.
[0025] The multi-mode frequency divider down-converts the frequency signal output by the voltage-controlled oscillator and transmits the down-converted signal to the accumulator and the multi-phase editor respectively.
[0026] The accumulator carry is driven by the down-frequency signal, causing its output signal to jump between two adjacent integers in order to control the division ratio of the multi-mode divider.
[0027] The multiphase editor divides the down-frequency signal into phases to generate the sequentially delayed feedback clock.
[0028] Optionally, the multiphase editor includes: a wide clock generation unit and multiple narrow clock generation units;
[0029] The wide clock generation unit splits the down-frequency signal into phases to obtain sequentially delayed wide clocks. According to the order of delay, two adjacent wide clocks are grouped together to form multiple groups of wide clocks and output to multiple narrow clock generation units. Among them, one group of wide clocks is output to one narrow clock generation unit.
[0030] Each narrow clock generation unit splits a set of wide clocks into phases to obtain a narrow clock;
[0031] Multiple narrow clock generation units each split a set of wide clocks input to themselves into phases to obtain successively delayed narrow clocks, which are the successively delayed feedback clocks.
[0032] Optionally, the wide clock generation unit includes: a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a first AND gate, an XOR gate, and a NOT gate;
[0033] The input terminal of the first D flip-flop is connected to the output terminal of the NOT gate, and the inverted signal of the down-frequency signal is used as the clock signal. The output terminal of the first D flip-flop is connected to the input terminal of the second D flip-flop and the first input terminal of the first AND gate, respectively.
[0034] The second D flip-flop uses the inverted signal of the down-frequency signal as the clock signal, and its output is connected to the second input of the first AND gate and the input of the NOT gate, respectively.
[0035] The output of the first AND gate is connected to the first input of the XOR gate; the output of the XOR gate is connected to the input of the third D flip-flop, which uses the inverted signal of the down-frequency signal as its clock signal.
[0036] The output of the third D flip-flop is connected to the input of the fourth D flip-flop and the second input of the XOR gate, respectively.
[0037] The fourth D flip-flop uses the inverted signal of the down-frequency signal as the clock signal, and its output terminal outputs a wide clock with sequential delays.
[0038] Optionally, the narrow clock generation unit includes: a second AND gate and a fifth D flip-flop;
[0039] The first input of the second AND gate receives the first wide clock in a set of wide clocks, and the second input receives the inverted signal of the second wide clock.
[0040] The output of the second AND gate is connected to the input of the fifth D flip-flop. The fifth D flip-flop uses the inverted signal of the down-frequency signal as the clock signal, and its output outputs a narrow clock with sequential delays.
[0041] Optionally, the main loop and each synchronization loop operate in the phase order of the sequentially delayed feedback clocks;
[0042] During the same time period, if the main crystal oscillator and the main phase detector are in working state, all slave crystal oscillators and slave phase detectors are in standby state.
[0043] If any one of the slave crystal oscillators and slave phase detectors and its connected slave phase detector are in working condition, then the remaining slave crystal oscillators and slave phase detectors, as well as the master crystal oscillator and the master phase detector, are in standby condition.
[0044] This invention also provides a system-on-a-chip, the system-on-a-chip including: a phase-locked loop with time-interleaved multi-reference clocks as described above.
[0045] This invention also provides an electronic device, which includes: a phase-locked loop with time-interleaved multi-reference clocks as described above.
[0046] The present invention provides a phase-locked loop with time interleaving and multiple reference clocks, comprising: a main loop, multiple synchronization loops, a multi-phase divider, and a voltage-controlled oscillator; the main loop includes: a main crystal oscillator and a main phase detector; each of the multiple synchronization loops includes: a slave crystal oscillator and a slave phase detector.
[0047] The multi-phase divider is connected to the master phase detector and all slave phase detectors respectively; the master crystal oscillator is connected to the master phase detector, and the slave crystal oscillator in each synchronization loop is connected to the slave phase detector; the output of all phase detectors is connected to the input of the voltage-controlled oscillator after passing through a filter, and the output of the voltage-controlled oscillator is connected to the multi-phase divider.
[0048] In this process, the main crystal oscillator and multiple reference clocks with different phases generated from the crystal oscillator are output to their respective connected phase detectors; the multi-phase divider generates feedback clocks with sequential delays and outputs them to all phase detectors respectively; the main phase detector compares the phase difference between the reference clock generated by the main crystal oscillator and any feedback clock transmitted from the multi-phase divider, aligns the two clocks, and outputs the aligned clock.
[0049] Each phase detector compares the phase difference between the reference clock generated from the crystal oscillator and the feedback clock transmitted from the multi-phase divider, which has a different phase phase than the feedback clock received by other phase detectors, and aligns the two clocks, and outputs the aligned clock.
[0050] Finally, the aligned clock output from the main phase detector is averaged with all the aligned clocks output from the phase detectors, filtered, and then output to the voltage-controlled oscillator.
[0051] The time-interleaved multi-reference clock phase-locked loop proposed in this invention differs from the conventional phase-locked loop structure that uses a reference clock with the same phase and a single-phase divider. Instead, it creatively proposes using a master crystal oscillator and multiple slave crystal oscillators to generate reference clocks with different phases, and innovatively proposes a multi-phase divider structure that generates sequentially delayed feedback clocks. Both of these clocks are input to phase detectors, and each phase detector performs comparison and phase alignment separately.
[0052] Essentially, this involves aligning multiple reference clocks with the multi-phase feedback clock of the frequency divider, achieving noise averaging of the reference clocks in the time domain, thereby reducing the noise of the equivalent reference clock in the phase-locked loop (PLL). Since the output load of the multi-phase frequency divider is distributed across multiple time-interleaved branches, the multiple reference clocks do not flip simultaneously but rather their edges are delayed sequentially, alternating—a process known as "time interleaving." This reduces the disturbance to the power supply and ground network during the phase detector's operation and also reduces the noise of the multi-phase frequency divider's output clock link. This further optimizes the overall noise of the reference clock path, allowing for the design of lower-noise voltage-controlled oscillators (VCOs), ultimately reducing the overall noise of the PLL and demonstrating high practicality. Attached Figure Description
[0053] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:
[0054] Figure 1 This is a schematic diagram of the structure of a phase-locked loop with time interleaving multiple reference clocks according to an embodiment of the present invention;
[0055] Figure 2This is a schematic diagram of the time-interleaved waveform in an embodiment of the present invention;
[0056] Figure 3 This is a schematic diagram of another phase-locked loop structure in an embodiment of the present invention;
[0057] Figure 4 This is a schematic diagram of a preferred structure of the multi-phase frequency divider in an embodiment of the present invention;
[0058] Figure 5 This is a schematic diagram of an exemplary time-interleaved multi-reference clock phase-locked loop structure in an embodiment of the present invention. Detailed Implementation
[0059] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention, and are only some, not all, embodiments of the present invention, and are not intended to limit the present invention.
[0060] In current SoC systems, the ever-advancing wireless communication technologies place higher demands on the phase noise of the frequency sources used (noise in the following text refers to phase noise). Lower noise often requires higher power consumption, and the trade-off between noise and power consumption has become an increasingly important issue in phase-locked loop design.
[0061] The inventors discovered that the noise of a phase-locked loop (PLL) can be broadly divided into two parts: in-band and out-of-band. Out-of-band noise is mainly determined by the voltage-controlled oscillator (VCO), while in-band noise is mainly determined by the reference clock.
[0062] In phase-locked loop (PLL) design, to minimize the overall noise of the PLL, the common strategy is to adjust the PLL bandwidth to balance the contribution ratio of in-band and out-of-band noise. The optimization result is generally that the contribution ratio of in-band noise and out-of-band noise to the total noise is roughly the same.
[0063] Further research by the inventors revealed that in traditional phase-locked loop (PLL) architectures, the reference clock is a single commercial crystal oscillator, lacking design freedom. The theoretical limit (lower bound) of in-band noise is the reference clock noise + log(N). div The overall phase noise of the phase-locked loop (PLL) is 0.5 dBc / Hz. Therefore, to reduce the overall phase noise, a smaller bandwidth is needed to reduce the in-band noise contributed by the reference clock. This necessitates designing a lower-noise VCO to avoid excessive out-of-band noise. However, in VCO design, noise and power consumption are interchangeable; achieving lower noise requires higher power consumption. Therefore, limited by the noise of the reference clock, the overall noise and power consumption of the PLL are difficult to further optimize.
[0064] Further investigation by the inventors revealed that some methods utilize averaging multiple reference clocks in the phase domain to reduce the noise of the equivalent reference clock in the phase-locked loop (PLL), thereby avoiding the aforementioned limitations related to noise and power consumption. However, after in-depth research, the inventors discovered two problems with this PLL architecture:
[0065] (1) In the phase-locked loop architecture, multiple phase detectors are connected to a frequency divider at the same time, which results in a large output load of the frequency divider. The large fan-out coefficient of the clock drive link will cause its noise to deteriorate.
[0066] (2) Since the reference clocks are in phase, multiple reference clocks flip at the same time, and multiple phase detectors work at the same time, resulting in a large instantaneous current of the power supply, which in turn causes the power ground network of the chip to fluctuate violently.
[0067] In response to the aforementioned significant discoveries, the inventors have creatively proposed a time-interleaved multi-reference clock phase-locked loop, on-chip system, and electronic device according to the present invention, which effectively solves the aforementioned problems. The following provides a detailed explanation and description of the time-interleaved multi-reference clock phase-locked loop, on-chip system, and electronic device proposed in this invention.
[0068] The phase-locked loop with time interleaving and multiple reference clocks proposed in this invention includes: a main loop, multiple synchronization loops, a multi-phase divider, and a voltage-controlled oscillator; the main loop includes: a main crystal oscillator and a main phase detector; each of the multiple synchronization loops includes: a slave crystal oscillator and a slave phase detector.
[0069] The multi-phase divider is connected to the master phase detector and all slave phase detectors respectively; the master crystal oscillator is connected to the master phase detector, and the slave crystal oscillator in each synchronization loop is connected to the slave phase detector; the output of all phase detectors is connected to the input of the voltage-controlled oscillator after passing through a filter, and the output of the voltage-controlled oscillator is connected to the multi-phase divider.
[0070] In this process, the main crystal oscillator and multiple reference clocks with different phases generated from the crystal oscillator are output to their respective connected phase detectors; the multi-phase divider generates feedback clocks with sequential delays and outputs them to all phase detectors respectively; the main phase detector compares the phase difference between the reference clock generated by the main crystal oscillator and any feedback clock transmitted from the multi-phase divider, aligns the two clocks, and outputs the aligned clock.
[0071] The above structure can be used Figure 1 The schematic diagram of the phase-locked loop with time interleaving multi-reference clocks shown provides a better understanding. Figure 1The leftmost set of multiple crystal oscillators CO1, CO2, ..., COn can be either master or slave. For example, the topmost crystal oscillator Co1 is the master, and the remaining CO2, ..., COn are slaves. Alternatively, crystal oscillator CO2 can be the master, and the remaining CO1, ..., COn are slaves. Among the multiple phase detectors PD1, PD2, ..., PDn, the one connected to the master crystal oscillator is the master phase detector. For example, if crystal oscillator Co1 is the master, then phase detector PD1 is the master phase detector, and the rest are slave phase detectors.
[0072] Figure 1 The circle and plus sign indicate averaging, which means averaging the output clocks of all phase detectors. The average clock signal is then transmitted to the voltage-controlled oscillator (VCO) via the filter LF. The output of the VCO is connected to the input of the multiphase divider (MPD). The output of the MPD outputs sequentially delayed feedback clocks to each phase detector (PD1, PD2, ..., PDn).
[0073] This invention creatively proposes a master crystal oscillator and multiple slave crystal oscillators generating reference clocks with different phases, referring to... Figure 2 The schematic diagram of the time-interleaved waveform shown shows that the reference clocks generated by the crystal oscillators CO1, CO2, ... Con are all in different phases, and VCO at the bottom represents the clock output by the voltage-controlled oscillator.
[0074] In some possible embodiments, the main loop further includes a main buffer; each synchronization loop further includes a slave buffer; the multi-phase divider is connected to the main phase detector through the main buffer; the multi-phase divider is connected to the slave phase detector in each synchronization loop through the slave buffer in that loop respectively.
[0075] Reference Figure 3 The diagram shows another structural schematic of the phase-locked loop. Figure 3 The example schematically represents multiple loops with 3 loops, where XO is used to represent the main crystal oscillator. Figure 2 For example, PD represents the main phase detector, LoopFilter represents the filter, Multi-ph Div represents the multi-phase divider, and triangle represents the buffer. The upper right corner shows the reference clock phase of each of the three loops, which are different phases.
[0076] Depend on Figure 2 , Figure 3It can be seen that there are as many phase detectors as there are crystal oscillators, and similarly, as many buffers. The feedback clocks output by the multi-ph divider are sequentially delayed. Each feedback clock passes through a buffer and is transmitted to a phase detector. In this way, the output load of the multi-ph divider is distributed across multiple branches with time interleaving. Since the multiple reference clocks do not flip simultaneously but are sequentially delayed at their edges, the main loop and each synchronization loop operate according to the phase order of the sequentially delayed feedback clocks. In the same time period, if the main crystal oscillator XO and the main phase detector PD are in working state, all slave crystal oscillators and slave phase detectors are in standby state.
[0077] If any one of the slave crystal oscillators and its connected slave phase detector is active, the remaining slave crystal oscillators and their corresponding slave phase detectors, as well as the master crystal oscillator XO and the master phase detector PD, are in standby mode. This reduces the disturbance to the power supply and ground network during phase detector operation and also reduces the noise in the multi-ph Div output clock link.
[0078] In some possible embodiments, the multi-phase frequency divider includes a multi-mode frequency divider, an accumulator carry unit, and a multi-phase editor. The multi-mode frequency divider is connected to both the accumulator carry unit and the multi-phase editor. Specifically, the multi-mode frequency divider down-divides the frequency signal output from the voltage-controlled oscillator and transmits the down-divided signal to both the accumulator carry unit and the multi-phase editor. The accumulator carry unit uses the down-divided signal to drive the output signal, causing it to jump between two adjacent integers to control the division ratio of the multi-mode frequency divider, achieving a fractional effect in an average sense. The multi-phase editor splits the down-divided signal into phases, generating sequentially delayed feedback clocks.
[0079] The function of the accumulator carry can be understood as follows: Within one reference clock cycle, the multi-mode divider outputs a total of 8 pulses. The division ratio is 6 for 6 pulses and 7 for 2 pulses. Therefore, the average division ratio of the multi-mode divider is (6*6 + 2*7) / 8 = 6.25. Thus, the 8 output pulses of the multi-mode divider correspond to 8*6.25 = 50, or 50 VCO cycles. This achieves 50 VCO cycles for one reference clock cycle, resulting in an overall division ratio of 50 for the phase-locked loop (PLL). With the help of the accumulator carry, the adjustment step value of the overall PLL division ratio can be 1, which is still equal to that of a traditional single-reference clock PLL. Therefore, the time-interleaved multi-reference structure proposed in this invention does not result in a loss of step accuracy.
[0080] Taking a voltage-controlled oscillator (VCO) output frequency signal of 1000MHz as an example: A multi-mode frequency divider down-divides the 1000MHz signal to obtain an 800MHz clock signal. This 800MHz clock signal is then transmitted to an accumulator and a multi-phase editor. Driven by the 800MHz clock signal, the accumulator's output signal transitions between two adjacent integers, controlling the division ratio of the multi-mode frequency divider to achieve a fractional-value effect in an average sense. The multi-phase editor divides the 800MHz clock signal into phases, generating sequentially delayed feedback clocks.
[0081] It should be noted that the multi-mode frequency divider, accumulator carry, and multi-phase editor mentioned above can be composed of any circuit or component that can achieve the corresponding function. For example, any circuit or component that can achieve frequency reduction can be used as a multi-mode frequency divider. The specific sampling circuit or component can be selected according to actual needs and area overhead, among other factors.
[0082] In some possible embodiments, the preferred structure of the multiphase editor includes: a wide clock generation unit and multiple narrow clock generation units; the wide clock generation unit splits the down-frequency signal into phases to obtain sequentially delayed wide clocks, and forms multiple groups of wide clocks by grouping two adjacent wide clocks according to the order of delay, and outputs them to multiple narrow clock generation units, wherein one group of wide clocks is output to one narrow clock generation unit.
[0083] Each narrow clock generation unit splits a set of wide clocks into phases to obtain a narrow clock; multiple narrow clock generation units each split their own set of wide clocks into phases to obtain sequentially delayed narrow clocks, which are thus sequentially delayed feedback clocks.
[0084] In a preferred structure, the wide clock generation unit includes: a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a first AND gate, an XOR gate, and a NOT gate.
[0085] The input of the first D flip-flop is connected to the output of the AND gate, and the inverted signal of the down-frequency signal is used as the clock signal. The output of the first D flip-flop is connected to the input of the second D flip-flop and the first input of the first AND gate, respectively.
[0086] The second D flip-flop uses the inverted signal of the down-frequency signal as its clock signal, and its output is connected to the second input of the first AND gate and the input of the NOT gate, respectively; the output of the first AND gate is connected to the first input of the XOR gate; the output of the XOR gate is connected to the input of the third D flip-flop, and the third D flip-flop uses the inverted signal of the down-frequency signal as its clock signal.
[0087] The output of the third D flip-flop is connected to the input of the fourth D flip-flop and the second input of the XOR gate, respectively. The fourth D flip-flop uses the inverted signal of the down-frequency signal as the clock signal, and its output outputs a wide clock with sequential delay.
[0088] The narrow clock generation unit includes: a second AND gate and a fifth D flip-flop; the first input of the second AND gate receives the first wide clock in a set of wide clocks, and the second input receives the inverted signal of the second wide clock; the output of the second AND gate is connected to the input of the fifth D flip-flop, which uses the inverted signal of the down-frequency signal as the clock signal, and its output outputs the sequentially delayed narrow clocks.
[0089] The structure of the above-mentioned multi-phase frequency divider can be referred to Figure 4 The schematic diagram of a superior structure of the multi-phase frequency divider shown provides a better understanding. Figure 4 In the example, MMD represents a multimode divider, DSM represents an accumulator carry, and MPG represents a multiphase editor (i.e., Figure 4 (Structure within the dashed box on the right). The upper part of the MPG is the wide clock generation unit, which receives the clock signal clk output from the multi-mode divider MMD and generates a sequentially delayed wide clock PH. W <0>...PH W <n>. Figure 4 In the example, D1 represents the first D flip-flop, D2 represents the second D flip-flop, D3 represents the third D flip-flop, D4 represents the fourth D flip-flop, AND1 represents the first AND gate, NOR represents the XOR gate, and NOT represents the NOT gate.
[0090] The lower half of the MPG consists of multiple narrow clock generation units that receive wide clocks PH. W <n: 0>, Figure 4 The example shows a first narrow clock generation unit that receives wide clocks PH in a delayed sequence, grouped together by two adjacent wide clocks. W <0>, pH W <1>, generates a narrow clock PH N <0>, and so on for the remaining narrow clock generation units. All narrow clock generation units eventually generate a sequentially delayed narrow clock PH. N <n:0>, which is the feedback clock that is delayed sequentially. Figure 4 In the example, D5 represents the fifth D flip-flop, and AND2 represents the second AND gate.
[0091] It should be noted that the above-mentioned wide clock generation unit and narrow clock generation unit are only provided as examples for better understanding. Those skilled in the art can use other circuit structures or components to implement the functions of the wide clock generation unit and narrow clock generation unit respectively, and all of these are within the protection scope of the multi-reference clock phase-locked loop with time interleaving proposed in this invention.
[0092] The sequentially delayed feedback clocks are transmitted to each loop. In addition to the main loop, in each synchronization loop, the aligned clock output from the phase detector is not only used for averaging calculation, but also needs to be output to the slave crystal oscillator connected to itself.
[0093] Reference Figure 5 The diagram shows an exemplary phase-locked loop structure of a time-interleaved multi-reference clock. Figure 5 In the diagram, XO represents the main crystal oscillator, and the PD connected to the main crystal oscillator is the main phase detector. Multiple synchronization loops are exemplarily represented by multiple dashed boxes, and one of the synchronization loops is shown exemplarily, in which the PD represents the slave phase detector.
[0094] The clock aligned to the output of the main phase detector (PD) is PHE. M The aligned clock output from the phase detector PD is PHE. Sk PHE M and PHE Sk All are involved in the averaging calculation. Figure 5 In the calculation, Avg represents the averaging operation. After passing through the filter LF, the clock is transmitted to the voltage-controlled oscillator (VCO). The clock output from the VCO is then transmitted to the multi-ph divider, which generates a sequentially delayed feedback clock that is transmitted to each phase detector (PD).
[0095] In each synchronization loop, the aligned clock PHE is output from the phase detector PD. Sk In addition to participating in the averaging calculation Avg, it also needs to pass through a filter Sync.LF to be output to the slave crystal oscillator VCXO connected to itself. That is, each synchronization loop also includes a filter Sync.LF.
[0096] With the circuit structure of the phase-locked loop described above, the output load of the multiphase divider is distributed across multiple branches with time interleaving. Since the multiple reference clocks do not flip simultaneously but are delayed sequentially at their edges, the main loop and each synchronization loop operate in the phase order of the sequentially delayed feedback clocks. This reduces the disturbance to the power supply and ground network during the moment the phase detector operates, and also reduces the noise in the output clock link of the multiphase divider.
[0097] Based on the above-described phase-locked loop with time-interleaved multi-reference clocks, this embodiment of the invention also provides a system-on-a-chip, the system-on-a-chip including: a phase-locked loop with time-interleaved multi-reference clocks as described above.
[0098] Based on the above-described phase-locked loop with time-interleaved multi-reference clocks, embodiments of the present invention also provide an electronic device, the electronic device comprising: a phase-locked loop with time-interleaved multi-reference clocks as described above.
[0099] In summary, the phase-locked loop of the time-interleaved multi-reference clock of the present invention includes: a main loop, multiple synchronization loops, a multi-phase divider, and a voltage-controlled oscillator; the main loop includes: a main crystal oscillator and a main phase detector; each of the multiple synchronization loops includes: a slave crystal oscillator and a slave phase detector.
[0100] The multi-phase divider is connected to the master phase detector and all slave phase detectors respectively; the master crystal oscillator is connected to the master phase detector, and the slave crystal oscillators in each synchronization loop are connected to the slave phase detectors; the outputs of all phase detectors are filtered and then connected to the input of the voltage-controlled oscillator (VCO), and the output of the VCO is connected to the multi-phase divider. Specifically, the master crystal oscillator and multiple slave crystal oscillators generate reference clocks of different phases and output them to their respective connected phase detectors; the multi-phase divider generates sequentially delayed feedback clocks and outputs them to all phase detectors; the master phase detector compares the phase difference between the reference clock generated by the master crystal oscillator and any feedback clock transmitted from the multi-phase divider, aligns the two clocks, and outputs the aligned clock.
[0101] Each slave phase detector compares the phase difference between the reference clock generated by the connected crystal oscillator and the feedback clock transmitted from the multi-phase divider, which has a different phase from the feedback clock received by other phase detectors. It then aligns the two clocks and outputs the aligned clock. Finally, the aligned clock output by the master phase detector is averaged with the aligned clocks output by all slave phase detectors, filtered, and then output to the voltage-controlled oscillator.
[0102] The time-interleaved multi-reference clock phase-locked loop proposed in this invention differs from the conventional phase-locked loop structure that uses a reference clock with the same phase and a single-phase divider. Instead, it creatively proposes using a master crystal oscillator and multiple slave crystal oscillators to generate reference clocks with different phases, and innovatively proposes a multi-phase divider structure that generates sequentially delayed feedback clocks. Both of these clocks are input to phase detectors, and each phase detector performs comparison and phase alignment separately.
[0103] Essentially, this involves aligning multiple reference clocks with the multi-phase feedback clock of the frequency divider, achieving noise averaging of the reference clocks in the time domain, thereby reducing the noise of the equivalent reference clock in the phase-locked loop (PLL). Since the output load of the multi-phase frequency divider is distributed across multiple time-interleaved branches, the multiple reference clocks do not flip simultaneously but rather their edges are delayed sequentially, alternating—a process known as "time interleaving." This reduces the disturbance to the power supply and ground network during the phase detector's operation and also reduces the noise of the multi-phase frequency divider's output clock link. This further optimizes the overall noise of the reference clock path, allowing for the design of lower-noise voltage-controlled oscillators (VCOs), ultimately reducing the overall noise of the PLL and demonstrating high practicality.
[0104] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.
[0105] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.
[0106] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.
Claims
1. A phase-locked loop with time-interleaved multi-reference clocks, characterized in that, The phase-locked loop includes: a main loop, multiple synchronous loops, a multi-phase frequency divider, and a voltage-controlled oscillator; The main loop includes: a main crystal oscillator and a main phase detector; Each of the plurality of synchronization loops includes: a slave crystal oscillator and a slave phase detector; The multi-phase divider is connected to the master phase detector and all slave phase detectors respectively; The master crystal oscillator is connected to the master phase detector, and the slave crystal oscillator in each synchronization loop is connected to the slave phase detector. The outputs of all phase detectors are connected to the input of the voltage-controlled oscillator after passing through a filter, and the output of the voltage-controlled oscillator is connected to the multi-phase frequency divider. The main crystal oscillator and multiple slave crystal oscillators generate reference clocks with different phases and output them to their respective connected phase detectors; The multi-phase divider generates sequentially delayed feedback clocks, which are then output to all phase detectors respectively. The main phase detector compares the phase difference between the reference clock generated by the main crystal oscillator and any feedback clock transmitted from the multi-phase divider, aligns the two clocks, and outputs the aligned clock. Each phase detector compares the phase difference between the reference clock generated from the crystal oscillator and the feedback clock transmitted from the multi-phase divider, which has a different phase from the feedback clock received by other phase detectors, and aligns the two clocks and outputs the aligned clock. The aligned clock output from the main phase detector is averaged with all aligned clocks output from the phase detectors, filtered by the filter, and then output to the voltage-controlled oscillator.
2. The phase-locked loop according to claim 1, characterized in that, In each synchronization loop, the aligned clock output from the phase detector participates in the averaging operation and is also output to the slave crystal oscillator connected to it.
3. The phase-locked loop according to claim 1, characterized in that, The main loop further includes a main buffer; each synchronization loop further includes a slave buffer. The multi-phase frequency divider is connected to the main phase detector through the main buffer; The multi-phase divider is connected to the slave phase detector in each synchronization loop through the slave buffer in that loop.
4. The phase-locked loop according to claim 1, characterized in that, The multi-phase frequency divider includes: a multi-mode frequency divider, an accumulator carry unit, and a multi-phase editor; The multi-mode frequency divider is connected to the accumulator and the multi-phase editor, respectively. The multi-mode frequency divider down-converts the frequency signal output by the voltage-controlled oscillator and transmits the down-converted signal to the accumulator and the multi-phase editor respectively. The accumulator carry is driven by the down-frequency signal, causing its output signal to jump between two adjacent integers in order to control the division ratio of the multi-mode divider. The multiphase editor divides the down-frequency signal into phases to generate the sequentially delayed feedback clock.
5. The phase-locked loop according to claim 4, characterized in that, The multiphase editor includes: a wide clock generation unit and multiple narrow clock generation units; The wide clock generation unit splits the down-frequency signal into phases to obtain sequentially delayed wide clocks. According to the order of delay, two adjacent wide clocks are grouped together to form multiple groups of wide clocks and output to multiple narrow clock generation units. Among them, one group of wide clocks is output to one narrow clock generation unit. Each narrow clock generation unit splits a set of wide clocks into phases to obtain a narrow clock; Multiple narrow clock generation units each split a set of wide clocks input to themselves into phases to obtain successively delayed narrow clocks, which are the successively delayed feedback clocks.
6. The phase-locked loop according to claim 5, characterized in that, The wide clock generation unit includes: a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a first AND gate, an XOR gate, and a NOT gate; The input terminal of the first D flip-flop is connected to the output terminal of the NOT gate, and the inverted signal of the down-frequency signal is used as the clock signal. The output terminal of the first D flip-flop is connected to the input terminal of the second D flip-flop and the first input terminal of the first AND gate, respectively. The second D flip-flop uses the inverted signal of the down-frequency signal as the clock signal, and its output is connected to the second input of the first AND gate and the input of the NOT gate, respectively. The output of the first AND gate is connected to the first input of the XOR gate; the output of the XOR gate is connected to the input of the third D flip-flop, which uses the inverted signal of the down-frequency signal as its clock signal. The output of the third D flip-flop is connected to the input of the fourth D flip-flop and the second input of the XOR gate, respectively. The fourth D flip-flop uses the inverted signal of the down-frequency signal as the clock signal, and its output terminal outputs a wide clock with sequential delays.
7. The phase-locked loop according to claim 5, characterized in that, The narrow clock generation unit includes: a second AND gate and a fifth D flip-flop; The first input of the second AND gate receives the first wide clock in a set of wide clocks, and the second input receives the inverted signal of the second wide clock. The output of the second AND gate is connected to the input of the fifth D flip-flop. The fifth D flip-flop uses the inverted signal of the down-frequency signal as the clock signal, and its output outputs a narrow clock with sequential delays.
8. The phase-locked loop according to claim 1, characterized in that, The main loop and each synchronization loop operate in the phase sequence of the sequentially delayed feedback clocks; During the same time period, if the main crystal oscillator and the main phase detector are in working state, all slave crystal oscillators and slave phase detectors are in standby state. If any one of the slave crystal oscillators and slave phase detectors and its connected slave phase detector are in working condition, then the remaining slave crystal oscillators and slave phase detectors, as well as the master crystal oscillator and the master phase detector, are in standby condition.
9. A system-on-a-chip, characterized in that, The system-on-a-chip includes: a phase-locked loop with time-interleaved multi-reference clocks as described in any one of claims 1-8.
10. An electronic device, characterized in that, The electronic device includes: a phase-locked loop with time-interleaved multi-reference clocks as described in any one of claims 1-8.