Artificial Intelligence Pixel Sensor Based on Memristor

Abstract

The present disclosure relates to an artificial intelligence pixel sensor based on a memristor. The artificial intelligence pixel sensor based on a memristor includes: a plurality of active pixel sensors, each of which includes: a photodiode configured to receive an image signal; a transmission gate; a selection controller; a reset controller; a voltage readout terminal; a first current readout terminal, a second current readout terminal, and a third current readout terminal connected to a first 1T1R unit, a second 1T1R unit, and a third 1T1R unit, respectively; a first total current readout terminal, a second total current readout terminal, and a third total current readout terminal, wherein the total current is equal to the sum of the currents of all the current readout terminals on each active pixel sensor.

Description

Technical Field

[0001] The present disclosure relates to the field of image sensing technology, and more particularly to an artificial intelligence pixel sensor based on a memristor, and more particularly to an artificial intelligence fusion pixel sensor with an active pixel sensor having a memristor for use in MLP. Background Art

[0002] Many systems include imaging devices that sense and capture optical images, which can be electronically converted into a digital representation of the image. An image sensor includes an array of photosensitive devices, such as photodiodes or phototransistors on a complementary metal oxide semiconductor (CMOS) device. Each photosensitive device is sensitive to light and can therefore generate an electrical charge proportional to the intensity of light impinging on the photosensitive device. The overall image captured by the image sensor includes a plurality of pixels arranged in an array, each of which is capable of detecting the light intensity at that pixel location.

[0003] Imaging devices formed according to conventional CMOS processes are called CMOS imagers and can be configured to include active pixel sensors (APS). An active pixel sensor (APS) includes an integrated circuit containing an array of pixels, each of which includes a photodetector (e.g., a photodiode or other similar device) and other transistors for resetting and gating the stored charge on the photodetector. In a conventional CMOS imager, each pixel cell in the pixel array converts light intensity into charge, accumulates the charge in proportion to the light intensity, and transfers the accumulated charge to an amplifier. In many CMOS imagers, a pixel can be reset to a specific reference voltage level before or after acquiring an image.

[0004] RRAM is a two-terminal passive device that can change resistance in response to an effective electrical stimulus and has attracted great attention in high-performance non-volatile storage applications. The resistance of RRAM can be electrically switched between two states: a high resistance state (HRS) and a low resistance state (LRS). The switching event from HRS to LRS is generally referred to as a "set" or "on" switch; the switching process from LRS to HRS is referred to as a "reset" or "off" switch process.

[0005] Multilayer Perceptron (MLP) is an artificial neural network widely used in many artificial intelligence applications, such as image processing, video processing, machine learning, and natural language processing. It is a neural network with multiple layers connected in a directed graph, which means that the signal path through each node has only one direction. All nodes except the input node have a nonlinear activation function. MLP is a deep learning technique due to the presence of multiple layers of neurons. In MLP, it is usually used as a classifier - determine whether the input vector belongs to one or more categories. It usually gives a probability of which category the input belongs to. For example, a classifier can be trained in MLP to recognize 5 categories of clothing in a low-resolution image.

[0006] Traditional MLP requires an algorithm to construct and train MLP class objects for classification tasks. In the present disclosure, a new architecture of a CMOS image sensor with a crossbar array based on memristors can be used to implement a hardware classifier for MLP. Summary of the invention

[0007] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides an artificial intelligence pixel sensor based on a memristor.

[0008] In a first aspect, an embodiment of the present disclosure provides an artificial intelligence pixel sensor based on a memristor, comprising: a plurality of active pixel sensors, each of which comprises:

[0009] a photodiode configured to receive an image signal;

[0010] Transmission gate;

[0011] Select the controller;

[0012] Reset controller;

[0013] Voltage reading terminal;

[0014] a first 1T1R cell, a second 1T1R cell and a third 1T1R cell connected to the voltage sensing terminal; and a first current sensing terminal, a second current sensing terminal and a third current sensing terminal connected to the first 1T1R cell, the second 1T1R cell and the third 1T1R cell, respectively;

[0015] A first total current readout terminal, wherein the total current is equal to the sum of the currents of the first current readout terminal in each of the active pixel sensors;

[0016] A second total current readout terminal, wherein the total current is equal to the sum of the currents of the second current readout terminal in each of the active pixel sensors;

[0017] A third total current readout terminal has a total current equal to the sum of currents of the third current readout terminal in each of the active pixel sensors.

[0018] In some embodiments, the transmission gate is configured to control a photodiode, the selection controller is configured to control a current transmitted to the voltage readout terminal, and the reset controller is configured to reset the received image signal.

[0019] In some embodiments, the pixel sensor is configured to operate as a classifier.

[0020] In some embodiments, the pixel sensor is configured to perform an analog dot product.

[0021] In some embodiments, each of the first 1T1R cell, the second 1T1R cell, and the third 1T1R cell includes a transistor and a memristor.

[0022] In some embodiments, a first voltage driver and a second voltage driver are further included, wherein the first voltage driver and the second voltage driver are configured to set or reset the first 1T1R cell, the second 1T1R cell, and the third 1T1R cell.

[0023] In some embodiments, it also includes:

[0024] a column decoder coupled to the active pixel sensor;

[0025] a row decoder coupled to the active pixel sensor;

[0026] a column amplifier connected to the first total current sensing terminal, the second total current sensing terminal and the third total current sensing terminal;

[0027] a multiplexer connected to the column amplifier; and

[0028] ADC connected to most multiplexers;

[0029] A memory connected to the ADC.

[0030] In a second aspect, the embodiments of the present disclosure further provide an artificial intelligence pixel sensor based on a memristor, comprising: an active pixel sensor;

[0031] The active pixel sensor comprises:

[0032] a photodiode configured to receive an image signal;

[0033] Transmission gate;

[0034] Select the controller;

[0035] Reset controller;

[0036] Voltage reading terminal;

[0037] a first transistor;

[0038] a second transistor;

[0039] A third transistor;

[0040] a fourth transistor;

[0041] a first voltage driver; and

[0042] a second voltage driver; and

[0043] A memristor-based crossbar array is connected to the active pixel sensor through the voltage readout terminal.

[0044] In some embodiments, a first voltage driver is connected to the first transistor;

[0045] The selection controller is connected to the gate of the second transistor;

[0046] The reset controller is connected to the gate of the third transistor;

[0047] The photodiode is connected to the source of the fourth transistor;

[0048] The transmission gate is connected to the gate of the fourth transistor;

[0049] The second voltage driver is connected to the voltage sensing terminal.

[0050] In some embodiments, the first transistor is configured to provide amplification of an image signal received from the photodiode;

[0051] The second transistor is configured to control a current transmitted to the voltage sensing terminal;

[0052] The third transistor is configured to reset the signal;

[0053] The fourth transistor is configured to control a signal transmitted from the photodiode.

[0054] In some embodiments, a memristor-based crossbar array includes a plurality of 1T1R cells.

[0055] In some embodiments, the first voltage driver and the second voltage driver are configured to set or reset the 1T1R cell.

[0056] In some embodiments, when in the setting mode, the voltage of the first voltage driver is higher than the voltage of the second voltage driver; when in the reset mode, the voltage of the first voltage driver is lower than the voltage of the second voltage driver.

[0057] In some embodiments, the pixel sensor is configured to perform an analog dot product. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0059] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0060] Figure 1A and Figure 1B A block diagram of an MLP architecture without a hidden layer and an MLP architecture with one hidden layer provided in an embodiment of the present disclosure;

[0061] Figure 2 A block diagram of a circuit based on a CMOS image sensor provided in an embodiment of the present disclosure;

[0062] Figure 3 A block diagram of an AI fusion active pixel sensor provided in an embodiment of the present disclosure;

[0063] Figure 4 An operation timing diagram of an AI fusion pixel sensor in AI mode provided by an embodiment of the present disclosure;

[0064] Figure 5 An operation timing diagram of an AI fusion pixel sensor in a memristor SET / RESET mode provided by an embodiment of the present disclosure;

[0065] Figure 6 A schematic layout diagram of the overall layout of an AI fusion pixel sensor with additional memristors and transistors provided in an embodiment of the present disclosure;

[0066] Fig. 7A A block diagram of a non-hidden layer MLP architecture under the operation of an AI fusion pixel sensor having three memristors with conductivity G1, G2 and G3 provided in an embodiment of the present disclosure;

[0067] Figure 7BA formula for the sum of the dot products of Iout1, Iout2 and Iout3 when receiving six Vout signals V1-V6 is provided for an embodiment of the present disclosure, wherein V1-V6 represent six image signals received from a photodiode;

[0068] Figure 8 A schematic block diagram of a modular AI fusion pixel sensor provided in an embodiment of the present disclosure;

[0069] Fig. 9 A schematic block diagram of a modular AI fusion pixel sensor provided in an embodiment of the present disclosure as a three-class classifier.

[0070] The embodiments disclosed herein are illustrated by way of example and not by way of limitation in the accompanying drawings. Like reference numerals refer to corresponding parts throughout the drawings. DETAILED DESCRIPTION

[0071] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0072] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0073] The present disclosure discloses AI fusion pixel sensor technology for MLP using active pixel sensors with memristors. The technology described in the present disclosure can provide the following technical advantages.

[0074] First, the disclosed technology integrates active pixel sensors and memristors, and the AI ​​fusion pixel sensor can perform analog dot products. It demonstrates the feasibility of analog accumulation during AI mode operation. This allows the AI ​​fusion pixel sensor to accumulate light signals received from photodiodes and generate analog dot product results through a memristor-based crossbar array.

[0075] Second, by applying two voltage drivers in the AI ​​fusion pixel sensor, the memristor can be turned on / off during the SET / RESET mode of operation. Therefore, the network can be trained or reprogrammed at different stages of in-memory computing.

[0076] Third, the disclosed technology can work as a classifier in an MLP neural network. This allows the AI ​​fusion pixel sensor to classify the received image signals into pre-set categories, which provides a promising method for making time-efficient deep learning inference hardware, especially for image recognition applications.

[0077] Figure 1A and Figure 1B A block diagram of an MLP architecture without hidden layers and an MLP architecture with one hidden layer provided for an embodiment of the present disclosure. As mentioned above, MLP is an artificial neural network applied to many AI applications, such as image processing, video processing, machine learning, and natural language processing. It is often used as a classifier—determining whether an input vector belongs to one or more categories. It generally gives a probability of which category an input belongs to. This classifier can be applied to image recognition technology, for example, a user can train an MLP classifier for three categories: cats, dogs, and rabbits. Then, the neural network can classify the received images into three categories. Traditional MLPs require the use of software algorithms to build and train MLP class objects for classification tasks. In the present disclosure, a new architecture of a CMOS image sensor with a memristor can be used to implement a hardware classifier for MLP. Figure 1A is an example of an MLP with no hidden layers. Figure 1B is an example of an MLP with one hidden layer. Both of these MLPs can be implemented using or in combination with embodiments of the present disclosure.

[0078] Figure 2 A block diagram 2000 of a circuit 200 based on a CMOS image sensor is provided in accordance with an embodiment of the present disclosure.

[0079] like Figure 2 As shown, the CMOS image sensor-based circuit 200 includes one or more CMOS image sensors 201 configured to receive image or light signals (e.g., AI fusion pixel sensors), a column decoder 203 configured to select pixels for reading out columns, a row decoder 205 configured to select pixels for reading out rows, an amplifier 211 configured to amplify signals from the CMOS image sensor 201 (e.g., column amplifiers), a multiplexer 213 configured to read out signals from the amplifier 211 in sequence or serially (e.g., a time division multiplexer), an ADC 215 configured to convert signals from the amplifier 211 from analog to digital, and a digital memory 221 configured to store signals from the ADC 215.

[0080] When light shines on the CMOS image sensor 201, the CMOS image sensor collects data only from the selected rows and columns. Then, the signal (usually in the form of voltage) is amplified by the amplifier 211. Then, the multiplexer 213 reads out the signal in sequence or serially and sends the signal to the ADC 215. The ADC 215 converts the signal from analog form to digital form so that the digital signal can be stored in the digital memory 221. The digital signal can be processed or accessed by a central processing unit (CPU) or other processor. Here, the CMOS image sensor 201, including an active pixel sensor, can be designed to be implemented as an MLP classifier.

[0081] It should be noted that in order to operate the MLP properly, the row decoder needs to be able to turn on multiple rows at the same time to achieve the vector dot product effect. In addition, in order to implement SET / RESET on the memristor, the VDD (or Vrst) of the image sensor can be adjustable, requiring a global DAC. At the same time, in order to be able to perform SET / RESET on the memristor, a driver for the memristor output node is required, which will be discussed later. Finally, since the VMM is a collection of information from multiple pixels, the result has a larger dynamic range than a single pixel. Therefore, the resolution or dynamic range of the ADC needs to be adjusted.

[0082] Figure 3 An exemplary block diagram 3000 of an AI fusion active pixel sensor 300 provided in an embodiment of the present disclosure. It should be noted that AI fusion here means that it can merge data from multiple sensors, sensors under different filters or classifications, or sensors with different weights, to achieve results far exceeding the results of using each sensor alone.

[0083] like Figure 3 As shown, the AI ​​fusion active pixel sensor 300 includes an active pixel sensor and a memristor-based crossbar array. The active pixel sensor includes a first transistor 301, a second transistor 303, a third transistor 305, and a fourth transistor 307.

[0084] The first transistor 301 is connected to a first voltage driver 331, which provides a drain voltage Vdd 321, a voltage source for amplification. In some embodiments, the first transistor 301 is configured to provide amplification of a signal received from the photodiode by adding a boost current.

[0085] The second transistor 303 includes a drain connected to the source of the first transistor 301. A selection controller (Rs) 313 is connected to the gate of the second transistor 303 and controls the current to the output terminal, wherein a voltage Vout is determined. In some embodiments, the second transistor 303 can be configured to turn on or off the current to the output terminal.

[0086] The third transistor 305 is connected to the gate 3011 of the first transistor 301 through its drain. A reset controller (RST) 315 is connected to the gate of the third transistor 305, and a reset voltage source (Vrst) 325 is connected to the source of the third transistor 305. The third transistor 305 including the reset controller (RST) 315 and the reset voltage source (Vrst) 325 is used for resetting. Specifically, the reset controller (RST) 315 is configured to turn on and off to reset the signal accumulated in the gate 3011 of the first transistor 301, wherein the gate 3011 is a readout node. In some embodiments, the third transistor 305 can be configured to reset the signal accumulated in the gate 3011 of the first transistor 301 in the previous cycle.

[0087] The fourth transistor 307 is connected to the gate of the first transistor 301 and the drain of the third transistor 305 through its drain. The photodiode 327 is connected to the source of the fourth transistor 307. The transmission gate controller Tx 317 is connected to the gate 3071 of the fourth transistor 307 and is configured to control the photodiode 327. Specifically, the photodiode 327 is drained by activating the transmission gate controller Tx 317, and the photodiode signal is transmitted to the readout node, which is the gate 3011 of the first transistor 301. In some embodiments, the fourth transistor 307 is configured to control the signal transmitted from the photodiode 327.

[0088] In addition to the active pixel sensor described above, the present disclosure further includes a unique design of a memristor-based crossbar array at the output.

[0089] like Figure 3As shown, the AI ​​fusion active pixel sensor 300 includes a memristor-based cross array 340. The memristor-based cross array 340 includes one or more 1T1R cells, including a first 1T1R cell 341, a second 1T1R cell 343, and a third 1T1R cell 345 connected in parallel. The memristor-based cross array 340 is connected to the output voltage Vout 323 of the active pixel sensor. At the same time, the second voltage driver 333 is connected to the output voltage Vout 323. The second voltage driver 333 is configured to set or reset the memristor of the memristor-based cross array 340 by applying a forward or reverse voltage to the memristor. By adding a 1T1R cell with an adjustable resistance or conductance circuit, an analog dot product on the pixel sensor can be achieved. For example, the first 1T1R cell 341 includes a first memristor with a conductivity G1, the second 1T1R cell 343 includes a second memristor with a conductivity G2, and the third 1T1R cell includes a third memristor with a conductivity G3. The output currents Iout1, Iout2, and Iout3 are Vout*G1, Vout*G2, and Vout*G3, respectively. By doing this, the user can program G1, G2, and G3 before receiving the signal from the photodiode. With the weighted setting, once the image signal is transmitted in, the image signal can be weighted or classified by multiplying the preset or pre-programmed G1, G2, and G3. This provides a good analog solution for implementing MLP using a pixel sensor with a crossbar array based on a memristor.

[0090] Figure 4 A timing diagram 4000 of an AI fusion pixel sensor operating in AI mode provided for an embodiment of the present disclosure. At the beginning, the selection controller (Rs) 313 is turned on, and the RST pulse is triggered, and the readout signal of the previous cycle is reset. When reset, a small voltage pump reads out Vout and Iout. Next, the transmission gate controller Tx 317 is activated, and the photodiode signal is transmitted to the readout node. As the image signal continues to accumulate, Vout and Iout will increase over time until Tx is turned off. Iout[2:0] refers to Iout2, Iout1, and Iout0. Since the conductivity G of the three memristors is different, the readout current is also different.

[0091] Figure 5A timing diagram 5000 of an AI fusion pixel sensor operating in a memristor SET / RESET mode provided for an embodiment of the present disclosure. As above, in order to program the memristor with different conductivities, the first voltage driver 331 and the second voltage driver 333 are used to set and reset the memristor. In SET / RESET mode, Rs is turned on. In SET mode, Vdd is set to be greater than Vout, so that current flows through the memristors in the forward direction so that they switch to the LRS or on state. Conversely, in RESET mode, VDD is set to be less than Vout, so that current flows through the memristors in the negative direction so that they switch to the HRS or OFF state.

[0092] Figure 6 An exemplary layout diagram 6000 of an overall layout of an AI fusion pixel sensor with additional memristors and transistors provided in an embodiment of the present disclosure. By adding memristors to the pixel sensor, the pixel size can be slightly increased.

[0093] Fig. 7A An architectural block diagram 7000 of an MLP without a hidden layer under the operation of an AI fusion pixel sensor having three memristors with conductivity G1, G2 and G3 provided in an embodiment of the present disclosure.

[0094] Figure 7B A formula 7100 for the sum of the dot products of Iout1, Iout2 and Iout3 when receiving six Vout signals V1-V6 is provided for an embodiment of the present disclosure, where V1-V6 represent six image signals received from the photodiode. Therefore, the AI ​​fusion pixel sensor is configured to classify five images into three categories, thereby implementing MLP.

[0095] Figure 8 A schematic block diagram 8000 of a modular AI fusion pixel sensor provided in accordance with an embodiment of the present disclosure.

[0096] Fig. 9 A schematic block diagram 9000 of a modular AI fusion pixel sensor as a three-class classifier provided in an embodiment of the present disclosure. Fig. 9 As shown, since there are 6 input image signals and three output signals Iout1, Iout2 and Iout3 transmitted through six transmission gates Tx, the total Iout is equal to six Iouts from six crossbar arrays of six pixels. Therefore, the classifier is implemented in a modular implementation.

[0097] like Fig. 9 As shown, it includes a plurality of active pixel sensors 901-906. Each active pixel sensor includes: a photodiode (not shown, it can be Figure 3The same photodiode 327 as shown); transmission gate 913; selection controller 911; reset controller 915; voltage readout terminal (not shown, it can be as Figure 3 same voltage sensing terminal 323 as shown); a first 1T1R unit (not shown, which may be Figure 3 the same 1T1R unit 341 as shown); a second 1T1R unit (not shown, which may be Figure 3 and a third 1T1R unit (not shown, which may be as shown) connected to the voltage sensing terminal. Figure 3 The invention relates to a first 1T1R cell 345 shown in the figure); a first current readout terminal 921, a second current readout terminal 923 and a third current readout terminal 925 connected to the first 1T1R cell, the second 1T1R cell and the third 1T1R cell, respectively; a first total current readout terminal 931, whose total current is equal to the sum of the currents of the first current readout terminal in each active pixel sensor; a second total current readout terminal 933, whose total current is equal to the sum of the currents of the second current readout terminal in each active pixel sensor; and a third total current readout terminal 935, whose total current is equal to the sum of the currents of the third current readout terminal in each active pixel sensor. Therefore, an analog MLP classifier using an active pixel sensor with a memristor is formed.

[0098] Plural instances can be provided for components, operations or structures described herein as singular instances. Finally, the boundaries between various components, operations, and data storage are arbitrary to some extent, and specific operations are explained in the context of specific illustrative configurations. Other functional allocations are foreseen and can fall within the scope of the subject matter of the present invention. Generally speaking, the structure and functionality of components presented as separate components in the exemplary configuration can be implemented as combined structures or components. Similarly, the structure or functionality presented as a single component can be implemented as a separate component. These and other variants, modifications, additions, and improvements can fall within the scope of the subject matter of the present invention.

[0099] It should also be understood that although the terms "first," "second," etc., are used to describe various elements at this point, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first column can be called the second column, and similarly, the second column can be called the first column without changing the meaning of the description, as long as all the first columns are uniformly renamed and all the second columns are uniformly renamed. The first column and the second column can both be S columns, but they are not the same column.

[0100] The terms used herein are only for describing specific implementations and are not intended to limit the claims. As used in the description of this specific implementation and the appended claims, the singular forms of "a" and "the" are intended to also cover the plural forms, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" used herein refers to and covers any and all possible combinations of one or more items in the associated listed items. It will also be understood that the term "comprising" when used in this specification specifies the presence of stated features, integers, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or their grouping.

[0101] As used herein, the term “if” may be interpreted to mean “when the antecedent is true” or “when the antecedent is true” or “in response to determining” or “upon determining” or “in response to detecting” that the antecedent is true, depending on the context. Similarly, the phrase “if it is determined that [the antecedent is true]” or “if [the antecedent is true]” or “when [the antecedent is true]” is interpreted to mean “upon determining that the antecedent is true” or “in response to determining” or “upon determining” that the antecedent is true or “when detecting that the antecedent is true” or “in response to detecting” that the antecedent is true, depending on the context.

[0102] The foregoing description includes example systems, methods, techniques, instruction sequences, and computing machine program products that embody illustrative embodiments. For purposes of explanation, numerous specific details are set forth in order to provide an understanding of various implementations of the subject matter of the invention. However, it will be apparent to those skilled in the art that embodiments of the subject matter of the invention may be practiced without these specific details. Typically, well-known instruction instances, protocols, structures, and techniques are not shown in detail.

[0103] For purposes of illustration, the foregoing description has been described with reference to specific embodiments. However, the above illustrative discussion is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. In light of the above teachings, many modifications and variations are possible. The embodiments are selected and described in order to best explain the principles and their practical application, thereby enabling others skilled in the art to best utilize the embodiments and various embodiments with various modifications to suit the particular use contemplated.

[0104] Although it is obvious to those skilled in the art that additional changes and modifications may be made to the present disclosure after understanding the above description, it should be understood that any specific embodiments shown and described by way of illustration should not be considered limiting. Therefore, the details of various embodiments are not intended to limit the scope of the claims, which themselves merely describe the disclosed technical features.

Claims

1. An artificial intelligence pixel sensor based on a memristor, characterized in that: include: A plurality of active pixel sensors, the active pixel sensors comprising: a photodiode configured to receive an image signal; Transmission gate; Select the controller; Reset controller; Voltage reading terminal; a first 1T1R cell, a second 1T1R cell and a third 1T1R cell connected to the voltage readout terminal, wherein each of the first 1T1R cell, the second 1T1R cell and the third 1T1R cell comprises a memristor; and a first current readout terminal, a second current readout terminal and a third current readout terminal connected to the first 1T1R cell, the second 1T1R cell and the third 1T1R cell, respectively; A first total current readout terminal, wherein the total current is equal to the sum of the currents of the first current readout terminal in each of the active pixel sensors; A second total current readout terminal, wherein the total current is equal to the sum of the currents of the second current readout terminal in each of the active pixel sensors; A third total current readout terminal has a total current equal to the sum of the currents of the third current readout terminal in each of the active pixel sensors.

2. The artificial intelligence pixel sensor based on memristor according to claim 1, characterized in that: The transmission gate is configured to control a photodiode, the selection controller is configured to control a current transmitted to the voltage readout terminal, and the reset controller is configured to reset the received image signal.

3. The artificial intelligence pixel sensor based on memristor according to claim 1, characterized in that: The pixel sensor is configured to operate as a classifier.

4. The artificial intelligence pixel sensor based on memristor according to claim 1, characterized in that: The pixel sensor is configured to perform an analog dot product.

5. The artificial intelligence pixel sensor based on memristor according to claim 1, characterized in that: Each of the first 1T1R cell, the second 1T1R cell and the third 1T1R cell further includes a transistor.

6. The artificial intelligence pixel sensor based on memristor according to claim 1, characterized in that: A first voltage driver and a second voltage driver are also included, and the first voltage driver and the second voltage driver are configured to set or reset the first 1T1R cell, the second 1T1R cell, and the third 1T1R cell.

7. The artificial intelligence pixel sensor based on memristor according to claim 1, characterized in that: Also includes: a column decoder coupled to the active pixel sensor; a row decoder coupled to the active pixel sensor; a column amplifier connected to the first total current sensing terminal, the second total current sensing terminal and the third total current sensing terminal; a multiplexer connected to the column amplifier; ADC connected to most multiplexers; and A memory connected to the ADC.

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