Programs and instructions processing, training and prediction methods and apparatuses, processors

Abstract

The embodiment of the present disclosure provides a program processing method and device, an instruction processing method, a training method of a fetch mode, a prediction method of the fetch mode and a processor. The program processing method comprises: creating an OP_BUILD_START instruction at a first position in a target program; creating an OP_BUILD_END instruction corresponding to the OP_BUILD_START instruction at a second position in the target program, the second position being behind the first position; the OP_BUILD_START instruction is used to instruct the processor to train instructions after the OP_BUILD_START instruction into a microinstruction cache, and the OP_BUILD_END instruction is used to inform the processor to stop training instructions after the OP_BUILD_END instruction into the microinstruction cache. The program processing method improves the utilization rate of the microinstruction cache, improves the switching efficiency and flexibility of the fetch mode, reduces the complexity and power consumption of the processor hardware, and further improves the performance of the system.

Description

TECHNICAL FIELD

[0001] One or more embodiments of the present disclosure relate to a program processing method and apparatus, an instruction processing method, a training method of a fetch mode, a prediction method of a fetch mode, and a processor. BACKGROUND

[0002] Modern processors generally use pipeline technology to process instructions in parallel to accelerate the efficiency of instruction processing. The processor core includes multiple pipeline stages, for example, after the pipeline sends various sources of program counters, the program counter corresponding to the instruction is selected by a multiplexer (Mux) to select the next program counter (PC), and the instruction needs to go through branch prediction, instruction fetch, instruction decoding, instruction dispatch and renaming, instruction execution, and instruction retirement.

[0003] When processing branch instructions, to avoid waiting for the execution result of the branch instruction to determine the branch direction, a branch prediction technology can be used. Through the branch prediction technology, the branch instruction can be predicted, including the branch prediction result of the branch direction, so as to promote the processor to perform the next fetch operation, and avoid the pipeline delay caused by waiting for the execution result of the branch instruction. The branch prediction technology used by the modern processor generally has multiple levels of branch prediction logic. When performing branch prediction, the higher the number of levels of branch prediction logic accessed, the higher the prediction accuracy of branch prediction.

[0004] The processor core translates each architecture instruction (instruction) into one or more micro-instructions (micro-op, uOp) in the micro-architecture. Each micro-instruction only performs a limited operation, which can ensure that different micro-instructions are sent to the corresponding execution component, and the execution flow stage of each micro-instruction is relatively short, and multiple micro-instructions can operate in parallel and out of order, thereby improving the performance of the processor core. SUMMARY

[0005] The program processing method provided in at least one embodiment of the present disclosure includes: creating an OP_BUILD_START instruction at a first position in a target program; and creating an OP_BUILD_END instruction corresponding to the OP_BUILD_START instruction at a second position in the target program, located after the first position, wherein the OP_BUILD_START instruction is used to instruct a processor to train instructions after the OP_BUILD_START instruction into a microinstruction cache, and the OP_BUILD_END instruction is used to inform the processor to stop training instructions after the OP_BUILD_END instruction into the microinstruction cache.

[0006] For example, the program processing method provided in at least one embodiment of the present disclosure further includes: determining an object loop body in the target program, taking an entry position of the object loop body as the first position, and taking an exit position of the object loop body as the second position.

[0007] For example, in the program processing method provided in at least one embodiment of the present disclosure, the target program includes a first loop body and a second loop body; and determining an object loop body in the target program includes: in response to a number of execution times or a number of instructions of the first loop body being greater than a number of execution times or a number of instructions of the second loop body, determining the first loop body as the object loop body.

[0008] For example, the program processing method provided in at least one embodiment of the present disclosure further includes: determining an object loop body in the target program; in response to a number of program instructions of the object loop body being greater than a storage capacity of the microinstruction cache, and in response to a difference between the number of program instructions of the object loop body and a number of program instructions stored in the microinstruction cache reaching a threshold value, taking an entry position of the object loop body as the first position, and determining the second position inside the object loop body.

[0009] For example, in the program processing method provided in at least one embodiment of the present disclosure, the OP_BUILD_START instruction and the OP_BUILD_END instruction are both empty instructions.

[0010] For example, in the program processing method provided in at least one embodiment of the present disclosure, a compiler is used to create the OP_BUILD_START instruction at the first position and create the OP_BUILD_END instruction at the second position.

[0011] The instruction processing method provided in at least one embodiment of the present disclosure comprises: in response to identifying an OP_BUILD_START instruction in the process of executing a target program, training instructions after the OP_BUILD_START instruction into a microinstruction cache; in response to identifying an OP_BUILD_END instruction corresponding to the OP_BUILD_START instruction in the process of executing the target program, stopping training instructions after the OP_BUILD_END instruction into the microinstruction cache, wherein the OP_BUILD_START instruction is at a first position of the target program, and the OP_BUILD_END instruction is at a second position of the target program after the first position.

[0012] For example, the instruction processing method provided in at least one embodiment of the present disclosure, wherein the target program comprises an object loop body, an entry position of the object loop body is the first position, and an exit position of the object loop body is the second position.

[0013] For example, the instruction processing method provided in at least one embodiment of the present disclosure further comprises: in response to entering an instruction cache fetch mode in response to a microinstruction cache fetch missing of a first object instruction after the OP_BUILD_START instruction, determining whether the first object instruction jumps out of the object loop body; in response to the first object instruction not jumping out of the object loop body, continuing to train the first object instruction and instructions after the first object instruction into the microinstruction cache.

[0014] The training method for the fetch mode of the processor provided in at least one embodiment of the present disclosure includes: obtaining branch instruction information of an object branch instruction immediately before an OP_BUILD_END instruction; determining whether the object branch instruction jumps according to the branch instruction information to determine a manner of updating a confidence value of a start microinstruction cache fetch mode corresponding to the object branch instruction; and reading a branch prediction buffer table entry corresponding to the object branch instruction and writing the updated confidence value of the start microinstruction cache fetch mode, wherein the OP_BUILD_START instruction is used to instruct the processor to train instructions after the OP_BUILD_START instruction into a microinstruction cache, the OP_BUILD_END instruction is used to inform the processor to stop training instructions after the OP_BUILD_END instruction into the microinstruction cache, the OP_BUILD_START instruction is at a first position of the target program, and the OP_BUILD_END instruction is at a second position of the target program after the first position.

[0015] For example, in the training method provided in at least one embodiment of the present disclosure, the branch instruction information of the object branch instruction immediately before the OP_BUILD_END instruction is obtained by: determining the branch instruction information of the object branch instruction when the OP_BUILD_END instruction reaches a release stage.

[0016] For example, in the training method provided in at least one embodiment of the present disclosure, the target program includes an object loop body, an entry position of the object loop body is the first position, and an exit position of the object loop body is the second position.

[0017] For example, the training method provided in at least one embodiment of the present disclosure further includes: in response to an instruction length of the loop body being less than or equal to a capacity of the microinstruction cache, determining that a branch instruction immediately before the OP_BUILD_END instruction in the microinstruction cache is the object branch instruction; or in response to the instruction length of the loop body being greater than the capacity of the microinstruction cache, determining that, when all instructions of the loop body are released, a branch instruction with a branch prediction target address being an instruction address of the OP_BUILD_START instruction is the object branch instruction.

[0018] For example, in the training method provided by at least one embodiment of the present disclosure, the manner of determining whether the object branch instruction jumps according to the branch instruction information to determine whether to update the confidence value of the start micro instruction cache fetch mode corresponding to the object branch instruction comprises: when it is determined according to the branch instruction information that the execution direction of the object branch instruction is not jump, it is determined to reduce the confidence value of the start micro instruction cache fetch mode; and when it is determined according to the branch instruction information that the execution direction of the object branch instruction is jump, it is determined to increase the confidence value of the start micro instruction cache fetch mode.

[0019] For example, in the training method provided by at least one embodiment of the present disclosure, writing the updated confidence value of the start micro instruction cache fetch mode comprises: when the OP_BUILD_END instruction is released, writing the updated confidence value of the start micro instruction cache fetch mode in the branch prediction buffer table entry corresponding to the object branch instruction.

[0020] At least one embodiment of the present disclosure provides a fetch mode prediction method, which comprises: obtaining an object branch instruction in a target program comprising an OP_BUILD_START instruction and an OP_BUILD_END instruction; querying the object branch instruction in a branch prediction buffer to determine whether to perform branch prediction on the object branch instruction and whether to determine the entry of a micro instruction cache fetch mode for the object instruction, wherein a table entry of the branch prediction buffer comprises a confidence value of a start micro instruction cache fetch path for predicting whether to start the micro instruction cache fetch mode, the OP_BUILD_START instruction is used to instruct a processor to train instructions after the OP_BUILD_START instruction into a micro instruction cache, the OP_BUILD_END instruction is used to instruct the processor to stop training instructions after the OP_BUILD_END instruction into the micro instruction cache, the OP_BUILD_START instruction is at a first position of the target program, and the OP_BUILD_END instruction is at a second position after the first position in the target program.

[0021] For example, in the prediction method provided by at least one embodiment of the present disclosure, in response to the branch prediction direction of the object branch instruction being jump and the confidence value of the start micro instruction cache fetch mode being greater than a set value, entering the micro instruction cache fetch mode after the branch target address of the object branch instruction arrives; and in response to the branch prediction direction of the object branch instruction being not jump or the confidence value of the start micro instruction cache fetch mode being <= the set value, maintaining the current fetch mode after the branch target address of the object branch instruction arrives.

[0022] The program processing apparatus provided by at least one embodiment of the present disclosure comprises: a first creating module configured to create an OP_BUILD_START instruction at a first position in a target program; and a second creating module configured to create an OP_BUILD_END instruction corresponding to the OP_BUILD_START instruction at a second position in the target program after the first position, wherein the OP_BUILD_START instruction is used to instruct a processor to train instructions after the OP_BUILD_START instruction into a microinstruction cache, and the OP_BUILD_END instruction is used to inform the processor to stop training instructions after the OP_BUILD_END instruction into the microinstruction cache.

[0023] The processor provided by at least one embodiment of the present disclosure comprises a decoding unit and a microinstruction cache, wherein the decoding unit is configured to, in response to identifying an OP_BUILD_START instruction in a process of executing a target program, train instructions after the OP_BUILD_START instruction into a microinstruction cache, and in response to identifying an OP_BUILD_END instruction corresponding to the OP_BUILD_START instruction in the process of executing the target program, stop training instructions after the OP_BUILD_END instruction into the microinstruction cache, wherein the OP_BUILD_START instruction is at a first position in the target program, and the OP_BUILD_END instruction is at a second position in the target program after the first position.

[0024] For example, the processor provided by at least one embodiment of the present disclosure further comprises a branch prediction unit and a branch prediction buffer, wherein the branch prediction unit is configured to: acquire branch instruction information of an object branch instruction immediately before the OP_BUILD_END instruction, determine whether the object branch instruction jumps according to the branch instruction information to determine whether to update a confidence value of a start microinstruction cache pointer mode corresponding to the object branch instruction, read a branch prediction buffer entry corresponding to the object branch instruction, and write the updated confidence value of the start microinstruction cache pointer mode.

[0025] For example, in the processor provided by at least one embodiment of the present disclosure, the branch prediction unit is further configured to: acquire an object branch instruction in a target program comprising an OP_BUILD_START instruction and an OP_BUILD_END instruction, and query the object branch instruction in a branch prediction buffer to determine whether to perform branch prediction on the object branch instruction and whether to determine whether the object instruction enters a microinstruction cache pointer mode. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and not all embodiments of the present disclosure.

[0027] Figure 1A A schematic diagram of a pipeline of a processor core is shown;

[0028] Figure 1A A schematic diagram of a front-end architecture of a processor is shown;

[0029] Figure 2 Examples of some loop bodies in a target program are shown;

[0030] Figure 3 Examples of a situation in which two loop bodies are nested in a target program are shown;

[0031] Figure 4 A flowchart of an instruction processing method according to an example of at least one embodiment of the present disclosure is shown;

[0032] Figure 5 A flowchart of a training method of a fetch mode according to an example of at least one embodiment of the present disclosure is shown;

[0033] Figure 6 A flowchart of a prediction method of a fetch mode according to an example of at least one embodiment of the present disclosure is shown;

[0034] Figure 7 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0035] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present disclosure.

[0036] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0037] The present disclosure is described below using several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numeral in each drawing.

[0038] In this disclosure, descriptions are generally made with respect to a "processor core", but for convenience, the "processor core" is also referred to as a "processor", that is, in this disclosure, at least in terms of the instruction processing pipeline, the "processor" and the "processor core" are equivalent.

[0039] Figure 1A FIG1 shows a schematic diagram of a pipeline of a processor core, wherein the dotted line with an arrow in the figure represents the redirected instruction flow. Figure 1AAs shown, the processor cores (e.g., CPU cores) of single-core or multi-core processors utilize pipeline technology to improve instruction-level parallelism. The processor core internally includes multiple pipeline stages. For example, after program counters (PCs) are fed into the pipeline from various sources and the next program counter (PC) is selected by a multiplexer (Mux), the instruction corresponding to that PC undergoes branch prediction, instruction fetch, instruction decoding, instruction dispatch and rename, instruction execution, and instruction retirement. Waiting queues are set up between each pipeline stage as needed; these queues are typically first-in, first-out (FIFO) queues. For example, after the branch prediction unit, there's a branch prediction (BP) FIFO queue to store branch prediction results; after the instruction fetch unit, there's an instruction cache (IC) FIFO to cache fetched instructions; after the instruction decode unit, there's a decode (DE) FIFO to cache decoded instructions; and after the instruction dispatch and rename unit, there's a finish (RT) FIFO to cache instructions waiting for completion confirmation. The processor core's pipeline also includes an instruction queue to cache instructions waiting for execution by the instruction execution unit after instruction dispatch and renaming.

[0040] The scalar processor (CPU) instruction pipeline consists of a five-stage pipeline, in which each instruction can be issued in each clock cycle and executed within a fixed time period (for example, 5 clock cycles). The execution of each instruction is divided into 5 steps: instruction fetch (IF) stage, decode (DE) stage, execute (EX) stage, memory access (MEM) stage, and write back (WB) stage. For example, superscalar processors can further support out-of-order execution. Out-of-order execution refers to the technology used by the CPU to allow multiple instructions to be sent to the corresponding circuit units for processing separately, not in the order specified by the program.

[0041] The processor pipeline can usually be divided into the front end and the back end. Figure 1B A schematic diagram of a front-end architecture of a processor is shown. Figure 1B As shown, the front-end architecture 10 of the processor includes a branch predictor 101, a branch instruction prediction information queue 102, an instruction cache (IC) 103, a decoder 104, a microinstruction processing module 105, a microinstruction cache (OC) 106, a microinstruction queue 107 and a dispatcher (instruction transmitter) 108.

[0042] The following combination Figure 1B The process of instruction fetch, decoding and transmission in the front-end architecture of the processor is described. In this process, the branch predictor 101 first sends the instruction fetch prediction information to the branch instruction prediction information queue 102 for buffering, waiting for the processing of the prediction information.

[0043] The instruction address obtained by the instruction fetch unit is predicted through branch prediction to obtain the address of the instruction to be executed next. The instruction address is determined by the instruction fetch mode selection logic to determine whether the instruction corresponding to the instruction address needs to be decoded. If "yes", then go to Figure 1B The left path in the middle decodes the instruction; if "no", then go to Figure 1B The path on the right does not need to decode the instruction, but instead accesses the microinstruction cache to directly obtain the corresponding microinstruction group data.

[0044] For the instruction fetch mode selection logic, for example, the processor initially enables the instruction cache instruction fetch mode (IC instruction fetch mode) to process the prediction information. For example, first, based on the predicted address information in the prediction information from the branch instruction prediction information queue (or branch target buffer) 102, try to extract the instruction data requested by the prediction information from the instruction cache 103, and send the instruction data to the decoder 104 for decoding. The instruction data here can be continuous binary data. The decoder 104 can decode the acquired instruction data into a corresponding microinstruction group (for example, each microinstruction group includes one or more microinstructions), and send the microinstruction group to the microinstruction queue 107 cache to wait for distribution ( Figure 1B not shown).

[0045] The decoder 104 also sends the decoded microinstruction group to the microinstruction buffer 106 for caching, that is, "training" the decoded microinstructions into the microinstruction buffer. At this time, a microinstruction buffer entry for storing the microinstructions can be created in the microinstruction buffer 106. One or more microinstructions in the microinstruction group are cached in the created microinstruction buffer entry. For example, one microinstruction buffer entry can store 8 microinstructions. When caching microinstructions, the microinstruction buffer 106 provides judgment information on whether the microinstruction already exists in the microinstruction buffer 106. For example, when a microinstruction already exists in the microinstruction buffer 106, the microinstruction buffer 106 can provide cache hit information, and when a microinstruction does not exist in the microinstruction buffer 106, the microinstruction buffer 106 can provide cache miss information.

[0046] The controller in the processor determines whether to enable an OC fetch mode based on the cache hit or miss information provided by the microinstruction cache 106. In one embodiment, for example, when the microinstruction cache 106 provides a cache hit information that a number of consecutive microinstruction groups are present in the microinstruction cache 106, the determination is "yes" and the OC fetch mode is enabled. When the determination is "no", the prediction information is processed in the IC fetch mode.

[0047] In response to enabling the OC fetch mode, the prediction information in the branch instruction prediction information queue 102 is sent to a microinstruction cache fetch queue included in the microinstruction processing module 105 and to the microinstruction cache 106. The microinstruction cache 106 determines whether a microinstruction group corresponding to the prediction information can be fetched from the microinstruction cache 106 based on the address information in the prediction information. For example, in response to being unable to fetch the microinstruction group corresponding to the prediction information, the system reverts to processing the prediction information in the IC fetch mode and processes the prediction information that is not currently cache hit in the IC fetch mode.

[0048] In response to being able to fetch the microinstruction group corresponding to the prediction information, the fetched microinstruction group is sent to the microinstruction queue 107 for dispatch. The microinstruction queue 107 sequentially sends microinstruction groups from the instruction cache (IC) fetch mode or the microinstruction cache (OC) fetch mode to the dispatcher 108 for backend execution, such as register renaming, execution, retirement, etc.

[0049] For branch prediction techniques, information related to branch instructions can be stored in a Branch Target Buffer (BTB). In current designs, the BTB is usually a multi-way set-associative structure, and the instruction address information (or the instruction address after hashing) is used as the index address. Meanwhile, the instruction address information (or the instruction address after hashing) is used as the tag for comparison, so as to determine whether the instruction address hits an entry (or data item) of the BTB.

[0050] The inventors of the present disclosure have noticed that a prediction system, for example, including an OC instruction fetch mode (or instruction fetch path), mostly needs to rely on the training of a microinstruction cache, that is, by guessing the hit rate of the microinstruction cache, to predict whether the instruction fetch system needs to enter the OC instruction fetch mode. For example, a microsystem corresponding to the microinstruction cache specification can be created in the instruction fetch module. By looking up the microsystem, it is predicted whether the system enters the OC instruction fetch mode. Therefore, branch instruction information needs to be considered in the design, for example, only when the current instruction is the jump target instruction of the branch instruction, the microsystem lookup information is selected to enter the OC instruction fetch mode. In the training process of the microinstruction cache, the system instruction fetch mode is mostly in the IC instruction fetch path, that is, the microinstruction information passing through the instruction decoding circuit is stored in the microinstruction cache.

[0051] In the above design, the instruction fetch path prediction system needs to additionally maintain a microsystem device corresponding to the microinstruction cache specification. The device increases the area of the chip, and due to the reading and training of the microsystem, the power consumption of the system is also increased.

[0052] In the training process of the microinstruction cache, the product expects to improve the hit rate of the microinstruction cache, so that all the microinstruction information obtained in the IC instruction fetch mode is trained into the microinstruction cache. However, the entering of the OC instruction fetch mode largely depends on the program itself. The characteristics of some program segments determine that it will not enter the OC instruction fetch mode, so the microinstruction cache training for the program segment is meaningless. Moreover, in this state, the training power consumption of the microinstruction cache is relatively large, and the efficiency of the OC instruction fetch mode is low. Moreover, since the instruction behavior of a computer program is usually very complex, the hardware system is forced to adapt to and perceive the complex instruction behavior, which leads to the need for the hardware to maintain a complex system, and the system is not friendly to all software program behaviors.

[0053] To solve the above problems, one or more embodiments of the present disclosure provide a program processing method and device, an instruction processing method, an instruction fetch mode training method, an instruction fetch mode prediction method, and a processor, which adopt a combination of software and hardware to improve the efficiency of the OC instruction fetch mode, reduce the power consumption of the microinstruction cache training, and reduce the hardware design overhead and manufacturing cost.

[0054] One or more embodiments of the present disclosure provide a program processing method, which comprises: creating an OP_BUILD_START instruction at a first position in a target program; creating an OP_BUILD_END instruction corresponding to the OP_BUILD_START instruction at a second position in the target program, which is behind the first position. Here, the OP_BUILD_START instruction is used to instruct the processor to train instructions after the OP_BUILD_START instruction into a microinstruction cache, and the OP_BUILD_END instruction is used to inform the processor to stop training instructions after the OP_BUILD_END instruction into the microinstruction cache.

[0055] In the above embodiments, at least two microinstruction cache (OC) instruction fetching mode prediction instructions are introduced, which include the OP_BUILD_START instruction and the OP_BUILD_END instruction, the former is used to indicate the start of OC instruction fetching mode training, and the latter indicates the end of OC instruction fetching mode training.

[0056] For example, the above microinstruction cache instruction fetching mode prediction instructions can be created in an instruction set, thereby providing a microarchitecture supporting the microinstruction cache instruction fetching mode prediction instructions and a processor having the microarchitecture. For example, taking the X86 instruction set as an example, two different OPCODE encodings can be defined to define the OP_BUILD_START instruction and the OP_BUILD_END instruction respectively. Embodiments of the present disclosure can also be used for other types of instruction sets, such as ARM, RISC-V, MIPS, etc.

[0057] For example, in at least one example, the OP_BUILD_START instruction and the OP_BUILD_END instruction are no-operation (NOP) instructions, for example, they are sent to a fixed-point execution unit when executed and do not perform specific operations; in other examples, one or more microinstruction cache instruction fetching mode prediction registers are provided, the OP_BUILD_START instruction modifies the register when executed to indicate that the current OC instruction fetching mode prediction state is entered (for example, the value of the register is modified to 1), and the OP_BUILD_END instruction modifies the register when executed to indicate that the current OC instruction fetching mode prediction state is exited (for example, the value of the register is modified to 0).

[0058] In the embodiment of the program processing method described above, there is no limitation on the form of the "target program" as the processing object, which can be a computing program in machine language, assembly language or high-level language. In order to insert / create the OP_BUILD_START instruction and the OP_BUILD_END instruction at a predetermined position in the target program, for example, it can be performed by a compiler when compiling the computing program, or manually operated by a programmer. For example, the OP_BUILD_START instruction and the OP_BUILD_END instruction appear in pairs, and multiple pairs of OP_BUILD_START instructions and OP_BUILD_END instructions can be included in the same target program, which are spaced apart from each other, i.e., the instruction sequence between the OP_BUILD_START instructions and the OP_BUILD_END instructions of different pairs does not overlap each other.

[0059] The OP_BUILD_START instruction is set at a first position in the target program, and the OP_BUILD_END instruction is set at a second position in the target program, which is after the first position. Therefore, each instruction in the target program between the OP_BUILD_START instruction and the OP_BUILD_END instruction will be trained into the microinstruction cache.

[0060] In at least one embodiment of the present disclosure, the first position and the second position are determined based on a loop body in the target program. The instructions in the loop body can be executed more than once, so training the instructions in the loop body into the microinstruction cache can improve the efficiency of instruction execution. The loop body (or loop structure) is a program structure set in the program to repeatedly perform a certain function, which can be regarded as a combination of a conditional judgment statement and a back steering statement. The loop structure is usually composed of three elements, namely the loop variable, the loop body and the loop termination condition. There are three common loop structures, namely for loop, while loop and do-while loop. Both while loop and for loop judge the expression first and then execute the loop body; do-while loop executes the loop body first and then judges the expression, the specific content is not described here.

[0061] For example, in at least one embodiment of the present disclosure, the program processing method further includes: determining a target loop body in the target program, taking the entry position of the target loop body as the first position and the exit position of the target loop body as the second position. Here, the "target loop body" is a loop body as a description object, which can be used to refer to any type of loop body.

[0062] For example, in at least one embodiment of the present disclosure, the program processing method further includes: determining an object loop body in the target program; in response to the number of program instructions of the object loop body being greater than the storage capacity of the microinstruction cache, and in response to the difference between the number of program instructions of the object loop body and the number of program instructions stored in the microinstruction cache reaching a threshold value, determining a first position inside the object loop body and taking the exit position of the object loop body as a second position. Generally, the storage capacity of the microinstruction cache is of a fixed size, so in some cases the number of program instructions of the object loop body of the program can be greater than the storage capacity of the microinstruction cache, so the object loop body cannot be completely cached in the microinstruction cache; when the number of program instructions of the object loop body exceeds a certain amount, the starting position (i.e., the first position) for training inside the object loop body can be selected. For example, the threshold value can be set as needed.

[0063] For example, Figure 2 Examples of some loop bodies in the target program are shown, for example, in Figure 2 (1) in which there is only one branch instruction in the loop body, in Figure 2 (2) in which there are only two branch instructions in the loop body, in Figure 2 (3) in which there are only three branch instructions in the loop body, and in Figure 2 (4) in which there are n branch instructions (n is greater than 3) in the loop body. The determination of the instruction loop body and the number of branch instructions included in the loop body have no absolute relationship. The loop body needs to include a branch instruction whose branch jump direction is determined to be taken (Taken, abbreviated as “T”) and the jump destination address is less than the address where the branch instruction is located; according to the type of the loop body (for loop, while loop, and do-while loop), the branch instruction can be at different positions in the loop body.

[0064] For example, in at least one embodiment of the present disclosure, the target program includes a plurality of loop bodies, for example, including a first loop body and a second loop body, and determining an object loop body in the target program includes: in response to the number of instructions or the number of executions of the first loop body in the target program being greater than the number of instructions or the number of executions of the second loop body, determining the first loop body as the object loop body.

[0065] In some cases, a plurality of (for example, two or more) loop bodies are nested or crossed, at which time one or a part of the loop bodies or all of the loop bodies can be selected for training according to the number of loops (also referred to as the HOT degree) of each loop body in the execution process of the target program.

[0066] Figure 3It is shown that the two loop bodies (i.e. loop body 1 and loop body 2) are nested in the target program. At this time, according to the HOT degree of the two loop bodies, it can be selected to train only the loop body 1 or the loop body 2, or to train both of the loop bodies, and for the two cases, the first position and the second position for inserting the OP_BUILD_START instruction and the OP_BUILD_END instruction are different respectively.

[0067] The target program after the processing of any of the above embodiments can be stored or transmitted, and then can be executed in a processor, for example. The embodiments of the present disclosure do not limit the type, structure, etc. of the processor.

[0068] Correspondingly, at least one embodiment of the present disclosure provides a program processing apparatus, which comprises a first creating module and a second creating module. The first creating module is configured to create an OP_BUILD_START instruction at a first position in a target program; and the second creating module is configured to create an OP_BUILD_END instruction corresponding to the OP_BUILD_START instruction at a second position in the target program, which is after the first position. For example, the first creating module and the second creating module can be implemented by software, firmware, hardware or any combination thereof; when they are at least partially implemented by software, when executed by a processor, the above-mentioned program processing method can be implemented.

[0069] For example, in at least one embodiment of the present disclosure, the program processing apparatus comprises an object loop body determining module, which is configured to determine an object loop body in the target program, and take an entry position of the object loop body as the first position and take an exit position of the object loop body as the second position.

[0070] For another example, in at least one embodiment of the present disclosure, the object loop body is configured to: in response to a program instruction number of the object loop body being greater than a storage capacity of a microinstruction cache, and in response to a difference between the program instruction number of the object loop body and a program instruction number stored in the microinstruction cache reaching a threshold value, take the entry position of the object loop body as the first position, and determine the second position inside the object loop body (insert the OP_BUILD_END instruction inside the object loop body).

[0071] For example, in at least one embodiment of the present disclosure, the object loop body is further configured to: in response to an execution frequency or an instruction number of a first loop body being greater than an execution frequency or an instruction number of a second loop body, determine the first loop body as the object loop body.

[0072] At least one embodiment of the present disclosure provides an instruction processing method, which comprises: in response to identifying an OP_BUILD_START instruction in the process of executing a target program, training instructions after the OP_BUILD_START instruction into an OC; and in response to identifying an OP_BUILD_END instruction corresponding to the OP_BUILD_START instruction in the process of executing the target program, stopping training instructions after the OP_BUILD_END instruction into a microinstruction cache.

[0073] As described above, instructions of a target program will be sent into a processor for execution. The processor generally uses pipeline technology to process instructions in parallel to accelerate the efficiency of instruction processing. During execution, if the processor identifies that the OP_BUILD_START instruction needs to be executed at present, other instructions after the OP_BUILD_START instruction need to be trained into a microinstruction cache, i.e., one or more microinstructions (such as a microinstruction group) obtained after decoding the instructions will be cached into the microinstruction cache; and during execution, if the processor identifies that the OP_BUILD_END instruction needs to be executed at present, the above training process will not be performed, i.e., training instructions after the OP_BUILD_END instruction into the microinstruction cache will be stopped. The above instruction processing method is performed in the front end of the processor, for example.

[0074] For example, in at least one embodiment of the present disclosure, in the above instruction processing method, the target program comprises an object loop body, an entry position of the object loop body is a first position, and an exit position of the object loop body is a second position. Thus, instructions in the loop body are trained into the microinstruction cache.

[0075] As described above, during the execution of a target program, one or more instructions to be processed can be processed in an IC instruction fetching mode or an OC instruction fetching mode. During the process of the IC instruction fetching mode, it can be determined whether to perform OC training according to the above setting; during the process of the OC instruction fetching mode, there is no decoding process for the instructions to be processed and corresponding microinstructions have been cached in the OC, so there is no need to perform OC training for the instructions to be processed. On the other hand, if an OC instruction fetching miss occurs, the processor exits the OC instruction fetching mode and returns to the IC instruction fetching mode, and it is necessary to determine whether to continue training the OC. For example, when a SNOOP operation occurs or a previous entry in the microinstruction cache is overwritten, the OC instruction fetching can miss, so that the OC instruction fetching of the loop body is stopped.

[0076] For example, in at least one embodiment of the present disclosure, the above-mentioned instruction processing method further comprises: in response to an OC miss (Miss) of a first object instruction after the OP_BUILD_START instruction, entering IC instruction fetching, determining whether the first object instruction jumps out of the object loop body; in response to the first object instruction not jumping out of the object loop body, continuing to train the first object instruction and the instructions after the first object instruction into the microinstruction cache. The subsequent instructions are continued to be trained into the microinstruction cache until the OP_BUILD_END instruction is identified. For example, the determination of whether to jump out of the loop body can be achieved by detecting whether the corresponding instruction is between the OP_BUILD_START instruction and the OP_BUILD_END instruction.

[0077] For example, in at least one embodiment of the present disclosure, the above-mentioned instruction processing method further comprises: in response to determining that the first object instruction does not jump out of the object loop body, creating a first identifier; after decoding the first object instruction, determining, according to the first identifier, to continue to train the first object instruction and the instructions after the first object instruction into the OC.

[0078] For example, in at least one embodiment of the present disclosure, in the case that the microinstruction cache instruction fetching mode prediction register is provided in the processor, it can be determined whether to continue the OC training by judging the value of the current microinstruction cache instruction fetching mode prediction register.

[0079] Figure 4 A flowchart of an instruction processing method according to an example of at least one embodiment of the present disclosure is shown. As shown in the figure, the processing method comprises the following steps 410-470. Figure 4

[0080] The instruction address fetched by the above-mentioned instruction fetching unit is predicted by branch prediction to obtain the instruction address to be executed next time (hereinafter referred to as "current instruction address", and the corresponding instruction is referred to as "current instruction"). The current instruction may, for example, be located in a certain loop body which needs to be trained by the OC, marked by the OP_BUILD_START instruction and the OP_BUILD_END instruction.

[0081] In step 410, it is determined by the instruction fetching mode selection logic whether the instruction corresponding to the current instruction address needs to be decoded. If the OC instruction fetching mode is selected, proceed to step 420; if the IC instruction fetching mode is selected, proceed to step 440.

[0082] In step 420, enter the OC instruction fetching mode, and use the instruction address to query whether the corresponding microinstruction exists in the microinstruction cache. If it exists, the query hits, the fetched microinstruction is sent to the microinstruction queue, and the transmission and other operations are performed; otherwise, the query misses, and proceed to step 430. ​

[0083] In step 430, it is determined whether the current instruction address (i.e. the current instruction) jumps out of the loop body, and whether the loop body is exited, and then returns to step 410 and selects to enter the IC instruction fetching mode.

[0084] For example, the identification is an example of the first identification in the present disclosure.

[0085] In step 440, the IC instruction fetching mode is entered, and it is queried whether the current instruction exists in the instruction cache using the instruction address, if yes, the query is a hit, and the subsequent step 450 is performed, otherwise, the query is a miss, the current instruction is obtained from the lower level cache or memory, and proceeds to step 450.

[0086] In step 450, the current instruction is decoded to obtain one or more micro-instructions corresponding thereto.

[0087] In step 460, the current instruction is identified to determine whether it is an OP_BUILD_START instruction or an OP_BUILD_END instruction, and whether the current instruction is identified as exiting the loop body.

[0088] In step 470, the result of the identification in step 460 and the identification (whether the loop body is exited) are used to determine whether to start or end the training of the OC.

[0089] For example, if the current instruction is an OP_BUILD_START instruction, the training of the OC is started; if the current instruction is an OP_BUILD_END instruction, the training of the OC is ended; if the current instruction is neither an OP_BUILD_START instruction nor an OP_BUILD_END instruction and the loop body has not been exited, the OC training is started (again). The one or more micro-instructions obtained by decoding the current instruction are filled into the micro-instruction cache, and the subsequent execution steps in the pipeline are performed.

[0090] In any of the above embodiments, the OC instruction fetching mode is trained, for example, the position of entering the OC instruction fetching mode is the jump position of the branch instruction, and therefore the information of the OC instruction fetching mode can be trained into the entry of the BTB corresponding to the branch instruction, for subsequent prediction of the OC instruction fetching mode.

[0091] The training method of the instruction fetch mode for the processor provided in at least one embodiment of the present disclosure includes: obtaining branch instruction information of an object branch instruction immediately before an OP_BUILD_END instruction during execution of an object program including an OP_BUILD_START instruction and the OP_BUILD_END instruction; determining whether the object branch instruction jumps according to the branch instruction information to determine whether to update a confidence value of starting an OC instruction fetch mode corresponding to the object branch instruction; reading a branch prediction buffer (BTB) table entry corresponding to the object branch instruction and writing the updated confidence value of starting the OC instruction fetch mode.

[0092] Here, the object branch instruction is used to refer to a branch instruction describing an object, which is immediately adjacent to the OP_BUILD_END instruction in the instruction sequence of the object program, that is, there is no other branch instruction between the object branch instruction and the OP_BUILD_END instruction.

[0093] For example, in at least one embodiment of the present disclosure, the branch instruction information of the object branch instruction immediately before the OP_BUILD_END instruction includes: determining the branch instruction information of the object branch instruction when the OP_BUILD_END instruction reaches the release stage. For example, the branch instruction information includes a branch execution direction, a branch jump destination address, and the like.

[0094] For example, in at least one embodiment of the present disclosure, the object program includes an object loop body, an entry position of the object loop body is a first position, and an exit position of the object loop body is a second position.

[0095] For example, in at least one embodiment of the present disclosure, the training method further includes: in response to an instruction length of the loop body being less than or equal to a capacity of a microinstruction cache, a branch instruction immediately before the OP_BUILD_END instruction in the microinstruction cache is the object branch instruction; or in response to the instruction length of the loop body being greater than the capacity of the microinstruction cache, a branch instruction with a branch prediction target address being an instruction address of the OP_BUILD_START instruction when all instructions of the loop body are released is the object branch instruction.

[0096] In the above embodiments, for example, there are two ways to obtain the branch instruction, respectively for the following two cases. In case 1, when the instruction length of the loop body is less than or equal to the capacity of the microinstruction cache, the instruction before the OP_BUILD_END instruction is the branch instruction, so the branch instruction can be easily obtained. In case 2, when the instruction length of the loop body is greater than the capacity of the microinstruction cache, the instruction before the OP_BUILD_END instruction has a high probability of being a non-branch instruction, so it can be waited for all instructions to be released, find the branch instruction whose branch prediction target address is the instruction address of the OP_BUILD_START instruction, and record it in order to obtain the branch instruction. Subsequently, the recorded BTB entry is searched with the instruction address of OP_BUILD_END as the index. If it is hit, the branch instruction can be obtained.

[0097] For example, in at least one embodiment of the present disclosure, the way of determining whether the target branch instruction jumps according to the branch instruction information to determine whether to update the confidence value (CONFIDENCE) of the start OC instruction fetching mode corresponding to the target branch instruction includes: when it is determined according to the branch instruction information that the execution direction of the target branch instruction is not taken (Not Taken), it is determined to reduce the confidence value of the start OC instruction fetching mode corresponding to the target branch instruction; when it is determined according to the branch instruction information that the execution direction of the target branch instruction is taken (Taken), it is determined to increase the confidence value of the start OC instruction fetching mode corresponding to the target branch instruction. Here, the greater the value of the confidence value, the greater the probability of the start OC instruction fetching mode, and vice versa.

[0098] For example, in at least one embodiment of the present disclosure, writing the updated confidence value of the start OC instruction fetching mode includes: when the OP_BUILD_END instruction is released, writing the updated confidence value of the start OC instruction fetching mode in the branch prediction buffer (BTB) entry corresponding to the target branch instruction, for example, writing the confidence value in the target (Target) address field of the BTB entry.

[0099] Figure 5 A flowchart of a training method of an instruction fetching mode according to an example of at least one embodiment of the present disclosure is shown. As shown in the figure, the processing method includes steps 510-580: Figure 5

[0100] In step 510, the current instruction (or the microinstruction corresponding thereto) is obtained by IC instruction fetching mode or OC instruction fetching mode.

[0101] In step 520, the current instruction is decoded to obtain a microinstruction or the microinstruction is obtained from the microinstruction cache, and the microinstruction is provided to the microinstruction queue for waiting for emission.

[0102] ​In step 530, the OP_BUILD_END instruction is identified, executed and released.

[0103] As mentioned above, for example, the OP_BUILD_END instruction / OP_BUILD_START instruction does not perform specific operation in the fixed-point execution unit, i.e., it is regarded as a null instruction (NOP).

[0104] In step 540, it is determined whether the instruction before the OP_BUILD_END instruction is a branch instruction. If yes, the branch instruction is recorded as a key branch instruction and the process proceeds to step 560. If no, the process proceeds to step 551.

[0105] In step 551, the instruction address of the branch instruction before the OP_BUILD_END instruction is recorded.

[0106] In step 552, it is determined whether there is a BTB entry corresponding to the released branch instruction in the BTB. If yes, the process proceeds to step 553. If no, the process proceeds to step 554.

[0107] In step 553, the branch instruction that hits the released branch instruction in the BTB is recorded.

[0108] In step 554, the branch instruction in the release queue is obtained, and it is determined whether the jump address of the branch instruction is the instruction address corresponding to the OP_BUILD_START instruction.

[0109] In step 555, the branch instruction whose jump address is the instruction address corresponding to the OP_BUILD_START instruction is recorded.

[0110] In step 556, it is determined whether the total capacity of the microinstruction cache can store the entire loop body.

[0111] In step 560, the attribute information of the key branch instruction is obtained and analyzed.

[0112] From the attribute information, the jump direction and the jump destination address of the branch instruction can be obtained.

[0113] In step 570, when it is determined according to the branch instruction information that the execution direction of the target branch instruction is not taken (Not Taken), the confidence value of the start OC instruction fetching mode corresponding to the branch instruction is decreased. When it is determined according to the branch instruction information that the execution direction of the branch instruction is taken (Taken), the confidence value of the start OC instruction fetching mode is increased.

[0114] In step 580, when there is a "start OC instruction fetching mode" training, the update of the BTB is started.

[0115] For example, the instruction address reading utilizes a branch instruction to read a BTB table item corresponding to the branch instruction, increase / decrease a confidence value and update a target position corresponding to the BTB table item.

[0116] At least one embodiment of the present disclosure provides a prediction method of a fetch mode, which comprises: obtaining an object branch instruction in an object program comprising an OP_BUILD_START instruction and an OP_BUILD_END instruction; querying the object branch instruction in a branch prediction buffer to determine whether to perform branch prediction on the object branch instruction and whether to determine whether the object instruction enters an OC fetch mode, wherein a table item of the branch prediction buffer comprises a confidence value of starting an OC fetch path for predicting whether to enter the OC fetch mode.

[0117] For example, in the prediction method of the fetch mode of at least one embodiment of the present disclosure, in response to a branch prediction direction of the object branch instruction being a jump and the confidence value of starting the OC fetch mode being greater than a set value, after waiting for a branch target address of the object branch instruction to arrive, the OC fetch mode is entered; in response to the branch prediction direction of the object branch instruction being a non-jump or the confidence value of starting the OC fetch mode being less than or equal to the set value, after waiting for the branch target address of the object branch instruction to arrive, the current fetch mode is maintained.

[0118] Figure 6 A flowchart of a prediction method of a fetch mode according to an example of at least one embodiment of the present disclosure is shown; for example, IC / OC fetch mode prediction functions are merged into a branch prediction unit, while branch prediction is performed, it is determined whether to enter an IC fetch mode or an OC fetch mode. As shown in the figure, the processing method comprises steps 610-650: Figure 6

[0119] In step 610, a fetch address is generated to obtain a current instruction address.

[0120] In step 620, branch prediction is performed using the current instruction address to obtain branch prediction information (for example, comprising a branch prediction direction, a branch target address, etc.) and a confidence value of starting an OC fetch mode, on the one hand, a new fetch address is obtained based on the branch prediction information, and on the other hand, proceed to step 630.

[0121] In step 630, it is determined whether to start an IC fetch mode or an OC fetch mode according to the branch prediction direction and the confidence value of starting the OC fetch mode, and wait for the branch target address to arrive, if the former, proceed to step 640, otherwise proceed to step 650.

[0122] ​Specifically, if the branch prediction direction of the object branch instruction is Taken and the confidence value of starting the OC instruction fetch mode is > a set value, it is determined to start the OC instruction fetch mode; if the branch prediction direction of the object branch instruction is Not Taken or the confidence value of starting the OC instruction fetch mode is <= the set value, the current instruction fetch mode is maintained, for example, maintained as the IC instruction fetch mode or the OC instruction fetch mode.

[0123] At step 640, the branch target address arrives, and the IC instruction fetch mode is started.

[0124] At step 650, the branch target address arrives, and the OC instruction fetch mode is started.

[0125] At least one embodiment of the present disclosure provides a processor, comprising a decoding unit and an OC, wherein the decoding unit is configured to: in response to identifying an OP_BUILD_START instruction in the process of executing a target program, train instructions after the OP_BUILD_START instruction into a microinstruction cache, and in response to identifying an OP_BUILD_END instruction corresponding to the OP_BUILD_START instruction in the process of executing the target program, stop training instructions after the OP_BUILD_END instruction into the microinstruction cache. Similarly, the OP_BUILD_START instruction is at a first position in the target program, and the OP_BUILD_END instruction is at a second position after the first position in the target program.

[0126] For example, in the processor of at least one embodiment of the present disclosure, the above-mentioned target program comprises an object loop body, an entry position of the object loop body is the first position, and an exit position of the object loop body is the second position.

[0127] For example, in the processor of at least one embodiment of the present disclosure, the decoding unit is further configured to: in response to entering the IC instruction fetch due to the OC instruction fetch miss of the first object instruction after the OP_BUILD_START instruction, determine whether the first object instruction jumps out of the object loop body, and in response to the first object instruction not jumping out of the object loop body, continue to train the first object instruction and instructions after the first object instruction into the microinstruction cache.

[0128] For example, in the processor of at least one embodiment of the present disclosure, the decoding unit is further configured to: in response to determining that the first object instruction does not jump out of the object loop body, create a first identifier, and after decoding the first object instruction, determine to continue to train the first object instruction and instructions after the first object instruction into the microinstruction cache according to the first identifier.

[0129] For example, in at least one embodiment of the present disclosure, the processor further comprises a branch prediction unit and a branch prediction buffer (BTB). The branch prediction unit is configured to: obtain branch instruction information of an object branch instruction immediately before the OP_BUILD_END instruction, determine whether the object branch instruction jumps according to the branch instruction information to determine whether to update the confidence value of the start-OC instruction fetch mode corresponding to the object branch instruction, read the branch prediction buffer (BTB) table item corresponding to the object branch instruction and write the updated confidence value of the start-OC instruction fetch mode.

[0130] For example, in the processor of at least one embodiment of the present disclosure, the branch prediction unit is further configured to: when the OP_BUILD_END instruction reaches the release stage, determine the branch instruction information of the object branch instruction.

[0131] For example, in at least one embodiment of the present disclosure, the target program includes an object loop body, the entry position of the object loop body is a first position, and the exit position of the object loop body is a second position. The branch prediction unit is further configured to: in response to the instruction length of the loop body being less than or equal to the capacity of the microinstruction cache, the branch instruction immediately before the OP_BUILD_END instruction in the microinstruction cache is the object branch instruction, or in response to the instruction length of the loop body being greater than the capacity of the microinstruction cache, the branch instruction with the branch prediction target address being the instruction address of the OP_BUILD_START instruction when all instructions of the loop body are released is the object branch instruction.

[0132] For example, in the processor of at least one embodiment of the present disclosure, the branch prediction unit is further configured to: when it is determined according to the branch instruction information that the execution direction of the object branch instruction is not jump, determine to decrease the confidence value of the start-OC instruction fetch mode, and when it is determined according to the branch instruction information that the execution direction of the object branch instruction is jump, determine to increase the confidence value of the start-OC instruction fetch mode.

[0133] For example, in the processor of at least one embodiment of the present disclosure, the branch prediction unit is further configured to: when it is determined according to the branch instruction information that the execution direction of the object branch instruction is not jump for consecutive N times, determine to decrease the confidence value of the start-OC instruction fetch mode, and when it is determined according to the branch instruction information that the execution direction of the object branch instruction is jump for consecutive M times, determine to increase the confidence value of the start-OC instruction fetch mode.

[0134] For example, in the processor of at least one embodiment of the present disclosure, the branch prediction unit is further configured to: when the OP_BUILD_END instruction is released, write the updated confidence value of the start-OC instruction fetch mode in the branch prediction buffer table item corresponding to the object branch instruction.

[0135] For example, in the processor of at least one embodiment of the present disclosure, the branch prediction unit is further configured to: obtain an object branch instruction in the object program including the OP_BUILD_START instruction and the OP_BUILD_END instruction, query the object branch instruction in the branch prediction buffer to determine whether to perform branch prediction on the object branch instruction and whether to determine whether to enter the OC instruction fetch mode for the object instruction.

[0136] For example, in the processor of at least one embodiment of the present disclosure, in response to the branch prediction direction of the object branch instruction being a jump and the confidence value for starting the OC instruction fetch mode being greater than the set value, after waiting for the branch target address of the object branch instruction to arrive, enter the OC instruction fetch mode; in response to the branch prediction direction of the object branch instruction being a non-jump or the confidence value for starting the OC instruction fetch mode being less than or equal to the set value, maintain the current instruction fetch mode.

[0137] At least one embodiment of the present disclosure also provides a non-transitory readable storage medium, wherein the non-transitory readable storage medium has computer instructions stored thereon, wherein the computer instructions are executed by a processor to implement the program processing method, the instruction processing method, the instruction fetch mode training method, and the instruction fetch mode prediction method of any of the above embodiments.

[0138] At least one embodiment of the present disclosure does not limit the type of instruction set or microarchitecture adopted by the processor, for example, a CISC microarchitecture or a RISC microarchitecture can be adopted, for example, an X86 type microarchitecture, an ARM type microarchitecture, a RISC-V type microarchitecture, etc. can be adopted.

[0139] At least some embodiments of the present disclosure also provide an electronic device including the processor of any of the above embodiments. Figure 7 A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure.

[0140] The electronic device in the embodiments of the present disclosure can include, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a PDA (Personal Digital Assistant), a PAD (Tablet Personal Computer), a PMP (Portable Multimedia Player), a car terminal (e.g., a car navigation terminal), etc., and a stationary terminal such as a digital TV, a desktop computer, etc. Figure 7 The electronic device 1000 shown is merely an example and should not impose any limitation on the functions and scope of use of the embodiments of the present disclosure.

[0141] For example, as Figure 7As shown, in some examples, the electronic device 1000 includes a processing device (e.g., a central processor, a graphics processor, etc.) 1001, which can include a processor of any of the above-described embodiments, that can perform various suitable actions and processes in accordance with programs stored in a read-only memory (ROM) 1002 or loaded into a random access memory (RAM) 1003 from a storage device 1008. Also stored in the RAM 1003 are various programs and data needed by the computer system to operate. The processor 1001, the ROM 1002, and the RAM 1003 are connected to each other by a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0142] For example, the following components can be connected to the I / O interface 1005: input devices 1006 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 1008 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 1009 including, for example, a network interface card, a modem, etc. The communication devices 1009 can allow the electronic device 1000 to communicate wirelessly or wired with other devices to exchange data, perform communication processing via a network such as the Internet. A driver 1010 is also connected to the I / O interface 1005 as necessary. A removable medium 1011 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. is mounted on the driver 1010 as necessary, so that a computer program read out therefrom is installed in the storage device 1008 as necessary. Although Figure 7 The electronic device 1000 is shown including various devices, but it should be understood that not all of the shown devices are required to be implemented or included. More or fewer devices can alternatively be implemented or included.

[0143] For example, the electronic device 1000 can further include a peripheral interface (not shown in the figure) and the like. The peripheral interface can be various types of interfaces, such as a USB interface, a lighting interface, and the like. The communication device 1009 can communicate with a network and other devices through wireless communication, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication can use any of a plurality of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0144] For example, the electronic device 1000 can be any device such as a mobile phone, a tablet computer, a notebook computer, an e-book, a game console, a television, a digital photo frame, a navigator, and the like, or any combination of data processing devices and hardware, and embodiments of the present disclosure are not limited thereto.

[0145] Although the present disclosure has been described in detail with general description and specific embodiments, some modifications or improvements can be made to the present disclosure on the basis of the embodiments of the present disclosure, which is obvious to those skilled in the art. Therefore, these modifications or improvements made on the basis of the spirit of the present disclosure are within the scope of the present disclosure.

[0146] For the present disclosure, the following points need to be explained:

[0147] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can be referred to general design.

[0148] (2) For the purpose of clarity, the thickness of a layer or region is exaggerated or reduced in the drawings used to describe the embodiments of the present disclosure, i.e., the drawings are not drawn according to the actual scale.

[0149] (3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0150] The above merely describes a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A program processing method, comprising: Create the OP_BUILD_START instruction at the first position in the target program; creating an OP_BUILD_END instruction corresponding to the OP_BUILD_START instruction at a second position after the first position in the target program, The OP_BUILD_START instruction is used to instruct the processor to train the instructions after the OP_BUILD_START instruction into the microinstruction cache, and the OP_BUILD_END instruction is used to notify the processor to stop training the instructions after the OP_BUILD_END instruction into the microinstruction cache. The target program includes an object loop body, the first position is an entry position of the object loop body, and the second position is an exit position of the object loop body or a position inside the object loop body. The jump position of the object branch instruction immediately before the OP_BUILD_END instruction is the position for entering the microinstruction cache fetch mode. wherein, in response to a microinstruction cache fetch miss for a first object instruction following the OP_BUILD_START instruction, entering the instruction cache fetch mode, the first object instruction is determined whether to jump out of the object loop body; In response to the first object instruction not jumping out of the object loop body, a first flag is created; After the first object instruction is decoded, the first object instruction and instructions subsequent to the first object instruction are determined to continue to be trained into the microinstruction cache according to the first identifier.

2. The program processing method according to claim 1, further comprising: The object loop body is determined in the target program.

3. The program processing method according to claim 2, wherein: The target program includes a first loop body and a second loop body, Determining the object loop body in the target program includes: In response to the first loop body being executed more times or having more instructions than the second loop body, the first loop body is determined as the target loop body.

4. The program processing method according to claim 1, further comprising: determining the object loop body in the target program; In response to the number of program instructions in the object loop being greater than a storage capacity of the microinstruction cache, and in response to the difference between the number of program instructions in the object loop and the number of program instructions stored in the microinstruction cache reaching a threshold, an entry position of the object loop is used as the first position, and the second position is determined within the object loop.

5. The program processing method according to any one of claims 1 to 4, wherein: The OP_BUILD_START instruction and the OP_BUILD_END instruction are both empty instructions.

6. The program processing method according to any one of claims 1 to 4, wherein: A compiler is used to create the OP_BUILD_START instruction at the first location and the OP_BUILD_END instruction at the second location.

7. A method for processing an instruction, comprising: In response to recognizing an OP_BUILD_START instruction during execution of the target program, training instructions subsequent to the OP_BUILD_START instruction into a microinstruction cache; In response to identifying an OP_BUILD_END instruction corresponding to the OP_BUILD_START instruction during execution of the target program, instructions following the OP_BUILD_END instruction are stopped from being trained into the microinstruction cache, wherein the OP_BUILD_START instruction is at a first position in the target program and the OP_BUILD_END instruction is at a second position in the target program after the first position, The target program includes an object loop body, the first position is an entry position of the object loop body, and the second position is an exit position of the object loop body or a position inside the object loop body. The jump position of the object branch instruction immediately before the OP_BUILD_END instruction is the position for entering the microinstruction cache fetch mode. The method further comprises: In response to a microinstruction cache fetch miss for a first object instruction following the OP_BUILD_START instruction, entering an instruction cache fetch mode, determining whether the first object instruction jumps out of the object loop body; In response to the first object instruction not jumping out of the object loop body, creating a first flag; After the first object instruction is decoded, it is determined according to the first identifier whether the first object instruction and instructions subsequent to the first object instruction are to be further trained into the microinstruction cache.

8. A method for training an instruction fetch mode of a processor, comprising: Obtain branch instruction information of the target branch instruction immediately before the OP_BUILD_END instruction; A method for determining whether the target branch instruction jumps according to the branch instruction information to determine whether to update the confidence value of the start microinstruction cache fetch mode corresponding to the target branch instruction; Reading the branch prediction cache entry corresponding to the target branch instruction and writing the updated confidence value of the startup microinstruction cache fetch mode, The OP_BUILD_START instruction is used to instruct the processor to train the instructions after the OP_BUILD_START instruction into the microinstruction cache, and the OP_BUILD_END instruction is used to notify the processor to stop training the instructions after the OP_BUILD_END instruction into the microinstruction cache. The OP_BUILD_START instruction is at the first position of the target program, and the OP_BUILD_END instruction is at the second position after the first position in the target program. The target program includes an object loop body, the first position is an entry position of the object loop body, and the second position is an exit position of the object loop body or a position inside the object loop body. The jump position of the object branch instruction immediately before the OP_BUILD_END instruction is the position for entering the microinstruction cache fetch mode. The method further comprises: In response to a microinstruction cache fetch miss for a first object instruction following the OP_BUILD_START instruction, entering an instruction cache fetch mode, determining whether the first object instruction jumps out of the object loop body; In response to the first object instruction not jumping out of the object loop body, creating a first flag; After the first object instruction is decoded, it is determined according to the first identifier whether the first object instruction and instructions subsequent to the first object instruction are to be further trained into the microinstruction cache.

9. The training method according to claim 8, wherein: Obtain branch instruction information of the target branch instruction immediately before the OP_BUILD_END instruction, including: When the OP_BUILD_END instruction reaches the release stage, the branch instruction information of the target branch instruction is determined.

10. The training method according to claim 9, further comprising: In response to an instruction length of the loop body being less than or equal to a capacity of the microinstruction cache, taking a branch instruction immediately preceding the OP_BUILD_END instruction in the microinstruction cache as the target branch instruction; or In response to the instruction length of the loop body being greater than the capacity of the microinstruction cache, when all instructions of the loop body are released, a branch instruction whose branch prediction target address is the instruction address of the OP_BUILD_START instruction is used as the target branch instruction.

11. The training method according to claim 8, wherein: The method of determining whether the target branch instruction jumps according to the branch instruction information to determine whether to update the confidence value of the microinstruction cache fetch mode corresponding to the target branch instruction includes: When it is determined according to the branch instruction information that the execution direction of the target branch instruction is not to jump, determining to reduce the confidence value of the microinstruction cache fetch mode; When it is determined according to the branch instruction information that the execution direction of the target branch instruction is a jump, it is determined to increase the confidence value of the microinstruction cache fetch mode.

12. The training method according to claim 8, wherein: Writing the updated confidence value of the microinstruction cache fetch mode includes: When the OP_BUILD_END instruction is released, the updated confidence value of the startup microinstruction cache fetch mode is written into the branch prediction cache entry corresponding to the target branch instruction.

13. A method for predicting an instruction fetch pattern, comprising: Obtaining a target branch instruction in a target program including an OP_BUILD_START instruction and an OP_BUILD_END instruction; querying the target branch instruction in the branch prediction buffer to determine whether to perform branch prediction on the target branch instruction and whether to enter the microinstruction cache fetch mode for the target instruction, The table entry of the branch prediction buffer includes a confidence value for starting a microinstruction cache instruction fetch path for predicting whether to start a microinstruction cache instruction fetch mode, the OP_BUILD_START instruction is used to instruct the processor to train instructions after the OP_BUILD_START instruction into the microinstruction cache, the OP_BUILD_END instruction is used to notify the processor to stop training instructions after the OP_BUILD_END instruction into the microinstruction cache, the OP_BUILD_START instruction is at the first position of the target program, and the OP_BUILD_END instruction is at the second position after the first position in the target program. The target program includes an object loop body, the first position is an entry position of the object loop body, and the second position is an exit position of the object loop body or a position inside the object loop body. The jump position of the object branch instruction immediately before the OP_BUILD_END instruction is the position for entering the microinstruction cache fetch mode. wherein, in response to a microinstruction cache fetch miss for a first object instruction following the OP_BUILD_START instruction, entering the instruction cache fetch mode, the first object instruction is determined whether to jump out of the object loop body; In response to the first object instruction not jumping out of the object loop body, a first flag is created; After the first object instruction is decoded, the first object instruction and instructions subsequent to the first object instruction are determined to continue to be trained into the microinstruction cache according to the first identifier.

14. The prediction method according to claim 13, wherein: In response to the branch prediction direction of the target branch instruction being a jump and the confidence value of starting the microinstruction cache fetch mode being greater than a set value, entering the microinstruction cache fetch mode after waiting for the branch target address of the target branch instruction to arrive; In response to the branch prediction direction of the object branch instruction being no jump or the confidence value of the microinstruction cache fetch mode being enabled being less than or equal to the set value, the current fetch mode is maintained after waiting for the branch target address of the object branch instruction to arrive.

15. A program processing device comprising: a first creation module configured to create an OP_BUILD_START instruction at a first location in the target program; A second creation module is configured to create an OP_BUILD_END instruction corresponding to the OP_BUILD_START instruction at a second position after the first position in the target program, The OP_BUILD_START instruction is used to instruct the processor to train the instructions after the OP_BUILD_START instruction into the microinstruction cache, and the OP_BUILD_END instruction is used to notify the processor to stop training the instructions after the OP_BUILD_END instruction into the microinstruction cache. The target program includes an object loop body, the first position is an entry position of the object loop body, and the second position is an exit position of the object loop body or a position inside the object loop body. The jump position of the object branch instruction immediately before the OP_BUILD_END instruction is the position for entering the microinstruction cache fetch mode. wherein, in response to a microinstruction cache fetch miss for a first object instruction following the OP_BUILD_START instruction, entering the instruction cache fetch mode, the first object instruction is determined whether to jump out of the object loop body; In response to the first object instruction not jumping out of the object loop body, a first flag is created; After the first object instruction is decoded, the first object instruction and instructions subsequent to the first object instruction are determined to continue to be trained into the microinstruction cache according to the first identifier.

16. A processor comprising a decoding unit and a microinstruction cache, in, The decoding unit is configured to, in response to recognizing an OP_BUILD_START instruction during execution of a target program, train instructions subsequent to the OP_BUILD_START instruction into a microinstruction cache, and in response to recognizing an OP_BUILD_END instruction corresponding to the OP_BUILD_START instruction during execution of the target program, stop training instructions subsequent to the OP_BUILD_END instruction into the microinstruction cache, The OP_BUILD_START instruction is at the first position of the target program, and the OP_BUILD_END instruction is at the second position after the first position in the target program. The target program includes an object loop body, the first position is an entry position of the object loop body, and the second position is an exit position of the object loop body or a position inside the object loop body. The jump position of the object branch instruction immediately before the OP_BUILD_END instruction is the position for entering the microinstruction cache fetch mode. The decoding unit is further configured to: In response to a microinstruction cache fetch miss for a first object instruction following the OP_BUILD_START instruction, entering an instruction cache fetch mode, determining whether the first object instruction jumps out of the object loop body; In response to the first object instruction not jumping out of the object loop body, creating a first flag; After the first object instruction is decoded, it is determined according to the first identifier whether the first object instruction and instructions subsequent to the first object instruction are to be further trained into the microinstruction cache.

17. The processor of claim 16, further comprising: A branch prediction unit and a branch prediction buffer, wherein the branch prediction unit is configured to: obtain branch instruction information of the object branch instruction immediately before the OP_BUILD_END instruction, determine whether the object branch instruction jumps based on the branch instruction information to determine whether to update the confidence value of the startup microinstruction cache instruction fetch mode corresponding to the object branch instruction, read the branch prediction buffer table entry corresponding to the object branch instruction and write the updated confidence value of the startup microinstruction cache instruction fetch mode.

18. The processor of claim 17, wherein: The branch prediction unit is also configured to: obtain the object branch instruction in the target program including the OP_BUILD_START instruction and the OP_BUILD_END instruction, query the object branch instruction in the branch prediction buffer to determine whether to perform branch prediction on the object branch instruction and whether to enter the microinstruction cache instruction fetch mode for the object instruction.

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