Pixel circuit, display device, and display driving method

Abstract

The present application relates to a pixel circuit capable of improving image display effect, a display device and a display driving method. The pixel circuit comprises: a first storage unit connected with a bit line, obtaining and storing i-th frame image data from the bit line, i being a positive integer; a second storage unit connected with the first storage unit, obtaining and storing i-th frame image data from the first storage unit and outputting the stored i-th frame image data to a pixel electrode; and the first storage unit further obtains and stores (i+1)-th frame image data from the bit line after the second storage unit obtains i-th frame image data from the first storage unit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a pixel circuit, a display device and a display driving method. BACKGROUND

[0002] Liquid Crystal On Silicon (LCOS) is a kind of reflective small size matrix liquid crystal display device.

[0003] The driving scheme of LCOS is to display the driving voltage of each row of pixels in turn for writing a frame of image, and to turn off the light source after the driving voltage of all pixels in a frame of image is written, so as to avoid the influence on the overall display effect when different frames of image are displayed at the same time.

[0004] However, the turning off of the light source will affect the display effect of the image. SUMMARY

[0005] Therefore, it is necessary to provide a pixel circuit, a display device and a display driving method capable of improving the display effect of the image.

[0006] In a first aspect, a pixel circuit is provided, which comprises:

[0007] a first storage unit connected with a bit line, configured to obtain and save i-th frame of image data from the bit line, i being a positive integer;

[0008] a second storage unit connected with the first storage unit, configured to obtain and save i-th frame of image data from the first storage unit and output the saved i-th frame of image data to a pixel electrode;

[0009] The first storage unit is further configured to obtain and save (i+1)-th frame of image data from the bit line after the second storage unit obtains i-th frame of image data from the first storage unit.

[0010] In a second aspect, a display device is provided, which comprises a plurality of bit lines and a plurality of pixel circuits provided in the first aspect; the plurality of pixel circuits are arranged into a plurality of rows along a first direction and a plurality of columns along a second direction, the first direction and the second direction being perpendicular to each other; each bit line is connected with a plurality of pixel circuits in the same column correspondingly.

[0011] In a third aspect, a display driving method is provided, which is applied to the pixel circuit provided in the first aspect, and the method comprises:

[0012] obtaining and saving i-th frame of image data from a bit line into a first storage unit, i being a positive integer;

[0013] writing the i-th frame image data from the first storage unit into a second storage unit;

[0014] outputting the i-th frame image data from the second storage unit to a pixel electrode; and

[0015] when the i-th frame image data is output to the pixel electrode, acquiring and storing i+1-th frame image data from the bit line into the first storage unit.

[0016] The pixel circuit, the display device and the display driving method have the advantages that the i-th frame image data is acquired and stored from the bit line into the first storage unit, the i-th frame image data is acquired and stored from the first storage unit into the second storage unit, and the stored i-th frame image data is output to the pixel electrode. The data acquisition from the bit line and the data output to the pixel electrode are implemented by different storage units, so that the data of the next frame can be written while the current frame is lightened. In addition, there is no case of displaying different frame images at the same time, so that the power supply does not need to be turned off between displaying different frame images. Therefore, the application can reduce the interval time between different frame images, improve the refresh speed and overall brightness of the image, and further improve the display effect of the image. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0018] Figure 1 A structural block diagram of a display device provided by an embodiment;

[0019] Figure 2 A structural schematic diagram of a pixel circuit provided by an embodiment;

[0020] Figure 3 For Figure 1 A specific circuit diagram of the first storage unit and the second storage unit in the embodiment;

[0021] Figure 4 A graph of the relationship between the transfer ratio and the applied voltage;

[0022] Figure 5 A flowchart of a display driving method provided by an embodiment;

[0023] Figure 6 A timing diagram of each signal line provided by an embodiment.

[0024] Explanation of reference signs:

[0025] 1000 - display device, 100 - pixel unit, 200 - scan line, 300 - data line, 400 - pixel circuit

[0026] 10 - first storage unit, 20 - second storage unit, 30 - output control unit DETAILED DESCRIPTION

[0027] For the purpose of promoting an understanding of the present application, the present application will now be described in more detail with reference to the relevant drawings. The embodiments of the present application are illustrated in the drawings. However, the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. It will be fully appreciated that the scope of the present application is defined by the appended claims.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application.

[0029] It should be understood that the terms "first", "second" and so on used herein can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the other element. For example, without departing from the scope of the present application, the first resistor can be referred to as the second resistor, and similarly, the second resistor can be referred to as the first resistor. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0030] It should be understood that "connection" in the following embodiments, if the circuits, modules, units and the like connected to each other have the transmission of electrical signals or data, should be understood as "electrically connected", "communicatively connected" and the like.

[0031] As used herein, the singular forms "a", "an" and "the" can include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprise / comprising" or "have / having" specifies the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0032] Reference Figure 1, as shown in the structural schematic diagram of the display device 1000 in an embodiment of the present application. The display device 1000 comprises a plurality of pixel units 100, a plurality of scanning lines 200 and a plurality of data lines 300. The plurality of scanning lines 200 and the plurality of data lines 300 cross to define the plurality of pixel units 100, and each pixel unit 100 comprises a pixel circuit 400. The pixel units 100 in the same row are connected to the same scanning line 200, and the pixel units 100 in the same column are connected to the same data line 300. According to the row scanning signals output on the scanning lines 200 in sequence, the data on the data lines 300 is written into the pixel units 100 in sequence for display. After the data is written into all the pixel units 100, the display of one frame of image is completed. At this time, if the data of the next frame of image is directly written into the pixel units 100 in sequence again, because the pixel units 100 in different rows write the data in different sequences, the pixel units 100 in the front row display the current frame of image, the pixel units 100 in the rear row display the previous frame of image, and the two frames of image are displayed simultaneously, thereby affecting the overall display effect.

[0033] For the LCoS display device, in order to avoid the display device 1000 from displaying different frames of image simultaneously, in the related art, after the data of the current frame of image is written into all the pixel units 100 for display, the light source of the LCoS display device is first turned off, and then the data of the next frame of image is written into the pixel units 100 in sequence again for display when the light source is turned off, thereby avoiding the two frames of image from being displayed simultaneously. However, the turning off of the light source occupies a certain time, thereby affecting the display effect of the image, for example, the display brightness of the image.

[0034] To solve the above problem, the present application provides a pixel circuit, a display device and a display driving method. The first storage unit of the pixel circuit acquires and saves the i-th frame of image data from a bit line, the second storage unit of the pixel circuit acquires and saves the i-th frame of image data from the first storage unit, and outputs the saved i-th frame of image data to a pixel electrode. In this way, the acquisition of data from the bit line and the output of data to the pixel electrode are realized by different storage units, so that the data of the next frame can be written while the current frame is lightened up; in addition, there is no case of simultaneous display of different frames of image, so that the power supply does not need to be turned off between the display of different frames of image. Therefore, the present application can reduce the interval time between different frames of image, improve the refresh speed and overall brightness of the image, and further improve the display effect of the image.

[0035] Reference will be made to Figure 2, as shown in the structural block diagram of the pixel circuit 400 provided by an embodiment of the present application. The pixel circuit includes a first storage unit 10 and a second storage unit 20. The first storage unit 10 is connected with a bit line (BL) and obtains and stores i-th frame image data from the bit line, i being a positive integer. The second storage unit 20 is connected with the first storage unit 10 and obtains and stores the i-th frame image data from the first storage unit 10, and outputs the frame image data to a pixel electrode when the frame image data is stored. In this way, the pixel light source corresponding to the frame image data is lit. After the second storage unit 20 obtains the i-th frame image data from the first storage unit 10, the first storage unit 10 obtains and stores (i+1)-th frame image data from the bit line.

[0036] In the embodiment, the bit line is a data line, and each frame image data is sequentially written on the bit line.

[0037] Specifically, the first frame image data is written on the bit line, and the first storage unit 10 obtains and stores the first frame image data from the bit line. Then, the second storage unit 20 obtains and stores the first frame image data from the first storage unit 10. Next, the first frame image data in the second storage unit 20 is output to the pixel electrode to light the pixel light source and display the first frame image.

[0038] The second frame image data is written on the bit line, and the first storage unit 10 obtains and stores the second frame image data from the bit line. Then, the second storage unit 20 obtains and stores the second frame image data from the first storage unit 10. Next, the second frame image data in the second storage unit 20 is output to the pixel electrode to light the pixel light source and display the second frame image. In the embodiment, the first storage unit 10 obtains the second frame image data from the bit line synchronously with the output of the first frame image data in the second storage unit 20 to the pixel electrode.

[0039] The third frame image data is written on the bit line, and the first storage unit 10 obtains and stores the third frame image data from the bit line. Then, the second storage unit 20 obtains and stores the third frame image data from the first storage unit 10. Next, the third frame image data in the second storage unit 20 is output to the pixel electrode to light the pixel light source and display the third frame image. In the embodiment, when the third frame image data in the second storage unit 20 is output to the pixel electrode, the first storage unit 10 obtains and stores the fourth frame image data from the bit line. In this way, each frame image data is sequentially displayed in the above-mentioned manner.

[0040] The pixel circuit includes a first storage unit and a second storage unit. The first storage unit obtains and stores the i-th frame image data from the bit line, and the second storage unit obtains and stores the i-th frame image data from the first storage unit and outputs the stored i-th frame image data to the pixel electrode. In this way, the data obtained from the bit line and the data output to the pixel electrode are implemented by different storage units, so that the data of the next frame can be written while the current frame is lit up. In addition, there is no case of displaying different frame images at the same time, so it is not necessary to turn off the power between displaying different frame images. Therefore, the application can reduce the interval time between different frame images, improve the refresh speed and overall brightness of the image, and further improve the display effect of the image.

[0041] In addition, the entire pixel circuit can be integrated together, and there is no need to separately set a control part outside, which is beneficial to reduce the overall occupied area and reduce the control difficulty.

[0042] In some embodiments, the first storage unit 10 obtains and stores the i+1-th frame image data from the bit line when the i-th frame image data is output to the pixel electrode.

[0043] Specifically, the first frame image data is written on the bit line, and the first storage unit 10 obtains and stores the first frame image data from the bit line. Then the second storage unit 20 obtains and stores the first frame image data from the first storage unit 10. Then the first frame image data in the second storage unit 20 is output to the pixel electrode to light up the pixel light source to display the first frame image.

[0044] When the first frame image data in the second storage unit 20 is output to the pixel electrode, the second frame image data is written on the bit line, and the first storage unit 10 obtains and stores the second frame image data from the bit line. Then the second storage unit 20 obtains and stores the second frame image data from the first storage unit 10. Then the second frame image data in the second storage unit 20 is output to the pixel electrode to light up the pixel light source to display the second frame image.

[0045] When the second frame image data in the second storage unit 20 is output to the pixel electrode, the third frame image data is written on the bit line, and the first storage unit 10 obtains and stores the third frame image data from the bit line. Then the second storage unit 20 obtains and stores the third frame image data from the first storage unit 10. Then the third frame image data in the second storage unit 20 is output to the pixel electrode to light up the pixel light source to display the third frame image.

[0046] Each frame image is displayed in turn according to the above-mentioned manner.

[0047] In the above embodiment, the first storage unit acquires the next frame image data and saves it while the previous frame image data is output to the pixel electrode in the second storage unit, so that the next frame image data is acquired synchronously with the display of the previous frame image. Thus, the next frame image can be displayed immediately after the previous frame image, and the power supply can be turned off between any two adjacent frames. The interval between different frames can be minimized, the refresh rate and overall brightness of the image can be effectively improved, and the display effect of the image can be improved.

[0048] Referring to Figure 3 , a specific circuit diagram of the pixel circuit 400 is shown. In some embodiments, the bit line includes a first bit line BLB, the first storage unit 10 includes a first switch tube T1, a second switch tube T2, and a third switch tube T3, and the on-off conditions of the first switch tube T1 and the second switch tube T2 are opposite. The control end of the third switch tube T3 is connected with the first word line WL0, the first end of the third switch tube T3 is connected with the first bit line BLB, and the second end of the third switch tube T3 is connected with the control end of the first switch tube T1 and the control end of the second switch tube T2. The first end of the first switch tube T1 and the first end of the second switch tube T2 are connected with the second storage unit 20, the second end of the first switch tube T1 is connected with a first working voltage, and the second end of the second switch tube T2 is connected with a second working voltage.

[0049] The first word line WL0 is a scanning line.

[0050] Exemplarily, the first switch tube T1 is a P-type Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the second switch tube T2 is an N-type MOSFET, and the third switch tube T3 is an N-type MOSFET.

[0051] The first working voltage is a power supply voltage (i.e., a high level), and the second working voltage is a ground voltage (i.e., a low level).

[0052] Specifically, when the first word line WL0 is connected with a high level, the control end of the third switch tube T3 is a high level. Since the third switch tube T3 is an N-type MOSFET, the first end and the second end of the third switch tube T3 are connected, i.e., the first bit line BLB is connected with the control end of the first switch tube T1 and the control end of the second switch tube T2.

[0053] When the first word line WL0 is accessed to high level, if the first bit line BLB is accessed to high level, the control end of the first switch tube T1 and the control end of the second switch tube T2 are high level. Since the first switch tube T1 is P-type MOSFET and the second switch tube T2 is N-type MOSFET, the first end and the second end of the first switch tube T1 are disconnected, and the first end and the second end of the second switch tube T2 are connected. Since the first end of the first switch tube T1 is connected with the first end of the second switch tube T2, and the second end of the second switch tube T2 is accessed to the second working voltage, the first end of the first switch tube T1 and the first end of the second switch tube T2 are accessed to the second working voltage, i.e. low level, which is opposite to the first bit line BLB.

[0054] When the first word line WL0 is accessed to high level, if the first bit line BLB is accessed to low level, the control end of the first switch tube T1 and the control end of the second switch tube T2 are low level. Since the first switch tube T1 is P-type MOSFET and the second switch tube T2 is N-type MOSFET, the first end and the second end of the first switch tube T1 are connected, and the first end and the second end of the second switch tube T2 are disconnected. Since the first end of the first switch tube T1 is connected with the first end of the second switch tube T2, and the second end of the first switch tube T1 is accessed to the first working voltage, the first end of the first switch tube T1 and the first end of the second switch tube T2 are accessed to the first working voltage, i.e. high level, which is opposite to the first bit line BLB.

[0055] No matter the first bit line BLB is accessed to high level or low level, the first end of the first switch tube T1 and the first end of the second switch tube T2 of the first storage unit 10 are accessed to the voltage which is opposite to the first bit line BLB, so that the first storage unit 10 obtains the data on the bit line and saves it.

[0056] When the first word line WL0 is accessed to low level, the control end of the third switch tube T3 is low level. Since the third switch tube T3 is N-type MOSFET, the first end and the second end of the third switch tube T3 are disconnected, i.e. the first bit line BLB is disconnected with the control end of the first switch tube T1 and the control end of the second switch tube T2, at this time the first storage unit 10 does not obtain the data on the bit line.

[0057] As Figure 3As shown, the bit line exemplarily comprises a second bit line BL, data on the second bit line BL is opposite to data on the first bit line BLB at the same time. The first storage unit 10 further comprises a fourth switch tube T4, a fifth switch tube T5 and a sixth switch tube T6, a turn-on condition of the fifth switch tube T5 is opposite to a turn-on condition of the sixth switch tube T6. A control end of the fourth switch tube T4 is connected with the first word line WL0, a first end of the fourth switch tube T4 is connected with the second bit line BL, and a second end of the fourth switch tube T4 is connected with a first end of the first switch tube T1, a first end of the second switch tube T2, a control end of the fifth switch tube T5 and a control end of the sixth switch tube T6. A first end of the fifth switch tube T5 and a first end of the sixth switch tube T6 are connected with a control end of the first switch tube T1, a control end of the second switch tube T2 and a second end of the third switch tube T3, a second end of the fifth switch tube T5 is connected with the first working voltage, and a second end of the sixth switch tube T6 is connected with the second working voltage.

[0058] Exemplarily, the fourth switch tube T4 is an N-type MOSFET, the fifth switch tube T5 is a P-type MOSFET, and the sixth switch tube T6 is an N-type MOSFET.

[0059] Specifically, when the first word line WL0 is connected with a high level, the control end of the fourth switch tube T4 is a high level. Since the fourth switch tube T4 is an N-type MOSFET, the first end and the second end of the fourth switch tube T4 are connected, that is, the second bit line BL is connected with the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6.

[0060] When the first word line WL0 is accessed with a high level, if the first bit line BLB is accessed with a high level and the second bit line BL is accessed with a low level, the control end of the first switch tube T1 and the control end of the second switch tube T2 are high level, and the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 are low level. Since the first switch tube T1 is a P-type MOSFET, the second switch tube T2 is an N-type MOSFET, the fifth switch tube T5 is a P-type MOSFET, and the sixth switch tube T6 is an N-type MOSFET, the first end and the second end of the first switch tube T1 are disconnected, the first end and the second end of the second switch tube T2 are connected, the first end and the second end of the fifth switch tube T5 are connected, and the first end and the second end of the sixth switch tube T6 are disconnected. Since the first end of the first switch tube T1 is connected to the first end of the second switch tube T2, and the second end of the second switch tube T2 is accessed with the second working voltage, the first end of the first switch tube T1 and the first end of the second switch tube T2 are accessed with the second working voltage (i.e. low level, same as the second bit line BL) from the second bit line BL. Since the first end of the fifth switch tube T5 is connected to the first end of the sixth switch tube T6, and the second end of the fifth switch tube T5 is accessed with the first working voltage, the first end of the fifth switch tube T5 and the first end of the sixth switch tube T6 are accessed with the first working voltage (i.e. high level, same as the first bit line BLB) from the first bit line BLB. In this way, the first storage unit 10 acquires the data on the bit line and saves it.

[0061] When the first word line WL0 is accessed with a high level, if the first bit line BLB is accessed with a low level and the second bit line BL is accessed with a high level, the control end of the first switch tube T1 and the control end of the second switch tube T2 are low level, and the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 are high level. Since the first switch tube T1 is a P-type MOSFET, the second switch tube T2 is an N-type MOSFET, the fifth switch tube T5 is a P-type MOSFET, and the sixth switch tube T6 is an N-type MOSFET, the first end and the second end of the first switch tube T1 are connected, the first end and the second end of the second switch tube T2 are disconnected, the first end and the second end of the fifth switch tube T5 are disconnected, and the first end and the second end of the sixth switch tube T6 are connected. Since the first end of the first switch tube T1 is connected to the first end of the second switch tube T2, and the second end of the first switch tube T1 is accessed with the first working voltage, the first end of the first switch tube T1 and the first end of the second switch tube T2 are accessed with the first working voltage (i.e. high level, same as the second bit line BL) from the second bit line BL. Since the first end of the fifth switch tube T5 is connected to the first end of the sixth switch tube T6, and the second end of the sixth switch tube T6 is accessed with the second working voltage, the first end of the fifth switch tube T5 and the first end of the sixth switch tube T6 are accessed with the second working voltage (i.e. low level, same as the first bit line BLB) from the first bit line BLB. Thus, the first storage unit 10 acquires the data on the bit line and saves it.

[0062] When the first word line WL0 is connected to a low level, the control terminal of the fourth switch transistor T4 is at a low level. Since the fourth switch transistor T4 is an N-type MOSFET, the first and second terminals of the fourth switch transistor T4 are disconnected, that is, the second bit line BL is disconnected from the control terminals of the fifth switch transistor T5 and the sixth switch transistor T6. At this time, the first storage unit 10 does not acquire and save data on the bit line, but it can acquire and save data in the first storage unit 10.

[0063] In this embodiment, the first switch T1 and the second switch T2 form an inverter, and the fifth switch T5 and the sixth switch T6 form another inverter. The two inverters form an interlocking structure to achieve data storage.

[0064] like Figure 3 As shown, exemplarily, the second storage unit 20 includes a seventh switch transistor T7, an eighth switch transistor T8, and a ninth switch transistor T9. The on / off conditions of the seventh switch transistor T7 are opposite to those of the eighth switch transistor T8. The control terminal of the ninth switch transistor T9 is connected to the second word line WL1. The first terminal of the ninth switch transistor T9 is connected to the control terminals of the first switch transistor T1, the second switch transistor T2, the third switch transistor T3, the fifth switch transistor T5, and the sixth switch transistor T6. The second terminal of the ninth switch transistor T9 is connected to the control terminals of the seventh switch transistor T7 and the eighth switch transistor T8. The first terminals of the seventh switch transistor T7 and the eighth switch transistor T8 are connected to the pixel electrode. The second terminal of the seventh switch transistor T7 is connected to a first operating voltage, and the second terminal of the eighth switch transistor T8 is connected to a second operating voltage.

[0065] Among them, the second word line WL1 is the scan line.

[0066] For example, the seventh switch T7 is a P-type MOSFET, the eighth switch T8 is an N-type MOSFET, and the ninth switch T9 is an N-type MOSFET.

[0067] Specifically, when the second word line WL1 is connected to a high level, the control terminal of the ninth switch transistor T9 is at a high level. Since the ninth switch transistor T9 is an N-type MOSFET, its first and second terminals are connected. Because the first terminal of the ninth switch transistor T9 is connected to the second terminal of the third switch transistor T3, and the second terminal of the ninth switch transistor T9 is connected to the control terminals of the seventh switch transistor T7 and the eighth switch transistor T8, the second terminal of the third switch transistor T3 is connected to the control terminals of the seventh switch transistor T7 and the eighth switch transistor T8.

[0068] When the second word line WL1 is accessed with a high level, if the second end of the third switch tube T3 is a high level, the control end of the seventh switch tube T7 and the control end of the eighth switch tube T8 are high levels. Since the seventh switch tube T7 is a P-type MOSFET and the eighth switch tube T8 is an N-type MOSFET, the first end and the second end of the seventh switch tube T7 are disconnected, and the first end and the second end of the eighth switch tube T8 are connected. Since the first end of the seventh switch tube T7 is connected with the first end of the eighth switch tube T8, and the second end of the eighth switch tube T8 is accessed with the second working voltage, the first end of the seventh switch tube T7 and the first end of the eighth switch tube T8 are accessed with the second working voltage, i.e. a low level, which is opposite to the second end of the third switch tube T3.

[0069] When the second word line WL1 is accessed with a high level, if the second end of the third switch tube T3 is a low level, the control end of the seventh switch tube T7 and the control end of the eighth switch tube T8 are low levels. Since the seventh switch tube T7 is a P-type MOSFET and the eighth switch tube T8 is an N-type MOSFET, the first end and the second end of the seventh switch tube T7 are connected, and the first end and the second end of the eighth switch tube T8 are disconnected. Since the first end of the seventh switch tube T7 is connected with the first end of the eighth switch tube T8, and the second end of the eighth switch tube T8 is accessed with the second working voltage, the first end of the seventh switch tube T7 and the first end of the eighth switch tube T8 are accessed with the first working voltage, i.e. a high level, which is opposite to the second end of the third switch tube T3.

[0070] No matter whether the second end of the third switch tube T3 is a high level or a low level, the first end of the seventh switch tube T7 and the first end of the eighth switch tube T8 are accessed with the voltage which is opposite to the second end of the third switch tube T3, so that the second storage unit 20 obtains the data in the first storage unit 10 and saves.

[0071] When the second word line WL1 is accessed with a low level, the control end of the ninth switch tube T9 is a low level. Since the ninth switch tube T9 is an N-type MOSFET, the first end and the second end of the ninth switch tube T9 are disconnected. Since the first end of the ninth switch tube T9 is connected with the second end of the third switch tube T3, and the second end of the ninth switch tube T9 is connected with the control end of the seventh switch tube T7 and the control end of the eighth switch tube T8, the second end of the third switch tube T3 is disconnected with the control end of the seventh switch tube T7 and the control end of the eighth switch tube T8, at this time the second storage unit 20 does not obtain the data in the first storage unit 10, and the first storage unit 10 can obtain the data on the bit line and save.

[0072] As Figure 3As shown, the second storage unit 20 also includes a tenth switch tube T10, an eleventh switch tube T11 and a twelfth switch tube T12. The on-off condition of the eleventh switch tube T11 is opposite to that of the twelfth switch tube T12. The control end of the tenth switch tube T10 is connected with the second word line WL1. The first end of the tenth switch tube T10 is connected with the first end of the first switch tube T1, the first end of the second switch tube T2, the second end of the fourth switch tube T4, the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6. The second end of the tenth switch tube T10 is connected with the first end of the seventh switch tube T7, the first end of the eighth switch tube T8, the control end of the eleventh switch tube T11 and the control end of the twelfth switch tube T12. The first end of the eleventh switch tube T11 and the first end of the twelfth switch tube T12 are connected with the control end of the seventh switch tube T7 and the control end of the eighth switch tube T8. The second end of the eleventh switch tube T11 is connected with the first working voltage, and the second end of the twelfth switch tube T12 is connected with the second working voltage.

[0073] As an example, the tenth switch tube T10 is an N-type MOSFET, the eleventh switch tube T11 is a P-type MOSFET, and the twelfth switch tube T12 is an N-type MOSFET.

[0074] Specifically, when the second word line WL1 is connected with a high level, the control end of the tenth switch tube T10 is a high level. Since the tenth switch tube T10 is an N-type MOSFET, the first end and the second end of the tenth switch tube T10 are connected. Since the first end of the tenth switch tube T10 is connected with the second end of the fourth switch tube T4, and the second end of the tenth switch tube T10 is connected with the control end of the eleventh switch tube T11 and the control end of the twelfth switch tube T12, the second end of the fourth switch tube T4 is connected with the control end of the eleventh switch tube T11 and the control end of the twelfth switch tube T12.

[0075] When the second word line WL1 is accessed to high level, if the second end of the third switch tube T3 is high level and the second end of the fourth switch tube T4 is low level, the control end of the seventh switch tube T7 and the control end of the eighth switch tube T8 are high level, and the control end of the eleventh switch tube T11 and the control end of the twelfth switch tube T12 are low level. Since the seventh switch tube T7 is P-type MOSFET, the eighth switch tube T8 is N-type MOSFET, the eleventh switch tube T11 is P-type MOSFET, and the twelfth switch tube T12 is N-type MOSFET, therefore the first end and the second end of the seventh switch tube T7 are disconnected, the first end and the second end of the eighth switch tube T8 are connected, the first end and the second end of the eleventh switch tube T11 are connected, and the first end and the second end of the twelfth switch tube T12 are disconnected. Since the first end of the seventh switch tube T7 is connected with the first end of the eighth switch tube T8, and the second end of the eighth switch tube T8 is accessed to the second working voltage, therefore the first end of the seventh switch tube T7 and the first end of the eighth switch tube T8 are accessed to the second working voltage (i.e. low level, same as the second end of the fourth switch tube T4); since the first end of the eleventh switch tube T11 is connected with the first end of the twelfth switch tube T12, and the second end of the eleventh switch tube T11 is accessed to the first working voltage, therefore the first end of the eleventh switch tube T11 and the first end of the twelfth switch tube T12 are accessed to the first working voltage (i.e. high level, same as the second end of the third switch tube T3), so as to realize that the second storage unit 20 acquires the data in the first storage unit 10 and saves.

[0076] When the second word line WL1 is connected to a high level, if the second end of the third switch T3 is connected to a low level and the second end of the fourth switch T4 is connected to a high level, the control ends of the seventh switch T7 and the eighth switch T8 are connected to a low level, and the control ends of the eleventh switch T11 and the twelfth switch T12 are connected to a high level. Since the seventh switch T7 is a P-type MOSFET, the eighth switch T8 is an N-type MOSFET, the eleventh switch T11 is a P-type MOSFET, and the twelfth switch T12 is an N-type MOSFET, the first end and the second end of the seventh switch T7 are connected, the first end and the second end of the eighth switch T8 are disconnected, the first end and the second end of the eleventh switch T11 are disconnected, and the first end and the second end of the twelfth switch T12 are connected. Since the first end of the seventh switch T7 is connected to the first end of the eighth switch T8 and the second end of the seventh switch T7 is connected to the first working voltage, the first end of the seventh switch T7 and the first end of the eighth switch T8 are connected to the first working voltage (i.e., a high level, which is the same as the second end of the fourth switch T4). Since the first end of the eleventh switch T11 is connected to the first end of the twelfth switch T12 and the second end of the twelfth switch T12 is connected to the second working voltage, the first end of the eleventh switch T11 and the first end of the twelfth switch T12 are connected to the second working voltage (i.e., a low level, which is the same as the second end of the third switch T3), so that the second storage unit 20 obtains the data in the first storage unit 10 and saves the data.

[0077] When the second word line WL1 is connected to a low level, the control ends of the ninth switch T9 and the tenth switch T10 are connected to a low level. Since the ninth switch T9 and the tenth switch T10 are N-type MOSFETs, the first end and the second end of the ninth switch T9 and the tenth switch T10 are disconnected. Since the first end of the ninth switch T9 is connected to the second end of the third switch T3 and the second end of the ninth switch T9 is connected to the control ends of the seventh switch T7 and the eighth switch T8, the second end of the third switch T3 is disconnected from the control ends of the seventh switch T7 and the eighth switch T8. Since the first end of the tenth switch T10 is connected to the second end of the fourth switch T4 and the second end of the tenth switch T10 is connected to the control ends of the eleventh switch T11 and the twelfth switch T12, the second end of the fourth switch T4 is disconnected from the control ends of the eleventh switch T11 and the twelfth switch T12. At this time, the second storage unit 20 does not obtain the data in the first storage unit 10, and the first storage unit 10 can obtain the data on the bit line and save the data.

[0078] In the embodiment, the seventh switch T7 and the eighth switch T8 form a flip-flop, the eleventh switch T11 and the twelfth switch T12 form another flip-flop, and the two flip-flops form a mutual locking structure, so that the data is saved.

[0079] In some embodiments, both the first storage unit 10 and the second storage unit 20 include static random-access memory (SRAM). The overall size of the SRAM in the first storage unit 10 is N times the overall size of the SRAM in the second storage unit 20, where N > 1. This ensures that when data is written from the first storage unit to the second storage unit, the voltage drop across the switching transistors in the SRAM of the first storage unit will not affect the data size, thus preventing data changes and ensuring data stability.

[0080] In some embodiments, the seventh switch T7, the eighth switch T8, the ninth switch T9, the tenth switch T10, the eleventh switch T11, and the twelfth switch T12 are all 3.3V devices, which can ensure that the output liquid crystal driving voltage V is sufficient to enable the LCOS to display normally.

[0081] See Figure 4 The diagram shows the relationship between the transmission ratio and the applied voltage in some embodiments of this application. Compared with a 5V device, a 3.3V device can meet the requirements of... Figure 4 The requirements shown in the liquid crystal voltage transfer curve can also reduce device size, improve device response speed, and reduce device power consumption, thus improving brightness while also taking into account size and power consumption.

[0082] Based on the same inventive concept, one embodiment of the present invention provides a display device (not shown), including multiple bit lines and multiple pixel circuits as provided in the above embodiment. The multiple pixel circuits are arranged in multiple rows along a first direction and in multiple columns along a second direction, the first and second directions intersecting perpendicularly. Each bit line is correspondingly connected to multiple pixel circuits in the same column.

[0083] In some embodiments, each bit line includes a first bit line and a second bit line, wherein the data on the second bit line is the opposite of the data on the first bit line at the same time.

[0084] In some embodiments, the display device further includes a plurality of first word lines and a plurality of second word lines, wherein the plurality of first word lines and the plurality of second word lines correspond one-to-one with a plurality of pixel circuits in the same row, each first word line is connected to a first storage unit in the plurality of pixel circuits in the same row, and each second word line is connected to a second storage unit in the plurality of pixel circuits in the same row.

[0085] See Figure 5 The diagram shows a flowchart of a display driving method in some embodiments of this application. Based on the same inventive concept, an embodiment of this invention provides a display driving method, including the following steps:

[0086] Step S502, obtaining and saving the i-th frame image data from the bit line to the first storage unit, i is a positive integer.

[0087] Step S504, writing the i-th frame image data from the first storage unit to the second storage unit.

[0088] Step S506, outputting the i-th frame image data from the second storage unit to the pixel electrode.

[0089] Step S508, obtaining and saving the i+1-th frame image data from the bit line to the first storage unit when the i-th frame image data is output to the pixel electrode.

[0090] Referring to Figure 6 , the timing diagram of the signal lines in some embodiments of the present application is shown. Specifically, in the first first stage, first the first word line WL0 is connected to high level, the first bit line BLB is connected to the control end of the first switch tube T1 and the control end of the second switch tube T2 in the first row of pixel circuits through the third switch tube T3, the second bit line BL is connected to the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 in the first row of pixel circuits through the fourth switch tube T4, so that the first storage unit 10 in the first row of pixel circuits obtains and saves the first frame image data on the bit line.

[0091] Then the first word line WL2 is connected to high level, the first bit line BLB is connected to the control end of the first switch tube T1 and the control end of the second switch tube T2 in the second row of pixel circuits, and the second bit line BL is connected to the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 in the second row of pixel circuits, so that the first storage unit 10 in the second row of pixel circuits obtains and saves the first frame image data on the bit line.

[0092] Then the first word line WL2i is connected to high level, the first bit line BLB is connected to the control end of the first switch tube T1 and the control end of the second switch tube T2 in the i+1-th row of pixel circuits, and the second bit line BL is connected to the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 in the i+1-th row of pixel circuits, so that the first storage unit 10 in the i+1-th row of pixel circuits obtains and saves the first frame image data on the bit line.

[0093] Finally, the first word line WL2n is connected to high level, the first bit line BLB is connected to the control end of the first switch tube T1 and the control end of the second switch tube T2 in the n+1-th row of pixel circuits, and the second bit line BL is connected to the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 in the n+1-th row of pixel circuits, so that the first storage unit 10 in the n+1-th row of pixel circuits obtains and saves the first frame image data on the bit line.

[0094] Meanwhile, the second word line WL1, the second word line WL3, and the second word line WL2n+1 are connected to low voltage, the second end of the third switch T3 in each pixel circuit is disconnected from the control end of the seventh switch T7 and the control end of the eighth switch T8, and the second end of the fourth switch T4 in each pixel circuit is disconnected from the control end of the eleventh switch T11 and the control end of the twelfth switch T12.

[0095] In the first second stage, the first word line WL0, the first word line WL2, and the first word line WL2n are sequentially connected to low voltage, the first bit line BL is disconnected from the control end of the first switch T1 and the control end of the second switch T2 in each pixel circuit, and the second bit line BL is disconnected from the control end of the fifth switch T5 and the control end of the sixth switch T6 in each pixel circuit.

[0096] Meanwhile, the second word line WL1, the second word line WL3, and the second word line WL2n+1 are sequentially connected to high voltage, the second end of the third switch T3 in each pixel circuit is connected to the control end of the seventh switch T7 and the control end of the eighth switch T8, and the second end of the fourth switch T4 in each pixel circuit is connected to the control end of the eleventh switch T11 and the control end of the twelfth switch T12. Since the third switch T3 and the fourth switch T4 are in the first storage unit 10, and the seventh switch T7, the eighth switch T8, the eleventh switch T11, and the twelfth switch T12 are in the second storage unit 20, the second storage unit 20 in each pixel circuit simultaneously acquires and saves the first frame image data in the first storage unit 10.

[0097] In the second first stage, the first storage unit 10 in each row of pixel circuits acquires and saves the second frame image data on the bit line in turn.

[0098] Meanwhile, the first frame image data in the second storage unit 20 in each pixel circuit is simultaneously output to the pixel electrode to light up the pixel light source to display the first frame image.

[0099] In the second second stage, the second storage unit 20 in each pixel circuit simultaneously acquires and saves the second frame image data in the first storage unit 10.

[0100] In the third first stage, the first storage unit 10 in each row of pixel circuits acquires and saves the third frame image data on the bit line in turn.

[0101] Meanwhile, the second frame image data in the second storage unit 20 in each pixel circuit is simultaneously output to the pixel electrode to light up the pixel light source to display the second frame image.

[0102] In the third second stage, the second storage unit 20 in each pixel circuit simultaneously acquires the third frame image data in the first storage unit 10 and saves it.

[0103] The frames of images are displayed in sequence according to the above method.

[0104] In actual application, after the power is turned on, the first storage unit 10 and the second storage unit 20 in each pixel circuit are written with low level, i.e. 0.

[0105] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", "ideal embodiments" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are contained in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example.

[0106] The technical features of the above-described embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above-described embodiments are not described, however, as long as the combinations of the technical features do not contradict, they should be considered as the scope of the present specification.

[0107] The above-described embodiments only express several implementation manners of the present application, the description is more specific and detailed, however, it should not be understood as the limitation of the patent scope of the present application. It should be pointed out that, for the ordinary skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A pixel circuit, characterized by comprising: The pixel circuit comprises: A first storage unit connected with the bit line, used for obtaining and saving the i-th frame image data from the bit line, i being a positive integer; A second storage unit connected with the first storage unit, used for obtaining and saving the i-th frame image data from the first storage unit and outputting the saved i-th frame image data to the pixel electrode; The first storage unit further obtains and saves the i+1-th frame image data from the bit line after the second storage unit obtains the i-th frame image data from the first storage unit; The first storage unit and the second storage unit both comprise static random access memories, the overall size of the static random access memories in the first storage unit is N times of the overall size of the static random access memories in the second storage unit, so that when data is written from the first storage unit to the second storage unit, the size of the data will not be affected by the voltage drop of the switch tube in the first storage unit, and N>1.

2. The pixel circuit of claim 1, wherein, The first storage unit obtains and saves the i+1-th frame image data from the bit line when the i-th frame image data is output to the pixel electrode.

3. The pixel circuit of claim 1, wherein, The bit line comprises a first bit line; the first storage unit comprises a first switch tube, a second switch tube and a third switch tube, the on-off condition of the first switch tube is opposite to that of the second switch tube; the control end of the third switch tube is connected with a first word line, the first end of the third switch tube is connected with the first bit line, and the second end of the third switch tube is connected with the control end of the first switch tube and the control end of the second switch tube; the first end of the first switch tube and the first end of the second switch tube are connected with the second storage unit, the second end of the first switch tube is connected with a first working voltage, and the second end of the second switch tube is connected with a second working voltage.

4. The pixel circuit of claim 3, wherein, The bit line further comprises a second bit line, the data on the second bit line is opposite to the data on the first bit line at the same time; the first storage unit further comprises a fourth switch tube, a fifth switch tube and a sixth switch tube, the on-off condition of the fifth switch tube is opposite to that of the sixth switch tube; the control end of the fourth switch tube is connected with the first word line, the first end of the fourth switch tube is connected with the second bit line, and the second end of the fourth switch tube is connected with the first end of the first switch tube, the first end of the second switch tube, the control end of the fifth switch tube and the control end of the sixth switch tube; the first end of the fifth switch tube and the first end of the sixth switch tube are connected with the control end of the first switch tube, the control end of the second switch tube and the second end of the third switch tube, the second end of the fifth switch tube is connected with the first working voltage, and the second end of the sixth switch tube is connected with the second working voltage.

5. The pixel circuit of claim 4, wherein, The second storage unit comprises a seventh switch tube, an eighth switch tube and a ninth switch tube, the on-off condition of the seventh switch tube is opposite to that of the eighth switch tube; the control end of the ninth switch tube is connected with the second word line, the first end of the ninth switch tube is connected with the control end of the first switch tube, the control end of the second switch tube, the second end of the third switch tube, the first end of the fifth switch tube and the first end of the sixth switch tube, the second end of the ninth switch tube is connected with the control end of the seventh switch tube and the control end of the eighth switch tube; the first end of the seventh switch tube and the first end of the eighth switch tube are connected with the pixel electrode, the second end of the seventh switch tube is connected with the first working voltage, and the second end of the eighth switch tube is connected with the second working voltage.

6. The pixel circuit of claim 5, wherein, The second storage unit further comprises a tenth switch tube, an eleventh switch tube and a twelfth switch tube, the on-off condition of the eleventh switch tube is opposite to that of the twelfth switch tube; the control end of the tenth switch tube is connected with the second word line, the first end of the tenth switch tube is connected with the first end of the first switch tube, the first end of the second switch tube, the second end of the fourth switch tube, the control end of the fifth switch tube and the control end of the sixth switch tube, the second end of the tenth switch tube is connected with the first end of the seventh switch tube, the first end of the eighth switch tube, the control end of the eleventh switch tube and the control end of the twelfth switch tube; the first end of the eleventh switch tube and the first end of the twelfth switch tube are connected with the control end of the seventh switch tube and the control end of the eighth switch tube, the second end of the eleventh switch tube is connected with the first working voltage, and the second end of the twelfth switch tube is connected with the second working voltage.

7. A display device, characterized by comprising: The display device comprises a plurality of pixel circuits according to any one of claims 1 to 6; the plurality of pixel circuits are arranged into a plurality of rows along a first direction and a plurality of columns along a second direction, the first direction and the second direction are perpendicular to each other; each bit line is connected with a plurality of pixel circuits in the same column.

8. The display device according to claim 7, wherein The display device further comprises a plurality of first word lines and a plurality of second word lines, the plurality of first word lines and the plurality of second word lines correspond to a plurality of pixel circuits in the same row one by one, each first word line is connected with a first storage unit in a plurality of pixel circuits in the same row, and each second word line is connected with a second storage unit in a plurality of pixel circuits in the same row.

9. A display driving method, comprising: The method is applied to the pixel circuit according to any one of claims 1 to 6, and the method comprises: acquiring and storing i-th frame image data from a bit line into a first storage unit, i being a positive integer; writing the i-th frame image data from the first storage unit into a second storage unit; outputting the i-th frame image data from the second storage unit to a pixel electrode; and acquiring and storing (i+1)-th frame image data from the bit line into the first storage unit when the i-th frame image data is output to the pixel electrode.

Images