Display panel and driving method thereof

Abstract

The application provides a display panel and a driving method thereof. The display panel comprises a plurality of sub-pixels arranged in an array, a plurality of data lines and a plurality of scan lines connected to the plurality of sub-pixels, wherein each scan line is connected to at least one row of sub-pixels; each column of sub-pixels is connected to two data lines, and each data line corresponds to only one column of sub-pixels; adjacent two sub-pixels in the same column of sub-pixels are connected to different data lines; the pixel voltages output by the two data lines connected to each column of sub-pixels are opposite in electrical property, so that the voltage phase of each sub-pixel after charging is opposite to that of the adjacent sub-pixel; wherein the display panel further comprises an array control unit connected to the plurality of data lines, for controlling one of the two data lines connected to the same column of sub-pixels to be turned on and the other to be turned off at the same time. In the 1G2D structure display panel, half of the source driving modules of the conventional ones are applied to drive all the data lines, thereby reducing the driving cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a driving method thereof. BACKGROUND

[0002] In the related art, a display panel is designed with a 1G2D structure, that is, there is one scanning line between two adjacent rows of sub-pixels, and the same column of sub-pixels has two data lines; one scanning line is connected with two rows of sub-pixels, and one row of sub-pixels is connected with only one scanning line; for two adjacent rows of sub-pixels, the pixels in the same column are connected with different data lines, so that the scanning line can be turned on for 2 rows of time, and the adjacent two rows of pixels are charged by different data lines, so that the charging time is doubled to achieve the required potential of liquid crystal flipping.

[0003] However, although the scanning line is halved, the aperture ratio can be increased, and it is beneficial to make a narrow frame, but the data line is doubled, which leads to the doubling of the Source Driver (source program driving module). For example, the resolution of the UHD (Ultra High Definition, ultra high definition) display panel is 3840*2160, 3840 columns of pixels are 3840*3=11520 sub-pixels, and one SourceDriver generally supports 960 column outputs. Originally, UHD needs 11520 / 960=12, but now it needs 11520*2 / 960=24, which brings great driving cost. SUMMARY

[0004] The present application provides a display panel and a driving method thereof, which can solve the problem of increased driving cost caused by the existing 1G2D structure.

[0005] To solve the above technical problems, the first technical solution provided by the present application is to provide a display panel, comprising a plurality of sub-pixels arranged in an array and a plurality of data lines and a plurality of scanning lines connected to the plurality of sub-pixels, wherein each scanning line is connected to at least one row of sub-pixels; each column of sub-pixels is connected to two data lines, and each data line corresponds to only one column of sub-pixels, and adjacent two sub-pixels in the same column of sub-pixels are connected to different data lines; the pixel voltages output by the two data lines connected to each column of sub-pixels are opposite in electrical properties, so that the voltage phase of each sub-pixel after charging is opposite to that of its adjacent sub-pixel; wherein the display panel further comprises an array control unit, the array control unit is connected to a plurality of data lines, and is used to control one of the two data lines connected to the same column of sub-pixels to be turned on and the other to be turned off at the same time.

[0006] In some embodiments, the array control unit comprises a switch control line and a plurality of transistors corresponding to the number of data lines; wherein each data line is connected to a first end of a transistor, and the second ends of two transistors connected to two data lines of the same column of the sub-pixels are shorted to receive a pixel voltage; the control end of each transistor is connected to the switch control line; wherein one of the two transistors connected to the two data lines of the same column of the sub-pixels is an N-type transistor, and the other is a P-type transistor; the switch control line is used to control the two transistors connected to the two data lines of the same column of the sub-pixels to be turned on at different times.

[0007] In some embodiments, the array control unit comprises a first control line and a second control line and a plurality of transistors corresponding to the number of data lines; wherein each data line is connected to a first end of a transistor, and the second ends of two transistors connected to two data lines of the same column of the sub-pixels are shorted to receive a pixel voltage; the control end of one of the two transistors connected to the two data lines of the same column of the sub-pixels is connected to the first control line, and the control end of the other transistor is connected to the second control line; the first control line and the second control line are used to control the two transistors connected to the two data lines of the same column of the sub-pixels to be turned on at different times.

[0008] In some embodiments, the sub-pixels located in the odd rows and the odd columns are connected to the data lines of the odd columns; the sub-pixels located in the odd rows and the even columns are connected to the data lines of the odd columns; the sub-pixels located in the even rows and the even columns are connected to the data lines of the even columns; the sub-pixels located in the even rows and the odd columns are connected to the data lines of the even columns; the data lines of all odd columns are connected to one of the first control line and the second control line, and the data lines of all even columns are connected to the other of the first control line and the second control line.

[0009] In some embodiments, the sub-pixels located in the odd rows and the odd columns are connected to the data lines of the odd columns; the sub-pixels located in the odd rows and the even columns are connected to the data lines of the even columns; the sub-pixels located in the even rows and the even columns are connected to the data lines of the odd columns; the sub-pixels located in the even rows and the odd columns are connected to the data lines of the even columns; one of the two data lines of adjacent odd columns is connected to one of the first control line and the second control line, and the other of the two data lines of adjacent odd columns is connected to the other of the first control line and the second control line; one of the two data lines of adjacent even columns is connected to one of the first control line and the second control line, and the other of the two data lines of adjacent even columns is connected to the other of the first control line and the second control line.

[0010] In some embodiments, each scan line connects two adjacent rows of the sub-pixels, and each row of the sub-pixels corresponds to only one scan line.

[0011] In some embodiments, each scan line connects only one row of the sub-pixels.

[0012] To solve the above technical problems, the second technical solution provided by the present application is to provide a driving method of a display panel, applied to the display panel of any of the above embodiments, comprising: using an array control unit to control one of two data lines connected to the same column of sub-pixels to be turned on and the other to be turned off at the same time; and simultaneously using a scan line to drive the turned-on data line to output a pixel voltage to the sub-pixels row by row; wherein the pixel voltages output by the two data lines connected to each column of sub-pixels are opposite in electrical properties, so that the voltage phase of each charged sub-pixel is opposite to that of its adjacent sub-pixel.

[0013] In some embodiments, each scan line connects two rows of the sub-pixels to drive a plurality of the data lines to charge the two rows of the sub-pixels respectively; the using of the array control unit to control one of two data lines connected to the same column of sub-pixels to be turned on and the other to be turned off at the same time, and simultaneously using a scan line to drive the turned-on data line to output a pixel voltage to the sub-pixels row by row, comprises: using the array control unit to control one of the two data lines connected to the same column of the sub-pixels to be turned on, and control the scan line to be turned on, to drive the turned-on data line to charge one row of the sub-pixels; wherein the turn-on start time of the scan line is later than the turn-on start time of the data line; using the array control unit to control the turned-on data line to be turned off, and simultaneously control the other of the two data lines connected to the same column of the sub-pixels to be turned on, and simultaneously keep the scan line in the turned-on state, to drive the turned-on data line to charge the next row of the sub-pixels; control the current scan line to be turned off, turn on the next row of the scan line, and use the array control unit to control the turned-on data line to be turned off, wherein the turn-off time of the scan line is earlier than the turn-off time of the data line, and simultaneously control the other of the two data lines connected to the same column of the sub-pixels to be turned on, to drive the turned-on data line to charge the next row of the sub-pixels.

[0014] In some embodiments, each scan line connects to a row of sub-pixels to drive multiple data lines to charge a row of sub-pixels; the step of using the array control unit to simultaneously control one of the two data lines connected to the same column of sub-pixels to be turned on and the other to be turned off; and simultaneously using the scan line to drive the turned-on data line to output pixel voltage to the sub-pixel row by row, includes: using the array control unit to control one of the two data lines connected to the same column of sub-pixels to be turned on, and controlling one scan line to be turned on, so as to drive the turned-on data line to charge a row of sub-pixels; controlling the current scan line to be turned off, turning on the next row of scan lines, and simultaneously using the array control unit to control the turned-on data line to be turned off, and simultaneously controlling the other of the two data lines connected to the same column of sub-pixels to be turned on, so as to drive the turned-on data line to charge the next row of sub-pixels.

[0015] The beneficial effect of this application, which differs from the prior art, is that the display panel and its driving method provided in this application, by setting an array control unit in the 1G2D display panel, can control one of the two data lines connecting the same column of sub-pixels to be turned on and the other to be turned off at the same time, thereby achieving time-division conduction. As a result, all data lines can be driven with half the number of source driving modules compared to the conventional method, thereby reducing driving costs. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0017] Figure 1 A schematic diagram of the structure of the first embodiment of the display panel provided in this application;

[0018] Figure 2 A schematic diagram of the structure of a second embodiment of the display panel provided in this application;

[0019] Figure 3 A schematic diagram of the structure of a third embodiment of the display panel provided in this application;

[0020] Figure 4 A schematic diagram of the structure of the fourth embodiment of the display panel provided in this application;

[0021] Figure 5 A driving timing diagram for a first embodiment of the display panel provided in this application;

[0022] Figure 6A driving timing diagram of a second embodiment of the display panel provided in the present application;

[0023] Figure 7 A structure schematic diagram of a fifth embodiment of the display panel provided in the present application;

[0024] Figure 8 A driving timing diagram of a third embodiment of the display panel provided in the present application;

[0025] Figure 9 A flow schematic diagram of an embodiment of the driving method of the display panel provided in the present application;

[0026] Figure 10 An embodiment of the display panel provided in the present application; Figure 9 A specific flow schematic diagram of a first embodiment of step S11 in the present application;

[0027] Figure 11 An embodiment of the display panel provided in the present application; Figure 9 A specific flow schematic diagram of a second embodiment of step S11 in the present application.

[0028] Explanation of the reference signs:

[0029] Sub-pixel p; data line S (S1-S12); scan line G (G1-G6); first data line S1; second data line S2; third data line S3; fourth data line S4; first data bus D1; second data bus D2; third data bus D3; fourth data bus D4; fifth data bus D5; first scan line G1; second scan line G2;

[0030] Array control unit 10; on-off control line X; first control line X1; second control line X2;

[0031] Transistor T; first transistor T1; second transistor T2; third transistor T3; fourth transistor T4. Specific implementation method

[0032] The terms "first", "second", "third", etc. in the present application are only used for descriptive purpose and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise explicitly and specifically limited. All directional indications (such as upper, lower, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0033] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment can be included in at least one embodiment of the application. The appearances of the phrase that the phrase in various places in the specification are not necessarily all referring to the same embodiment, or are necessarily referring to different or alternative embodiments. It is explicitly and implicitly understood that the embodiments described herein can be combined with each other.

[0034] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0035] Reference is made to Figure 1 , Figure 1A structural schematic diagram of a first embodiment of a display panel provided by the present application is shown. The embodiment of the present application provides a display panel, which comprises a plurality of sub-pixels p arranged in an array and a plurality of data lines S and a plurality of scan lines G connected to the plurality of sub-pixels p, wherein each scan line G is connected to at least one row of sub-pixels p; each column of sub-pixels p is connected to two data lines S, and each data line S corresponds to only one column of sub-pixels p, and adjacent two sub-pixels p in the same column of sub-pixels p are connected to different data lines S, thereby realizing a 1G2D architecture. In the embodiment, the pixel voltages output by the two data lines S connected to each column of sub-pixels p are electrically opposite to each other, so that the voltage phases of each sub-pixel p and its adjacent sub-pixel p after charging are opposite to each other, thereby realizing dot inversion of the array of sub-pixels p. Specifically, the dot inversion has the advantages of good display uniformity and good display quality.

[0036] In the embodiment, the data line S is generally connected to the sub-pixel p through the source-drain end of the transistor T, and the scan line G is connected to the control end of the transistor T. In the state that the scan line G controls the transistor T to be turned on, the pixel voltage on the data line S charges the sub-pixel p through the corresponding transistor T.

[0037] In the embodiment of the present application, each column of sub-pixels p can be sub-pixels p of the same color, for example, the first column of sub-pixels p is red, the second column of sub-pixels p is green, the third column of sub-pixels p is blue, and the fourth column of sub-pixels p is red again, and so on. Of course, in other embodiments, the colors of each column of sub-pixels p can be different, which is not limited herein.

[0038] Further, to avoid the problem that the display panel with the 1G2D architecture causes the number of data lines S to double, thereby increasing the driving cost, in the embodiment, the display panel further comprises an array control unit 10, wherein the array control unit 10 is connected to the plurality of data lines S and is configured to control one of the two data lines S connected to the same column of sub-pixels p to be turned on and the other to be turned off at the same time.

[0039] Specifically, in the embodiment of the present application, one Source Driver is used to drive the two data lines S of the same column of sub-pixels p, and the array control unit 10 is used to control one of the two data lines S connected to the same column of sub-pixels p to be turned on and the other to be turned off at the same time, thereby realizing time-sharing conduction, so that half of the Source Drivers can be used to drive all the data lines S, thereby reducing the driving cost.

[0040] Referring to Figures 2 to 4 , Figure 2 A structural schematic diagram of a second embodiment of a display panel provided by the present application is shown. Figure 3 A structural schematic diagram of a third embodiment of a display panel provided by the present application is shown. Figure 4 A structural schematic diagram of a fourth embodiment of a display panel provided by the present application is shown.

[0041] Specifically, to achieve the above-mentioned drive control, the input ends of the two data lines S connected to the sub-pixel p in the same column are shorted and connected to the Source Driver. The array control unit 10 is located between the shorting point of the two data lines S and the sub-pixel p.

[0042] See Figure 2 In one embodiment, the array control unit 10 includes an on / off control line X and a plurality of transistors T, the same number as the plurality of data lines S. Each data line S is connected to the first terminal of a transistor T. The second terminals of the two transistors T connected to the two data lines S of the same column of sub-pixels p are short-circuited to receive the pixel voltage output by the Source Driver. The control terminal of each transistor T is connected to the on / off control line X. One of the two transistors T connected to the two data lines S of the same column of sub-pixels p is an N-type transistor, and the other is a P-type transistor. The on / off control line X is used to control the two transistors T connected to the two data lines S of the same column of sub-pixels p to be turned on in a time-division multiplexing manner.

[0043] by Figure 2 For example, the first column of sub-pixels p is connected to the first data line S1 and the second data line S2, the second column of sub-pixels p is connected to the third data line S3 and the fourth data line S4, and the first data line S1 and the third data line S3 are connected to the on / off control line X through a P-type transistor T, and the second data line S2 and the fourth data line S4 are connected to the on / off control line X through an N-type transistor T. When the first scan line G1 is turned on and a low-level signal is output on the on / off control line X, the P-type transistor is turned on, so that the Source Driver is turned on with the first data line S1 and the third data line S3. The pixel voltage output by the Source Driver powers the sub-pixels p in the first row of the first column connected to the first data line S1 through the first data line S1, and powers the sub-pixels p in the first row of the second column connected to the third data line S3 through the third data line S3. When the first scan line G1 is turned on and a high-level signal is output on the on / off control line X, the N-type transistor is turned on, enabling the Source Driver to conduct with the second data line S2 and the fourth data line S4. The pixel voltage output by the Source Driver powers the sub-pixels p in the first column and second row connected to the second data line S2 through the second data line S2, and powers the sub-pixels p in the second column and second row connected to the fourth data line S4 through the fourth data line S4. Similarly, the charging principle for the sub-pixels p in other columns of the first and second rows is the same. When the sub-pixels p in the first and second rows are fully charged, the first scan line G1 is turned off, and the second scan line G2 corresponding to the sub-pixels p in the next two rows is turned on, and so on, to complete the charging of all sub-pixels p in the display panel.

[0044] SeeFigure 3 and Figure 4 The array control unit 10 includes a first control line X1 and a second control line X2, and a plurality of transistors T which are the same number as the data lines S; wherein each data line S is connected to the first end of a transistor T, the second ends of the two transistors T connected by the two data lines S of the same column of sub-pixels p are shorted and connected to the Source Driver for receiving the pixel voltage, the control end of one of the two transistors T connected by the two data lines S of the same column of sub-pixels p is connected to the first control line X1, and the control end of the other transistor T is connected to the second control line X2, the first control line X1 and the second control line X2 are used to control the two transistors T connected by the two data lines S of the same column of sub-pixels p to be turned on at different times.

[0045] As shown in Figure 3 and Figure 4 The plurality of transistors T are the same type of transistors, for example, can be N-type transistors T, the first end of the N-type transistor is the source end, the second end is the drain end, and the control end is the gate end; or can be P-type transistors, the first end of the P-type transistor is the drain end, the second end is the source end, and the control end is the gate end.

[0046] As shown in Figure 3and the plurality of transistors T are P-type transistors, the first column of sub-pixels p are connected to the first data line S1 and the second data line S2, the second column of sub-pixels p are connected to the third data line S3 and the fourth data line S4, and the first data line S1 is connected to the second control line X2 through the first transistor T1, the second data line S2 is connected to the first control line X1 through the second transistor T2, the third data line S3 is connected to the second control line X2 through the third transistor T3, and the fourth data line S4 is connected to the first control line X1 through the fourth transistor T4. When the first scan line G1 is turned on and a low-level signal is output on the second control line X2, the first transistor T1 and the third transistor T3 are turned on to enable the Source Driver to be connected to the first data line S1 and the third data line S3, and the pixel voltage output by the Source Driver is supplied to the first column of sub-pixels p in the first row through the first data line S1 and to the second column of sub-pixels p in the first row through the third data line S3. When the first scan line G1 is turned on and a low-level signal is output on the second control line X2, the second transistor T2 and the fourth transistor T4 are turned on to enable the Source Driver to be connected to the second data line S2 and the fourth data line S4, and the pixel voltage output by the Source Driver is supplied to the first column of sub-pixels p in the second row through the second data line S2 and to the second column of sub-pixels p in the second row through the fourth data line S4. Similarly, the charging principle of the other column of sub-pixels p in the first row and the second row is the same; after the first row and the second row of sub-pixels p are charged, the first scan line G1 is turned off, and the second scan line G2 corresponding to the next two rows of sub-pixels p is turned on, and the charging of all the sub-pixels p in the display panel is completed in this way.

[0047] Please continue to see Figure 3 , the sub-pixels p located in the odd rows and the odd columns are connected to the data lines S in the odd columns; the sub-pixels p located in the odd rows and the even columns are connected to the data lines S in the odd columns; the sub-pixels p located in the even rows and the even columns are connected to the data lines S in the even columns; the sub-pixels p located in the even rows and the odd columns are connected to the data lines S in the even columns; all the data lines S in the odd columns are connected to one of the first control line X1 and the second control line X2, and all the data lines S in the even columns are connected to the other of the first control line X1 and the second control line X2.

[0048] Specifically, the data lines S include S1-S12 in a horizontal direction, each column of sub-pixels p is connected to two data lines S, and the electrical properties of the pixel voltages output by the two data lines S are opposite, that is, the pixel voltages output by the data lines S1-S12 in turn are negative-positive-positive-negative-negative-positive-positive-negative-negative-positive-negative, and the input ends of S1 and S2 are connected to a first data bus D1, the input ends of S3 and S4 are connected to a second data bus D2, the input ends of S5 and S6 are connected to a third data bus D3, the input ends of S7 and S8 are connected to a fourth data bus D4, the input ends of S9 and S10 are connected to a fifth data bus D5, the input ends of S11 and S12 are connected to a sixth data bus D6, and the above data buses are connected to a Source Driver to receive pixel voltages.

[0049] For Figure 3 , and for ease of description, charging of each row of sub-pixels p is only exemplified by the first data bus D1 and the second data bus D2, and the driving principle is that G1 is turned on for two rows, X2 is turned on, X1 is turned off, D1 charges S1, D2 charges S3, S1 and S3 need different polarities, and the Source Driver supports. After S1 and S3 are charged, G1 remains turned on, X2 is turned off, X1 is turned on, D1 charges S2, D2 charges S4, S2 and S4 need different polarities, and the Source Driver supports. Then G1 is turned off, G2 is turned on, and the charging is the same. Channel selection driving is achieved through the first control line X1 and the second control line X2, so that the UHD display panel in the background art still only needs 12 Source Drivers, achieving the purpose of reducing the driving cost.

[0050] However, X2 is first turned on, so that S3 is first charged, G1 remains turned on, then X2 is turned off, X1 is turned on, and S2 is charged. Since S2 and S3 are close to each other, S2 may be coupled to S3, causing the voltage of the sub-pixel p connected to S3 to drift. Then G1 is turned off, and the voltage of the sub-pixel p will be in a drifting state all the time, which is easy to affect the display effect.

[0051] Therefore, please refer to Figure 4 , the sub-pixels p located in the odd rows and the odd columns are connected to the data lines S in the odd columns; the sub-pixels p located in the odd rows and the even columns are connected to the data lines S in the even columns; the sub-pixels p located in the even rows and the even columns are connected to the data lines S in the odd columns; the sub-pixels p located in the even rows and the odd columns are connected to the data lines S in the even columns; one of the two data lines S in adjacent odd columns is connected to one of the first control line X1 and the second control line X2, and the other of the two data lines S in adjacent odd columns is connected to the other of the first control line X1 and the second control line X2; one of the two data lines S in adjacent even columns is connected to one of the first control line X1 and the second control line X2, and the other of the two data lines S in adjacent even columns is connected to the other of the first control line X1 and the second control line X2.

[0052] Specifically, the pixel voltages outputted by the two data lines S connected to each column of sub-pixels p are opposite in polarity, i.e., the pixel voltages outputted by S1 to S12 in sequence are negative-positive-negative-positive-negative-positive-negative-positive-negative-positive-negative, and the input ends of S1 and S2 are connected to the first data bus D1, the input ends of S3 and S4 are connected to the second data bus D2, the input ends of S5 and S6 are connected to the third data bus D3, the input ends of S7 and S8 are connected to the fourth data bus D4, the input ends of S9 and S10 are connected to the fifth data bus D5, and the input ends of S11 and S12 are connected to the sixth data bus D6, and the above data buses are connected to the Source Driver to receive the pixel voltages.

[0053] For Figure 4 , and for ease of description, charging of each row of sub-pixels p is exemplified by only the first data bus D1, the second data bus D2, the third data bus D3, and the fourth data bus D4, and the driving principle is that G1 opens two rows, X1 is on, X2 is off, D1 charges S1, D2 charges S4, D3 charges S5, and D4 charges S8, S1 and S4, S5 and S8 need different polarities, the Source Driver supports this, and S4 and S5 are relatively close to each other, S4S5 are coupled to each other, but at this time S4 and S5 are connected to D2 and D3 respectively, and D2 and D3 output constant pixel voltages, thereby being able to eliminate voltage fluctuation stabilization.

[0054] In an embodiment, X1 and X2 are connected to a control unit (such as an IC, COF, etc.) in the display device, and when there are multiple control units, X1 and X2 are connected in parallel to each control unit, and X1 and X2 are arranged at the bottom or top of the display panel. Referring to Figure 5 and Figure 6 , Figure 5 the driving timing diagram of the first embodiment of the display panel provided in the present application; Figure 6 the driving timing diagram of the second embodiment of the display panel provided in the present application. Specifically, since the sub-pixels p are located in the plane, signal transmission needs to pass through glass traces, and there is a large RC in the glass traces, which causes signal line output signal delay, such as G1 signal delay G1', G2 signal delay G2', we make X1 and X2 connected to the control unit in parallel to be sent into the plane, and X1 and X2 are arranged at the bottom or top of the display panel, compared with being sent into the plane only from the leftmost or rightmost of the display panel, X1 and X2 basically do not have horizontal transmission delay, and can be switched synchronously with D1, D2, etc. outputted by the Source Drivers as shown in Figure 5

[0055] wherein, as Figures 1-4 ​The display panel shown, each scan line G connects two adjacent rows of sub-pixels p, and each row of sub-pixels p corresponds to only one scan line G. Its driving principle is described with reference to Figure 5 , at T1, G1 opens two rows, X1 is opened, X2 is closed, the first row of sub-pixels p starts to charge, D1 charges S1, D2 charges S4, at T3, X2 is opened, X1 is closed, the second row of sub-pixels p starts to charge, D1 charges S2, D2 charges S3, at T4, G1 needs to close two rows, G1 and G2 are affected by delay, it takes time to close the transistors T connected with the sub-pixels p, because X1 is opened, X2 is closed, S2 and S3 are normal and not affected, and the second row of sub-pixels p can be slowly closed. However, the first row of sub-pixels p connected with S1 and S4 will have the new voltage of the third row of sub-pixels p poured in, causing the charging of the first row of sub-pixels p to be changed, so the time of one row is divided into charging time and error prevention charging time, which is the same as the existing product.

[0056] In order to prevent error charging, refer to Figure 6 , G1 does not close at T6, but closes at T5 in advance, T4 to T6 is the second row charging time and error prevention charging time, T4 to T5 is the charging time, and T5 to T6 is the error prevention charging time. In order to make the charging uniform, we let the first row and the second row have the same charging time, and let the first row not start charging from T1 but delay to T2. Among them, due to different delay degrees of different areas of the display screen, the error prevention charging time length that can consider all display areas can be selected according to the timing sequence after the product is output.

[0057] Among them, taking the UHD 60Hz display panel as an example, the resolution of the display is 3840*2160, and the actual driving needs 4400*2250 time. The time of one row is 1 / 60 / 2250=7.41uS. Taking a 55-inch model as an example, the error prevention charging needs about 2.5uS to 3uS, and the charging time is about 4.41uS to 4.91uS, which is relatively sufficient. However, if it is 120Hz, the time of one row is 1 / 120 / 2250=3.705uS. The delay degree of the wire will not change with the refresh rate, and the error prevention charging still needs about 2.5uS to 3uS, and the charging time is only about 0.705uS to 1.205uS, which is difficult to charge. If the refresh rate is higher, the resolution is higher, and the product size is larger, the charging will be more difficult.

[0058] Therefore, in order to avoid the charging difficulty problem caused by high refresh rate and resolution, refer to Figure 7 and Figure 8 , Figure 7 is a structure schematic diagram of a fifth embodiment of the display panel provided by the present application. Figure 8 is a driving timing diagram of a third embodiment of the display panel provided by the present application.

[0059] In the embodiment, each scan line G is connected with one row of sub-pixels p. Specifically, referring to FIG. 2, the display panel includes a plurality of scan lines G and a plurality of sub-pixels p arranged in a matrix form. Figure 8 At T1, G1 is turned on to the first row, X1 is turned on, X2 is turned off, the first row of sub-pixels p starts to charge, D1 charges S1, and D2 charges S4. At T3, G1 starts to turn off the first row, G2 is turned on to the second row, X2 is turned on, X1 is turned off, the second row of sub-pixels p starts to charge, D1 charges S2, and D2 charges S3. Similarly, at T5, G2 starts to turn off the second row, G3 is turned on to the third row, X2 is turned on again, X1 is turned off again, D1 charges S1 again, and D2 charges S4 again. However, at this time, one row of time has passed since G1 started to turn off. Due to the switching of X1 being turned on and X2 being turned off, S2 and S3 are not affected normally, and similarly, one row of time is needed to slowly turn off the second row of sub-pixels p. In the process of slowly turning off, the possibility of being coupled by the adjacent data line S is avoided. Due to the non-delay characteristics of X1 being turned on and X2 being turned off, one row of time is used for charging time and one row of time is used for error prevention charging time. Similarly, for the UHD 120Hz display screen, 3.705uS of charging time and 3.705uS of error prevention charging time are needed.

[0060] Referring to FIG. 2, Figure 9 , Figure 9 FIG. 4 is a flowchart of an embodiment of a driving method of a display panel provided in the present application.

[0061] The embodiment of the present application further provides a driving method of a display panel, which is applied to the display panel provided in any of the above embodiments and includes the following steps.

[0062] In step S11, the array control unit 10 is used to control one of the two data lines S connected with the same column of sub-pixels p to be turned on and the other to be turned off at the same time, and the scan line G is used to drive the turned-on data line S to output a pixel voltage to the sub-pixels p row by row. The pixel voltages output by the two data lines S connected with each column of sub-pixels p are opposite in electrical properties, so that the voltage phase of each sub-pixel p after charging is opposite to that of the adjacent sub-pixel p.

[0063] Specifically, the display panel comprises a plurality of sub-pixels p arranged in an array and a plurality of data lines S and a plurality of scan lines G connected to the plurality of sub-pixels p, wherein each scan line G is connected to at least one row of sub-pixels p; each column of sub-pixels p is connected to two data lines S, and each data line S corresponds to only one column of sub-pixels p, and adjacent two sub-pixels p in the same column of sub-pixels p are connected to different data lines S, thereby realizing a 1G2D architecture. Wherein, the pixel voltages output by the two data lines S connected to each column of sub-pixels p are electrically opposite, so that the voltage phase of each sub-pixel p after charging is opposite to that of its adjacent sub-pixel p, thereby realizing dot inversion of the sub-pixel p array. In addition, by means of the array control unit 10, at the same time, one of the two data lines S connected to the same column of sub-pixels p is turned on, and the other is turned off, thereby realizing time-sharing conduction, so that half of the SourceDriver can be applied to drive all the data lines S, thereby reducing the driving cost.

[0064] For the display panel as shown in Figures 1-4 , that is, for the embodiment in which each scan line G is connected to two rows of sub-pixels p to drive the plurality of data lines S to charge the two rows of sub-pixels p, respectively, referring to Figure 10 , Figure 10 , the specific flowchart of the first embodiment of step S11 is shown in Figure 9 , and step S11 specifically comprises:

[0065] Step S21: using the array control unit 10 to control one of the two data lines S connected to the same column of sub-pixels p to be turned on, and to control one scan line G to be turned on, so as to drive the turned-on data line S to charge one row of sub-pixels p; wherein the turn-on start time of the scan line G is later than the turn-on start time of the data line S.

[0066] Step S22: using the array control unit 10 to control the turned-on data line S to be turned off, and at the same time, to control the other data line S connected to the same column of sub-pixels p to be turned on, and at the same time, to keep the scan line G in the turned-on state, so as to drive the turned-on data line S to charge the next row of sub-pixels p.

[0067] Step S23: controlling the current scan line G to be turned off, and the next row of scan lines G to be turned on, and using the array control unit 10 to control the turned-on data line S to be turned off, wherein the turn-off time of the scan line G is earlier than the turn-off time of the data line S, and at the same time, to control the other data line S connected to the same column of sub-pixels p to be turned on, so as to drive the turned-on data line S to charge the next row of sub-pixels p.

[0068] Specifically, referring to Figure 6, T1, X1 is on, X2 is off, T2, G1 is on for two rows, the first row of sub-pixels p starts to charge, D1 charges S1, D2 charges S4, T4, X2 is on, X1 is off, the second row of sub-pixels p starts to charge, D1 charges S2, D2 charges S3, T5, G1 is off for two rows, T7, G1 is off, G2 is on, and the charging is the same.

[0069] Specifically, T4 to T6 are the second row charging time and the anti-error charging time, T4 to T5 are the second row charging time, and T5 to T6 are the first row anti-error charging time.

[0070] For the display panel as shown in Figure 7 , that is, the embodiment in which each scanning line G is connected with a row of sub-pixels p to drive a plurality of data lines S to charge a row of sub-pixels p, referring to Figure 11 , Figure 11 is Figure 9 , the specific flowchart of the second embodiment of step S11 is shown in FIG. 6, and step S11 specifically includes:

[0071] Step S31: using the array control unit 10 to control one of the two data lines S connected with the same column of sub-pixels p to be on, and control one scanning line G to be on, so as to drive the on data line S to charge a row of sub-pixels p.

[0072] Step S32: control the current scanning line G to be off, and control the next row of scanning lines G to be on, at the same time, using the array control unit 10 to control the on data line S to be off, and at the same time, control the other data line S connected with the same column of sub-pixels p to be on, so as to drive the on data line S to charge the next row of sub-pixels p.

[0073] Specifically, referring to Figure 8 , T1, G1 is on for the first row, X1 is on, X2 is off, the first row of sub-pixels p starts to charge, D1 charges S1, D2 charges S4, T3, G1 starts to close the first row, G2 is on for the second row, X2 is on, X1 is off, the second row of sub-pixels p starts to charge, D1 charges S2, D2 charges S3, and similarly, T5, G2 starts to close the second row, G3 is on for the third row, X2 is on again, X1 is off again, D1 charges S1 again, D2 charges S4 again, but at this time, it has been one row time since G1 started to close. Due to the switching of X1 on and X2 off, S2 and S3 are not affected normally, and similarly, it takes one row time to slowly close the second row of sub-pixels p. When slowly closing, we avoid the possibility of being capacitively coupled by adjacent data lines S. With the non-delayed characteristics of X1 and X2 on and off, we will have one row time for charging time and one row time for anti-error charging time.

[0074] The above merely describes the implementation methods of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation, or direct or indirect application in other related technical fields, which is made by using the content of the present application specification and drawings, is also included in the patent protection scope of the present application.

Claims

1. A display panel, comprising a plurality of sub-pixels arranged in an array and a plurality of data lines and a plurality of scan lines connecting the plurality of said sub-pixels, wherein, Each scan line connects to at least one row of sub-pixels; each column of sub-pixels connects to two data lines, and each data line connects to only one column of sub-pixels; adjacent sub-pixels in the same column of sub-pixels connect to different data lines. The feature is that the pixel voltages output by the two data lines connected to each column of sub-pixels are electrically opposite, so that the voltage phase of each sub-pixel after charging is opposite to that of its neighboring sub-pixels; The display panel further includes an array control unit, which is connected to multiple data lines and is used to control one of the two data lines connected to the same column of sub-pixels to be turned on and the other to be turned off at the same time. The array control unit includes a first control line and a second control line, as well as a plurality of transistors, the same number as the plurality of data lines. Each data line is connected to the first end of a transistor. The second ends of the two transistors connected by the two data lines of the same column of sub-pixels are shorted to receive pixel voltage. The control end of one of the two transistors connected by the two data lines of the same column of sub-pixels is connected to the first control line, and the control end of the other transistor is connected to the second control line. The first control line and the second control line are used to control the two transistors connected by the two data lines of the same column of sub-pixels to be turned on in a time-division manner. Wherein, the sub-pixels located in odd-numbered rows and odd-numbered columns are connected to the data lines in odd-numbered columns; the sub-pixels located in odd-numbered rows and even-numbered columns are connected to the data lines in even-numbered columns; the sub-pixels located in even-numbered rows and even-numbered columns are connected to the data lines in odd-numbered columns; and the sub-pixels located in even-numbered rows and odd-numbered columns are connected to the data lines in even-numbered columns. One of the two data lines in an adjacent odd-numbered column is connected to one of the first control line and the second control line, and the other of the two data lines in an adjacent odd-numbered column is connected to the other of the first control line and the second control line. One of the two data lines in an adjacent even-numbered column is connected to one of the first control line and the second control line, and the other of the two data lines in an adjacent odd-numbered column is connected to the other of the first control line and the second control line.

2. The display panel according to claim 1, characterized in that, Each scan line connects two adjacent rows of sub-pixels, and each row of sub-pixels corresponds to only one scan line.

3. The display panel according to claim 1, characterized in that, Each scan line connects only one row of the sub-pixels.

4. A driving method for a display panel, applied to the display panel according to any one of claims 1-3, characterized in that, include: The array control unit controls one of the two data lines connected to the same column of sub-pixels to be turned on and the other to be turned off at the same time; and simultaneously uses scan lines to drive the turned-on data lines to output pixel voltages to the sub-pixels row by row; wherein the pixel voltages output by the two data lines connected to each column of sub-pixels are electrically opposite, so that the voltage of each sub-pixel after charging is out of phase with the voltage of its neighboring sub-pixels.

5. The driving method according to claim 4, characterized in that, Each of the scan lines connects two rows of the sub-pixels to drive multiple data lines to charge the two rows of the sub-pixels respectively; The method of using an array control unit to simultaneously control one of the two data lines connected to the same column of sub-pixels to be turned on and the other to be turned off; and simultaneously using scan lines to drive the turned-on data line to output pixel voltage to the sub-pixel, includes: The array control unit controls one of the two data lines connecting the sub-pixels in the same column to be turned on, and controls one of the scan lines to be turned on, so as to drive the turned-on data line to charge a row of sub-pixels; wherein the turn-on start time of the scan line is later than the turn-on start time of the data line. The array control unit controls the turned-on data line to be turned off, and simultaneously controls the other data line of the two data lines connecting the sub-pixels in the same column to be turned on, while keeping the scan line in the on state, so as to drive the turned-on data line to charge the sub-pixels in the next row. The current scan line is controlled to be cut off, and the next scan line is turned on. The array control unit is used to control the turned-on data line to be cut off, wherein the cut-off time of the scan line is earlier than the cut-off time of the data line. At the same time, the other data line of the two data lines connecting the sub-pixels in the same column is turned on to drive the turned-on data line to charge the sub-pixels in the next row.

6. The driving method according to claim 4, characterized in that, Each of the scan lines connects to a row of the sub-pixels to drive multiple data lines to charge the row of the sub-pixels; The method of using an array control unit to simultaneously control one of the two data lines connected to the same column of sub-pixels to be turned on and the other to be turned off; and simultaneously using scan lines to drive the turned-on data line to output pixel voltage to the sub-pixel, includes: The array control unit controls one of the two data lines connecting the sub-pixels in the same column to be turned on, and controls one of the scan lines to be turned on, so as to drive the turned-on data line to charge a row of sub-pixels. The current scan line is controlled to be cut off, and the next scan line is turned on. At the same time, the array control unit controls the turned-on data line to be cut off, and simultaneously controls the other data line of the two data lines connecting the sub-pixels in the same column to be turned on, so as to drive the turned-on data line to charge the sub-pixels in the next row.

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